tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

powerpc/perf: MMCR0 control for PMU registers under PMCC=00

PowerISA v3.1 introduces new control bit (PMCCEXT) for restricting
access to group B PMU registers in problem state when
MMCR0 PMCC=0b00. In problem state and when MMCR0 PMCC=0b00,
setting the Monitor Mode Control Register bit 54 (MMCR0 PMCCEXT),
will restrict read permission on Group B Performance Monitor
Registers (SIER, SIAR, SDAR and MMCR1). When this bit is set to zero,
group B registers will be readable. In other platforms (like power9),
the older behaviour is retained where group B PMU SPRs are readable.

Patch adds support for MMCR0 PMCCEXT bit in power10 by enabling
this bit during boot and during the PMU event enable/disable callback
functions.

Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1606409684-1589-8-git-send-email-atrajeev@linux.vnet.ibm.com

authored by

Athira Rajeev and committed by
Michael Ellerman 91668ab7 9a8ee526

+15
+1
arch/powerpc/include/asm/reg.h
··· 864 864 #define MMCR0_BHRBA 0x00200000UL /* BHRB Access allowed in userspace */ 865 865 #define MMCR0_EBE 0x00100000UL /* Event based branch enable */ 866 866 #define MMCR0_PMCC 0x000c0000UL /* PMC control */ 867 + #define MMCR0_PMCCEXT ASM_CONST(0x00000200) /* PMCCEXT control */ 867 868 #define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */ 868 869 #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 869 870 #define MMCR0_PMCjCE ASM_CONST(0x00004000) /* PMCj count enable*/
+1
arch/powerpc/kernel/cpu_setup_power.c
··· 123 123 { 124 124 mtspr(SPRN_MMCR3, 0); 125 125 mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE); 126 + mtspr(SPRN_MMCR0, MMCR0_PMCCEXT); 126 127 } 127 128 128 129 /*
+1
arch/powerpc/kernel/dt_cpu_ftrs.c
··· 454 454 455 455 mtspr(SPRN_MMCR3, 0); 456 456 mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE); 457 + mtspr(SPRN_MMCR0, MMCR0_PMCCEXT); 457 458 } 458 459 459 460 static int __init feat_enable_pmu_power10(struct dt_cpu_feature *f)
+4
arch/powerpc/perf/core-book3s.c
··· 95 95 #define SPRN_SIER3 0 96 96 #define MMCRA_SAMPLE_ENABLE 0 97 97 #define MMCRA_BHRB_DISABLE 0 98 + #define MMCR0_PMCCEXT 0 98 99 99 100 static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 100 101 { ··· 1274 1273 val |= MMCR0_FC; 1275 1274 val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | 1276 1275 MMCR0_FC56); 1276 + /* Set mmcr0 PMCCEXT for p10 */ 1277 + if (ppmu->flags & PPMU_ARCH_31) 1278 + val |= MMCR0_PMCCEXT; 1277 1279 1278 1280 /* 1279 1281 * The barrier is to make sure the mtspr has been
+8
arch/powerpc/perf/isa207-common.c
··· 558 558 if (!(pmc_inuse & 0x60)) 559 559 mmcr->mmcr0 |= MMCR0_FC56; 560 560 561 + /* 562 + * Set mmcr0 (PMCCEXT) for p10 which 563 + * will restrict access to group B registers 564 + * when MMCR0 PMCC=0b00. 565 + */ 566 + if (cpu_has_feature(CPU_FTR_ARCH_31)) 567 + mmcr->mmcr0 |= MMCR0_PMCCEXT; 568 + 561 569 mmcr->mmcr1 = mmcr1; 562 570 mmcr->mmcra = mmcra; 563 571 mmcr->mmcr2 = mmcr2;