Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: renesas: r9a09g057: Add clock and reset entries for TSU
Add module clock and reset entries for the TSU0 and TSU1 blocks on the
Renesas RZ/V2H (R9A09G057) SoC.
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251020143107.13974-2-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Ovidiu Panait
and committed by
Geert Uytterhoeven
919bf298
934dcccf
+6
+6
drivers/clk/renesas/r9a09g057-cpg.c
+6
drivers/clk/renesas/r9a09g057-cpg.c
···
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BUS_MSTOP(3, BIT(4))),
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DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
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BUS_MSTOP(3, BIT(4))),
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+
DEF_MOD("tsu_0_pclk", CLK_QEXTAL, 16, 9, 8, 9,
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+
BUS_MSTOP(5, BIT(2))),
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+
DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
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+
BUS_MSTOP(2, BIT(15))),
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};
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static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
···
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DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
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DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
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DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */
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+
DEF_RST(15, 7, 7, 8), /* TSU_0_PRESETN */
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+
DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
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};
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const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {