fbnic: Set Relaxed Ordering PCIe TLP attributes for DMA engines

Add ATTR CSR bit field definitions for the DMA engine TLP header
configuration registers:
AW_CFG: RDE_ATTR[17:15], RQM_ATTR[14:12], TQM_ATTR[11:9]
AR_CFG: TDE_ATTR[17:15], RQM_ATTR[14:12], TQM_ATTR[11:9]

These fields control the PCIe TLP attribute bits for outbound
transactions from the TQM, RQM, RDE (write path), and TDE (read path)
DMA engines. An enum is added with standard PCIe TLP attribute values:
NS (No Snoop), RO (Relaxed Ordering), and IDO (ID-based Ordering).

Read the PCIe Relaxed Ordering capability at probe time and store it in
fbnic_dev. Configure Relaxed Ordering on the PCIe TLP attributes in
fbnic_mbx_init_desc_ring when the capability is enabled. For the write
path (AW_CFG), set RO on RDE and TQM attributes. For the read path
(AR_CFG), set RO on all three attributes (TDE, RQM, TQM). This allows
the PCIe fabric to reorder these transactions for improved throughput.

Signed-off-by: Alexander Duyck <alexanderduyck@fb.com>
Signed-off-by: Dimitri Daskalakis <daskald@meta.com>
Link: https://patch.msgid.link/20260327204445.3074446-1-dimitri.daskalakis1@gmail.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

authored by

Alexander Duyck and committed by

Paolo Abeni 2 months ago 9229cb5a 93d04e76

+27 -2

4 changed files

expand all

drivers

net

ethernet

meta

fbnic

fbnic.h

fbnic_csr.h

fbnic_devlink.c

fbnic_fw.c

drivers/net/ethernet/meta/fbnic/fbnic.h

··· 57 57 u64 dsn; 58 58 u32 mps; 59 59 u32 readrq; 60 + u8 relaxed_ord; 60 61 61 62 /* Local copy of the devices TCAM */ 62 63 struct fbnic_act_tcam act_tcam[FBNIC_RPC_TCAM_ACT_NUM_ENTRIES];

+12

drivers/net/ethernet/meta/fbnic/fbnic_csr.h

··· 975 975 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG 0x3103d /* 0xc40f4 */ 976 976 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_FLUSH CSR_BIT(19) 977 977 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_BME CSR_BIT(18) 978 + #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_RDE_ATTR CSR_GENMASK(17, 15) 979 + #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_RQM_ATTR CSR_GENMASK(14, 12) 980 + #define FBNIC_PUL_OB_TLP_HDR_AW_CFG_TQM_ATTR CSR_GENMASK(11, 9) 981 + enum { 982 + FBNIC_TLP_ATTR_NS = 1, 983 + FBNIC_TLP_ATTR_RO = 2, 984 + FBNIC_TLP_ATTR_IDO = 4, 985 + }; 986 + 978 987 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG 0x3103e /* 0xc40f8 */ 979 988 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_FLUSH CSR_BIT(19) 980 989 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_BME CSR_BIT(18) 990 + #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_TDE_ATTR CSR_GENMASK(17, 15) 991 + #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_RQM_ATTR CSR_GENMASK(14, 12) 992 + #define FBNIC_PUL_OB_TLP_HDR_AR_CFG_TQM_ATTR CSR_GENMASK(11, 9) 981 993 #define FBNIC_PUL_USER_OB_RD_TLP_CNT_31_0 \ 982 994 0x3106e /* 0xc41b8 */ 983 995 #define FBNIC_PUL_USER_OB_RD_DWORD_CNT_31_0 \

drivers/net/ethernet/meta/fbnic/fbnic_devlink.c

··· 647 647 fbd->dsn = pci_get_dsn(pdev); 648 648 fbd->mps = pcie_get_mps(pdev); 649 649 fbd->readrq = pcie_get_readrq(pdev); 650 + fbd->relaxed_ord = pcie_relaxed_ordering_enabled(pdev); 650 651 651 652 fbd->mac_addr_boundary = FBNIC_RPC_TCAM_MACDA_DEFAULT_BOUNDARY; 652 653

+13 -2

drivers/net/ethernet/meta/fbnic/fbnic_fw.c

··· 448 448 449 449 static int fbnic_mbx_init_desc_ring(struct fbnic_dev *fbd, int mbx_idx) 450 450 { 451 + u8 tlp_attr = fbd->relaxed_ord ? FBNIC_TLP_ATTR_RO : 0; 451 452 struct fbnic_fw_mbx *mbx = &fbd->mbx[mbx_idx]; 452 453 453 454 mbx->ready = true; ··· 457 456 case FBNIC_IPC_MBX_RX_IDX: 458 457 /* Enable DMA writes from the device */ 459 458 wr32(fbd, FBNIC_PUL_OB_TLP_HDR_AW_CFG, 460 - FBNIC_PUL_OB_TLP_HDR_AW_CFG_BME); 459 + FBNIC_PUL_OB_TLP_HDR_AW_CFG_BME | 460 + FIELD_PREP(FBNIC_PUL_OB_TLP_HDR_AW_CFG_RDE_ATTR, 461 + tlp_attr) | 462 + FIELD_PREP(FBNIC_PUL_OB_TLP_HDR_AW_CFG_TQM_ATTR, 463 + tlp_attr)); 461 464 462 465 /* Make sure we have a page for the FW to write to */ 463 466 return fbnic_mbx_alloc_rx_msgs(fbd); 464 467 case FBNIC_IPC_MBX_TX_IDX: 465 468 /* Enable DMA reads from the device */ 466 469 wr32(fbd, FBNIC_PUL_OB_TLP_HDR_AR_CFG, 467 - FBNIC_PUL_OB_TLP_HDR_AR_CFG_BME); 470 + FBNIC_PUL_OB_TLP_HDR_AR_CFG_BME | 471 + FIELD_PREP(FBNIC_PUL_OB_TLP_HDR_AR_CFG_TDE_ATTR, 472 + tlp_attr) | 473 + FIELD_PREP(FBNIC_PUL_OB_TLP_HDR_AR_CFG_RQM_ATTR, 474 + tlp_attr) | 475 + FIELD_PREP(FBNIC_PUL_OB_TLP_HDR_AR_CFG_TQM_ATTR, 476 + tlp_attr)); 468 477 break; 469 478 } 470 479

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