Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: rk805: Add rk806 pinctrl support
Add support for rk806 dvs pinctrl to the existing rk805
driver.
This has been implemented using shengfei Xu's rk806
specific driver from the vendor tree as reference.
Co-developed-by: shengfei Xu <xsf@rock-chips.com>
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230504173618.142075-10-sebastian.reichel@collabora.com
Signed-off-by: Lee Jones <lee@kernel.org>
authored by
Sebastian Reichel
and committed by
Lee Jones
924764aa
210f418f
+168
-21
+168
-21
drivers/pinctrl/pinctrl-rk805.c
+168
-21
drivers/pinctrl/pinctrl-rk805.c
···
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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-
* Pinctrl driver for Rockchip RK805 PMIC
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* Pinctrl driver for Rockchip RK805/RK806 PMIC
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*
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* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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* Author: Joseph Chen <chenjh@rock-chips.com>
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* Author: Xu Shengfei <xsf@rock-chips.com>
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*
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* Based on the pinctrl-as3722 driver
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*/
···
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/*
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* @reg: gpio setting register;
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* @fun_reg: functions select register;
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* @fun_mask: functions select mask value, when set is gpio;
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* @dir_mask: input or output mask value, when set is output, otherwise input;
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* @val_mask: gpio set value, when set is level high, otherwise low;
···
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*/
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struct rk805_pin_config {
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u8 reg;
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u8 fun_reg;
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u8 fun_msk;
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u8 dir_msk;
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u8 val_msk;
···
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RK805_PINMUX_GPIO,
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};
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enum rk806_pinmux_option {
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RK806_PINMUX_FUN0 = 0,
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RK806_PINMUX_FUN1,
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RK806_PINMUX_FUN2,
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RK806_PINMUX_FUN3,
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RK806_PINMUX_FUN4,
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RK806_PINMUX_FUN5,
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};
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enum {
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RK805_GPIO0,
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RK805_GPIO1,
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};
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enum {
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RK806_GPIO_DVS1,
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RK806_GPIO_DVS2,
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RK806_GPIO_DVS3
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};
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static const char *const rk805_gpio_groups[] = {
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"gpio0",
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"gpio1",
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};
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static const char *const rk806_gpio_groups[] = {
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"gpio_pwrctrl1",
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"gpio_pwrctrl2",
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"gpio_pwrctrl3",
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};
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/* RK805: 2 output only GPIOs */
···
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PINCTRL_PIN(RK805_GPIO1, "gpio1"),
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};
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/* RK806 */
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static const struct pinctrl_pin_desc rk806_pins_desc[] = {
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PINCTRL_PIN(RK806_GPIO_DVS1, "gpio_pwrctrl1"),
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PINCTRL_PIN(RK806_GPIO_DVS2, "gpio_pwrctrl2"),
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PINCTRL_PIN(RK806_GPIO_DVS3, "gpio_pwrctrl3"),
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};
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static const struct rk805_pin_function rk805_pin_functions[] = {
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{
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.name = "gpio",
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.groups = rk805_gpio_groups,
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.ngroups = ARRAY_SIZE(rk805_gpio_groups),
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.mux_option = RK805_PINMUX_GPIO,
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},
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};
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static const struct rk805_pin_function rk806_pin_functions[] = {
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{
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.name = "pin_fun0",
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.groups = rk806_gpio_groups,
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.ngroups = ARRAY_SIZE(rk806_gpio_groups),
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.mux_option = RK806_PINMUX_FUN0,
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},
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{
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.name = "pin_fun1",
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.groups = rk806_gpio_groups,
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.ngroups = ARRAY_SIZE(rk806_gpio_groups),
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.mux_option = RK806_PINMUX_FUN1,
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},
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{
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.name = "pin_fun2",
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.groups = rk806_gpio_groups,
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.ngroups = ARRAY_SIZE(rk806_gpio_groups),
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.mux_option = RK806_PINMUX_FUN2,
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},
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{
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.name = "pin_fun3",
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.groups = rk806_gpio_groups,
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.ngroups = ARRAY_SIZE(rk806_gpio_groups),
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.mux_option = RK806_PINMUX_FUN3,
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},
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{
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.name = "pin_fun4",
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.groups = rk806_gpio_groups,
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.ngroups = ARRAY_SIZE(rk806_gpio_groups),
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.mux_option = RK806_PINMUX_FUN4,
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},
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{
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.name = "pin_fun5",
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.groups = rk806_gpio_groups,
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.ngroups = ARRAY_SIZE(rk806_gpio_groups),
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.mux_option = RK806_PINMUX_FUN5,
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},
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};
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···
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},
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};
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static const struct rk805_pin_group rk806_pin_groups[] = {
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{
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.name = "gpio_pwrctrl1",
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.pins = { RK806_GPIO_DVS1 },
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.npins = 1,
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},
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{
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.name = "gpio_pwrctrl2",
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.pins = { RK806_GPIO_DVS2 },
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.npins = 1,
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},
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{
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.name = "gpio_pwrctrl3",
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.pins = { RK806_GPIO_DVS3 },
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.npins = 1,
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}
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};
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#define RK805_GPIO0_VAL_MSK BIT(0)
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#define RK805_GPIO1_VAL_MSK BIT(1)
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···
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.reg = RK805_OUT_REG,
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.val_msk = RK805_GPIO1_VAL_MSK,
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},
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};
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#define RK806_PWRCTRL1_DR BIT(0)
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#define RK806_PWRCTRL2_DR BIT(1)
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#define RK806_PWRCTRL3_DR BIT(2)
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#define RK806_PWRCTRL1_DATA BIT(4)
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#define RK806_PWRCTRL2_DATA BIT(5)
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#define RK806_PWRCTRL3_DATA BIT(6)
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#define RK806_PWRCTRL1_FUN GENMASK(2, 0)
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#define RK806_PWRCTRL2_FUN GENMASK(6, 4)
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#define RK806_PWRCTRL3_FUN GENMASK(2, 0)
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static struct rk805_pin_config rk806_gpio_cfgs[] = {
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{
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.fun_reg = RK806_SLEEP_CONFIG0,
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.fun_msk = RK806_PWRCTRL1_FUN,
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.reg = RK806_SLEEP_GPIO,
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.val_msk = RK806_PWRCTRL1_DATA,
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.dir_msk = RK806_PWRCTRL1_DR,
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},
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{
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.fun_reg = RK806_SLEEP_CONFIG0,
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.fun_msk = RK806_PWRCTRL2_FUN,
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.reg = RK806_SLEEP_GPIO,
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.val_msk = RK806_PWRCTRL2_DATA,
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.dir_msk = RK806_PWRCTRL2_DR,
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},
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{
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.fun_reg = RK806_SLEEP_CONFIG1,
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.fun_msk = RK806_PWRCTRL3_FUN,
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.reg = RK806_SLEEP_GPIO,
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.val_msk = RK806_PWRCTRL3_DATA,
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.dir_msk = RK806_PWRCTRL3_DR,
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}
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};
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/* generic gpio chip */
···
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if (!pci->pin_cfg[offset].fun_msk)
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return 0;
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if (mux == RK805_PINMUX_GPIO) {
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ret = regmap_update_bits(pci->rk808->regmap,
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pci->pin_cfg[offset].reg,
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pci->pin_cfg[offset].fun_msk,
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pci->pin_cfg[offset].fun_msk);
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if (ret) {
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dev_err(pci->dev, "set gpio%d GPIO failed\n", offset);
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return ret;
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}
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} else {
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dev_err(pci->dev, "Couldn't find function mux %d\n", mux);
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return -EINVAL;
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}
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mux <<= ffs(pci->pin_cfg[offset].fun_msk) - 1;
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ret = regmap_update_bits(pci->rk808->regmap,
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pci->pin_cfg[offset].fun_reg,
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pci->pin_cfg[offset].fun_msk, mux);
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if (ret)
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dev_err(pci->dev, "set gpio%d func%d failed\n", offset, mux);
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return 0;
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}
···
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return _rk805_pinctrl_set_mux(pctldev, offset, mux);
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}
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static int rk805_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int offset)
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{
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struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
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switch (pci->rk808->variant) {
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case RK805_ID:
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return _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO);
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case RK806_ID:
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return _rk805_pinctrl_set_mux(pctldev, offset, RK806_PINMUX_FUN5);
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}
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return -ENOTSUPP;
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}
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static int rk805_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int offset, bool input)
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{
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struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
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int ret;
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-
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/* switch to gpio function */
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ret = _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO);
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if (ret) {
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dev_err(pci->dev, "set gpio%d mux failed\n", offset);
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return ret;
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}
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/* set direction */
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if (!pci->pin_cfg[offset].dir_msk)
···
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.get_function_name = rk805_pinctrl_get_func_name,
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.get_function_groups = rk805_pinctrl_get_func_groups,
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.set_mux = rk805_pinctrl_set_mux,
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.gpio_request_enable = rk805_pinctrl_gpio_request_enable,
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.gpio_set_direction = rk805_pmx_gpio_set_direction,
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};
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···
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switch (param) {
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case PIN_CONFIG_OUTPUT:
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case PIN_CONFIG_INPUT_ENABLE:
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arg = rk805_gpio_get(&pci->gpio_chip, pin);
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break;
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default:
···
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rk805_gpio_set(&pci->gpio_chip, pin, arg);
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rk805_pmx_gpio_set_direction(pctldev, NULL, pin, false);
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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if (pci->rk808->variant != RK805_ID && arg) {
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rk805_pmx_gpio_set_direction(pctldev, NULL, pin, true);
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break;
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}
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fallthrough;
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default:
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dev_err(pci->dev, "Properties not supported\n");
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return -ENOTSUPP;
···
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pci->pin_cfg = rk805_gpio_cfgs;
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pci->gpio_chip.ngpio = ARRAY_SIZE(rk805_gpio_cfgs);
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break;
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case RK806_ID:
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pci->pins = rk806_pins_desc;
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pci->num_pins = ARRAY_SIZE(rk806_pins_desc);
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pci->functions = rk806_pin_functions;
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pci->num_functions = ARRAY_SIZE(rk806_pin_functions);
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pci->groups = rk806_pin_groups;
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pci->num_pin_groups = ARRAY_SIZE(rk806_pin_groups);
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pci->pinctrl_desc.pins = rk806_pins_desc;
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pci->pinctrl_desc.npins = ARRAY_SIZE(rk806_pins_desc);
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pci->pin_cfg = rk806_gpio_cfgs;
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pci->gpio_chip.ngpio = ARRAY_SIZE(rk806_gpio_cfgs);
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break;
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default:
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dev_err(&pdev->dev, "unsupported RK805 ID %lu\n",
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pci->rk808->variant);
···
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module_platform_driver(rk805_pinctrl_driver);
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MODULE_DESCRIPTION("RK805 pin control and GPIO driver");
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MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>");
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MODULE_AUTHOR("Joseph Chen <chenjh@rock-chips.com>");
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MODULE_LICENSE("GPL v2");