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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
Add target mode support for the DesignWare SPI
Merge series from Benoît Monin <benoit.monin@bootlin.com>:
The DesignWare SPI controller can act as a host or a target; the
choice between the two is set in hardware and cannot be changed by
software. When configured in target mode, the controller has a much
reduced set of capabilities. It only has a single chip-select input and
can only run standard SPI mode (no dual, quad, or octal mode). Despite
this, the overall logic of doing an SPI transfer and the register layout
is identical between both modes, so implementing the target mode reuses
much of the existing code.
The first part of this two-patch series renames the spi_controller to
ctlr instead of host and also changes the suffix of the related functions
to controller. This is done to avoid confusion when referring to the
controller in target mode.
The second patch implements the target mode support by allocating an
SPI controller of the correct type based on the spi-slave property. The
controller is then configured differently depending on the mode. For
an SPI transfer, the same transfer_one() callback is used, with the
difference being in dw_spi_update_config() where only the CTRLR0
register is set. The other registers are not relevant in target mode
and are read-only.
I am posting this as an RFC because I could only perform partial testing
on my setup. I am using an SoC with two DesignWare SPI memory-mapped
controllers identified as Synopsys DWC APB SSI v4.03, one in host mode and
the other in target mode. On the evaluation board, a microcontroller acts
as an SPI relay between the two, but it has some limitations. The number
of bits per word is fixed, as are the clock phase and polarity. It also
only copies data from the host to the target. With this limited setup,
I did test that data can be successfully transferred from the host
to the target using spidev_test. I also checked that polling works by
temporarily disabling the IRQ, but I cannot test DMA. Therefore, more
testing on different devices would be welcome.
+135
-108
+2
-2
drivers/spi/spi-dw-bt1.c
+2
-2
drivers/spi/spi-dw-bt1.c
···
288
288
289
289
pm_runtime_enable(&pdev->dev);
290
290
291
-
ret = dw_spi_add_host(&pdev->dev, dws);
291
+
ret = dw_spi_add_controller(&pdev->dev, dws);
292
292
if (ret) {
293
293
pm_runtime_disable(&pdev->dev);
294
294
return ret;
···
303
303
{
304
304
struct dw_spi_bt1 *dwsbt1 = platform_get_drvdata(pdev);
305
305
306
-
dw_spi_remove_host(&dwsbt1->dws);
306
+
dw_spi_remove_controller(&dwsbt1->dws);
307
307
308
308
pm_runtime_disable(&pdev->dev);
309
309
}
+110
-78
drivers/spi/spi-dw-core.c
+110
-78
drivers/spi/spi-dw-core.c
···
63
63
{
64
64
char name[32];
65
65
66
-
snprintf(name, 32, "dw_spi%d", dws->host->bus_num);
66
+
snprintf(name, 32, "dw_spi%d", dws->ctlr->bus_num);
67
67
dws->debugfs = debugfs_create_dir(name, NULL);
68
68
69
69
dws->regset.regs = dw_spi_dbgfs_regs;
···
185
185
irq_status = dw_readl(dws, DW_SPI_ISR);
186
186
187
187
if (irq_status & DW_SPI_INT_RXOI) {
188
-
dev_err(&dws->host->dev, "RX FIFO overflow detected\n");
188
+
dev_err(&dws->ctlr->dev, "RX FIFO overflow detected\n");
189
189
ret = -EIO;
190
190
}
191
191
192
192
if (irq_status & DW_SPI_INT_RXUI) {
193
-
dev_err(&dws->host->dev, "RX FIFO underflow detected\n");
193
+
dev_err(&dws->ctlr->dev, "RX FIFO underflow detected\n");
194
194
ret = -EIO;
195
195
}
196
196
197
197
if (irq_status & DW_SPI_INT_TXOI) {
198
-
dev_err(&dws->host->dev, "TX FIFO overflow detected\n");
198
+
dev_err(&dws->ctlr->dev, "TX FIFO overflow detected\n");
199
199
ret = -EIO;
200
200
}
201
201
202
202
/* Generically handle the erroneous situation */
203
203
if (ret) {
204
204
dw_spi_reset_chip(dws);
205
-
if (dws->host->cur_msg)
206
-
dws->host->cur_msg->status = ret;
205
+
if (dws->ctlr->cur_msg)
206
+
dws->ctlr->cur_msg->status = ret;
207
207
}
208
208
209
209
return ret;
···
215
215
u16 irq_status = dw_readl(dws, DW_SPI_ISR);
216
216
217
217
if (dw_spi_check_status(dws, false)) {
218
-
spi_finalize_current_transfer(dws->host);
218
+
spi_finalize_current_transfer(dws->ctlr);
219
219
return IRQ_HANDLED;
220
220
}
221
221
···
229
229
dw_reader(dws);
230
230
if (!dws->rx_len) {
231
231
dw_spi_mask_intr(dws, 0xff);
232
-
spi_finalize_current_transfer(dws->host);
232
+
spi_finalize_current_transfer(dws->ctlr);
233
233
} else if (dws->rx_len <= dw_readl(dws, DW_SPI_RXFTLR)) {
234
234
dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1);
235
235
}
···
250
250
251
251
static irqreturn_t dw_spi_irq(int irq, void *dev_id)
252
252
{
253
-
struct spi_controller *host = dev_id;
254
-
struct dw_spi *dws = spi_controller_get_devdata(host);
253
+
struct spi_controller *ctlr = dev_id;
254
+
struct dw_spi *dws = spi_controller_get_devdata(ctlr);
255
255
u16 irq_status = dw_readl(dws, DW_SPI_ISR) & DW_SPI_INT_MASK;
256
256
257
257
if (!irq_status)
258
258
return IRQ_NONE;
259
259
260
-
if (!host->cur_msg) {
260
+
if (!ctlr->cur_msg) {
261
261
dw_spi_mask_intr(dws, 0xff);
262
262
return IRQ_HANDLED;
263
263
}
···
331
331
cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_TMOD_MASK, cfg->tmode);
332
332
333
333
dw_writel(dws, DW_SPI_CTRLR0, cr0);
334
+
335
+
if (spi_controller_is_target(dws->ctlr))
336
+
return;
334
337
335
338
if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD ||
336
339
cfg->tmode == DW_SPI_CTRLR0_TMOD_RO)
···
413
410
return 0;
414
411
}
415
412
416
-
static int dw_spi_transfer_one(struct spi_controller *host,
413
+
static int dw_spi_transfer_one(struct spi_controller *ctlr,
417
414
struct spi_device *spi,
418
415
struct spi_transfer *transfer)
419
416
{
420
-
struct dw_spi *dws = spi_controller_get_devdata(host);
417
+
struct dw_spi *dws = spi_controller_get_devdata(ctlr);
421
418
struct dw_spi_cfg cfg = {
422
419
.tmode = DW_SPI_CTRLR0_TMOD_TR,
423
420
.dfs = transfer->bits_per_word,
···
442
439
transfer->effective_speed_hz = dws->current_freq;
443
440
444
441
/* Check if current transfer is a DMA transaction */
445
-
dws->dma_mapped = spi_xfer_is_dma_mapped(host, spi, transfer);
442
+
dws->dma_mapped = spi_xfer_is_dma_mapped(ctlr, spi, transfer);
446
443
447
444
/* For poll mode just disable all interrupts */
448
445
dw_spi_mask_intr(dws, 0xff);
···
465
462
return 1;
466
463
}
467
464
468
-
static void dw_spi_handle_err(struct spi_controller *host,
469
-
struct spi_message *msg)
465
+
static inline void dw_spi_abort(struct spi_controller *ctlr)
470
466
{
471
-
struct dw_spi *dws = spi_controller_get_devdata(host);
467
+
struct dw_spi *dws = spi_controller_get_devdata(ctlr);
472
468
473
469
if (dws->dma_mapped)
474
470
dws->dma_ops->dma_stop(dws);
475
471
476
472
dw_spi_reset_chip(dws);
473
+
}
474
+
475
+
static void dw_spi_handle_err(struct spi_controller *ctlr,
476
+
struct spi_message *msg)
477
+
{
478
+
dw_spi_abort(ctlr);
479
+
}
480
+
481
+
static int dw_spi_target_abort(struct spi_controller *ctlr)
482
+
{
483
+
dw_spi_abort(ctlr);
484
+
485
+
return 0;
477
486
}
478
487
479
488
static int dw_spi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op)
···
589
574
while (len) {
590
575
entries = readl_relaxed(dws->regs + DW_SPI_TXFLR);
591
576
if (!entries) {
592
-
dev_err(&dws->host->dev, "CS de-assertion on Tx\n");
577
+
dev_err(&dws->ctlr->dev, "CS de-assertion on Tx\n");
593
578
return -EIO;
594
579
}
595
580
room = min(dws->fifo_len - entries, len);
···
609
594
if (!entries) {
610
595
sts = readl_relaxed(dws->regs + DW_SPI_RISR);
611
596
if (sts & DW_SPI_INT_RXOI) {
612
-
dev_err(&dws->host->dev, "FIFO overflow on Rx\n");
597
+
dev_err(&dws->ctlr->dev, "FIFO overflow on Rx\n");
613
598
return -EIO;
614
599
}
615
600
continue;
···
650
635
spi_delay_exec(&delay, NULL);
651
636
652
637
if (retry < 0) {
653
-
dev_err(&dws->host->dev, "Mem op hanged up\n");
638
+
dev_err(&dws->ctlr->dev, "Mem op hanged up\n");
654
639
return -EIO;
655
640
}
656
641
···
849
834
DW_SPI_GET_BYTE(dws->ver, 1));
850
835
}
851
836
852
-
/*
853
-
* Try to detect the number of native chip-selects if the platform
854
-
* driver didn't set it up. There can be up to 16 lines configured.
855
-
*/
856
-
if (!dws->num_cs) {
857
-
u32 ser;
837
+
if (spi_controller_is_target(dws->ctlr)) {
838
+
/* There is only one CS input signal in target mode */
839
+
dws->num_cs = 1;
840
+
} else {
841
+
/*
842
+
* Try to detect the number of native chip-selects if the platform
843
+
* driver didn't set it up. There can be up to 16 lines configured.
844
+
*/
845
+
if (!dws->num_cs) {
846
+
u32 ser;
858
847
859
-
dw_writel(dws, DW_SPI_SER, 0xffff);
860
-
ser = dw_readl(dws, DW_SPI_SER);
861
-
dw_writel(dws, DW_SPI_SER, 0);
848
+
dw_writel(dws, DW_SPI_SER, 0xffff);
849
+
ser = dw_readl(dws, DW_SPI_SER);
850
+
dw_writel(dws, DW_SPI_SER, 0);
862
851
863
-
dws->num_cs = hweight16(ser);
852
+
dws->num_cs = hweight16(ser);
853
+
}
864
854
}
865
855
866
856
/*
···
918
898
.per_op_freq = true,
919
899
};
920
900
921
-
int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
901
+
int dw_spi_add_controller(struct device *dev, struct dw_spi *dws)
922
902
{
923
-
struct spi_controller *host;
903
+
struct spi_controller *ctlr;
904
+
bool target;
924
905
int ret;
925
906
926
907
if (!dws)
927
908
return -EINVAL;
928
909
929
-
host = spi_alloc_host(dev, 0);
930
-
if (!host)
910
+
target = device_property_read_bool(dev, "spi-slave");
911
+
if (target)
912
+
ctlr = spi_alloc_target(dev, 0);
913
+
else
914
+
ctlr = spi_alloc_host(dev, 0);
915
+
916
+
if (!ctlr)
931
917
return -ENOMEM;
932
918
933
-
device_set_node(&host->dev, dev_fwnode(dev));
919
+
device_set_node(&ctlr->dev, dev_fwnode(dev));
934
920
935
-
dws->host = host;
921
+
dws->ctlr = ctlr;
936
922
dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
937
923
938
-
spi_controller_set_devdata(host, dws);
924
+
spi_controller_set_devdata(ctlr, dws);
939
925
940
926
/* Basic HW init */
941
927
dw_spi_hw_init(dev, dws);
942
928
943
929
ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
944
-
host);
930
+
ctlr);
945
931
if (ret < 0 && ret != -ENOTCONN) {
946
932
dev_err(dev, "can not get IRQ\n");
947
-
goto err_free_host;
933
+
goto err_free_ctlr;
948
934
}
949
935
950
936
dw_spi_init_mem_ops(dws);
951
937
952
-
host->use_gpio_descriptors = true;
953
-
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
938
+
ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
954
939
if (dws->caps & DW_SPI_CAP_DFS32)
955
-
host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
940
+
ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
956
941
else
957
-
host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
958
-
host->bus_num = dws->bus_num;
959
-
host->num_chipselect = dws->num_cs;
960
-
host->setup = dw_spi_setup;
961
-
host->cleanup = dw_spi_cleanup;
962
-
if (dws->set_cs)
963
-
host->set_cs = dws->set_cs;
964
-
else
965
-
host->set_cs = dw_spi_set_cs;
966
-
host->transfer_one = dw_spi_transfer_one;
967
-
host->handle_err = dw_spi_handle_err;
968
-
if (dws->mem_ops.exec_op) {
969
-
host->mem_ops = &dws->mem_ops;
970
-
host->mem_caps = &dw_spi_mem_caps;
942
+
ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
943
+
ctlr->bus_num = dws->bus_num;
944
+
ctlr->num_chipselect = dws->num_cs;
945
+
ctlr->setup = dw_spi_setup;
946
+
ctlr->cleanup = dw_spi_cleanup;
947
+
ctlr->transfer_one = dw_spi_transfer_one;
948
+
ctlr->handle_err = dw_spi_handle_err;
949
+
ctlr->auto_runtime_pm = true;
950
+
951
+
if (!target) {
952
+
ctlr->use_gpio_descriptors = true;
953
+
ctlr->mode_bits |= SPI_LOOP;
954
+
if (dws->set_cs)
955
+
ctlr->set_cs = dws->set_cs;
956
+
else
957
+
ctlr->set_cs = dw_spi_set_cs;
958
+
if (dws->mem_ops.exec_op) {
959
+
ctlr->mem_ops = &dws->mem_ops;
960
+
ctlr->mem_caps = &dw_spi_mem_caps;
961
+
}
962
+
ctlr->max_speed_hz = dws->max_freq;
963
+
ctlr->flags = SPI_CONTROLLER_GPIO_SS;
964
+
} else {
965
+
ctlr->target_abort = dw_spi_target_abort;
971
966
}
972
-
host->max_speed_hz = dws->max_freq;
973
-
host->flags = SPI_CONTROLLER_GPIO_SS;
974
-
host->auto_runtime_pm = true;
975
967
976
968
/* Get default rx sample delay */
977
969
device_property_read_u32(dev, "rx-sample-delay-ns",
···
996
964
} else if (ret) {
997
965
dev_warn(dev, "DMA init failed\n");
998
966
} else {
999
-
host->can_dma = dws->dma_ops->can_dma;
1000
-
host->flags |= SPI_CONTROLLER_MUST_TX;
967
+
ctlr->can_dma = dws->dma_ops->can_dma;
968
+
ctlr->flags |= SPI_CONTROLLER_MUST_TX;
1001
969
}
1002
970
}
1003
971
1004
-
ret = spi_register_controller(host);
972
+
ret = spi_register_controller(ctlr);
1005
973
if (ret) {
1006
-
dev_err_probe(dev, ret, "problem registering spi host\n");
974
+
dev_err_probe(dev, ret, "problem registering spi controller\n");
1007
975
goto err_dma_exit;
1008
976
}
1009
977
···
1015
983
dws->dma_ops->dma_exit(dws);
1016
984
dw_spi_enable_chip(dws, 0);
1017
985
err_free_irq:
1018
-
free_irq(dws->irq, host);
1019
-
err_free_host:
1020
-
spi_controller_put(host);
986
+
free_irq(dws->irq, ctlr);
987
+
err_free_ctlr:
988
+
spi_controller_put(ctlr);
1021
989
return ret;
1022
990
}
1023
-
EXPORT_SYMBOL_NS_GPL(dw_spi_add_host, "SPI_DW_CORE");
991
+
EXPORT_SYMBOL_NS_GPL(dw_spi_add_controller, "SPI_DW_CORE");
1024
992
1025
-
void dw_spi_remove_host(struct dw_spi *dws)
993
+
void dw_spi_remove_controller(struct dw_spi *dws)
1026
994
{
1027
995
dw_spi_debugfs_remove(dws);
1028
996
1029
-
spi_unregister_controller(dws->host);
997
+
spi_unregister_controller(dws->ctlr);
1030
998
1031
999
if (dws->dma_ops && dws->dma_ops->dma_exit)
1032
1000
dws->dma_ops->dma_exit(dws);
1033
1001
1034
1002
dw_spi_shutdown_chip(dws);
1035
1003
1036
-
free_irq(dws->irq, dws->host);
1004
+
free_irq(dws->irq, dws->ctlr);
1037
1005
}
1038
-
EXPORT_SYMBOL_NS_GPL(dw_spi_remove_host, "SPI_DW_CORE");
1006
+
EXPORT_SYMBOL_NS_GPL(dw_spi_remove_controller, "SPI_DW_CORE");
1039
1007
1040
-
int dw_spi_suspend_host(struct dw_spi *dws)
1008
+
int dw_spi_suspend_controller(struct dw_spi *dws)
1041
1009
{
1042
1010
int ret;
1043
1011
1044
-
ret = spi_controller_suspend(dws->host);
1012
+
ret = spi_controller_suspend(dws->ctlr);
1045
1013
if (ret)
1046
1014
return ret;
1047
1015
1048
1016
dw_spi_shutdown_chip(dws);
1049
1017
return 0;
1050
1018
}
1051
-
EXPORT_SYMBOL_NS_GPL(dw_spi_suspend_host, "SPI_DW_CORE");
1019
+
EXPORT_SYMBOL_NS_GPL(dw_spi_suspend_controller, "SPI_DW_CORE");
1052
1020
1053
-
int dw_spi_resume_host(struct dw_spi *dws)
1021
+
int dw_spi_resume_controller(struct dw_spi *dws)
1054
1022
{
1055
-
dw_spi_hw_init(&dws->host->dev, dws);
1056
-
return spi_controller_resume(dws->host);
1023
+
dw_spi_hw_init(&dws->ctlr->dev, dws);
1024
+
return spi_controller_resume(dws->ctlr);
1057
1025
}
1058
-
EXPORT_SYMBOL_NS_GPL(dw_spi_resume_host, "SPI_DW_CORE");
1026
+
EXPORT_SYMBOL_NS_GPL(dw_spi_resume_controller, "SPI_DW_CORE");
1059
1027
1060
1028
MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
1061
1029
MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
+11
-11
drivers/spi/spi-dw-dma.c
+11
-11
drivers/spi/spi-dw-dma.c
···
139
139
if (!dws->txchan)
140
140
goto free_rxchan;
141
141
142
-
dws->host->dma_rx = dws->rxchan;
143
-
dws->host->dma_tx = dws->txchan;
142
+
dws->ctlr->dma_rx = dws->rxchan;
143
+
dws->ctlr->dma_tx = dws->txchan;
144
144
145
145
init_completion(&dws->dma_completion);
146
146
···
183
183
goto free_rxchan;
184
184
}
185
185
186
-
dws->host->dma_rx = dws->rxchan;
187
-
dws->host->dma_tx = dws->txchan;
186
+
dws->ctlr->dma_rx = dws->rxchan;
187
+
dws->ctlr->dma_tx = dws->txchan;
188
188
189
189
init_completion(&dws->dma_completion);
190
190
···
242
242
}
243
243
}
244
244
245
-
static bool dw_spi_can_dma(struct spi_controller *host,
245
+
static bool dw_spi_can_dma(struct spi_controller *ctlr,
246
246
struct spi_device *spi, struct spi_transfer *xfer)
247
247
{
248
-
struct dw_spi *dws = spi_controller_get_devdata(host);
248
+
struct dw_spi *dws = spi_controller_get_devdata(ctlr);
249
249
enum dma_slave_buswidth dma_bus_width;
250
250
251
251
if (xfer->len <= dws->fifo_len)
···
271
271
msecs_to_jiffies(ms));
272
272
273
273
if (ms == 0) {
274
-
dev_err(&dws->host->cur_msg->spi->dev,
274
+
dev_err(&dws->ctlr->cur_msg->spi->dev,
275
275
"DMA transaction timed out\n");
276
276
return -ETIMEDOUT;
277
277
}
···
299
299
spi_delay_exec(&delay, xfer);
300
300
301
301
if (retry < 0) {
302
-
dev_err(&dws->host->dev, "Tx hanged up\n");
302
+
dev_err(&dws->ctlr->dev, "Tx hanged up\n");
303
303
return -EIO;
304
304
}
305
305
···
400
400
spi_delay_exec(&delay, NULL);
401
401
402
402
if (retry < 0) {
403
-
dev_err(&dws->host->dev, "Rx hanged up\n");
403
+
dev_err(&dws->ctlr->dev, "Rx hanged up\n");
404
404
return -EIO;
405
405
}
406
406
···
656
656
if (ret)
657
657
return ret;
658
658
659
-
if (dws->host->cur_msg->status == -EINPROGRESS) {
659
+
if (dws->ctlr->cur_msg->status == -EINPROGRESS) {
660
660
ret = dw_spi_dma_wait_tx_done(dws, xfer);
661
661
if (ret)
662
662
return ret;
663
663
}
664
664
665
-
if (xfer->rx_buf && dws->host->cur_msg->status == -EINPROGRESS)
665
+
if (xfer->rx_buf && dws->ctlr->cur_msg->status == -EINPROGRESS)
666
666
ret = dw_spi_dma_wait_rx_done(dws);
667
667
668
668
return ret;
+2
-7
drivers/spi/spi-dw-mmio.c
+2
-7
drivers/spi/spi-dw-mmio.c
···
321
321
struct dw_spi *dws;
322
322
int ret;
323
323
324
-
if (device_property_read_bool(&pdev->dev, "spi-slave")) {
325
-
dev_warn(&pdev->dev, "spi-slave is not yet supported\n");
326
-
return -ENODEV;
327
-
}
328
-
329
324
dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
330
325
GFP_KERNEL);
331
326
if (!dwsmmio)
···
377
382
378
383
pm_runtime_enable(&pdev->dev);
379
384
380
-
ret = dw_spi_add_host(&pdev->dev, dws);
385
+
ret = dw_spi_add_controller(&pdev->dev, dws);
381
386
if (ret)
382
387
goto out;
383
388
···
396
401
{
397
402
struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
398
403
399
-
dw_spi_remove_host(&dwsmmio->dws);
404
+
dw_spi_remove_controller(&dwsmmio->dws);
400
405
pm_runtime_disable(&pdev->dev);
401
406
reset_control_assert(dwsmmio->rstc);
402
407
}
+4
-4
drivers/spi/spi-dw-pci.c
+4
-4
drivers/spi/spi-dw-pci.c
···
127
127
goto err_free_irq_vectors;
128
128
}
129
129
130
-
ret = dw_spi_add_host(&pdev->dev, dws);
130
+
ret = dw_spi_add_controller(&pdev->dev, dws);
131
131
if (ret)
132
132
goto err_free_irq_vectors;
133
133
···
156
156
pm_runtime_forbid(&pdev->dev);
157
157
pm_runtime_get_noresume(&pdev->dev);
158
158
159
-
dw_spi_remove_host(dws);
159
+
dw_spi_remove_controller(dws);
160
160
pci_free_irq_vectors(pdev);
161
161
}
162
162
···
165
165
{
166
166
struct dw_spi *dws = dev_get_drvdata(dev);
167
167
168
-
return dw_spi_suspend_host(dws);
168
+
return dw_spi_suspend_controller(dws);
169
169
}
170
170
171
171
static int dw_spi_pci_resume(struct device *dev)
172
172
{
173
173
struct dw_spi *dws = dev_get_drvdata(dev);
174
174
175
-
return dw_spi_resume_host(dws);
175
+
return dw_spi_resume_controller(dws);
176
176
}
177
177
#endif
178
178
+6
-6
drivers/spi/spi-dw.h
+6
-6
drivers/spi/spi-dw.h
···
142
142
int (*dma_init)(struct device *dev, struct dw_spi *dws);
143
143
void (*dma_exit)(struct dw_spi *dws);
144
144
int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
145
-
bool (*can_dma)(struct spi_controller *host, struct spi_device *spi,
145
+
bool (*can_dma)(struct spi_controller *ctlr, struct spi_device *spi,
146
146
struct spi_transfer *xfer);
147
147
int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
148
148
void (*dma_stop)(struct dw_spi *dws);
149
149
};
150
150
151
151
struct dw_spi {
152
-
struct spi_controller *host;
152
+
struct spi_controller *ctlr;
153
153
154
154
u32 ip; /* Synopsys DW SSI IP-core ID */
155
155
u32 ver; /* Synopsys component version */
···
288
288
extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
289
289
struct dw_spi_cfg *cfg);
290
290
extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
291
-
extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
292
-
extern void dw_spi_remove_host(struct dw_spi *dws);
293
-
extern int dw_spi_suspend_host(struct dw_spi *dws);
294
-
extern int dw_spi_resume_host(struct dw_spi *dws);
291
+
extern int dw_spi_add_controller(struct device *dev, struct dw_spi *dws);
292
+
extern void dw_spi_remove_controller(struct dw_spi *dws);
293
+
extern int dw_spi_suspend_controller(struct dw_spi *dws);
294
+
extern int dw_spi_resume_controller(struct dw_spi *dws);
295
295
296
296
#ifdef CONFIG_SPI_DW_DMA
297
297