Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: qat - add firmware headers for GEN6 devices
Add firmware headers related to compression that define macros for
building the hardware configuration word, along with bitfields related
to algorithm settings.
Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Suman Kumar Chakraborty
and committed by
Herbert Xu
942028bc
f14a2de5
+417
+99
drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h
+99
drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp.h
···
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+
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2025 Intel Corporation */
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#ifndef ICP_QAT_HW_51_COMP_H_
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#define ICP_QAT_HW_51_COMP_H_
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#include <linux/types.h>
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#include "icp_qat_fw.h"
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#include "icp_qat_hw_51_comp_defs.h"
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struct icp_qat_hw_comp_51_config_csr_lower {
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enum icp_qat_hw_comp_51_abd abd;
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enum icp_qat_hw_comp_51_lllbd_ctrl lllbd;
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enum icp_qat_hw_comp_51_search_depth sd;
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enum icp_qat_hw_comp_51_min_match_control mmctrl;
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enum icp_qat_hw_comp_51_lz4_block_checksum lbc;
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};
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static inline u32
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ICP_QAT_FW_COMP_51_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_51_config_csr_lower csr)
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{
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u32 val32 = 0;
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QAT_FIELD_SET(val32, csr.abd,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_BITPOS,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_MASK);
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QAT_FIELD_SET(val32, csr.lllbd,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_BITPOS,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_MASK);
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QAT_FIELD_SET(val32, csr.sd,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_BITPOS,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_MASK);
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QAT_FIELD_SET(val32, csr.mmctrl,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
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QAT_FIELD_SET(val32, csr.lbc,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_BITPOS,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_MASK);
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return val32;
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}
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struct icp_qat_hw_comp_51_config_csr_upper {
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enum icp_qat_hw_comp_51_dmm_algorithm edmm;
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enum icp_qat_hw_comp_51_bms bms;
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enum icp_qat_hw_comp_51_scb_mode_reset_mask scb_mode_reset;
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};
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static inline u32
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ICP_QAT_FW_COMP_51_BUILD_CONFIG_UPPER(struct icp_qat_hw_comp_51_config_csr_upper csr)
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{
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u32 val32 = 0;
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QAT_FIELD_SET(val32, csr.edmm,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_BITPOS,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_MASK);
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QAT_FIELD_SET(val32, csr.bms,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_BITPOS,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_MASK);
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QAT_FIELD_SET(val32, csr.scb_mode_reset,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS,
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ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK);
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return val32;
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}
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struct icp_qat_hw_decomp_51_config_csr_lower {
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enum icp_qat_hw_decomp_51_lz4_block_checksum lbc;
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};
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static inline u32
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ICP_QAT_FW_DECOMP_51_BUILD_CONFIG_LOWER(struct icp_qat_hw_decomp_51_config_csr_lower csr)
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{
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u32 val32 = 0;
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QAT_FIELD_SET(val32, csr.lbc,
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ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_BITPOS,
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ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_MASK);
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return val32;
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}
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struct icp_qat_hw_decomp_51_config_csr_upper {
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enum icp_qat_hw_decomp_51_bms bms;
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};
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static inline u32
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ICP_QAT_FW_DECOMP_51_BUILD_CONFIG_UPPER(struct icp_qat_hw_decomp_51_config_csr_upper csr)
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{
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u32 val32 = 0;
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QAT_FIELD_SET(val32, csr.bms,
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ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_BITPOS,
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ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_MASK);
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return val32;
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}
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#endif /* ICP_QAT_HW_51_COMP_H_ */
+318
drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h
+318
drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h
···
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2025 Intel Corporation */
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#ifndef ICP_QAT_HW_51_COMP_DEFS_H_
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#define ICP_QAT_HW_51_COMP_DEFS_H_
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#include <linux/bits.h>
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_BITPOS 28
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_MASK GENMASK(1, 0)
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enum icp_qat_hw_comp_51_som_control {
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ICP_QAT_HW_COMP_51_SOM_CONTROL_NORMAL_MODE = 0x0,
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ICP_QAT_HW_COMP_51_SOM_CONTROL_DICTIONARY_MODE = 0x1,
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ICP_QAT_HW_COMP_51_SOM_CONTROL_INPUT_CRC = 0x2,
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ICP_QAT_HW_COMP_51_SOM_CONTROL_RESERVED_MODE = 0x3,
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};
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_SOM_CONTROL_NORMAL_MODE
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS 27
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_skip_hash_rd_control {
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ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_NO_SKIP = 0x0,
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ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_SKIP_HASH_READS = 0x1,
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};
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_NO_SKIP
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_BITPOS 25
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_bypass_compression {
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ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_DISABLED = 0x0,
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ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_ENABLED = 0x1,
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};
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_DISABLED
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_BITPOS 22
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_dmm_algorithm {
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ICP_QAT_HW_COMP_51_DMM_ALGORITHM_EDMM_ENABLED = 0x0,
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ICP_QAT_HW_COMP_51_DMM_ALGORITHM_ZSTD_DMM_LITE = 0x1,
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};
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_DMM_ALGORITHM_EDMM_ENABLED
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_BITPOS 21
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_token_fusion_internal_only {
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ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_ENABLED = 0x0,
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ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_DISABLED = 0x1,
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};
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_ENABLED
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_BITPOS 19
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_MASK GENMASK(1, 0)
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enum icp_qat_hw_comp_51_bms {
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ICP_QAT_HW_COMP_51_BMS_BMS_64KB = 0x0,
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ICP_QAT_HW_COMP_51_BMS_BMS_256KB = 0x1,
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ICP_QAT_HW_COMP_51_BMS_BMS_1MB = 0x2,
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ICP_QAT_HW_COMP_51_BMS_BMS_4MB = 0x3,
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};
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_BMS_BMS_64KB
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS 18
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_scb_mode_reset_mask {
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ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_DO_NOT_RESET_HB_HT = 0x0,
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ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_RESET_HB_HT = 0x1,
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};
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_DO_NOT_RESET_HB_HT
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_BITPOS 2
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_zstd_frame_gen_dec_en {
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ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_DISABLE = 0x0,
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ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE = 0x1,
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};
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_BITPOS 1
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_cnv_disable {
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ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_ENABLED = 0x0,
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ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_DISABLED = 0x1,
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};
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_ENABLED
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ASB_DISABLE_BITPOS 0
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ASB_DISABLE_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_asb_disable {
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ICP_QAT_HW_COMP_51_ASB_DISABLE_ASB_ENABLED = 0x0,
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ICP_QAT_HW_COMP_51_ASB_DISABLE_ASB_DISABLED = 0x1,
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};
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ASB_DISABLE_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_ASB_DISABLE_ASB_ENABLED
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_BITPOS 21
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_spec_decoder_internal_only {
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ICP_QAT_HW_COMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL = 0x0,
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ICP_QAT_HW_COMP_51_SPEC_DECODER_INTERNAL_ONLY_DISABLED = 0x1,
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};
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_BITPOS 20
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_mini_xcam_internal_only {
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ICP_QAT_HW_COMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL = 0x0,
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ICP_QAT_HW_COMP_51_MINI_XCAM_INTERNAL_ONLY_DISABLED = 0x1,
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};
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+
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_REP_OFF_ENC_INTERNAL_ONLY_BITPOS 19
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_REP_OFF_ENC_INTERNAL_ONLY_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_rep_off_enc_internal_only {
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ICP_QAT_HW_COMP_51_REP_OFF_ENC_INTERNAL_ONLY_ENABLED = 0x0,
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ICP_QAT_HW_COMP_51_REP_OFF_ENC_INTERNAL_ONLY_DISABLED = 0x1,
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};
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+
127
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_REP_OFF_ENC_INTERNAL_ONLY_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_REP_OFF_ENC_INTERNAL_ONLY_ENABLED
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_PROG_BLOCK_DROP_INTERNAL_ONLY_BITPOS 18
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_PROG_BLOCK_DROP_INTERNAL_ONLY_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_prog_block_drop_internal_only {
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ICP_QAT_HW_COMP_51_PROG_BLOCK_DROP_INTERNAL_ONLY_DISABLE = 0x0,
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ICP_QAT_HW_COMP_51_PROG_BLOCK_DROP_INTERNAL_ONLY_ENABLE = 0x1,
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};
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+
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_PROG_BLOCK_DROP_INTERNAL_ONLY_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_PROG_BLOCK_DROP_INTERNAL_ONLY_DISABLE
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_BITPOS 17
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_skip_hash_override_internal_only {
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ICP_QAT_HW_COMP_51_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_DETERMINE_HASH_PARAMS = 0x0,
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ICP_QAT_HW_COMP_51_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_OVERRIDE_HASH_PARAMS = 0x1,
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};
144
+
145
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_DETERMINE_HASH_PARAMS
147
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_HBS_BITPOS 14
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_HBS_MASK GENMASK(2, 0)
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enum icp_qat_hw_comp_51_hbs {
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ICP_QAT_HW_COMP_51_HBS_32KB = 0x0,
151
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ICP_QAT_HW_COMP_51_HBS_64KB = 0x1,
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+
};
153
+
154
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_HBS_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_HBS_32KB
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_BITPOS 13
157
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_MASK GENMASK(0, 0)
158
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enum icp_qat_hw_comp_51_abd {
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ICP_QAT_HW_COMP_51_ABD_ABD_ENABLED = 0x0,
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ICP_QAT_HW_COMP_51_ABD_ABD_DISABLED = 0x1,
161
+
};
162
+
163
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_ABD_ABD_ENABLED
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_BITPOS 12
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_MASK GENMASK(0, 0)
167
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enum icp_qat_hw_comp_51_lllbd_ctrl {
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ICP_QAT_HW_COMP_51_LLLBD_CTRL_LLLBD_ENABLED = 0x0,
169
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ICP_QAT_HW_COMP_51_LLLBD_CTRL_LLLBD_DISABLED = 0x1,
170
+
};
171
+
172
+
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_LLLBD_CTRL_LLLBD_ENABLED
174
+
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_BITPOS 8
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_MASK GENMASK(3, 0)
176
+
enum icp_qat_hw_comp_51_search_depth {
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+
ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_1 = 0x1,
178
+
ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_6 = 0x3,
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+
ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_9 = 0x4,
180
+
ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_10 = 0x4,
181
+
};
182
+
183
+
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_1
185
+
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_FORMAT_BITPOS 5
186
+
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_FORMAT_MASK GENMASK(2, 0)
187
+
enum icp_qat_hw_comp_51_format {
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+
ICP_QAT_HW_COMP_51_FORMAT_ILZ77 = 0x1,
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+
ICP_QAT_HW_COMP_51_FORMAT_LZ4 = 0x2,
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+
ICP_QAT_HW_COMP_51_FORMAT_LZ4s = 0x3,
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+
ICP_QAT_HW_COMP_51_FORMAT_ZSTD = 0x4,
192
+
};
193
+
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+
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_FORMAT_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_FORMAT_ILZ77
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS 4
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_min_match_control {
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ICP_QAT_HW_COMP_51_MIN_MATCH_CONTROL_MATCH_3B = 0x0,
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ICP_QAT_HW_COMP_51_MIN_MATCH_CONTROL_MATCH_4B = 0x1,
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+
};
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+
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_MIN_MATCH_CONTROL_MATCH_3B
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS 3
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_COLLISION_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_skip_hash_collision {
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ICP_QAT_HW_COMP_51_SKIP_HASH_COLLISION_ALLOW = 0x0,
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ICP_QAT_HW_COMP_51_SKIP_HASH_COLLISION_DONT_ALLOW = 0x1,
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};
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+
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_COLLISION_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_SKIP_HASH_COLLISION_ALLOW
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS 2
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_UPDATE_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_skip_hash_update {
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ICP_QAT_HW_COMP_51_SKIP_HASH_UPDATE_ALLOW = 0x0,
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ICP_QAT_HW_COMP_51_SKIP_HASH_UPDATE_DONT_ALLOW = 0x1,
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+
};
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+
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_UPDATE_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_SKIP_HASH_UPDATE_ALLOW
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYTE_SKIP_BITPOS 1
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYTE_SKIP_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_byte_skip {
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ICP_QAT_HW_COMP_51_BYTE_SKIP_3BYTE_TOKEN = 0x0,
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ICP_QAT_HW_COMP_51_BYTE_SKIP_3BYTE_LITERAL = 0x1,
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+
};
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+
230
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYTE_SKIP_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_BYTE_SKIP_3BYTE_TOKEN
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_BITPOS 0
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_MASK GENMASK(0, 0)
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enum icp_qat_hw_comp_51_lz4_block_checksum {
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ICP_QAT_HW_COMP_51_LZ4_BLOCK_CHECKSUM_ABSENT = 0x0,
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ICP_QAT_HW_COMP_51_LZ4_BLOCK_CHECKSUM_PRESENT = 0x1,
237
+
};
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+
239
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#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_DEFAULT_VAL \
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ICP_QAT_HW_COMP_51_LZ4_BLOCK_CHECKSUM_ABSENT
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+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_DISCARD_DATA_BITPOS 26
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#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_DISCARD_DATA_MASK GENMASK(0, 0)
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enum icp_qat_hw_decomp_51_discard_data {
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ICP_QAT_HW_DECOMP_51_DISCARD_DATA_DISABLED = 0x0,
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ICP_QAT_HW_DECOMP_51_DISCARD_DATA_ENABLED = 0x1,
246
+
};
247
+
248
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_DISCARD_DATA_DEFAULT_VAL \
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ICP_QAT_HW_DECOMP_51_DISCARD_DATA_DISABLED
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+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_BITPOS 19
251
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_MASK GENMASK(1, 0)
252
+
enum icp_qat_hw_decomp_51_bms {
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ICP_QAT_HW_DECOMP_51_BMS_BMS_64KB = 0x0,
254
+
ICP_QAT_HW_DECOMP_51_BMS_BMS_256KB = 0x1,
255
+
ICP_QAT_HW_DECOMP_51_BMS_BMS_1MB = 0x2,
256
+
ICP_QAT_HW_DECOMP_51_BMS_BMS_4MB = 0x3,
257
+
};
258
+
259
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_DEFAULT_VAL \
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+
ICP_QAT_HW_DECOMP_51_BMS_BMS_64KB
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+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_BITPOS 2
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+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_MASK GENMASK(0, 0)
263
+
enum icp_qat_hw_decomp_51_zstd_frame_gen_dec_en {
264
+
ICP_QAT_HW_DECOMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_DISABLE = 0x0,
265
+
ICP_QAT_HW_DECOMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE = 0x1,
266
+
};
267
+
268
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_DEFAULT_VAL \
269
+
ICP_QAT_HW_DECOMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE
270
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_BITPOS 21
271
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_MASK GENMASK(0, 0)
272
+
enum icp_qat_hw_decomp_51_spec_decoder_internal_only {
273
+
ICP_QAT_HW_DECOMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL = 0x0,
274
+
ICP_QAT_HW_DECOMP_51_SPEC_DECODER_INTERNAL_ONLY_DISABLED = 0x1,
275
+
};
276
+
277
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_DEFAULT_VAL \
278
+
ICP_QAT_HW_DECOMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL
279
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_BITPOS 20
280
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_MASK GENMASK(0, 0)
281
+
enum icp_qat_hw_decomp_51_mini_xcam_internal_only {
282
+
ICP_QAT_HW_DECOMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL = 0x0,
283
+
ICP_QAT_HW_DECOMP_51_MINI_XCAM_INTERNAL_ONLY_DISABLED = 0x1,
284
+
};
285
+
286
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_DEFAULT_VAL \
287
+
ICP_QAT_HW_DECOMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL
288
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_HBS_BITPOS 14
289
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_HBS_MASK GENMASK(2, 0)
290
+
enum icp_qat_hw_decomp_51_hbs {
291
+
ICP_QAT_HW_DECOMP_51_HBS_32KB = 0x0,
292
+
ICP_QAT_HW_DECOMP_51_HBS_64KB = 0x1,
293
+
};
294
+
295
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_HBS_DEFAULT_VAL \
296
+
ICP_QAT_HW_DECOMP_51_HBS_32KB
297
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_FORMAT_BITPOS 5
298
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_FORMAT_MASK GENMASK(2, 0)
299
+
enum icp_qat_hw_decomp_51_format {
300
+
ICP_QAT_HW_DECOMP_51_FORMAT_ILZ77 = 0x1,
301
+
ICP_QAT_HW_DECOMP_51_FORMAT_LZ4 = 0x2,
302
+
ICP_QAT_HW_DECOMP_51_FORMAT_RESERVED = 0x3,
303
+
ICP_QAT_HW_DECOMP_51_FORMAT_ZSTD = 0x4,
304
+
};
305
+
306
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_FORMAT_DEFAULT_VAL \
307
+
ICP_QAT_HW_DECOMP_51_FORMAT_ILZ77
308
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_BITPOS 0
309
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_MASK GENMASK(0, 0)
310
+
enum icp_qat_hw_decomp_51_lz4_block_checksum {
311
+
ICP_QAT_HW_DECOMP_51_LZ4_BLOCK_CHECKSUM_ABSENT = 0x0,
312
+
ICP_QAT_HW_DECOMP_51_LZ4_BLOCK_CHECKSUM_PRESENT = 0x1,
313
+
};
314
+
315
+
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_DEFAULT_VAL \
316
+
ICP_QAT_HW_DECOMP_51_LZ4_BLOCK_CHECKSUM_ABSENT
317
+
318
+
#endif /* ICP_QAT_HW_51_COMP_DEFS_H_ */