Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/powerplay: cover the powerplay implementation details V3
This can save users much troubles. As they do not
actually need to care whether swSMU or traditional
powerplay routine should be used.
V2: apply the fixes to vi.c and cik.c also
V3: squash in oops fix
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Evan Quan
and committed by
Alex Deucher
9530273e
a434b94c
+212
-208
+3
-9
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+3
-9
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
···
613
613
{
614
614
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
615
615
616
-
if (is_support_sw_smu(adev))
617
-
smu_switch_power_profile(&adev->smu,
618
-
PP_SMC_POWER_PROFILE_COMPUTE,
619
-
!idle);
620
-
else if (adev->powerplay.pp_funcs &&
621
-
adev->powerplay.pp_funcs->switch_power_profile)
622
-
amdgpu_dpm_switch_power_profile(adev,
623
-
PP_SMC_POWER_PROFILE_COMPUTE,
624
-
!idle);
616
+
amdgpu_dpm_switch_power_profile(adev,
617
+
PP_SMC_POWER_PROFILE_COMPUTE,
618
+
!idle);
625
619
}
626
620
627
621
bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
+6
-47
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+6
-47
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
2345
2345
adev->ip_blocks[i].status.hw = false;
2346
2346
/* handle putting the SMC in the appropriate state */
2347
2347
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2348
-
if (is_support_sw_smu(adev)) {
2349
-
r = smu_set_mp1_state(&adev->smu, adev->mp1_state);
2350
-
} else if (adev->powerplay.pp_funcs &&
2351
-
adev->powerplay.pp_funcs->set_mp1_state) {
2352
-
r = adev->powerplay.pp_funcs->set_mp1_state(
2353
-
adev->powerplay.pp_handle,
2354
-
adev->mp1_state);
2355
-
}
2348
+
r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
2356
2349
if (r) {
2357
2350
DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
2358
2351
adev->mp1_state, r);
···
4352
4359
if (ras && ras->supported)
4353
4360
adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
4354
4361
4355
-
if (is_support_sw_smu(adev)) {
4356
-
struct smu_context *smu = &adev->smu;
4357
-
int ret;
4358
-
4359
-
ret = smu_baco_enter(smu);
4360
-
if (ret)
4361
-
return ret;
4362
-
} else {
4363
-
void *pp_handle = adev->powerplay.pp_handle;
4364
-
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
4365
-
4366
-
if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
4367
-
return -ENOENT;
4368
-
4369
-
/* enter BACO state */
4370
-
if (pp_funcs->set_asic_baco_state(pp_handle, 1))
4371
-
return -EIO;
4372
-
}
4373
-
4374
-
return 0;
4362
+
return amdgpu_dpm_baco_enter(adev);
4375
4363
}
4376
4364
4377
4365
int amdgpu_device_baco_exit(struct drm_device *dev)
4378
4366
{
4379
4367
struct amdgpu_device *adev = dev->dev_private;
4380
4368
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
4369
+
int ret = 0;
4381
4370
4382
4371
if (!amdgpu_device_supports_baco(adev->ddev))
4383
4372
return -ENOTSUPP;
4384
4373
4385
-
if (is_support_sw_smu(adev)) {
4386
-
struct smu_context *smu = &adev->smu;
4387
-
int ret;
4388
-
4389
-
ret = smu_baco_exit(smu);
4390
-
if (ret)
4391
-
return ret;
4392
-
4393
-
} else {
4394
-
void *pp_handle = adev->powerplay.pp_handle;
4395
-
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
4396
-
4397
-
if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
4398
-
return -ENOENT;
4399
-
4400
-
/* exit BACO state */
4401
-
if (pp_funcs->set_asic_baco_state(pp_handle, 0))
4402
-
return -EIO;
4403
-
}
4374
+
ret = amdgpu_dpm_baco_exit(adev);
4375
+
if (ret)
4376
+
return ret;
4404
4377
4405
4378
if (ras && ras->supported)
4406
4379
adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
+160
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+160
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
···
983
983
984
984
return ret;
985
985
}
986
+
987
+
int amdgpu_dpm_baco_enter(struct amdgpu_device *adev)
988
+
{
989
+
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
990
+
void *pp_handle = adev->powerplay.pp_handle;
991
+
struct smu_context *smu = &adev->smu;
992
+
int ret = 0;
993
+
994
+
if (is_support_sw_smu(adev)) {
995
+
ret = smu_baco_enter(smu);
996
+
} else {
997
+
if (!pp_funcs || !pp_funcs->set_asic_baco_state)
998
+
return -ENOENT;
999
+
1000
+
/* enter BACO state */
1001
+
ret = pp_funcs->set_asic_baco_state(pp_handle, 1);
1002
+
}
1003
+
1004
+
return ret;
1005
+
}
1006
+
1007
+
int amdgpu_dpm_baco_exit(struct amdgpu_device *adev)
1008
+
{
1009
+
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1010
+
void *pp_handle = adev->powerplay.pp_handle;
1011
+
struct smu_context *smu = &adev->smu;
1012
+
int ret = 0;
1013
+
1014
+
if (is_support_sw_smu(adev)) {
1015
+
ret = smu_baco_exit(smu);
1016
+
} else {
1017
+
if (!pp_funcs || !pp_funcs->set_asic_baco_state)
1018
+
return -ENOENT;
1019
+
1020
+
/* exit BACO state */
1021
+
ret = pp_funcs->set_asic_baco_state(pp_handle, 0);
1022
+
}
1023
+
1024
+
return ret;
1025
+
}
1026
+
1027
+
int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
1028
+
enum pp_mp1_state mp1_state)
1029
+
{
1030
+
int ret = 0;
1031
+
1032
+
if (is_support_sw_smu(adev)) {
1033
+
ret = smu_set_mp1_state(&adev->smu, mp1_state);
1034
+
} else if (adev->powerplay.pp_funcs &&
1035
+
adev->powerplay.pp_funcs->set_mp1_state) {
1036
+
ret = adev->powerplay.pp_funcs->set_mp1_state(
1037
+
adev->powerplay.pp_handle,
1038
+
mp1_state);
1039
+
}
1040
+
1041
+
return ret;
1042
+
}
1043
+
1044
+
bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev)
1045
+
{
1046
+
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1047
+
void *pp_handle = adev->powerplay.pp_handle;
1048
+
struct smu_context *smu = &adev->smu;
1049
+
bool baco_cap;
1050
+
1051
+
if (is_support_sw_smu(adev)) {
1052
+
return smu_baco_is_support(smu);
1053
+
} else {
1054
+
if (!pp_funcs || !pp_funcs->get_asic_baco_capability)
1055
+
return false;
1056
+
1057
+
if (pp_funcs->get_asic_baco_capability(pp_handle, &baco_cap))
1058
+
return false;
1059
+
1060
+
return baco_cap ? true : false;
1061
+
}
1062
+
}
1063
+
1064
+
int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev)
1065
+
{
1066
+
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1067
+
void *pp_handle = adev->powerplay.pp_handle;
1068
+
struct smu_context *smu = &adev->smu;
1069
+
1070
+
if (is_support_sw_smu(adev)) {
1071
+
return smu_mode2_reset(smu);
1072
+
} else {
1073
+
if (!pp_funcs || !pp_funcs->asic_reset_mode_2)
1074
+
return -ENOENT;
1075
+
1076
+
return pp_funcs->asic_reset_mode_2(pp_handle);
1077
+
}
1078
+
}
1079
+
1080
+
int amdgpu_dpm_baco_reset(struct amdgpu_device *adev)
1081
+
{
1082
+
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
1083
+
void *pp_handle = adev->powerplay.pp_handle;
1084
+
struct smu_context *smu = &adev->smu;
1085
+
int ret = 0;
1086
+
1087
+
dev_info(adev->dev, "GPU BACO reset\n");
1088
+
1089
+
if (is_support_sw_smu(adev)) {
1090
+
ret = smu_baco_enter(smu);
1091
+
if (ret)
1092
+
return ret;
1093
+
1094
+
ret = smu_baco_exit(smu);
1095
+
if (ret)
1096
+
return ret;
1097
+
} else {
1098
+
if (!pp_funcs
1099
+
|| !pp_funcs->set_asic_baco_state)
1100
+
return -ENOENT;
1101
+
1102
+
/* enter BACO state */
1103
+
ret = pp_funcs->set_asic_baco_state(pp_handle, 1);
1104
+
if (ret)
1105
+
return ret;
1106
+
1107
+
/* exit BACO state */
1108
+
ret = pp_funcs->set_asic_baco_state(pp_handle, 0);
1109
+
if (ret)
1110
+
return ret;
1111
+
}
1112
+
1113
+
return 0;
1114
+
}
1115
+
1116
+
int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,
1117
+
enum PP_SMC_POWER_PROFILE type,
1118
+
bool en)
1119
+
{
1120
+
int ret = 0;
1121
+
1122
+
if (is_support_sw_smu(adev))
1123
+
ret = smu_switch_power_profile(&adev->smu, type, en);
1124
+
else if (adev->powerplay.pp_funcs &&
1125
+
adev->powerplay.pp_funcs->switch_power_profile)
1126
+
ret = adev->powerplay.pp_funcs->switch_power_profile(
1127
+
adev->powerplay.pp_handle, type, en);
1128
+
1129
+
return ret;
1130
+
}
1131
+
1132
+
int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
1133
+
uint32_t pstate)
1134
+
{
1135
+
int ret = 0;
1136
+
1137
+
if (is_support_sw_smu_xgmi(adev))
1138
+
ret = smu_set_xgmi_pstate(&adev->smu, pstate);
1139
+
else if (adev->powerplay.pp_funcs &&
1140
+
adev->powerplay.pp_funcs->set_xgmi_pstate)
1141
+
ret = adev->powerplay.pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
1142
+
pstate);
1143
+
1144
+
return ret;
1145
+
}
+20
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+20
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
···
341
341
((adev)->powerplay.pp_funcs->reset_power_profile_state(\
342
342
(adev)->powerplay.pp_handle, request))
343
343
344
-
#define amdgpu_dpm_switch_power_profile(adev, type, en) \
345
-
((adev)->powerplay.pp_funcs->switch_power_profile(\
346
-
(adev)->powerplay.pp_handle, type, en))
347
-
348
344
#define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
349
345
((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
350
346
(adev)->powerplay.pp_handle, msg_id))
···
512
516
extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low);
513
517
514
518
extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low);
519
+
520
+
int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
521
+
uint32_t pstate);
522
+
523
+
int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,
524
+
enum PP_SMC_POWER_PROFILE type,
525
+
bool en);
526
+
527
+
int amdgpu_dpm_baco_reset(struct amdgpu_device *adev);
528
+
529
+
int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev);
530
+
531
+
bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev);
532
+
533
+
int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
534
+
enum pp_mp1_state mp1_state);
535
+
536
+
int amdgpu_dpm_baco_exit(struct amdgpu_device *adev);
537
+
538
+
int amdgpu_dpm_baco_enter(struct amdgpu_device *adev);
515
539
516
540
#endif
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
···
543
543
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
544
544
return;
545
545
546
-
if (!is_support_sw_smu(adev) &&
547
-
(!adev->powerplay.pp_funcs ||
548
-
!adev->powerplay.pp_funcs->set_powergating_by_smu))
549
-
return;
550
-
551
-
552
546
mutex_lock(&adev->gfx.gfx_off_mutex);
553
547
554
548
if (!enable)
+1
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+1
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
···
291
291
292
292
dev_dbg(adev->dev, "Set xgmi pstate %d.\n", pstate);
293
293
294
-
if (is_support_sw_smu_xgmi(adev))
295
-
ret = smu_set_xgmi_pstate(&adev->smu, pstate);
296
-
else if (adev->powerplay.pp_funcs &&
297
-
adev->powerplay.pp_funcs->set_xgmi_pstate)
298
-
ret = adev->powerplay.pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
299
-
pstate);
300
-
294
+
ret = amdgpu_dpm_set_xgmi_pstate(adev, pstate);
301
295
if (ret) {
302
296
dev_err(adev->dev,
303
297
"XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
+3
-9
drivers/gpu/drm/amd/amdgpu/cik.c
+3
-9
drivers/gpu/drm/amd/amdgpu/cik.c
···
1312
1312
1313
1313
static bool cik_asic_supports_baco(struct amdgpu_device *adev)
1314
1314
{
1315
-
bool baco_support;
1316
-
1317
1315
switch (adev->asic_type) {
1318
1316
case CHIP_BONAIRE:
1319
1317
case CHIP_HAWAII:
1320
-
smu7_asic_get_baco_capability(adev, &baco_support);
1321
-
break;
1318
+
return amdgpu_dpm_is_baco_supported(adev);
1322
1319
default:
1323
-
baco_support = false;
1324
-
break;
1320
+
return false;
1325
1321
}
1326
-
1327
-
return baco_support;
1328
1322
}
1329
1323
1330
1324
static enum amd_reset_method
···
1360
1366
if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
1361
1367
if (!adev->in_suspend)
1362
1368
amdgpu_inc_vram_lost(adev);
1363
-
r = smu7_asic_baco_reset(adev);
1369
+
r = amdgpu_dpm_baco_reset(adev);
1364
1370
} else {
1365
1371
r = cik_asic_pci_config_reset(adev);
1366
1372
}
-2
drivers/gpu/drm/amd/amdgpu/cik.h
-2
drivers/gpu/drm/amd/amdgpu/cik.h
+4
-4
drivers/gpu/drm/amd/amdgpu/nv.c
+4
-4
drivers/gpu/drm/amd/amdgpu/nv.c
···
478
478
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
479
479
amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
480
480
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
481
-
is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
481
+
!amdgpu_sriov_vf(adev))
482
482
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
483
483
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
484
484
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
···
489
489
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
490
490
amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
491
491
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
492
-
is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
492
+
!amdgpu_sriov_vf(adev))
493
493
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
494
494
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
495
495
amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
···
502
502
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
503
503
amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
504
504
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
505
-
is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
505
+
!amdgpu_sriov_vf(adev))
506
506
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
507
507
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
508
508
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
···
513
513
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
514
514
amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
515
515
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
516
-
is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
516
+
!amdgpu_sriov_vf(adev))
517
517
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
518
518
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
519
519
amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
+11
-74
drivers/gpu/drm/amd/amdgpu/soc15.c
+11
-74
drivers/gpu/drm/amd/amdgpu/soc15.c
···
479
479
return ret;
480
480
}
481
481
482
-
static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
483
-
{
484
-
if (is_support_sw_smu(adev)) {
485
-
struct smu_context *smu = &adev->smu;
486
-
487
-
*cap = smu_baco_is_support(smu);
488
-
return 0;
489
-
} else {
490
-
void *pp_handle = adev->powerplay.pp_handle;
491
-
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
492
-
493
-
if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
494
-
*cap = false;
495
-
return -ENOENT;
496
-
}
497
-
498
-
return pp_funcs->get_asic_baco_capability(pp_handle, cap);
499
-
}
500
-
}
501
-
502
482
static int soc15_asic_baco_reset(struct amdgpu_device *adev)
503
483
{
504
484
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
485
+
int ret = 0;
505
486
506
487
/* avoid NBIF got stuck when do RAS recovery in BACO reset */
507
488
if (ras && ras->supported)
508
489
adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
509
490
510
-
dev_info(adev->dev, "GPU BACO reset\n");
511
-
512
-
if (is_support_sw_smu(adev)) {
513
-
struct smu_context *smu = &adev->smu;
514
-
int ret;
515
-
516
-
ret = smu_baco_enter(smu);
517
-
if (ret)
518
-
return ret;
519
-
520
-
ret = smu_baco_exit(smu);
521
-
if (ret)
522
-
return ret;
523
-
} else {
524
-
void *pp_handle = adev->powerplay.pp_handle;
525
-
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
526
-
527
-
if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
528
-
return -ENOENT;
529
-
530
-
/* enter BACO state */
531
-
if (pp_funcs->set_asic_baco_state(pp_handle, 1))
532
-
return -EIO;
533
-
534
-
/* exit BACO state */
535
-
if (pp_funcs->set_asic_baco_state(pp_handle, 0))
536
-
return -EIO;
537
-
}
491
+
ret = amdgpu_dpm_baco_reset(adev);
492
+
if (ret)
493
+
return ret;
538
494
539
495
/* re-enable doorbell interrupt after BACO exit */
540
496
if (ras && ras->supported)
541
497
adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
542
498
543
499
return 0;
544
-
}
545
-
546
-
static int soc15_mode2_reset(struct amdgpu_device *adev)
547
-
{
548
-
if (is_support_sw_smu(adev))
549
-
return smu_mode2_reset(&adev->smu);
550
-
if (!adev->powerplay.pp_funcs ||
551
-
!adev->powerplay.pp_funcs->asic_reset_mode_2)
552
-
return -ENOENT;
553
-
554
-
return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle);
555
500
}
556
501
557
502
static enum amd_reset_method
···
512
567
case CHIP_VEGA10:
513
568
case CHIP_VEGA12:
514
569
case CHIP_ARCTURUS:
515
-
soc15_asic_get_baco_capability(adev, &baco_reset);
570
+
baco_reset = amdgpu_dpm_is_baco_supported(adev);
516
571
break;
517
572
case CHIP_VEGA20:
518
573
if (adev->psp.sos_fw_version >= 0x80067)
519
-
soc15_asic_get_baco_capability(adev, &baco_reset);
574
+
baco_reset = amdgpu_dpm_is_baco_supported(adev);
520
575
521
576
/*
522
577
* 1. PMFW version > 0x284300: all cases use baco
···
543
598
amdgpu_inc_vram_lost(adev);
544
599
return soc15_asic_baco_reset(adev);
545
600
case AMD_RESET_METHOD_MODE2:
546
-
return soc15_mode2_reset(adev);
601
+
return amdgpu_dpm_mode2_reset(adev);
547
602
default:
548
603
if (!adev->in_suspend)
549
604
amdgpu_inc_vram_lost(adev);
···
553
608
554
609
static bool soc15_supports_baco(struct amdgpu_device *adev)
555
610
{
556
-
bool baco_support;
557
-
558
611
switch (adev->asic_type) {
559
612
case CHIP_VEGA10:
560
613
case CHIP_VEGA12:
561
614
case CHIP_ARCTURUS:
562
-
soc15_asic_get_baco_capability(adev, &baco_support);
563
-
break;
615
+
return amdgpu_dpm_is_baco_supported(adev);
564
616
case CHIP_VEGA20:
565
617
if (adev->psp.sos_fw_version >= 0x80067)
566
-
soc15_asic_get_baco_capability(adev, &baco_support);
567
-
else
568
-
baco_support = false;
569
-
break;
618
+
return amdgpu_dpm_is_baco_supported(adev);
619
+
return false;
570
620
default:
571
621
return false;
572
622
}
573
-
574
-
return baco_support;
575
623
}
576
624
577
625
/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
···
784
846
amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
785
847
if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
786
848
amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
787
-
if (is_support_sw_smu(adev))
788
-
amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
849
+
amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
789
850
amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
790
851
amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
791
852
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+4
-44
drivers/gpu/drm/amd/amdgpu/vi.c
+4
-44
drivers/gpu/drm/amd/amdgpu/vi.c
···
689
689
return -EINVAL;
690
690
}
691
691
692
-
int smu7_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
693
-
{
694
-
void *pp_handle = adev->powerplay.pp_handle;
695
-
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
696
-
697
-
if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
698
-
*cap = false;
699
-
return -ENOENT;
700
-
}
701
-
702
-
return pp_funcs->get_asic_baco_capability(pp_handle, cap);
703
-
}
704
-
705
-
int smu7_asic_baco_reset(struct amdgpu_device *adev)
706
-
{
707
-
void *pp_handle = adev->powerplay.pp_handle;
708
-
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
709
-
710
-
if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
711
-
return -ENOENT;
712
-
713
-
/* enter BACO state */
714
-
if (pp_funcs->set_asic_baco_state(pp_handle, 1))
715
-
return -EIO;
716
-
717
-
/* exit BACO state */
718
-
if (pp_funcs->set_asic_baco_state(pp_handle, 0))
719
-
return -EIO;
720
-
721
-
dev_info(adev->dev, "GPU BACO reset\n");
722
-
723
-
return 0;
724
-
}
725
-
726
692
/**
727
693
* vi_asic_pci_config_reset - soft reset GPU
728
694
*
···
713
747
714
748
static bool vi_asic_supports_baco(struct amdgpu_device *adev)
715
749
{
716
-
bool baco_support;
717
-
718
750
switch (adev->asic_type) {
719
751
case CHIP_FIJI:
720
752
case CHIP_TONGA:
···
720
756
case CHIP_POLARIS11:
721
757
case CHIP_POLARIS12:
722
758
case CHIP_TOPAZ:
723
-
smu7_asic_get_baco_capability(adev, &baco_support);
724
-
break;
759
+
return amdgpu_dpm_is_baco_supported(adev);
725
760
default:
726
-
baco_support = false;
727
-
break;
761
+
return false;
728
762
}
729
-
730
-
return baco_support;
731
763
}
732
764
733
765
static enum amd_reset_method
···
738
778
case CHIP_POLARIS11:
739
779
case CHIP_POLARIS12:
740
780
case CHIP_TOPAZ:
741
-
smu7_asic_get_baco_capability(adev, &baco_reset);
781
+
baco_reset = amdgpu_dpm_is_baco_supported(adev);
742
782
break;
743
783
default:
744
784
baco_reset = false;
···
767
807
if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
768
808
if (!adev->in_suspend)
769
809
amdgpu_inc_vram_lost(adev);
770
-
r = smu7_asic_baco_reset(adev);
810
+
r = amdgpu_dpm_baco_reset(adev);
771
811
} else {
772
812
r = vi_asic_pci_config_reset(adev);
773
813
}
-2
drivers/gpu/drm/amd/amdgpu/vi.h
-2
drivers/gpu/drm/amd/amdgpu/vi.h