Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-intel-gt-next-2026-01-16' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
Driver Changes:
- Bump recommended GuC version for DG2 and MTL
- Fix for syzkaller found NULL deref in execbuf (Krzyssztof, Gangmin)
- Use designated initializers in debugfs code (Sebastian)
- Selftest and static checker fixes (Ard, Sk)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patch.msgid.link/aWnzOx78S4Vh38QE@jlahtine-mobl
+75
-52
+17
-20
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+17
-20
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
···
951
951
vma = eb_lookup_vma(eb, eb->exec[i].handle);
952
952
if (IS_ERR(vma)) {
953
953
err = PTR_ERR(vma);
954
-
goto err;
954
+
return err;
955
955
}
956
956
957
957
err = eb_validate_vma(eb, &eb->exec[i], vma);
958
958
if (unlikely(err)) {
959
959
i915_vma_put(vma);
960
-
goto err;
960
+
return err;
961
961
}
962
962
963
963
err = eb_add_vma(eb, ¤t_batch, i, vma);
···
966
966
967
967
if (i915_gem_object_is_userptr(vma->obj)) {
968
968
err = i915_gem_object_userptr_submit_init(vma->obj);
969
-
if (err) {
970
-
if (i + 1 < eb->buffer_count) {
971
-
/*
972
-
* Execbuffer code expects last vma entry to be NULL,
973
-
* since we already initialized this entry,
974
-
* set the next value to NULL or we mess up
975
-
* cleanup handling.
976
-
*/
977
-
eb->vma[i + 1].vma = NULL;
978
-
}
979
-
969
+
if (err)
980
970
return err;
981
-
}
982
971
983
972
eb->vma[i].flags |= __EXEC_OBJECT_USERPTR_INIT;
984
973
eb->args->flags |= __EXEC_USERPTR_USED;
···
975
986
}
976
987
977
988
return 0;
978
-
979
-
err:
980
-
eb->vma[i].vma = NULL;
981
-
return err;
982
989
}
983
990
984
991
static int eb_lock_vmas(struct i915_execbuffer *eb)
···
3360
3375
3361
3376
eb.exec = exec;
3362
3377
eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1);
3363
-
eb.vma[0].vma = NULL;
3378
+
memset(eb.vma, 0, (args->buffer_count + 1) * sizeof(struct eb_vma));
3379
+
3364
3380
eb.batch_pool = NULL;
3365
3381
3366
3382
eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
···
3570
3584
if (err)
3571
3585
return err;
3572
3586
3573
-
/* Allocate extra slots for use by the command parser */
3587
+
/*
3588
+
* Allocate extra slots for use by the command parser.
3589
+
*
3590
+
* Note that this allocation handles two different arrays (the
3591
+
* exec2_list array, and the eventual eb.vma array introduced in
3592
+
* i915_gem_do_execbuffer()), that reside in virtually contiguous
3593
+
* memory. Also note that the allocation intentionally doesn't fill the
3594
+
* area with zeros, because the exec2_list part doesn't need to be, as
3595
+
* it's immediately overwritten by user data a few lines below.
3596
+
* However, the eb.vma part is explicitly zeroed later in
3597
+
* i915_gem_do_execbuffer().
3598
+
*/
3574
3599
exec2_list = kvmalloc_array(count + 2, eb_element_size(),
3575
3600
__GFP_NOWARN | GFP_KERNEL);
3576
3601
if (exec2_list == NULL) {
+2
-2
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+2
-2
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
···
75
75
static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
76
76
{
77
77
static const struct intel_gt_debugfs_file files[] = {
78
-
{ "reset", &reset_fops, NULL },
79
-
{ "steering", &steering_fops },
78
+
{ .name = "reset", .fops = &reset_fops },
79
+
{ .name = "steering", .fops = &steering_fops },
80
80
};
81
81
82
82
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+1
-1
drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.c
+1
-1
drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.c
···
29
29
void intel_gt_engines_debugfs_register(struct intel_gt *gt, struct dentry *root)
30
30
{
31
31
static const struct intel_gt_debugfs_file files[] = {
32
-
{ "engines", &engines_fops },
32
+
{ .name = "engines", .fops = &engines_fops },
33
33
};
34
34
35
35
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+8
-7
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+8
-7
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
···
588
588
void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
589
589
{
590
590
static const struct intel_gt_debugfs_file files[] = {
591
-
{ "drpc", &drpc_fops, NULL },
592
-
{ "frequency", &frequency_fops, NULL },
593
-
{ "forcewake", &fw_domains_fops, NULL },
594
-
{ "forcewake_user", &forcewake_user_fops, NULL},
595
-
{ "llc", &llc_fops, llc_eval },
596
-
{ "rps_boost", &rps_boost_fops, rps_eval },
597
-
{ "perf_limit_reasons", &perf_limit_reasons_fops, perf_limit_reasons_eval },
591
+
{ .name = "drpc", .fops = &drpc_fops },
592
+
{ .name = "frequency", .fops = &frequency_fops },
593
+
{ .name = "forcewake", .fops = &fw_domains_fops },
594
+
{ .name = "forcewake_user", .fops = &forcewake_user_fops},
595
+
{ .name = "llc", .fops = &llc_fops, .eval = llc_eval },
596
+
{ .name = "rps_boost", .fops = &rps_boost_fops, .eval = rps_eval },
597
+
{ .name = "perf_limit_reasons", .fops = &perf_limit_reasons_fops,
598
+
.eval = perf_limit_reasons_eval },
598
599
};
599
600
600
601
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+2
-2
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+2
-2
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
···
293
293
void intel_sseu_debugfs_register(struct intel_gt *gt, struct dentry *root)
294
294
{
295
295
static const struct intel_gt_debugfs_file files[] = {
296
-
{ "sseu_status", &sseu_status_fops, NULL },
297
-
{ "sseu_topology", &sseu_topology_fops, NULL },
296
+
{ .name = "sseu_status", .fops = &sseu_status_fops },
297
+
{ .name = "sseu_topology", .fops = &sseu_topology_fops },
298
298
};
299
299
300
300
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+29
-5
drivers/gpu/drm/i915/gt/selftest_rps.c
+29
-5
drivers/gpu/drm/i915/gt/selftest_rps.c
···
378
378
enum intel_engine_id id;
379
379
struct igt_spinner spin;
380
380
intel_wakeref_t wakeref;
381
+
u32 throttle;
381
382
int err = 0;
382
383
383
384
/*
···
464
463
max = rps_set_check(rps, limit);
465
464
max_dt = ktime_sub(ktime_get(), max_dt);
466
465
466
+
throttle = intel_uncore_read(gt->uncore, intel_gt_perf_limit_reasons_reg(gt));
467
+
throttle &= GT0_PERF_LIMIT_REASONS_MASK;
468
+
467
469
min_dt = ktime_get();
468
470
min = rps_set_check(rps, rps->min_freq);
469
471
min_dt = ktime_sub(ktime_get(), min_dt);
···
482
478
min, max, ktime_to_ns(min_dt), ktime_to_ns(max_dt));
483
479
484
480
if (limit != rps->max_freq) {
485
-
u32 throttle = intel_uncore_read(gt->uncore,
486
-
intel_gt_perf_limit_reasons_reg(gt));
487
-
488
-
pr_warn("%s: GPU throttled with reasons 0x%08x\n",
489
-
engine->name, throttle & GT0_PERF_LIMIT_REASONS_MASK);
481
+
if (throttle)
482
+
pr_warn("%s: GPU throttled with reasons 0x%08x\n",
483
+
engine->name, throttle);
490
484
show_pstate_limits(rps);
491
485
}
492
486
···
1140
1138
struct intel_engine_cs *engine;
1141
1139
enum intel_engine_id id;
1142
1140
struct igt_spinner spin;
1141
+
u32 throttle;
1143
1142
int err = 0;
1144
1143
1145
1144
/*
···
1198
1195
max.freq = rps->max_freq;
1199
1196
max.power = measure_power_at(rps, &max.freq);
1200
1197
1198
+
throttle = intel_uncore_read(gt->uncore, intel_gt_perf_limit_reasons_reg(gt));
1199
+
throttle &= GT0_PERF_LIMIT_REASONS_MASK;
1200
+
1201
1201
min.freq = rps->min_freq;
1202
1202
min.power = measure_power_at(rps, &min.freq);
1203
1203
···
1216
1210
pr_notice("Could not control frequency, ran at [%d:%uMHz, %d:%uMhz]\n",
1217
1211
min.freq, intel_gpu_freq(rps, min.freq),
1218
1212
max.freq, intel_gpu_freq(rps, max.freq));
1213
+
1214
+
if (throttle)
1215
+
pr_warn("%s: GPU throttled with reasons 0x%08x\n",
1216
+
engine->name, throttle);
1219
1217
continue;
1220
1218
}
1221
1219
1222
1220
if (11 * min.power > 10 * max.power) {
1223
1221
pr_err("%s: did not conserve power when setting lower frequency!\n",
1224
1222
engine->name);
1223
+
1224
+
if (throttle)
1225
+
pr_warn("%s: GPU throttled with reasons 0x%08x\n",
1226
+
engine->name, throttle);
1227
+
1225
1228
err = -EINVAL;
1226
1229
break;
1227
1230
}
···
1256
1241
struct intel_engine_cs *engine;
1257
1242
enum intel_engine_id id;
1258
1243
struct igt_spinner spin;
1244
+
u32 throttle;
1259
1245
int err = 0;
1260
1246
1261
1247
/*
···
1309
1293
max.freq = wait_for_freq(rps, rps->max_freq, 500);
1310
1294
max.dt = ktime_sub(ktime_get(), max.dt);
1311
1295
1296
+
throttle = intel_uncore_read(gt->uncore, intel_gt_perf_limit_reasons_reg(gt));
1297
+
throttle &= GT0_PERF_LIMIT_REASONS_MASK;
1298
+
1312
1299
igt_spinner_end(&spin);
1313
1300
1314
1301
min.dt = ktime_get();
···
1327
1308
if (min.freq >= max.freq) {
1328
1309
pr_err("%s: dynamic reclocking of spinner failed\n!",
1329
1310
engine->name);
1311
+
1312
+
if (throttle)
1313
+
pr_warn("%s: GPU throttled with reasons 0x%08x\n",
1314
+
engine->name, throttle);
1315
+
1330
1316
err = -EINVAL;
1331
1317
}
1332
1318
+1
-1
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.c
+1
-1
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.c
···
29
29
void intel_gsc_uc_debugfs_register(struct intel_gsc_uc *gsc_uc, struct dentry *root)
30
30
{
31
31
static const struct intel_gt_debugfs_file files[] = {
32
-
{ "gsc_info", &gsc_info_fops, NULL },
32
+
{ .name = "gsc_info", .fops = &gsc_info_fops },
33
33
};
34
34
35
35
if (!intel_gsc_uc_is_supported(gsc_uc))
+7
-6
drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
+7
-6
drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
···
132
132
void intel_guc_debugfs_register(struct intel_guc *guc, struct dentry *root)
133
133
{
134
134
static const struct intel_gt_debugfs_file files[] = {
135
-
{ "guc_info", &guc_info_fops, NULL },
136
-
{ "guc_registered_contexts", &guc_registered_contexts_fops, NULL },
137
-
{ "guc_slpc_info", &guc_slpc_info_fops, &intel_eval_slpc_support},
138
-
{ "guc_sched_disable_delay_ms", &guc_sched_disable_delay_ms_fops, NULL },
139
-
{ "guc_sched_disable_gucid_threshold", &guc_sched_disable_gucid_threshold_fops,
140
-
NULL },
135
+
{ .name = "guc_info", .fops = &guc_info_fops },
136
+
{ .name = "guc_registered_contexts", .fops = &guc_registered_contexts_fops },
137
+
{ .name = "guc_slpc_info", .fops = &guc_slpc_info_fops,
138
+
.eval = intel_eval_slpc_support },
139
+
{ .name = "guc_sched_disable_delay_ms", .fops = &guc_sched_disable_delay_ms_fops },
140
+
{ .name = "guc_sched_disable_gucid_threshold",
141
+
.fops = &guc_sched_disable_gucid_threshold_fops },
141
142
};
142
143
143
144
if (!intel_guc_is_supported(guc))
+4
-4
drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
+4
-4
drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
···
162
162
struct dentry *root)
163
163
{
164
164
static const struct intel_gt_debugfs_file files[] = {
165
-
{ "guc_log_dump", &guc_log_dump_fops, NULL },
166
-
{ "guc_load_err_log_dump", &guc_load_err_log_dump_fops, NULL },
167
-
{ "guc_log_level", &guc_log_level_fops, NULL },
168
-
{ "guc_log_relay", &guc_log_relay_fops, NULL },
165
+
{ .name = "guc_log_dump", .fops = &guc_log_dump_fops },
166
+
{ .name = "guc_load_err_log_dump", .fops = &guc_load_err_log_dump_fops},
167
+
{ .name = "guc_log_level", .fops = &guc_log_level_fops },
168
+
{ .name = "guc_log_relay", .fops = &guc_log_relay_fops },
169
169
};
170
170
171
171
if (!intel_guc_is_supported(log_to_guc(log)))
+1
-1
drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.c
+1
-1
drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.c
···
26
26
void intel_huc_debugfs_register(struct intel_huc *huc, struct dentry *root)
27
27
{
28
28
static const struct intel_gt_debugfs_file files[] = {
29
-
{ "huc_info", &huc_info_fops, NULL },
29
+
{ .name = "huc_info", .fops = &huc_info_fops },
30
30
};
31
31
32
32
if (!intel_huc_is_supported(huc))
+1
-1
drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
+1
-1
drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
+2
-2
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+2
-2
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
···
88
88
* security fixes, etc. to be enabled.
89
89
*/
90
90
#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \
91
-
fw_def(METEORLAKE, 0, guc_maj(mtl, 70, 12, 1)) \
92
-
fw_def(DG2, 0, guc_maj(dg2, 70, 12, 1)) \
91
+
fw_def(METEORLAKE, 0, guc_maj(mtl, 70, 53, 0)) \
92
+
fw_def(DG2, 0, guc_maj(dg2, 70, 53, 0)) \
93
93
fw_def(ALDERLAKE_P, 0, guc_maj(adlp, 70, 12, 1)) \
94
94
fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 70, 1, 1)) \
95
95
fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 69, 0, 3)) \