Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Drop MMIO_REMAP domain bit and keep it Internal
"AMDGPU_GEM_DOMAIN_MMIO_REMAP" - Never activated as UAPI and it turned
out that this was to inflexible.
Allocate the MMIO_REMAP buffer object as a regular GEM BO and explicitly
move it into the fixed AMDGPU_PL_MMIO_REMAP placement at the TTM level.
This avoids relying on GEM domain bits for MMIO_REMAP, keeps the
placement purely internal, and makes the lifetime and pinning of the
global MMIO_REMAP BO explicit. The BO is pinned in TTM so it cannot be
migrated or evicted.
The corresponding free path relies on normal DRM teardown ordering,
where no further user ioctls can access the global BO once TTM teardown
begins.
v2 (Srini):
- Updated patch title.
- Drop use of AMDGPU_GEM_DOMAIN_MMIO_REMAP in amdgpu_ttm.c. The
MMIO_REMAP domain bit is removed from UAPI, so keep the MMIO_REMAP BO
allocation domain-less (bp.domain = 0) and rely on the TTM placement
(AMDGPU_PL_MMIO_REMAP) for backing/pinning.
- Keep fdinfo/mem-stats visibility for MMIO_REMAP by classifying BOs
based on bo->tbo.resource->mem_type == AMDGPU_PL_MMIO_REMAP, since the
domain bit is removed.
v3: Squash patches #1 & #3
Fixes: 056132483724 ("drm/amdgpu/uapi: Introduce AMDGPU_GEM_DOMAIN_MMIO_REMAP")
Fixes: 2a7a794eb82c ("drm/amdgpu/ttm: Allocate/Free 4K MMIO_REMAP Singleton")
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Leo Liu <leo.liu@amd.com>
Cc: Ruijing Dong <ruijing.dong@amd.com>
Cc: David (Ming Qiang) Wu <David.Wu3@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Christian König
and committed by
Alex Deucher
96e97a56
cf3f100c
+60
-49
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
···
417
417
/* always clear VRAM */
418
418
flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
419
419
420
-
if (args->in.domains & AMDGPU_GEM_DOMAIN_MMIO_REMAP)
421
-
return -EINVAL;
422
-
423
420
/* create a gem object to contain this object in */
424
421
if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
425
422
AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
+10
-11
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+10
-11
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
···
153
153
c++;
154
154
}
155
155
156
-
if (domain & AMDGPU_GEM_DOMAIN_MMIO_REMAP) {
157
-
places[c].fpfn = 0;
158
-
places[c].lpfn = 0;
159
-
places[c].mem_type = AMDGPU_PL_MMIO_REMAP;
160
-
places[c].flags = 0;
161
-
c++;
162
-
}
163
-
164
156
if (domain & AMDGPU_GEM_DOMAIN_GTT) {
165
157
places[c].fpfn = 0;
166
158
places[c].lpfn = 0;
···
1538
1546
*/
1539
1547
uint32_t amdgpu_bo_mem_stats_placement(struct amdgpu_bo *bo)
1540
1548
{
1541
-
uint32_t domain = bo->preferred_domains & AMDGPU_GEM_DOMAIN_MASK;
1549
+
u32 domain;
1542
1550
1551
+
/*
1552
+
* MMIO_REMAP is internal now, so it no longer maps from a userspace
1553
+
* domain bit. Keep fdinfo/mem-stats visibility by checking the actual
1554
+
* TTM placement.
1555
+
*/
1556
+
if (bo->tbo.resource && bo->tbo.resource->mem_type == AMDGPU_PL_MMIO_REMAP)
1557
+
return AMDGPU_PL_MMIO_REMAP;
1558
+
1559
+
domain = bo->preferred_domains & AMDGPU_GEM_DOMAIN_MASK;
1543
1560
if (!domain)
1544
1561
return TTM_PL_SYSTEM;
1545
1562
···
1567
1566
return AMDGPU_PL_OA;
1568
1567
case AMDGPU_GEM_DOMAIN_DOORBELL:
1569
1568
return AMDGPU_PL_DOORBELL;
1570
-
case AMDGPU_GEM_DOMAIN_MMIO_REMAP:
1571
-
return AMDGPU_PL_MMIO_REMAP;
1572
1569
default:
1573
1570
return TTM_PL_SYSTEM;
1574
1571
}
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+49
-28
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+49
-28
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
···
1909
1909
}
1910
1910
1911
1911
/**
1912
-
* amdgpu_ttm_mmio_remap_bo_init - Allocate the singleton 4K MMIO_REMAP BO
1912
+
* amdgpu_ttm_mmio_remap_bo_init - Allocate the singleton MMIO_REMAP BO
1913
1913
* @adev: amdgpu device
1914
1914
*
1915
-
* Allocates a one-page (4K) GEM BO in AMDGPU_GEM_DOMAIN_MMIO_REMAP when the
1915
+
* Allocates a global BO with backing AMDGPU_PL_MMIO_REMAP when the
1916
1916
* hardware exposes a remap base (adev->rmmio_remap.bus_addr) and the host
1917
1917
* PAGE_SIZE is <= AMDGPU_GPU_PAGE_SIZE (4K). The BO is created as a regular
1918
1918
* GEM object (amdgpu_bo_create).
1919
-
*
1920
-
* The BO is created as a normal GEM object via amdgpu_bo_create(), then
1921
-
* reserved and pinned at the TTM level (ttm_bo_pin()) so it can never be
1922
-
* migrated or evicted. No CPU mapping is established here.
1923
1919
*
1924
1920
* Return:
1925
1921
* * 0 on success or intentional skip (feature not present/unsupported)
1926
1922
* * negative errno on allocation failure
1927
1923
*/
1928
-
static int amdgpu_ttm_mmio_remap_bo_init(struct amdgpu_device *adev)
1924
+
static int amdgpu_ttm_alloc_mmio_remap_bo(struct amdgpu_device *adev)
1929
1925
{
1926
+
struct ttm_operation_ctx ctx = { false, false };
1927
+
struct ttm_placement placement;
1928
+
struct ttm_buffer_object *tbo;
1929
+
struct ttm_place placements;
1930
1930
struct amdgpu_bo_param bp;
1931
+
struct ttm_resource *tmp;
1931
1932
int r;
1932
1933
1933
1934
/* Skip if HW doesn't expose remap, or if PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE (4K). */
1934
1935
if (!adev->rmmio_remap.bus_addr || PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE)
1935
1936
return 0;
1936
1937
1938
+
/*
1939
+
* Allocate a BO first and then move it to AMDGPU_PL_MMIO_REMAP.
1940
+
* The initial TTM resource assigned by amdgpu_bo_create() is
1941
+
* replaced below with a fixed MMIO_REMAP placement.
1942
+
*/
1937
1943
memset(&bp, 0, sizeof(bp));
1938
-
1939
-
/* Create exactly one GEM BO in the MMIO_REMAP domain. */
1940
-
bp.type = ttm_bo_type_device; /* userspace-mappable GEM */
1941
-
bp.size = AMDGPU_GPU_PAGE_SIZE; /* 4K */
1944
+
bp.type = ttm_bo_type_device;
1945
+
bp.size = AMDGPU_GPU_PAGE_SIZE;
1942
1946
bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
1943
-
bp.domain = AMDGPU_GEM_DOMAIN_MMIO_REMAP;
1947
+
bp.domain = 0;
1944
1948
bp.flags = 0;
1945
1949
bp.resv = NULL;
1946
1950
bp.bo_ptr_size = sizeof(struct amdgpu_bo);
1947
-
1948
1951
r = amdgpu_bo_create(adev, &bp, &adev->rmmio_remap.bo);
1949
1952
if (r)
1950
1953
return r;
···
1956
1953
if (r)
1957
1954
goto err_unref;
1958
1955
1956
+
tbo = &adev->rmmio_remap.bo->tbo;
1957
+
1959
1958
/*
1960
1959
* MMIO_REMAP is a fixed I/O placement (AMDGPU_PL_MMIO_REMAP).
1961
-
* Use TTM-level pin so the BO cannot be evicted/migrated,
1962
-
* independent of GEM domains. This
1963
-
* enforces the “fixed I/O window”
1964
1960
*/
1965
-
ttm_bo_pin(&adev->rmmio_remap.bo->tbo);
1961
+
placement.num_placement = 1;
1962
+
placement.placement = &placements;
1963
+
placements.fpfn = 0;
1964
+
placements.lpfn = 0;
1965
+
placements.mem_type = AMDGPU_PL_MMIO_REMAP;
1966
+
placements.flags = 0;
1967
+
/* Force the BO into the fixed MMIO_REMAP placement */
1968
+
r = ttm_bo_mem_space(tbo, &placement, &tmp, &ctx);
1969
+
if (unlikely(r))
1970
+
goto err_unlock;
1971
+
1972
+
ttm_resource_free(tbo, &tbo->resource);
1973
+
ttm_bo_assign_mem(tbo, tmp);
1974
+
ttm_bo_pin(tbo);
1966
1975
1967
1976
amdgpu_bo_unreserve(adev->rmmio_remap.bo);
1968
1977
return 0;
1969
1978
1979
+
err_unlock:
1980
+
amdgpu_bo_unreserve(adev->rmmio_remap.bo);
1981
+
1970
1982
err_unref:
1971
-
if (adev->rmmio_remap.bo)
1972
-
amdgpu_bo_unref(&adev->rmmio_remap.bo);
1983
+
amdgpu_bo_unref(&adev->rmmio_remap.bo);
1973
1984
adev->rmmio_remap.bo = NULL;
1974
1985
return r;
1975
1986
}
1976
1987
1977
1988
/**
1978
-
* amdgpu_ttm_mmio_remap_bo_fini - Free the singleton MMIO_REMAP BO
1989
+
* amdgpu_ttm_free_mmio_remap_bo - Free the singleton MMIO_REMAP BO
1979
1990
* @adev: amdgpu device
1980
1991
*
1981
1992
* Frees the kernel-owned MMIO_REMAP BO if it was allocated by
1982
1993
* amdgpu_ttm_mmio_remap_bo_init().
1983
1994
*/
1984
-
static void amdgpu_ttm_mmio_remap_bo_fini(struct amdgpu_device *adev)
1995
+
static void amdgpu_ttm_free_mmio_remap_bo(struct amdgpu_device *adev)
1985
1996
{
1986
-
struct amdgpu_bo *bo = adev->rmmio_remap.bo;
1987
-
1988
-
if (!bo)
1989
-
return; /* <-- safest early exit */
1997
+
if (!adev->rmmio_remap.bo)
1998
+
return;
1990
1999
1991
2000
if (!amdgpu_bo_reserve(adev->rmmio_remap.bo, true)) {
1992
2001
ttm_bo_unpin(&adev->rmmio_remap.bo->tbo);
1993
2002
amdgpu_bo_unreserve(adev->rmmio_remap.bo);
1994
2003
}
2004
+
2005
+
/*
2006
+
* At this point we rely on normal DRM teardown ordering:
2007
+
* no new user ioctls can access the global MMIO_REMAP BO
2008
+
* once TTM teardown begins.
2009
+
*/
1995
2010
amdgpu_bo_unref(&adev->rmmio_remap.bo);
1996
2011
adev->rmmio_remap.bo = NULL;
1997
2012
}
···
2193
2172
return r;
2194
2173
}
2195
2174
2196
-
/* Allocate the singleton MMIO_REMAP BO (4K) if supported */
2197
-
r = amdgpu_ttm_mmio_remap_bo_init(adev);
2175
+
/* Allocate the singleton MMIO_REMAP BO if supported */
2176
+
r = amdgpu_ttm_alloc_mmio_remap_bo(adev);
2198
2177
if (r)
2199
2178
return r;
2200
2179
···
2262
2241
amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL,
2263
2242
&adev->mman.sdma_access_ptr);
2264
2243
2265
-
amdgpu_ttm_mmio_remap_bo_fini(adev);
2244
+
amdgpu_ttm_free_mmio_remap_bo(adev);
2266
2245
amdgpu_ttm_fw_reserve_vram_fini(adev);
2267
2246
amdgpu_ttm_drv_reserve_vram_fini(adev);
2268
2247
+1
-5
include/uapi/drm/amdgpu_drm.h
+1
-5
include/uapi/drm/amdgpu_drm.h
···
105
105
*
106
106
* %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for
107
107
* signalling user mode queues.
108
-
*
109
-
* %AMDGPU_GEM_DOMAIN_MMIO_REMAP MMIO remap page (special mapping for HDP flushing).
110
108
*/
111
109
#define AMDGPU_GEM_DOMAIN_CPU 0x1
112
110
#define AMDGPU_GEM_DOMAIN_GTT 0x2
···
113
115
#define AMDGPU_GEM_DOMAIN_GWS 0x10
114
116
#define AMDGPU_GEM_DOMAIN_OA 0x20
115
117
#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
116
-
#define AMDGPU_GEM_DOMAIN_MMIO_REMAP 0x80
117
118
#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
118
119
AMDGPU_GEM_DOMAIN_GTT | \
119
120
AMDGPU_GEM_DOMAIN_VRAM | \
120
121
AMDGPU_GEM_DOMAIN_GDS | \
121
122
AMDGPU_GEM_DOMAIN_GWS | \
122
123
AMDGPU_GEM_DOMAIN_OA | \
123
-
AMDGPU_GEM_DOMAIN_DOORBELL | \
124
-
AMDGPU_GEM_DOMAIN_MMIO_REMAP)
124
+
AMDGPU_GEM_DOMAIN_DOORBELL)
125
125
126
126
/* Flag that CPU access will be required for the case of VRAM domain */
127
127
#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)