tjh.dev / kernel
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drm/amd/pm: Use message control for debug mailbox

Migrate existing debug message mechanism so that it uses debug message
callbacks in message control block.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Lijo Lazar and committed by
Alex Deucher cf3f100c 2f0d5eca

+26 -31
-4
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
··· 755 755 756 756 struct firmware pptable_firmware; 757 757 758 - u32 debug_param_reg; 759 - u32 debug_msg_reg; 760 - u32 debug_resp_reg; 761 - 762 758 struct delayed_work swctf_delayed_work; 763 759 764 760 /* data structures for wbrf feature support */
+1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
··· 2366 2366 ctl->ops = &smu_msg_v1_ops; 2367 2367 ctl->default_timeout = adev->usec_timeout * 20; 2368 2368 ctl->message_map = message_map; 2369 + ctl->flags = 0; 2369 2370 } 2370 2371 2371 2372 int smu_v13_0_mode1_reset(struct smu_context *smu)
+10 -6
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
··· 2882 2882 return -EOPNOTSUPP; 2883 2883 } 2884 2884 2885 - static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu) 2885 + static void smu_v13_0_0_init_msg_ctl(struct smu_context *smu) 2886 2886 { 2887 2887 struct amdgpu_device *adev = smu->adev; 2888 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 2888 2889 2889 - smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53); 2890 - smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75); 2891 - smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54); 2890 + smu_v13_0_init_msg_ctl(smu, smu_v13_0_0_message_map); 2891 + 2892 + /* Set up debug mailbox registers */ 2893 + ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53); 2894 + ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75); 2895 + ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54); 2896 + ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX; 2892 2897 } 2893 2898 2894 2899 static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu, ··· 3221 3216 smu->pwr_src_map = smu_v13_0_0_pwr_src_map; 3222 3217 smu->workload_map = smu_v13_0_0_workload_map; 3223 3218 smu->smc_driver_if_version = SMU13_0_0_DRIVER_IF_VERSION; 3224 - smu_v13_0_0_set_smu_mailbox_registers(smu); 3225 - smu_v13_0_init_msg_ctl(smu, smu_v13_0_0_message_map); 3219 + smu_v13_0_0_init_msg_ctl(smu); 3226 3220 3227 3221 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == 3228 3222 IP_VERSION(13, 0, 10) &&
+7 -10
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
··· 2107 2107 return -EOPNOTSUPP; 2108 2108 } 2109 2109 2110 - static void smu_v14_0_2_set_smu_mailbox_registers(struct smu_context *smu) 2111 - { 2112 - struct amdgpu_device *adev = smu->adev; 2113 - 2114 - smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_53); 2115 - smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_75); 2116 - smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54); 2117 - } 2118 - 2119 2110 static void smu_v14_0_2_init_msg_ctl(struct smu_context *smu) 2120 2111 { 2121 2112 struct amdgpu_device *adev = smu->adev; ··· 2121 2130 ctl->ops = &smu_msg_v1_ops; 2122 2131 ctl->default_timeout = adev->usec_timeout * 20; 2123 2132 ctl->message_map = smu_v14_0_2_message_map; 2133 + ctl->flags = 0; 2134 + 2135 + /* Set up debug mailbox registers */ 2136 + ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_53); 2137 + ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_75); 2138 + ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54); 2139 + ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX; 2124 2140 } 2125 2141 2126 2142 static ssize_t smu_v14_0_2_get_gpu_metrics(struct smu_context *smu, ··· 2874 2876 smu->table_map = smu_v14_0_2_table_map; 2875 2877 smu->pwr_src_map = smu_v14_0_2_pwr_src_map; 2876 2878 smu->workload_map = smu_v14_0_2_workload_map; 2877 - smu_v14_0_2_set_smu_mailbox_registers(smu); 2878 2879 smu_v14_0_2_init_msg_ctl(smu); 2879 2880 }
+8 -11
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
··· 102 102 return 0; 103 103 } 104 104 105 - static int __smu_cmn_send_debug_msg(struct smu_context *smu, 106 - u32 msg, 107 - u32 param) 105 + static int __smu_cmn_send_debug_msg(struct smu_msg_ctl *ctl, 106 + u32 msg, 107 + u32 param) 108 108 { 109 - struct amdgpu_device *adev = smu->adev; 109 + if (!ctl->ops || !ctl->ops->send_debug_msg) 110 + return -EOPNOTSUPP; 110 111 111 - WREG32(smu->debug_param_reg, param); 112 - WREG32(smu->debug_msg_reg, msg); 113 - WREG32(smu->debug_resp_reg, 0); 114 - 115 - return 0; 112 + return ctl->ops->send_debug_msg(ctl, msg, param); 116 113 } 117 114 118 115 /** ··· 196 199 int smu_cmn_send_debug_smc_msg(struct smu_context *smu, 197 200 uint32_t msg) 198 201 { 199 - return __smu_cmn_send_debug_msg(smu, msg, 0); 202 + return __smu_cmn_send_debug_msg(&smu->msg_ctl, msg, 0); 200 203 } 201 204 202 205 int smu_cmn_send_debug_smc_msg_with_param(struct smu_context *smu, 203 206 uint32_t msg, uint32_t param) 204 207 { 205 - return __smu_cmn_send_debug_msg(smu, msg, param); 208 + return __smu_cmn_send_debug_msg(&smu->msg_ctl, msg, param); 206 209 } 207 210 208 211 static int smu_msg_v1_decode_response(u32 resp)