Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: unify MQD programming sequence for kfd and amdgpu v2
Use the same gfx_*_mqd_commit function for kfd and amdgpu codepaths.
This removes the last duplicates of this programming sequence.
v2: fix cp_hqd_pq_wptr value
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Andres Rodriguez
and committed by
Alex Deucher
97bf47b2
486d807c
+97
-100
+4
-47
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+4
-47
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
···
29
29
#include "cikd.h"
30
30
#include "cik_sdma.h"
31
31
#include "amdgpu_ucode.h"
32
+
#include "gfx_v7_0.h"
32
33
#include "gca/gfx_7_2_d.h"
33
34
#include "gca/gfx_7_2_enum.h"
34
35
#include "gca/gfx_7_2_sh_mask.h"
···
310
309
m = get_mqd(mqd);
311
310
312
311
is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
312
+
if (is_wptr_shadow_valid)
313
+
m->cp_hqd_pq_wptr = wptr_shadow;
313
314
314
315
acquire_queue(kgd, pipe_id, queue_id);
315
-
WREG32(mmCP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
316
-
WREG32(mmCP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
317
-
WREG32(mmCP_MQD_CONTROL, m->cp_mqd_control);
318
-
319
-
WREG32(mmCP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
320
-
WREG32(mmCP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
321
-
WREG32(mmCP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
322
-
323
-
WREG32(mmCP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
324
-
WREG32(mmCP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo);
325
-
WREG32(mmCP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi);
326
-
327
-
WREG32(mmCP_HQD_IB_RPTR, m->cp_hqd_ib_rptr);
328
-
329
-
WREG32(mmCP_HQD_PERSISTENT_STATE, m->cp_hqd_persistent_state);
330
-
WREG32(mmCP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd);
331
-
WREG32(mmCP_HQD_MSG_TYPE, m->cp_hqd_msg_type);
332
-
333
-
WREG32(mmCP_HQD_ATOMIC0_PREOP_LO, m->cp_hqd_atomic0_preop_lo);
334
-
WREG32(mmCP_HQD_ATOMIC0_PREOP_HI, m->cp_hqd_atomic0_preop_hi);
335
-
WREG32(mmCP_HQD_ATOMIC1_PREOP_LO, m->cp_hqd_atomic1_preop_lo);
336
-
WREG32(mmCP_HQD_ATOMIC1_PREOP_HI, m->cp_hqd_atomic1_preop_hi);
337
-
338
-
WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, m->cp_hqd_pq_rptr_report_addr_lo);
339
-
WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
340
-
m->cp_hqd_pq_rptr_report_addr_hi);
341
-
342
-
WREG32(mmCP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr);
343
-
344
-
WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, m->cp_hqd_pq_wptr_poll_addr_lo);
345
-
WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, m->cp_hqd_pq_wptr_poll_addr_hi);
346
-
347
-
WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, m->cp_hqd_pq_doorbell_control);
348
-
349
-
WREG32(mmCP_HQD_VMID, m->cp_hqd_vmid);
350
-
351
-
WREG32(mmCP_HQD_QUANTUM, m->cp_hqd_quantum);
352
-
353
-
WREG32(mmCP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
354
-
WREG32(mmCP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
355
-
356
-
WREG32(mmCP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr);
357
-
358
-
if (is_wptr_shadow_valid)
359
-
WREG32(mmCP_HQD_PQ_WPTR, wptr_shadow);
360
-
361
-
WREG32(mmCP_HQD_ACTIVE, m->cp_hqd_active);
316
+
gfx_v7_0_mqd_commit(adev, m);
362
317
release_queue(kgd);
363
318
364
319
return 0;
+4
-45
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+4
-45
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
···
28
28
#include "amdgpu.h"
29
29
#include "amdgpu_amdkfd.h"
30
30
#include "amdgpu_ucode.h"
31
+
#include "gfx_v8_0.h"
31
32
#include "gca/gfx_8_0_sh_mask.h"
32
33
#include "gca/gfx_8_0_d.h"
33
34
#include "gca/gfx_8_0_enum.h"
···
252
251
m = get_mqd(mqd);
253
252
254
253
valid_wptr = copy_from_user(&shadow_wptr, wptr, sizeof(shadow_wptr));
255
-
acquire_queue(kgd, pipe_id, queue_id);
256
-
257
-
WREG32(mmCP_MQD_CONTROL, m->cp_mqd_control);
258
-
WREG32(mmCP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
259
-
WREG32(mmCP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
260
-
261
-
WREG32(mmCP_HQD_VMID, m->cp_hqd_vmid);
262
-
WREG32(mmCP_HQD_PERSISTENT_STATE, m->cp_hqd_persistent_state);
263
-
WREG32(mmCP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
264
-
WREG32(mmCP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
265
-
WREG32(mmCP_HQD_QUANTUM, m->cp_hqd_quantum);
266
-
WREG32(mmCP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
267
-
WREG32(mmCP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
268
-
WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, m->cp_hqd_pq_rptr_report_addr_lo);
269
-
WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
270
-
m->cp_hqd_pq_rptr_report_addr_hi);
271
-
272
254
if (valid_wptr > 0)
273
-
WREG32(mmCP_HQD_PQ_WPTR, shadow_wptr);
255
+
m->cp_hqd_pq_wptr = shadow_wptr;
274
256
275
-
WREG32(mmCP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
276
-
WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, m->cp_hqd_pq_doorbell_control);
277
-
278
-
WREG32(mmCP_HQD_EOP_BASE_ADDR, m->cp_hqd_eop_base_addr_lo);
279
-
WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, m->cp_hqd_eop_base_addr_hi);
280
-
WREG32(mmCP_HQD_EOP_CONTROL, m->cp_hqd_eop_control);
281
-
WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr);
282
-
WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr);
283
-
WREG32(mmCP_HQD_EOP_EVENTS, m->cp_hqd_eop_done_events);
284
-
285
-
WREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO, m->cp_hqd_ctx_save_base_addr_lo);
286
-
WREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI, m->cp_hqd_ctx_save_base_addr_hi);
287
-
WREG32(mmCP_HQD_CTX_SAVE_CONTROL, m->cp_hqd_ctx_save_control);
288
-
WREG32(mmCP_HQD_CNTL_STACK_OFFSET, m->cp_hqd_cntl_stack_offset);
289
-
WREG32(mmCP_HQD_CNTL_STACK_SIZE, m->cp_hqd_cntl_stack_size);
290
-
WREG32(mmCP_HQD_WG_STATE_OFFSET, m->cp_hqd_wg_state_offset);
291
-
WREG32(mmCP_HQD_CTX_SAVE_SIZE, m->cp_hqd_ctx_save_size);
292
-
293
-
WREG32(mmCP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
294
-
295
-
WREG32(mmCP_HQD_DEQUEUE_REQUEST, m->cp_hqd_dequeue_request);
296
-
WREG32(mmCP_HQD_ERROR, m->cp_hqd_error);
297
-
WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem);
298
-
WREG32(mmCP_HQD_EOP_DONES, m->cp_hqd_eop_dones);
299
-
300
-
WREG32(mmCP_HQD_ACTIVE, m->cp_hqd_active);
301
-
257
+
acquire_queue(kgd, pipe_id, queue_id);
258
+
gfx_v8_0_mqd_commit(adev, mqd);
302
259
release_queue(kgd);
303
260
304
261
return 0;
+36
-2
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+36
-2
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
···
3067
3067
/* set the vmid for the queue */
3068
3068
mqd->cp_hqd_vmid = 0;
3069
3069
3070
+
/* defaults */
3071
+
mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
3072
+
mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);
3073
+
mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);
3074
+
mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);
3075
+
mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);
3076
+
mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);
3077
+
mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);
3078
+
mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);
3079
+
mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);
3080
+
mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
3081
+
mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
3082
+
mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3083
+
mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
3084
+
mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
3085
+
mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
3086
+
mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
3087
+
3070
3088
/* activate the queue */
3071
3089
mqd->cp_hqd_active = 1;
3072
3090
}
3073
3091
3074
-
static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev,
3075
-
struct cik_mqd *mqd)
3092
+
int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
3076
3093
{
3077
3094
u32 tmp;
3078
3095
···
3112
3095
WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, mqd->cp_hqd_pq_doorbell_control);
3113
3096
WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3114
3097
WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3098
+
3099
+
WREG32(mmCP_HQD_IB_CONTROL, mqd->cp_hqd_ib_control);
3100
+
WREG32(mmCP_HQD_IB_BASE_ADDR, mqd->cp_hqd_ib_base_addr_lo);
3101
+
WREG32(mmCP_HQD_IB_BASE_ADDR_HI, mqd->cp_hqd_ib_base_addr_hi);
3102
+
WREG32(mmCP_HQD_IB_RPTR, mqd->cp_hqd_ib_rptr);
3103
+
WREG32(mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
3104
+
WREG32(mmCP_HQD_SEMA_CMD, mqd->cp_hqd_sema_cmd);
3105
+
WREG32(mmCP_HQD_MSG_TYPE, mqd->cp_hqd_msg_type);
3106
+
WREG32(mmCP_HQD_ATOMIC0_PREOP_LO, mqd->cp_hqd_atomic0_preop_lo);
3107
+
WREG32(mmCP_HQD_ATOMIC0_PREOP_HI, mqd->cp_hqd_atomic0_preop_hi);
3108
+
WREG32(mmCP_HQD_ATOMIC1_PREOP_LO, mqd->cp_hqd_atomic1_preop_lo);
3109
+
WREG32(mmCP_HQD_ATOMIC1_PREOP_HI, mqd->cp_hqd_atomic1_preop_hi);
3110
+
WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3111
+
WREG32(mmCP_HQD_QUANTUM, mqd->cp_hqd_quantum);
3112
+
WREG32(mmCP_HQD_PIPE_PRIORITY, mqd->cp_hqd_pipe_priority);
3113
+
WREG32(mmCP_HQD_QUEUE_PRIORITY, mqd->cp_hqd_queue_priority);
3114
+
WREG32(mmCP_HQD_IQ_RPTR, mqd->cp_hqd_iq_rptr);
3115
3115
3116
3116
/* activate the HQD */
3117
3117
WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
+5
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
+5
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.h
+43
-6
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+43
-6
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
···
4913
4913
tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
4914
4914
mqd->cp_hqd_ctx_save_control = tmp;
4915
4915
4916
+
/* defaults */
4917
+
mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
4918
+
mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
4919
+
mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
4920
+
mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
4921
+
mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
4922
+
mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
4923
+
mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
4924
+
mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
4925
+
mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);
4926
+
mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);
4927
+
mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);
4928
+
mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);
4929
+
mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);
4930
+
mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
4931
+
mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
4932
+
4916
4933
/* activate the queue */
4917
4934
mqd->cp_hqd_active = 1;
4918
4935
4919
4936
return 0;
4920
4937
}
4921
4938
4922
-
static int gfx_v8_0_mqd_commit(struct amdgpu_ring *ring)
4939
+
int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
4940
+
struct vi_mqd *mqd)
4923
4941
{
4924
-
struct amdgpu_device *adev = ring->adev;
4925
-
struct vi_mqd *mqd = ring->mqd_ptr;
4926
-
4927
4942
/* disable wptr polling */
4928
4943
WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);
4929
4944
···
4985
4970
4986
4971
/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4987
4972
WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
4973
+
WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);
4974
+
WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);
4975
+
4976
+
/* set the HQD priority */
4977
+
WREG32(mmCP_HQD_PIPE_PRIORITY, mqd->cp_hqd_pipe_priority);
4978
+
WREG32(mmCP_HQD_QUEUE_PRIORITY, mqd->cp_hqd_queue_priority);
4979
+
WREG32(mmCP_HQD_QUANTUM, mqd->cp_hqd_quantum);
4980
+
4981
+
/* set cwsr save area */
4982
+
WREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO, mqd->cp_hqd_ctx_save_base_addr_lo);
4983
+
WREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI, mqd->cp_hqd_ctx_save_base_addr_hi);
4984
+
WREG32(mmCP_HQD_CTX_SAVE_CONTROL, mqd->cp_hqd_ctx_save_control);
4985
+
WREG32(mmCP_HQD_CNTL_STACK_OFFSET, mqd->cp_hqd_cntl_stack_offset);
4986
+
WREG32(mmCP_HQD_CNTL_STACK_SIZE, mqd->cp_hqd_cntl_stack_size);
4987
+
WREG32(mmCP_HQD_WG_STATE_OFFSET, mqd->cp_hqd_wg_state_offset);
4988
+
WREG32(mmCP_HQD_CTX_SAVE_SIZE, mqd->cp_hqd_ctx_save_size);
4989
+
4990
+
WREG32(mmCP_HQD_IB_CONTROL, mqd->cp_hqd_ib_control);
4991
+
WREG32(mmCP_HQD_EOP_EVENTS, mqd->cp_hqd_eop_done_events);
4992
+
WREG32(mmCP_HQD_ERROR, mqd->cp_hqd_error);
4993
+
WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);
4994
+
WREG32(mmCP_HQD_EOP_DONES, mqd->cp_hqd_eop_dones);
4988
4995
4989
4996
/* set the vmid for the queue */
4990
4997
WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
···
5043
5006
dev_err(adev->dev, "failed to deactivate ring %s\n", ring->name);
5044
5007
goto out_unlock;
5045
5008
}
5046
-
gfx_v8_0_mqd_commit(ring);
5009
+
gfx_v8_0_mqd_commit(adev, mqd);
5047
5010
vi_srbm_select(adev, 0, 0, 0, 0);
5048
5011
mutex_unlock(&adev->srbm_mutex);
5049
5012
} else {
···
5055
5018
dev_err(adev->dev, "failed to deactivate ring %s\n", ring->name);
5056
5019
goto out_unlock;
5057
5020
}
5058
-
gfx_v8_0_mqd_commit(ring);
5021
+
gfx_v8_0_mqd_commit(adev, mqd);
5059
5022
vi_srbm_select(adev, 0, 0, 0, 0);
5060
5023
mutex_unlock(&adev->srbm_mutex);
5061
5024
+5
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h
+5
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.h