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arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability

Implement the GCIE capability as a strict boot cpu capability to
detect whether architectural GICv5 support is available in HW.

Plug it in with a naming consistent with the existing GICv3
CPU interface capability.

Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-17-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

authored by

Lorenzo Pieralisi and committed by
Marc Zyngier 988699f9 0bb5b6fa

+8
+7
arch/arm64/kernel/cpufeature.c
··· 3061 3061 .matches = has_pmuv3, 3062 3062 }, 3063 3063 #endif 3064 + { 3065 + .desc = "GICv5 CPU interface", 3066 + .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 3067 + .capability = ARM64_HAS_GICV5_CPUIF, 3068 + .matches = has_cpuid_feature, 3069 + ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) 3070 + }, 3064 3071 {}, 3065 3072 }; 3066 3073
+1
arch/arm64/tools/cpucaps
··· 36 36 HAS_GENERIC_AUTH_ARCH_QARMA5 37 37 HAS_GENERIC_AUTH_IMP_DEF 38 38 HAS_GICV3_CPUIF 39 + HAS_GICV5_CPUIF 39 40 HAS_GIC_PRIO_MASKING 40 41 HAS_GIC_PRIO_RELAXED_SYNC 41 42 HAS_HCR_NV1