Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Add soc24 common ip block (v2)
Add initial soc24 support.
v1: Add soc24 common ip block.
v2: Switch to new select_se_sh/enter_safe_mode
interface.
v3: squash in correct ext rev id, etc. (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Hawking Zhang
and committed by
Alex Deucher
98b912c5
ef4af63e
+561
-1
+1
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+1
-1
drivers/gpu/drm/amd/amdgpu/Makefile
···
97
97
amdgpu-y += \
98
98
vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
99
99
vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o mxgpu_nv.o \
100
-
nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o \
100
+
nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o soc24.o \
101
101
sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o \
102
102
nbio_v7_9.o aqua_vanjaram.o nbio_v7_11.o lsdma_v7_0.o hdp_v7_0.o nbif_v6_3_1.o
103
103
+530
drivers/gpu/drm/amd/amdgpu/soc24.c
+530
drivers/gpu/drm/amd/amdgpu/soc24.c
···
1
+
/*
2
+
* Copyright 2023 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
#include <linux/firmware.h>
24
+
#include <linux/slab.h>
25
+
#include <linux/module.h>
26
+
#include <linux/pci.h>
27
+
28
+
#include "amdgpu.h"
29
+
#include "amdgpu_atombios.h"
30
+
#include "amdgpu_ih.h"
31
+
#include "amdgpu_uvd.h"
32
+
#include "amdgpu_vce.h"
33
+
#include "amdgpu_ucode.h"
34
+
#include "amdgpu_psp.h"
35
+
#include "amdgpu_smu.h"
36
+
#include "atom.h"
37
+
#include "amd_pcie.h"
38
+
39
+
#include "gc/gc_12_0_0_offset.h"
40
+
#include "gc/gc_12_0_0_sh_mask.h"
41
+
#include "mp/mp_14_0_2_offset.h"
42
+
43
+
#include "soc15.h"
44
+
#include "soc15_common.h"
45
+
#include "soc24.h"
46
+
#include "mxgpu_nv.h"
47
+
48
+
static const struct amd_ip_funcs soc24_common_ip_funcs;
49
+
50
+
static u32 soc24_get_config_memsize(struct amdgpu_device *adev)
51
+
{
52
+
return adev->nbio.funcs->get_memsize(adev);
53
+
}
54
+
55
+
static u32 soc24_get_xclk(struct amdgpu_device *adev)
56
+
{
57
+
return adev->clock.spll.reference_freq;
58
+
}
59
+
60
+
void soc24_grbm_select(struct amdgpu_device *adev,
61
+
u32 me, u32 pipe, u32 queue, u32 vmid)
62
+
{
63
+
u32 grbm_gfx_cntl = 0;
64
+
grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
65
+
grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
66
+
grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
67
+
grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
68
+
69
+
WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
70
+
}
71
+
72
+
static struct soc15_allowed_register_entry soc24_allowed_read_registers[] = {
73
+
{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
74
+
{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
75
+
{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
76
+
{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
77
+
{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
78
+
{ SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
79
+
{ SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
80
+
{ SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
81
+
{ SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
82
+
{ SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
83
+
{ SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
84
+
{ SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
85
+
{ SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
86
+
{ SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
87
+
{ SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
88
+
{ SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
89
+
{ SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
90
+
{ SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
91
+
{ SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
92
+
};
93
+
94
+
static uint32_t soc24_read_indexed_register(struct amdgpu_device *adev,
95
+
u32 se_num,
96
+
u32 sh_num,
97
+
u32 reg_offset)
98
+
{
99
+
uint32_t val;
100
+
101
+
mutex_lock(&adev->grbm_idx_mutex);
102
+
if (se_num != 0xffffffff || sh_num != 0xffffffff)
103
+
amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
104
+
105
+
val = RREG32(reg_offset);
106
+
107
+
if (se_num != 0xffffffff || sh_num != 0xffffffff)
108
+
amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
109
+
mutex_unlock(&adev->grbm_idx_mutex);
110
+
return val;
111
+
}
112
+
113
+
static uint32_t soc24_get_register_value(struct amdgpu_device *adev,
114
+
bool indexed, u32 se_num,
115
+
u32 sh_num, u32 reg_offset)
116
+
{
117
+
if (indexed) {
118
+
return soc24_read_indexed_register(adev, se_num, sh_num, reg_offset);
119
+
} else {
120
+
if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) &&
121
+
adev->gfx.config.gb_addr_config)
122
+
return adev->gfx.config.gb_addr_config;
123
+
return RREG32(reg_offset);
124
+
}
125
+
}
126
+
127
+
static int soc24_read_register(struct amdgpu_device *adev, u32 se_num,
128
+
u32 sh_num, u32 reg_offset, u32 *value)
129
+
{
130
+
uint32_t i;
131
+
struct soc15_allowed_register_entry *en;
132
+
133
+
*value = 0;
134
+
for (i = 0; i < ARRAY_SIZE(soc24_allowed_read_registers); i++) {
135
+
en = &soc24_allowed_read_registers[i];
136
+
if (!adev->reg_offset[en->hwip][en->inst])
137
+
continue;
138
+
else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
139
+
+ en->reg_offset))
140
+
continue;
141
+
142
+
*value = soc24_get_register_value(adev,
143
+
soc24_allowed_read_registers[i].grbm_indexed,
144
+
se_num, sh_num, reg_offset);
145
+
return 0;
146
+
}
147
+
return -EINVAL;
148
+
}
149
+
150
+
static enum amd_reset_method
151
+
soc24_asic_reset_method(struct amdgpu_device *adev)
152
+
{
153
+
if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
154
+
amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
155
+
amdgpu_reset_method == AMD_RESET_METHOD_BACO)
156
+
return amdgpu_reset_method;
157
+
158
+
if (amdgpu_reset_method != -1)
159
+
dev_warn(adev->dev,
160
+
"Specified reset method:%d isn't supported, using AUTO instead.\n",
161
+
amdgpu_reset_method);
162
+
163
+
switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
164
+
case IP_VERSION(14, 0, 2):
165
+
return AMD_RESET_METHOD_MODE1;
166
+
default:
167
+
if (amdgpu_dpm_is_baco_supported(adev))
168
+
return AMD_RESET_METHOD_BACO;
169
+
else
170
+
return AMD_RESET_METHOD_MODE1;
171
+
}
172
+
}
173
+
174
+
static int soc24_asic_reset(struct amdgpu_device *adev)
175
+
{
176
+
int ret = 0;
177
+
178
+
switch (soc24_asic_reset_method(adev)) {
179
+
case AMD_RESET_METHOD_PCI:
180
+
dev_info(adev->dev, "PCI reset\n");
181
+
ret = amdgpu_device_pci_reset(adev);
182
+
break;
183
+
case AMD_RESET_METHOD_BACO:
184
+
dev_info(adev->dev, "BACO reset\n");
185
+
ret = amdgpu_dpm_baco_reset(adev);
186
+
break;
187
+
case AMD_RESET_METHOD_MODE2:
188
+
dev_info(adev->dev, "MODE2 reset\n");
189
+
ret = amdgpu_dpm_mode2_reset(adev);
190
+
break;
191
+
default:
192
+
dev_info(adev->dev, "MODE1 reset\n");
193
+
ret = amdgpu_device_mode1_reset(adev);
194
+
break;
195
+
}
196
+
197
+
return ret;
198
+
}
199
+
200
+
static void soc24_program_aspm(struct amdgpu_device *adev)
201
+
{
202
+
if (!amdgpu_device_should_use_aspm(adev))
203
+
return;
204
+
205
+
if (!(adev->flags & AMD_IS_APU) &&
206
+
(adev->nbio.funcs->program_aspm))
207
+
adev->nbio.funcs->program_aspm(adev);
208
+
}
209
+
210
+
static void soc24_enable_doorbell_aperture(struct amdgpu_device *adev,
211
+
bool enable)
212
+
{
213
+
adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
214
+
adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
215
+
}
216
+
217
+
const struct amdgpu_ip_block_version soc24_common_ip_block = {
218
+
.type = AMD_IP_BLOCK_TYPE_COMMON,
219
+
.major = 1,
220
+
.minor = 0,
221
+
.rev = 0,
222
+
.funcs = &soc24_common_ip_funcs,
223
+
};
224
+
225
+
static bool soc24_need_full_reset(struct amdgpu_device *adev)
226
+
{
227
+
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
228
+
case IP_VERSION(12, 0, 0):
229
+
case IP_VERSION(12, 0, 1):
230
+
default:
231
+
return true;
232
+
}
233
+
}
234
+
235
+
static bool soc24_need_reset_on_init(struct amdgpu_device *adev)
236
+
{
237
+
u32 sol_reg;
238
+
239
+
if (adev->flags & AMD_IS_APU)
240
+
return false;
241
+
242
+
/* Check sOS sign of life register to confirm sys driver and sOS
243
+
* are already been loaded.
244
+
*/
245
+
sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);
246
+
if (sol_reg)
247
+
return true;
248
+
249
+
return false;
250
+
}
251
+
252
+
static uint64_t soc24_get_pcie_replay_count(struct amdgpu_device *adev)
253
+
{
254
+
/* TODO
255
+
* dummy implement for pcie_replay_count sysfs interface
256
+
* */
257
+
return 0;
258
+
}
259
+
260
+
static void soc24_init_doorbell_index(struct amdgpu_device *adev)
261
+
{
262
+
adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
263
+
adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
264
+
adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
265
+
adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
266
+
adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
267
+
adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
268
+
adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
269
+
adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
270
+
adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
271
+
adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
272
+
adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
273
+
adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
274
+
adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
275
+
adev->doorbell_index.gfx_userqueue_start =
276
+
AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
277
+
adev->doorbell_index.gfx_userqueue_end =
278
+
AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
279
+
adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
280
+
adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
281
+
adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
282
+
adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
283
+
adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
284
+
adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
285
+
adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
286
+
adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
287
+
adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
288
+
adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
289
+
adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
290
+
291
+
adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
292
+
adev->doorbell_index.sdma_doorbell_range = 20;
293
+
}
294
+
295
+
static void soc24_pre_asic_init(struct amdgpu_device *adev)
296
+
{
297
+
}
298
+
299
+
static int soc24_update_umd_stable_pstate(struct amdgpu_device *adev,
300
+
bool enter)
301
+
{
302
+
if (enter)
303
+
amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
304
+
else
305
+
amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
306
+
307
+
if (adev->gfx.funcs->update_perfmon_mgcg)
308
+
adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
309
+
310
+
return 0;
311
+
}
312
+
313
+
static const struct amdgpu_asic_funcs soc24_asic_funcs = {
314
+
.read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
315
+
.read_register = &soc24_read_register,
316
+
.reset = &soc24_asic_reset,
317
+
.reset_method = &soc24_asic_reset_method,
318
+
.get_xclk = &soc24_get_xclk,
319
+
.get_config_memsize = &soc24_get_config_memsize,
320
+
.init_doorbell_index = &soc24_init_doorbell_index,
321
+
.need_full_reset = &soc24_need_full_reset,
322
+
.need_reset_on_init = &soc24_need_reset_on_init,
323
+
.get_pcie_replay_count = &soc24_get_pcie_replay_count,
324
+
.supports_baco = &amdgpu_dpm_is_baco_supported,
325
+
.pre_asic_init = &soc24_pre_asic_init,
326
+
.update_umd_stable_pstate = &soc24_update_umd_stable_pstate,
327
+
};
328
+
329
+
static int soc24_common_early_init(void *handle)
330
+
{
331
+
#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
332
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
333
+
334
+
adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
335
+
adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
336
+
adev->smc_rreg = NULL;
337
+
adev->smc_wreg = NULL;
338
+
adev->pcie_rreg = &amdgpu_device_indirect_rreg;
339
+
adev->pcie_wreg = &amdgpu_device_indirect_wreg;
340
+
adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
341
+
adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
342
+
adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
343
+
adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
344
+
adev->uvd_ctx_rreg = NULL;
345
+
adev->uvd_ctx_wreg = NULL;
346
+
adev->didt_rreg = NULL;
347
+
adev->didt_wreg = NULL;
348
+
349
+
adev->asic_funcs = &soc24_asic_funcs;
350
+
351
+
adev->rev_id = amdgpu_device_get_rev_id(adev);
352
+
adev->external_rev_id = 0xff;
353
+
354
+
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
355
+
case IP_VERSION(12, 0, 0):
356
+
adev->cg_flags = 0;
357
+
adev->pg_flags = 0;
358
+
adev->external_rev_id = adev->rev_id + 0x40;
359
+
break;
360
+
case IP_VERSION(12, 0, 1):
361
+
adev->cg_flags = 0;
362
+
adev->pg_flags = 0;
363
+
adev->external_rev_id = adev->rev_id + 0x50;
364
+
break;
365
+
default:
366
+
/* FIXME: not supported yet */
367
+
return -EINVAL;
368
+
}
369
+
370
+
if (amdgpu_sriov_vf(adev)) {
371
+
amdgpu_virt_init_setting(adev);
372
+
xgpu_nv_mailbox_set_irq_funcs(adev);
373
+
}
374
+
375
+
return 0;
376
+
}
377
+
378
+
static int soc24_common_late_init(void *handle)
379
+
{
380
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
381
+
382
+
if (amdgpu_sriov_vf(adev))
383
+
xgpu_nv_mailbox_get_irq(adev);
384
+
385
+
return 0;
386
+
}
387
+
388
+
static int soc24_common_sw_init(void *handle)
389
+
{
390
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
391
+
392
+
if (amdgpu_sriov_vf(adev))
393
+
xgpu_nv_mailbox_add_irq_id(adev);
394
+
395
+
return 0;
396
+
}
397
+
398
+
static int soc24_common_sw_fini(void *handle)
399
+
{
400
+
return 0;
401
+
}
402
+
403
+
static int soc24_common_hw_init(void *handle)
404
+
{
405
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
406
+
407
+
/* enable aspm */
408
+
soc24_program_aspm(adev);
409
+
/* setup nbio registers */
410
+
adev->nbio.funcs->init_registers(adev);
411
+
/* remap HDP registers to a hole in mmio space,
412
+
* for the purpose of expose those registers
413
+
* to process space
414
+
*/
415
+
if (adev->nbio.funcs->remap_hdp_registers)
416
+
adev->nbio.funcs->remap_hdp_registers(adev);
417
+
/* enable the doorbell aperture */
418
+
soc24_enable_doorbell_aperture(adev, true);
419
+
420
+
return 0;
421
+
}
422
+
423
+
static int soc24_common_hw_fini(void *handle)
424
+
{
425
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
426
+
427
+
/* disable the doorbell aperture */
428
+
soc24_enable_doorbell_aperture(adev, false);
429
+
430
+
if (amdgpu_sriov_vf(adev))
431
+
xgpu_nv_mailbox_put_irq(adev);
432
+
433
+
return 0;
434
+
}
435
+
436
+
static int soc24_common_suspend(void *handle)
437
+
{
438
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
439
+
440
+
return soc24_common_hw_fini(adev);
441
+
}
442
+
443
+
static int soc24_common_resume(void *handle)
444
+
{
445
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
446
+
447
+
return soc24_common_hw_init(adev);
448
+
}
449
+
450
+
static bool soc24_common_is_idle(void *handle)
451
+
{
452
+
return true;
453
+
}
454
+
455
+
static int soc24_common_wait_for_idle(void *handle)
456
+
{
457
+
return 0;
458
+
}
459
+
460
+
static int soc24_common_soft_reset(void *handle)
461
+
{
462
+
return 0;
463
+
}
464
+
465
+
static int soc24_common_set_clockgating_state(void *handle,
466
+
enum amd_clockgating_state state)
467
+
{
468
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
469
+
470
+
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
471
+
case IP_VERSION(6, 3, 1):
472
+
adev->nbio.funcs->update_medium_grain_clock_gating(adev,
473
+
state == AMD_CG_STATE_GATE);
474
+
adev->nbio.funcs->update_medium_grain_light_sleep(adev,
475
+
state == AMD_CG_STATE_GATE);
476
+
adev->hdp.funcs->update_clock_gating(adev,
477
+
state == AMD_CG_STATE_GATE);
478
+
break;
479
+
default:
480
+
break;
481
+
}
482
+
return 0;
483
+
}
484
+
485
+
static int soc24_common_set_powergating_state(void *handle,
486
+
enum amd_powergating_state state)
487
+
{
488
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
489
+
490
+
switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
491
+
case IP_VERSION(7, 0, 0):
492
+
case IP_VERSION(7, 0, 1):
493
+
adev->lsdma.funcs->update_memory_power_gating(adev,
494
+
state == AMD_PG_STATE_GATE);
495
+
break;
496
+
default:
497
+
break;
498
+
}
499
+
500
+
return 0;
501
+
}
502
+
503
+
static void soc24_common_get_clockgating_state(void *handle, u64 *flags)
504
+
{
505
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
506
+
507
+
adev->nbio.funcs->get_clockgating_state(adev, flags);
508
+
509
+
adev->hdp.funcs->get_clock_gating_state(adev, flags);
510
+
511
+
return;
512
+
}
513
+
514
+
static const struct amd_ip_funcs soc24_common_ip_funcs = {
515
+
.name = "soc24_common",
516
+
.early_init = soc24_common_early_init,
517
+
.late_init = soc24_common_late_init,
518
+
.sw_init = soc24_common_sw_init,
519
+
.sw_fini = soc24_common_sw_fini,
520
+
.hw_init = soc24_common_hw_init,
521
+
.hw_fini = soc24_common_hw_fini,
522
+
.suspend = soc24_common_suspend,
523
+
.resume = soc24_common_resume,
524
+
.is_idle = soc24_common_is_idle,
525
+
.wait_for_idle = soc24_common_wait_for_idle,
526
+
.soft_reset = soc24_common_soft_reset,
527
+
.set_clockgating_state = soc24_common_set_clockgating_state,
528
+
.set_powergating_state = soc24_common_set_powergating_state,
529
+
.get_clockgating_state = soc24_common_get_clockgating_state,
530
+
};
+30
drivers/gpu/drm/amd/amdgpu/soc24.h
+30
drivers/gpu/drm/amd/amdgpu/soc24.h
···
1
+
/*
2
+
* Copyright 2023 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
#ifndef __SOC24_H__
24
+
#define __SOC24_H__
25
+
26
+
extern const struct amdgpu_ip_block_version soc24_common_ip_block;
27
+
28
+
void soc24_grbm_select(struct amdgpu_device *adev,
29
+
u32 me, u32 pipe, u32 queue, u32 vmid);
30
+
#endif