+13

Documentation/devicetree/bindings/arm/ti/k3.yaml

reviewed

··· 25 25 - ti,am62a7-sk 26 26 - const: ti,am62a7 27 27 28 28 + - description: K3 AM62P5 SoC and Boards 29 29 + items: 30 30 + - enum: 31 31 + - ti,am62p5-sk 32 32 + - const: ti,am62p5 33 33 + 28 34 - description: K3 AM625 SoC PHYTEC phyBOARD-Lyra 29 35 items: 30 36 - const: phytec,am625-phyboard-lyra-rdk ··· 76 70 items: 77 71 - const: phytec,am642-phyboard-electra-rdk 78 72 - const: phytec,am64-phycore-som 73 73 + - const: ti,am642 74 74 + 75 75 + - description: K3 AM642 SoC on TQ-Systems TQMaX4XxL SoM 76 76 + items: 77 77 + - enum: 78 78 + - tq,am642-tqma6442l-mbax4xxl # MBaX4XxL base board 79 79 + - const: tq,am642-tqma6442l 79 80 - const: ti,am642 80 81 81 82 - description: K3 AM654 SoC

+13 -1

Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml

reviewed

··· 66 66 required: 67 67 - compatible 68 68 - reg 69 69 - - power-domains 70 69 - dmas 71 70 - dma-names 71 71 + 72 72 + allOf: 73 73 + - if: 74 74 + properties: 75 75 + compatible: 76 76 + contains: 77 77 + const: ti,am62-sa3ul 78 78 + then: 79 79 + properties: 80 80 + power-domains: false 81 81 + else: 82 82 + required: 83 83 + - power-domains 72 84 73 85 additionalProperties: false 74 86

+7 -2

Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml

reviewed

··· 34 34 - const: ti,am654-navss-ringacc 35 35 36 36 reg: 37 37 + minItems: 4 37 38 items: 38 39 - description: real time registers regions 39 40 - description: fifos registers regions 40 41 - description: proxy gcfg registers regions 41 42 - description: proxy target registers regions 43 43 + - description: configuration registers region 42 44 43 45 reg-names: 46 46 + minItems: 4 44 47 items: 45 48 - const: rt 46 49 - const: fifos 47 50 - const: proxy_gcfg 48 51 - const: proxy_target 52 52 + - const: cfg 49 53 50 54 msi-parent: true 51 55 ··· 84 80 reg = <0x0 0x3c000000 0x0 0x400000>, 85 81 <0x0 0x38000000 0x0 0x400000>, 86 82 <0x0 0x31120000 0x0 0x100>, 87 87 - <0x0 0x33000000 0x0 0x40000>; 88 88 - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 83 83 + <0x0 0x33000000 0x0 0x40000>, 84 84 + <0x0 0x31080000 0x0 0x40000>; 85 85 + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 89 86 ti,num-rings = <818>; 90 87 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ 91 88 ti,sci = <&dmsc>;

+19

arch/arm64/boot/dts/ti/Makefile

reviewed

··· 19 19 dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb 20 20 dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb 21 21 dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb 22 22 + dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo 22 23 23 24 # Boards with AM62Ax SoC 24 25 dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb 26 26 + 27 27 + # Boards with AM62Px SoC 28 28 + dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb 25 29 26 30 # Boards with AM64x SoC 27 31 dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb 28 32 dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb 29 33 dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb 34 34 + dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb 35 35 + 36 36 + k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ 37 37 + k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo 38 38 + k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ 39 39 + k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo 40 40 + 41 41 + dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb 42 42 + dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb 30 43 31 44 # Boards with AM65x SoC 32 45 k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo ··· 59 46 k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo 60 47 dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb 61 48 dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb 49 49 + dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo 62 50 dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb 63 51 64 52 # Boards with J721s2 SoC 65 53 dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb 66 54 dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb 55 55 + dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo 67 56 68 57 # Boards with J784s4 SoC 69 58 dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb 70 59 dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb 71 60 72 61 # Enable support for device-tree overlays 62 62 + DTC_FLAGS_k3-am625-sk += -@ 63 63 + DTC_FLAGS_k3-am62-lp-sk += -@ 73 64 DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ 65 65 + DTC_FLAGS_k3-j721e-common-proc-board += -@ 66 66 + DTC_FLAGS_k3-j721s2-common-proc-board += -@

+47 -5

arch/arm64/boot/dts/ti/k3-am62-main.dtsi

reviewed

··· 55 55 #phy-cells = <1>; 56 56 }; 57 57 58 58 - epwm_tbclk: clock@4130 { 59 59 - compatible = "ti,am62-epwm-tbclk", "syscon"; 58 58 + epwm_tbclk: clock-controller@4130 { 59 59 + compatible = "ti,am62-epwm-tbclk"; 60 60 reg = <0x4130 0x4>; 61 61 #clock-cells = <1>; 62 62 + }; 63 63 + 64 64 + audio_refclk0: clock-controller@82e0 { 65 65 + compatible = "ti,am62-audio-refclk"; 66 66 + reg = <0x82e0 0x4>; 67 67 + clocks = <&k3_clks 157 0>; 68 68 + assigned-clocks = <&k3_clks 157 0>; 69 69 + assigned-clock-parents = <&k3_clks 157 8>; 70 70 + #clock-cells = <0>; 71 71 + }; 72 72 + 73 73 + audio_refclk1: clock-controller@82e4 { 74 74 + compatible = "ti,am62-audio-refclk"; 75 75 + reg = <0x82e4 0x4>; 76 76 + clocks = <&k3_clks 157 10>; 77 77 + assigned-clocks = <&k3_clks 157 10>; 78 78 + assigned-clock-parents = <&k3_clks 157 18>; 79 79 + #clock-cells = <0>; 62 80 }; 63 81 }; 64 82 ··· 192 174 crypto: crypto@40900000 { 193 175 compatible = "ti,am62-sa3ul"; 194 176 reg = <0x00 0x40900000 0x00 0x1200>; 195 195 - power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>; 196 177 #address-cells = <2>; 197 178 #size-cells = <2>; 198 179 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; ··· 607 590 608 591 usb0: usb@31000000 { 609 592 compatible = "snps,dwc3"; 610 610 - reg =<0x00 0x31000000 0x00 0x50000>; 593 593 + reg = <0x00 0x31000000 0x00 0x50000>; 611 594 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 612 595 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 613 596 interrupt-names = "host", "peripheral"; ··· 630 613 631 614 usb1: usb@31100000 { 632 615 compatible = "snps,dwc3"; 633 633 - reg =<0x00 0x31100000 0x00 0x50000>; 616 616 + reg = <0x00 0x31100000 0x00 0x50000>; 634 617 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 635 618 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 636 619 interrupt-names = "host", "peripheral"; ··· 732 715 interrupt-names = "cpts"; 733 716 ti,cpts-ext-ts-inputs = <4>; 734 717 ti,cpts-periodic-outputs = <2>; 718 718 + }; 719 719 + }; 720 720 + 721 721 + dss: dss@30200000 { 722 722 + compatible = "ti,am625-dss"; 723 723 + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ 724 724 + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ 725 725 + <0x00 0x30206000 0x00 0x1000>, /* vid */ 726 726 + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ 727 727 + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ 728 728 + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ 729 729 + <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ 730 730 + reg-names = "common", "vidl1", "vid", 731 731 + "ovr1", "ovr2", "vp1", "vp2"; 732 732 + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 733 733 + clocks = <&k3_clks 186 6>, 734 734 + <&dss_vp1_clk>, 735 735 + <&k3_clks 186 2>; 736 736 + clock-names = "fck", "vp1", "vp2"; 737 737 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 738 738 + status = "disabled"; 739 739 + 740 740 + dss_ports: ports { 741 741 + #address-cells = <1>; 742 742 + #size-cells = <0>; 735 743 }; 736 744 }; 737 745

+24

arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi

reviewed

··· 147 147 /* Tightly coupled to M4F */ 148 148 status = "reserved"; 149 149 }; 150 150 + 151 151 + mcu_mcan0: can@4e08000 { 152 152 + compatible = "bosch,m_can"; 153 153 + reg = <0x00 0x4e08000 0x00 0x200>, 154 154 + <0x00 0x4e00000 0x00 0x8000>; 155 155 + reg-names = "m_can", "message_ram"; 156 156 + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 157 157 + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; 158 158 + clock-names = "hclk", "cclk"; 159 159 + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 160 160 + status = "disabled"; 161 161 + }; 162 162 + 163 163 + mcu_mcan1: can@4e18000 { 164 164 + compatible = "bosch,m_can"; 165 165 + reg = <0x00 0x4e18000 0x00 0x200>, 166 166 + <0x00 0x4e10000 0x00 0x8000>; 167 167 + reg-names = "m_can", "message_ram"; 168 168 + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 169 169 + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; 170 170 + clock-names = "hclk", "cclk"; 171 171 + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 172 172 + status = "disabled"; 173 173 + }; 150 174 };

+58

arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi

reviewed

··· 8 8 * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit 9 9 */ 10 10 11 11 + / { 12 12 + reg_1v8_sw: regulator-1v8-sw { 13 13 + compatible = "regulator-fixed"; 14 14 + regulator-max-microvolt = <1800000>; 15 15 + regulator-min-microvolt = <1800000>; 16 16 + regulator-name = "On-carrier +V1.8_SW"; 17 17 + }; 18 18 + 19 19 + sound { 20 20 + compatible = "simple-audio-card"; 21 21 + simple-audio-card,bitclock-master = <&codec_dai>; 22 22 + simple-audio-card,format = "i2s"; 23 23 + simple-audio-card,frame-master = <&codec_dai>; 24 24 + simple-audio-card,name = "verdin-wm8904"; 25 25 + simple-audio-card,routing = 26 26 + "Headphone Jack", "HPOUTL", 27 27 + "Headphone Jack", "HPOUTR", 28 28 + "IN2L", "Line In Jack", 29 29 + "IN2R", "Line In Jack", 30 30 + "Headphone Jack", "MICBIAS", 31 31 + "IN1L", "Headphone Jack"; 32 32 + simple-audio-card,widgets = 33 33 + "Microphone", "Headphone Jack", 34 34 + "Headphone", "Headphone Jack", 35 35 + "Line", "Line In Jack"; 36 36 + 37 37 + codec_dai: simple-audio-card,codec { 38 38 + clocks = <&audio_refclk1>; 39 39 + sound-dai = <&wm8904_1a>; 40 40 + }; 41 41 + 42 42 + simple-audio-card,cpu { 43 43 + sound-dai = <&mcasp0>; 44 44 + }; 45 45 + }; 46 46 + }; 47 47 + 11 48 /* Verdin ETHs */ 12 49 &cpsw3g { 13 50 status = "okay"; ··· 82 45 /* Verdin I2C_1 */ 83 46 &main_i2c1 { 84 47 status = "okay"; 48 48 + 49 49 + /* Audio Codec */ 50 50 + wm8904_1a: audio-codec@1a { 51 51 + compatible = "wlf,wm8904"; 52 52 + reg = <0x1a>; 53 53 + pinctrl-names = "default"; 54 54 + pinctrl-0 = <&pinctrl_i2s1_mclk>; 55 55 + #sound-dai-cells = <0>; 56 56 + clocks = <&audio_refclk1>; 57 57 + clock-names = "mclk"; 58 58 + AVDD-supply = <&reg_1v8_sw>; 59 59 + CPVDD-supply = <&reg_1v8_sw>; 60 60 + DBVDD-supply = <&reg_1v8_sw>; 61 61 + DCVDD-supply = <&reg_1v8_sw>; 62 62 + MICVDD-supply = <&reg_1v8_sw>; 63 63 + }; 85 64 86 65 /* Current measurement into module VCC */ 87 66 hwmon@40 { ··· 165 112 166 113 /* Verdin I2C_3_HDMI */ 167 114 &mcu_i2c0 { 115 115 + status = "okay"; 116 116 + }; 117 117 + 118 118 + /* Verdin CAN_2 */ 119 119 + &mcu_mcan0 { 168 120 status = "okay"; 169 121 }; 170 122

+50

arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi

reviewed

··· 8 8 * https://www.toradex.com/products/carrier-board/verdin-development-board-kit 9 9 */ 10 10 11 11 + / { 12 12 + sound { 13 13 + compatible = "simple-audio-card"; 14 14 + simple-audio-card,bitclock-master = <&codec_dai>; 15 15 + simple-audio-card,format = "i2s"; 16 16 + simple-audio-card,frame-master = <&codec_dai>; 17 17 + simple-audio-card,name = "verdin-nau8822"; 18 18 + simple-audio-card,routing = 19 19 + "Headphones", "LHP", 20 20 + "Headphones", "RHP", 21 21 + "Speaker", "LSPK", 22 22 + "Speaker", "RSPK", 23 23 + "Line Out", "AUXOUT1", 24 24 + "Line Out", "AUXOUT2", 25 25 + "LAUX", "Line In", 26 26 + "RAUX", "Line In", 27 27 + "LMICP", "Mic In", 28 28 + "RMICP", "Mic In"; 29 29 + simple-audio-card,widgets = 30 30 + "Headphones", "Headphones", 31 31 + "Line Out", "Line Out", 32 32 + "Speaker", "Speaker", 33 33 + "Microphone", "Mic In", 34 34 + "Line", "Line In"; 35 35 + 36 36 + codec_dai: simple-audio-card,codec { 37 37 + clocks = <&audio_refclk1>; 38 38 + sound-dai = <&nau8822_1a>; 39 39 + }; 40 40 + 41 41 + simple-audio-card,cpu { 42 42 + sound-dai = <&mcasp0>; 43 43 + }; 44 44 + }; 45 45 + }; 46 46 + 11 47 /* Verdin ETHs */ 12 48 &cpsw3g { 13 49 pinctrl-names = "default"; ··· 100 64 /* Verdin I2C_1 */ 101 65 &main_i2c1 { 102 66 status = "okay"; 67 67 + 68 68 + /* Audio Codec */ 69 69 + nau8822_1a: audio-codec@1a { 70 70 + compatible = "nuvoton,nau8822"; 71 71 + reg = <0x1a>; 72 72 + pinctrl-names = "default"; 73 73 + pinctrl-0 = <&pinctrl_i2s1_mclk>; 74 74 + #sound-dai-cells = <0>; 75 75 + }; 103 76 104 77 /* IO Expander */ 105 78 gpio_expander_21: gpio@21 { ··· 186 141 187 142 /* Verdin I2C_3_HDMI */ 188 143 &mcu_i2c0 { 144 144 + status = "okay"; 145 145 + }; 146 146 + 147 147 + /* Verdin CAN_2 */ 148 148 + &mcu_mcan0 { 189 149 status = "okay"; 190 150 }; 191 151

+5

arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi

reviewed

··· 167 167 status = "okay"; 168 168 }; 169 169 170 170 + /* Verdin CAN_2 */ 171 171 + &mcu_mcan0 { 172 172 + status = "okay"; 173 173 + }; 174 174 + 170 175 /* Verdin UART_4 */ 171 176 &mcu_uart0 { 172 177 status = "okay";

+43 -2

arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi

reviewed

··· 19 19 }; 20 20 21 21 aliases { 22 22 + can0 = &main_mcan0; 23 23 + can1 = &mcu_mcan0; 22 24 ethernet0 = &cpsw_port1; 23 25 ethernet1 = &cpsw_port2; 24 26 i2c0 = &main_i2c0; ··· 734 732 >; 735 733 }; 736 734 735 735 + /* Verdin CAN_2 */ 736 736 + pinctrl_mcu_mcan0: mcu-mcan0-default-pins { 737 737 + pinctrl-single,pins = < 738 738 + AM62X_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ /* SODIMM 26 */ 739 739 + AM62X_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ /* SODIMM 24 */ 740 740 + >; 741 741 + }; 742 742 + 737 743 /* Verdin UART_4 - Reserved to Cortex-M4 */ 738 744 pinctrl_mcu_uart0: mcu-uart0-default-pins { 739 745 pinctrl-single,pins = < ··· 766 756 AM62X_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ /* SODIMM 139 */ 767 757 >; 768 758 }; 759 759 + }; 760 760 + 761 761 + /* VERDIN I2S_1_MCLK */ 762 762 + &audio_refclk1 { 763 763 + assigned-clock-rates = <25000000>; 769 764 }; 770 765 771 766 &cpsw3g { ··· 812 797 reset-deassert-us = <1000>; 813 798 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 814 799 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 800 800 + }; 801 801 + }; 802 802 + 803 803 + &dss { 804 804 + pinctrl-names = "default"; 805 805 + pinctrl-0 = <&pinctrl_parallel_rgb>; 806 806 + status = "disabled"; 807 807 + }; 808 808 + 809 809 + &dss_ports { 810 810 + #address-cells = <1>; 811 811 + #size-cells = <0>; 812 812 + 813 813 + /* VP2: DPI Output */ 814 814 + port@1 { 815 815 + reg = <1>; 816 816 + 817 817 + dpi_out: endpoint { 818 818 + remote-endpoint = <&rgb_in>; 819 819 + }; 815 820 }; 816 821 }; 817 822 ··· 1071 1036 1072 1037 rgb_in: endpoint { 1073 1038 data-lines = <18>; 1039 1039 + remote-endpoint = <&dpi_out>; 1074 1040 }; 1075 1041 }; 1076 1042 ··· 1274 1238 status = "disabled"; 1275 1239 }; 1276 1240 1277 1277 - /* Verdin CAN_2 - Reserved to Cortex-M4 */ 1278 1278 - 1279 1241 /* Verdin SPI_1 */ 1280 1242 &main_spi1 { 1281 1243 pinctrl-names = "default"; ··· 1365 1331 "", 1366 1332 "", 1367 1333 ""; 1334 1334 + }; 1335 1335 + 1336 1336 + /* Verdin CAN_2 */ 1337 1337 + &mcu_mcan0 { 1338 1338 + pinctrl-names = "default"; 1339 1339 + pinctrl-0 = <&pinctrl_mcu_mcan0>; 1340 1340 + status = "disabled"; 1368 1341 }; 1369 1342 1370 1343 /* Verdin UART_4 - Cortex-M4 UART */

+8

arch/arm64/boot/dts/ti/k3-am62.dtsi

reviewed

··· 102 102 }; 103 103 }; 104 104 105 105 + dss_vp1_clk: clock-divider-oldi { 106 106 + compatible = "fixed-factor-clock"; 107 107 + clocks = <&k3_clks 186 0>; 108 108 + #clock-cells = <0>; 109 109 + clock-div = <7>; 110 110 + clock-mult = <1>; 111 111 + }; 112 112 + 105 113 #include "k3-am62-thermal.dtsi" 106 114 }; 107 115

+152 -2

arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts

reviewed

··· 14 14 #include "k3-am625.dtsi" 15 15 16 16 / { 17 17 - compatible = "beagle,am625-beagleplay", "ti,am625"; 17 17 + compatible = "beagle,am625-beagleplay", "ti,am625"; 18 18 model = "BeagleBoard.org BeaglePlay"; 19 19 20 20 aliases { ··· 190 190 gpios = <&main_gpio0 18 GPIO_ACTIVE_LOW>; 191 191 }; 192 192 193 193 + }; 194 194 + 195 195 + hdmi0: connector-hdmi { 196 196 + compatible = "hdmi-connector"; 197 197 + label = "hdmi"; 198 198 + type = "a"; 199 199 + port { 200 200 + hdmi_connector_in: endpoint { 201 201 + remote-endpoint = <&it66121_out>; 202 202 + }; 203 203 + }; 204 204 + }; 205 205 + 206 206 + sound { 207 207 + compatible = "simple-audio-card"; 208 208 + simple-audio-card,name = "it66121 HDMI"; 209 209 + simple-audio-card,format = "i2s"; 210 210 + simple-audio-card,bitclock-master = <&hdmi_dailink_master>; 211 211 + simple-audio-card,frame-master = <&hdmi_dailink_master>; 212 212 + 213 213 + hdmi_dailink_master: simple-audio-card,cpu { 214 214 + sound-dai = <&mcasp1>; 215 215 + system-clock-direction-out; 216 216 + }; 217 217 + 218 218 + simple-audio-card,codec { 219 219 + sound-dai = <&it66121>; 220 220 + }; 193 221 }; 194 222 195 223 /* Workaround for errata i2329 - just use mdio bitbang */ ··· 450 422 AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */ 451 423 >; 452 424 }; 425 425 + 426 426 + hdmi_gpio_pins_default: hdmi-gpio-default-pins { 427 427 + pinctrl-single,pins = < 428 428 + AM62X_IOPAD(0x0094, PIN_INPUT_PULLUP | PIN_DEBOUNCE_CONF6, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ 429 429 + AM62X_IOPAD(0x0054, PIN_OUTPUT_PULLUP, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ 430 430 + >; 431 431 + }; 432 432 + 433 433 + mcasp_hdmi_pins_default: mcasp-hdmi-default-pins { 434 434 + pinctrl-single,pins = < 435 435 + AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ 436 436 + AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ 437 437 + AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */ 438 438 + AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */ 439 439 + AM62X_IOPAD(0x0084, PIN_INPUT, 2) /* (L23) GPMC0_ADVn_ALE.MCASP1_AXR2 */ 440 440 + AM62X_IOPAD(0x007c, PIN_INPUT, 2) /* (P25) GPMC0_CLK.MCASP1_AXR3 */ 441 441 + >; 442 442 + }; 443 443 + 444 444 + dss0_pins_default: dss0-default-pins { 445 445 + pinctrl-single,pins = < 446 446 + AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ 447 447 + AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ 448 448 + AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ 449 449 + AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ 450 450 + AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ 451 451 + AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ 452 452 + AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ 453 453 + AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ 454 454 + AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ 455 455 + AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ 456 456 + AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ 457 457 + AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ 458 458 + AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ 459 459 + AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ 460 460 + AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ 461 461 + AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ 462 462 + AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ 463 463 + AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ 464 464 + AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ 465 465 + AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ 466 466 + AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ 467 467 + AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ 468 468 + AM62X_IOPAD(0x0064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */ 469 469 + AM62X_IOPAD(0x0068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */ 470 470 + AM62X_IOPAD(0x006c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ 471 471 + AM62X_IOPAD(0x0070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */ 472 472 + AM62X_IOPAD(0x0074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */ 473 473 + AM62X_IOPAD(0x0078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ 474 474 + >; 475 475 + }; 453 476 }; 454 477 455 478 &mcu_pmx0 { ··· 511 432 >; 512 433 }; 513 434 514 514 - gbe_pmx_obsclk: gbe-pmx-clk-default { 435 435 + gbe_pmx_obsclk: gbe-pmx-obsclk-default-pins { 515 436 pinctrl-single,pins = < 516 437 AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */ 517 438 >; ··· 749 670 pinctrl-0 = <&i2c2_1v8_pins_default>; 750 671 clock-frequency = <100000>; 751 672 status = "okay"; 673 673 + 674 674 + it66121: bridge-hdmi@4c { 675 675 + compatible = "ite,it66121"; 676 676 + reg = <0x4c>; 677 677 + pinctrl-names = "default"; 678 678 + pinctrl-0 = <&hdmi_gpio_pins_default>; 679 679 + vcn33-supply = <&vdd_3v3>; 680 680 + vcn18-supply = <&buck2_reg>; 681 681 + vrf12-supply = <&buck3_reg>; 682 682 + reset-gpios = <&main_gpio0 21 GPIO_ACTIVE_LOW>; 683 683 + interrupt-parent = <&main_gpio0>; 684 684 + interrupts = <36 IRQ_TYPE_EDGE_FALLING>; 685 685 + #sound-dai-cells = <0>; 686 686 + 687 687 + ports { 688 688 + #address-cells = <1>; 689 689 + #size-cells = <0>; 690 690 + 691 691 + port@0 { 692 692 + reg = <0>; 693 693 + 694 694 + it66121_in: endpoint { 695 695 + bus-width = <24>; 696 696 + remote-endpoint = <&dpi1_out>; 697 697 + }; 698 698 + }; 699 699 + 700 700 + port@1 { 701 701 + reg = <1>; 702 702 + 703 703 + it66121_out: endpoint { 704 704 + remote-endpoint = <&hdmi_connector_in>; 705 705 + }; 706 706 + }; 707 707 + }; 708 708 + }; 752 709 }; 753 710 754 711 &main_i2c3 { ··· 870 755 pinctrl-names = "default"; 871 756 pinctrl-0 = <&wifi_debug_uart_pins_default>; 872 757 status = "okay"; 758 758 + }; 759 759 + 760 760 + &dss { 761 761 + status = "okay"; 762 762 + pinctrl-names = "default"; 763 763 + pinctrl-0 = <&dss0_pins_default>; 764 764 + }; 765 765 + 766 766 + &dss_ports { 767 767 + /* VP2: DPI Output */ 768 768 + port@1 { 769 769 + reg = <1>; 770 770 + 771 771 + dpi1_out: endpoint { 772 772 + remote-endpoint = <&it66121_in>; 773 773 + }; 774 774 + }; 775 775 + }; 776 776 + 777 777 + &mcasp1 { 778 778 + status = "okay"; 779 779 + #sound-dai-cells = <0>; 780 780 + pinctrl-names = "default"; 781 781 + pinctrl-0 = <&mcasp_hdmi_pins_default>; 782 782 + auxclk-fs-ratio = <2177>; 783 783 + op-mode = <0>; /* MCASP_IIS_MODE */ 784 784 + tdm-slots = <2>; 785 785 + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 786 786 + 1 0 0 0 787 787 + 0 0 0 0 788 788 + 0 0 0 0 789 789 + 0 0 0 0 790 790 + >; 791 791 + tx-num-evt = <32>; 792 792 + rx-num-evt = <32>; 873 793 };

+1 -1

arch/arm64/boot/dts/ti/k3-am625-sk.dts

reviewed

··· 212 212 pinctrl-names = "default"; 213 213 pinctrl-0 = <&ospi0_pins_default>; 214 214 215 215 - flash@0{ 215 215 + flash@0 { 216 216 compatible = "jedec,spi-nor"; 217 217 reg = <0x0>; 218 218 spi-tx-bus-width = <8>;

+5 -5

arch/arm64/boot/dts/ti/k3-am62a-main.dtsi

reviewed

··· 56 56 }; 57 57 58 58 epwm_tbclk: clock-controller@4130 { 59 59 - compatible = "ti,am62-epwm-tbclk", "syscon"; 59 59 + compatible = "ti,am62-epwm-tbclk"; 60 60 reg = <0x4130 0x4>; 61 61 #clock-cells = <1>; 62 62 }; ··· 150 150 reg-names = "debug_messages"; 151 151 ti,host-id = <12>; 152 152 mbox-names = "rx", "tx"; 153 153 - mboxes= <&secure_proxy_main 12>, 154 154 - <&secure_proxy_main 13>; 153 153 + mboxes = <&secure_proxy_main 12>, 154 154 + <&secure_proxy_main 13>; 155 155 156 156 k3_pds: power-controller { 157 157 compatible = "ti,sci-pm-domain"; ··· 527 527 528 528 usb0: usb@31000000 { 529 529 compatible = "snps,dwc3"; 530 530 - reg =<0x00 0x31000000 0x00 0x50000>; 530 530 + reg = <0x00 0x31000000 0x00 0x50000>; 531 531 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 532 532 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 533 533 interrupt-names = "host", "peripheral"; ··· 550 550 551 551 usb1: usb@31100000 { 552 552 compatible = "snps,dwc3"; 553 553 - reg =<0x00 0x31100000 0x00 0x50000>; 553 553 + reg = <0x00 0x31100000 0x00 0x50000>; 554 554 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 555 555 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 556 556 interrupt-names = "host", "peripheral";

+24

arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi

reviewed

··· 143 143 /* Tightly coupled to M4F */ 144 144 status = "reserved"; 145 145 }; 146 146 + 147 147 + mcu_mcan0: can@4e08000 { 148 148 + compatible = "bosch,m_can"; 149 149 + reg = <0x00 0x4e08000 0x00 0x200>, 150 150 + <0x00 0x4e00000 0x00 0x8000>; 151 151 + reg-names = "m_can", "message_ram"; 152 152 + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 153 153 + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; 154 154 + clock-names = "hclk", "cclk"; 155 155 + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 156 156 + status = "disabled"; 157 157 + }; 158 158 + 159 159 + mcu_mcan1: can@4e18000 { 160 160 + compatible = "bosch,m_can"; 161 161 + reg = <0x00 0x4e18000 0x00 0x200>, 162 162 + <0x00 0x4e10000 0x00 0x8000>; 163 163 + reg-names = "m_can", "message_ram"; 164 164 + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 165 165 + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; 166 166 + clock-names = "hclk", "cclk"; 167 167 + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 168 168 + status = "disabled"; 169 169 + }; 146 170 };

+34 -1

arch/arm64/boot/dts/ti/k3-am62a7-sk.dts

reviewed

··· 13 13 #include "k3-am62a7.dtsi" 14 14 15 15 / { 16 16 - compatible = "ti,am62a7-sk", "ti,am62a7"; 16 16 + compatible = "ti,am62a7-sk", "ti,am62a7"; 17 17 model = "Texas Instruments AM62A7 SK"; 18 18 19 19 aliases { ··· 226 226 pinctrl-names = "default"; 227 227 pinctrl-0 = <&main_i2c0_pins_default>; 228 228 clock-frequency = <400000>; 229 229 + 230 230 + typec_pd0: usb-power-controller@3f { 231 231 + compatible = "ti,tps6598x"; 232 232 + reg = <0x3f>; 233 233 + 234 234 + connector { 235 235 + compatible = "usb-c-connector"; 236 236 + label = "USB-C"; 237 237 + self-powered; 238 238 + data-role = "dual"; 239 239 + power-role = "sink"; 240 240 + port { 241 241 + usb_con_hs: endpoint { 242 242 + remote-endpoint = <&usb0_hs_ep>; 243 243 + }; 244 244 + }; 245 245 + }; 246 246 + }; 229 247 }; 230 248 231 249 &main_i2c1 { ··· 306 288 pinctrl-names = "default"; 307 289 pinctrl-0 = <&main_uart1_pins_default>; 308 290 status = "reserved"; 291 291 + }; 292 292 + 293 293 + &usbss0 { 294 294 + status = "okay"; 295 295 + ti,vbus-divider; 296 296 + }; 297 297 + 298 298 + &usb0 { 299 299 + usb-role-switch; 300 300 + 301 301 + port { 302 302 + usb0_hs_ep: endpoint { 303 303 + remote-endpoint = <&usb_con_hs>; 304 304 + }; 305 305 + }; 309 306 }; 310 307 311 308 &usbss1 {

+136

arch/arm64/boot/dts/ti/k3-am62p-main.dtsi

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Device Tree file for the AM62P main domain peripherals 4 4 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 5 5 + */ 6 6 + 7 7 + &cbass_main { 8 8 + oc_sram: sram@70000000 { 9 9 + compatible = "mmio-sram"; 10 10 + reg = <0x00 0x70000000 0x00 0x10000>; 11 11 + #address-cells = <1>; 12 12 + #size-cells = <1>; 13 13 + ranges = <0x00 0x00 0x70000000 0x10000>; 14 14 + }; 15 15 + 16 16 + gic500: interrupt-controller@1800000 { 17 17 + compatible = "arm,gic-v3"; 18 18 + #address-cells = <2>; 19 19 + #size-cells = <2>; 20 20 + ranges; 21 21 + #interrupt-cells = <3>; 22 22 + interrupt-controller; 23 23 + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 24 24 + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 25 25 + <0x01 0x00000000 0x00 0x2000>, /* GICC */ 26 26 + <0x01 0x00010000 0x00 0x1000>, /* GICH */ 27 27 + <0x01 0x00020000 0x00 0x2000>; /* GICV */ 28 28 + /* 29 29 + * vcpumntirq: 30 30 + * virtual CPU interface maintenance interrupt 31 31 + */ 32 32 + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 33 33 + 34 34 + gic_its: msi-controller@1820000 { 35 35 + compatible = "arm,gic-v3-its"; 36 36 + reg = <0x00 0x01820000 0x00 0x10000>; 37 37 + socionext,synquacer-pre-its = <0x1000000 0x400000>; 38 38 + msi-controller; 39 39 + #msi-cells = <1>; 40 40 + }; 41 41 + }; 42 42 + 43 43 + dmss: bus@48000000 { 44 44 + bootph-all; 45 45 + compatible = "simple-mfd"; 46 46 + #address-cells = <2>; 47 47 + #size-cells = <2>; 48 48 + dma-ranges; 49 49 + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 50 50 + 51 51 + ti,sci-dev-id = <25>; 52 52 + 53 53 + secure_proxy_main: mailbox@4d000000 { 54 54 + bootph-all; 55 55 + compatible = "ti,am654-secure-proxy"; 56 56 + #mbox-cells = <1>; 57 57 + reg-names = "target_data", "rt", "scfg"; 58 58 + reg = <0x00 0x4d000000 0x00 0x80000>, 59 59 + <0x00 0x4a600000 0x00 0x80000>, 60 60 + <0x00 0x4a400000 0x00 0x80000>; 61 61 + interrupt-names = "rx_012"; 62 62 + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 63 63 + }; 64 64 + }; 65 65 + 66 66 + dmsc: system-controller@44043000 { 67 67 + bootph-all; 68 68 + compatible = "ti,k2g-sci"; 69 69 + ti,host-id = <12>; 70 70 + mbox-names = "rx", "tx"; 71 71 + mboxes = <&secure_proxy_main 12>, 72 72 + <&secure_proxy_main 13>; 73 73 + reg-names = "debug_messages"; 74 74 + reg = <0x00 0x44043000 0x00 0xfe0>; 75 75 + 76 76 + k3_pds: power-controller { 77 77 + bootph-all; 78 78 + compatible = "ti,sci-pm-domain"; 79 79 + #power-domain-cells = <2>; 80 80 + }; 81 81 + 82 82 + k3_clks: clock-controller { 83 83 + bootph-all; 84 84 + compatible = "ti,k2g-sci-clk"; 85 85 + #clock-cells = <2>; 86 86 + }; 87 87 + 88 88 + k3_reset: reset-controller { 89 89 + bootph-all; 90 90 + compatible = "ti,sci-reset"; 91 91 + #reset-cells = <2>; 92 92 + }; 93 93 + }; 94 94 + 95 95 + main_pmx0: pinctrl@f4000 { 96 96 + bootph-all; 97 97 + compatible = "pinctrl-single"; 98 98 + reg = <0x00 0xf4000 0x00 0x2ac>; 99 99 + #pinctrl-cells = <1>; 100 100 + pinctrl-single,register-width = <32>; 101 101 + pinctrl-single,function-mask = <0xffffffff>; 102 102 + }; 103 103 + 104 104 + main_timer0: timer@2400000 { 105 105 + bootph-all; 106 106 + compatible = "ti,am654-timer"; 107 107 + reg = <0x00 0x2400000 0x00 0x400>; 108 108 + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 109 109 + clocks = <&k3_clks 36 2>; 110 110 + clock-names = "fck"; 111 111 + assigned-clocks = <&k3_clks 36 2>; 112 112 + assigned-clock-parents = <&k3_clks 36 3>; 113 113 + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 114 114 + ti,timer-pwm; 115 115 + }; 116 116 + 117 117 + main_uart0: serial@2800000 { 118 118 + compatible = "ti,am64-uart", "ti,am654-uart"; 119 119 + reg = <0x00 0x02800000 0x00 0x100>; 120 120 + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 121 121 + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 122 122 + clocks = <&k3_clks 146 0>; 123 123 + clock-names = "fclk"; 124 124 + status = "disabled"; 125 125 + }; 126 126 + 127 127 + main_uart1: serial@2810000 { 128 128 + compatible = "ti,am64-uart", "ti,am654-uart"; 129 129 + reg = <0x00 0x02810000 0x00 0x100>; 130 130 + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 131 131 + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 132 132 + clocks = <&k3_clks 152 0>; 133 133 + clock-names = "fclk"; 134 134 + status = "disabled"; 135 135 + }; 136 136 + };

+15

arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Device Tree file for the AM62P MCU domain peripherals 4 4 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 5 5 + */ 6 6 + 7 7 + &cbass_mcu { 8 8 + mcu_pmx0: pinctrl@4084000 { 9 9 + compatible = "pinctrl-single"; 10 10 + reg = <0x00 0x04084000 0x00 0x88>; 11 11 + #pinctrl-cells = <1>; 12 12 + pinctrl-single,register-width = <32>; 13 13 + pinctrl-single,function-mask = <0xffffffff>; 14 14 + }; 15 15 + };

+32

arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Device Tree file for the AM62P wakeup domain peripherals 4 4 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 5 5 + */ 6 6 + 7 7 + &cbass_wakeup { 8 8 + wkup_conf: bus@43000000 { 9 9 + bootph-all; 10 10 + compatible = "simple-bus"; 11 11 + reg = <0x00 0x43000000 0x00 0x20000>; 12 12 + #address-cells = <1>; 13 13 + #size-cells = <1>; 14 14 + ranges = <0x00 0x00 0x43000000 0x20000>; 15 15 + 16 16 + chipid: chipid@14 { 17 17 + bootph-all; 18 18 + compatible = "ti,am654-chipid"; 19 19 + reg = <0x14 0x4>; 20 20 + }; 21 21 + }; 22 22 + 23 23 + wkup_uart0: serial@2b300000 { 24 24 + compatible = "ti,am64-uart", "ti,am654-uart"; 25 25 + reg = <0x00 0x2b300000 0x00 0x100>; 26 26 + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 27 27 + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 28 28 + clocks = <&k3_clks 114 0>; 29 29 + clock-names = "fclk"; 30 30 + status = "disabled"; 31 31 + }; 32 32 + };

+122

arch/arm64/boot/dts/ti/k3-am62p.dtsi

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Device Tree Source for AM62P SoC Family 4 4 + * 5 5 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 6 6 + */ 7 7 + 8 8 + #include <dt-bindings/gpio/gpio.h> 9 9 + #include <dt-bindings/interrupt-controller/irq.h> 10 10 + #include <dt-bindings/interrupt-controller/arm-gic.h> 11 11 + #include <dt-bindings/soc/ti,sci_pm_domain.h> 12 12 + 13 13 + #include "k3-pinctrl.h" 14 14 + 15 15 + / { 16 16 + model = "Texas Instruments K3 AM62P5 SoC"; 17 17 + compatible = "ti,am62p5"; 18 18 + interrupt-parent = <&gic500>; 19 19 + #address-cells = <2>; 20 20 + #size-cells = <2>; 21 21 + 22 22 + firmware { 23 23 + optee { 24 24 + compatible = "linaro,optee-tz"; 25 25 + method = "smc"; 26 26 + }; 27 27 + 28 28 + psci: psci { 29 29 + compatible = "arm,psci-1.0"; 30 30 + method = "smc"; 31 31 + }; 32 32 + }; 33 33 + 34 34 + a53_timer0: timer-cl0-cpu0 { 35 35 + compatible = "arm,armv8-timer"; 36 36 + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 37 37 + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 38 38 + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 39 39 + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 40 40 + }; 41 41 + 42 42 + pmu: pmu { 43 43 + compatible = "arm,cortex-a53-pmu"; 44 44 + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 45 45 + }; 46 46 + 47 47 + cbass_main: bus@f0000 { 48 48 + bootph-all; 49 49 + compatible = "simple-bus"; 50 50 + #address-cells = <2>; 51 51 + #size-cells = <2>; 52 52 + 53 53 + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ 54 54 + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ 55 55 + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 56 56 + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ 57 57 + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ 58 58 + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ 59 59 + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ 60 60 + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ 61 61 + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ 62 62 + <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ 63 63 + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ 64 64 + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ 65 65 + <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ 66 66 + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ 67 67 + <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ 68 68 + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ 69 69 + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ 70 70 + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ 71 71 + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ 72 72 + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ 73 73 + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ 74 74 + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ 75 75 + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ 76 76 + <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ 77 77 + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ 78 78 + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ 79 79 + 80 80 + /* MCU Domain Range */ 81 81 + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, 82 82 + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, 83 83 + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, 84 84 + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, 85 85 + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, 86 86 + 87 87 + /* Wakeup Domain Range */ 88 88 + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, 89 89 + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, 90 90 + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, 91 91 + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, 92 92 + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; 93 93 + 94 94 + cbass_mcu: bus@4000000 { 95 95 + compatible = "simple-bus"; 96 96 + #address-cells = <2>; 97 97 + #size-cells = <2>; 98 98 + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ 99 99 + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ 100 100 + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ 101 101 + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ 102 102 + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ 103 103 + }; 104 104 + 105 105 + cbass_wakeup: bus@b00000 { 106 106 + bootph-all; 107 107 + compatible = "simple-bus"; 108 108 + #address-cells = <2>; 109 109 + #size-cells = <2>; 110 110 + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ 111 111 + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ 112 112 + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ 113 113 + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ 114 114 + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ 115 115 + }; 116 116 + }; 117 117 + }; 118 118 + 119 119 + /* Now include peripherals for each bus segment */ 120 120 + #include "k3-am62p-main.dtsi" 121 121 + #include "k3-am62p-mcu.dtsi" 122 122 + #include "k3-am62p-wakeup.dtsi"

+116

arch/arm64/boot/dts/ti/k3-am62p5-sk.dts

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Device Tree file for the AM62P5-SK 4 4 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 5 5 + * 6 6 + * Schematics: https://www.ti.com/lit/zip/sprr487 7 7 + */ 8 8 + 9 9 + /dts-v1/; 10 10 + 11 11 + #include "k3-am62p5.dtsi" 12 12 + 13 13 + / { 14 14 + compatible = "ti,am62p5-sk", "ti,am62p5"; 15 15 + model = "Texas Instruments AM62P5 SK"; 16 16 + 17 17 + aliases { 18 18 + serial0 = &wkup_uart0; 19 19 + serial2 = &main_uart0; 20 20 + serial3 = &main_uart1; 21 21 + }; 22 22 + 23 23 + chosen { 24 24 + stdout-path = &main_uart0; 25 25 + }; 26 26 + 27 27 + memory@80000000 { 28 28 + /* 8G RAM */ 29 29 + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 30 30 + <0x00000008 0x80000000 0x00000001 0x80000000>; 31 31 + device_type = "memory"; 32 32 + }; 33 33 + 34 34 + reserved-memory { 35 35 + #address-cells = <2>; 36 36 + #size-cells = <2>; 37 37 + ranges; 38 38 + 39 39 + secure_tfa_ddr: tfa@9e780000 { 40 40 + reg = <0x00 0x9e780000 0x00 0x80000>; 41 41 + no-map; 42 42 + }; 43 43 + 44 44 + secure_ddr: optee@9e800000 { 45 45 + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 46 46 + no-map; 47 47 + }; 48 48 + 49 49 + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { 50 50 + compatible = "shared-dma-pool"; 51 51 + reg = <0x00 0x9c900000 0x00 0x01e00000>; 52 52 + no-map; 53 53 + }; 54 54 + }; 55 55 + }; 56 56 + 57 57 + &main_pmx0 { 58 58 + main_uart0_pins_default: main-uart0-default-pins { 59 59 + bootph-all; 60 60 + pinctrl-single,pins = < 61 61 + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ 62 62 + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ 63 63 + AM62PX_IOPAD(0x1d0, PIN_INPUT, 0) /* (A23) UART0_CTSn */ 64 64 + AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0) /* (C22) UART0_RTSn */ 65 65 + >; 66 66 + }; 67 67 + 68 68 + main_uart1_pins_default: main-uart1-default-pins { 69 69 + bootph-all; 70 70 + pinctrl-single,pins = < 71 71 + AM62PX_IOPAD(0x194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3 */ 72 72 + AM62PX_IOPAD(0x198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2 */ 73 73 + AM62PX_IOPAD(0x1ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR */ 74 74 + AM62PX_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR */ 75 75 + >; 76 76 + }; 77 77 + }; 78 78 + 79 79 + &main_uart0 { 80 80 + bootph-all; 81 81 + pinctrl-names = "default"; 82 82 + pinctrl-0 = <&main_uart0_pins_default>; 83 83 + status = "okay"; 84 84 + }; 85 85 + 86 86 + &main_uart1 { 87 87 + pinctrl-names = "default"; 88 88 + pinctrl-0 = <&main_uart1_pins_default>; 89 89 + /* Main UART1 is used by TIFS firmware */ 90 90 + status = "reserved"; 91 91 + }; 92 92 + 93 93 + &cbass_mcu { 94 94 + bootph-all; 95 95 + }; 96 96 + 97 97 + &mcu_pmx0 { 98 98 + bootph-all; 99 99 + wkup_uart0_pins_default: wkup-uart0-default-pins { 100 100 + bootph-all; 101 101 + pinctrl-single,pins = < 102 102 + AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ 103 103 + AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ 104 104 + AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ 105 105 + AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ 106 106 + >; 107 107 + }; 108 108 + }; 109 109 + 110 110 + &wkup_uart0 { 111 111 + /* WKUP UART0 is used by DM firmware */ 112 112 + bootph-all; 113 113 + pinctrl-names = "default"; 114 114 + pinctrl-0 = <&wkup_uart0_pins_default>; 115 115 + status = "reserved"; 116 116 + };

+107

arch/arm64/boot/dts/ti/k3-am62p5.dtsi

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Device Tree file for the AM62P5 SoC family (quad core) 4 4 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 5 5 + * 6 6 + * TRM: https://www.ti.com/lit/pdf/spruj83 7 7 + */ 8 8 + 9 9 + /dts-v1/; 10 10 + 11 11 + #include "k3-am62p.dtsi" 12 12 + 13 13 + / { 14 14 + cpus { 15 15 + #address-cells = <1>; 16 16 + #size-cells = <0>; 17 17 + 18 18 + cpu-map { 19 19 + cluster0: cluster0 { 20 20 + core0 { 21 21 + cpu = <&cpu0>; 22 22 + }; 23 23 + 24 24 + core1 { 25 25 + cpu = <&cpu1>; 26 26 + }; 27 27 + 28 28 + core2 { 29 29 + cpu = <&cpu2>; 30 30 + }; 31 31 + 32 32 + core3 { 33 33 + cpu = <&cpu3>; 34 34 + }; 35 35 + }; 36 36 + }; 37 37 + 38 38 + cpu0: cpu@0 { 39 39 + compatible = "arm,cortex-a53"; 40 40 + reg = <0x000>; 41 41 + device_type = "cpu"; 42 42 + enable-method = "psci"; 43 43 + i-cache-size = <0x8000>; 44 44 + i-cache-line-size = <64>; 45 45 + i-cache-sets = <256>; 46 46 + d-cache-size = <0x8000>; 47 47 + d-cache-line-size = <64>; 48 48 + d-cache-sets = <128>; 49 49 + next-level-cache = <&l2_0>; 50 50 + clocks = <&k3_clks 135 0>; 51 51 + }; 52 52 + 53 53 + cpu1: cpu@1 { 54 54 + compatible = "arm,cortex-a53"; 55 55 + reg = <0x001>; 56 56 + device_type = "cpu"; 57 57 + enable-method = "psci"; 58 58 + i-cache-size = <0x8000>; 59 59 + i-cache-line-size = <64>; 60 60 + i-cache-sets = <256>; 61 61 + d-cache-size = <0x8000>; 62 62 + d-cache-line-size = <64>; 63 63 + d-cache-sets = <128>; 64 64 + next-level-cache = <&l2_0>; 65 65 + clocks = <&k3_clks 136 0>; 66 66 + }; 67 67 + 68 68 + cpu2: cpu@2 { 69 69 + compatible = "arm,cortex-a53"; 70 70 + reg = <0x002>; 71 71 + device_type = "cpu"; 72 72 + enable-method = "psci"; 73 73 + i-cache-size = <0x8000>; 74 74 + i-cache-line-size = <64>; 75 75 + i-cache-sets = <256>; 76 76 + d-cache-size = <0x8000>; 77 77 + d-cache-line-size = <64>; 78 78 + d-cache-sets = <128>; 79 79 + next-level-cache = <&l2_0>; 80 80 + clocks = <&k3_clks 137 0>; 81 81 + }; 82 82 + 83 83 + cpu3: cpu@3 { 84 84 + compatible = "arm,cortex-a53"; 85 85 + reg = <0x003>; 86 86 + device_type = "cpu"; 87 87 + enable-method = "psci"; 88 88 + i-cache-size = <0x8000>; 89 89 + i-cache-line-size = <64>; 90 90 + i-cache-sets = <256>; 91 91 + d-cache-size = <0x8000>; 92 92 + d-cache-line-size = <64>; 93 93 + d-cache-sets = <128>; 94 94 + next-level-cache = <&l2_0>; 95 95 + clocks = <&k3_clks 138 0>; 96 96 + }; 97 97 + }; 98 98 + 99 99 + l2_0: l2-cache0 { 100 100 + compatible = "cache"; 101 101 + cache-unified; 102 102 + cache-level = <2>; 103 103 + cache-size = <0x80000>; 104 104 + cache-line-size = <64>; 105 105 + cache-sets = <512>; 106 106 + }; 107 107 + };

+92 -1

arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi

reviewed

··· 114 114 clocks = <&tlv320_mclk>; 115 115 }; 116 116 }; 117 117 + 118 118 + hdmi0: connector-hdmi { 119 119 + compatible = "hdmi-connector"; 120 120 + label = "hdmi"; 121 121 + type = "a"; 122 122 + port { 123 123 + hdmi_connector_in: endpoint { 124 124 + remote-endpoint = <&sii9022_out>; 125 125 + }; 126 126 + }; 127 127 + }; 117 128 }; 118 129 119 130 &main_pmx0 { ··· 237 226 AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */ 238 227 >; 239 228 }; 229 229 + 230 230 + main_dss0_pins_default: main-dss0-default-pins { 231 231 + pinctrl-single,pins = < 232 232 + AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ 233 233 + AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ 234 234 + AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ 235 235 + AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ 236 236 + AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ 237 237 + AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ 238 238 + AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ 239 239 + AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ 240 240 + AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ 241 241 + AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ 242 242 + AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ 243 243 + AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ 244 244 + AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ 245 245 + AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ 246 246 + AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ 247 247 + AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ 248 248 + AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ 249 249 + AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ 250 250 + AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ 251 251 + AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ 252 252 + AM62X_IOPAD(0x05c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ 253 253 + AM62X_IOPAD(0x060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ 254 254 + AM62X_IOPAD(0x064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */ 255 255 + AM62X_IOPAD(0x068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */ 256 256 + AM62X_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ 257 257 + AM62X_IOPAD(0x070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */ 258 258 + AM62X_IOPAD(0x074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */ 259 259 + AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ 260 260 + >; 261 261 + }; 240 262 }; 241 263 242 264 &mcu_pmx0 { ··· 344 300 status = "okay"; 345 301 pinctrl-names = "default"; 346 302 pinctrl-0 = <&main_i2c1_pins_default>; 347 347 - clock-frequency = <400000>; 303 303 + clock-frequency = <100000>; 348 304 349 305 tlv320aic3106: audio-codec@1b { 350 306 #sound-dai-cells = <0>; ··· 356 312 AVDD-supply = <&vcc_3v3_sys>; 357 313 IOVDD-supply = <&vcc_3v3_sys>; 358 314 DRVDD-supply = <&vcc_3v3_sys>; 315 315 + }; 316 316 + 317 317 + sii9022: bridge-hdmi@3b { 318 318 + compatible = "sil,sii9022"; 319 319 + reg = <0x3b>; 320 320 + interrupt-parent = <&exp1>; 321 321 + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 322 322 + #sound-dai-cells = <0>; 323 323 + sil,i2s-data-lanes = < 0 >; 324 324 + 325 325 + ports { 326 326 + #address-cells = <1>; 327 327 + #size-cells = <0>; 328 328 + 329 329 + port@0 { 330 330 + reg = <0>; 331 331 + 332 332 + sii9022_in: endpoint { 333 333 + remote-endpoint = <&dpi1_out>; 334 334 + }; 335 335 + }; 336 336 + 337 337 + port@1 { 338 338 + reg = <1>; 339 339 + 340 340 + sii9022_out: endpoint { 341 341 + remote-endpoint = <&hdmi_connector_in>; 342 342 + }; 343 343 + }; 344 344 + }; 359 345 }; 360 346 }; 361 347 ··· 483 409 >; 484 410 tx-num-evt = <32>; 485 411 rx-num-evt = <32>; 412 412 + }; 413 413 + 414 414 + &dss { 415 415 + status = "okay"; 416 416 + pinctrl-names = "default"; 417 417 + pinctrl-0 = <&main_dss0_pins_default>; 418 418 + }; 419 419 + 420 420 + &dss_ports { 421 421 + /* VP2: DPI Output */ 422 422 + port@1 { 423 423 + reg = <1>; 424 424 + 425 425 + dpi1_out: endpoint { 426 426 + remote-endpoint = <&sii9022_in>; 427 427 + }; 428 428 + }; 486 429 };

+40

arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /** 3 3 + * Audio playback via HDMI for AM625-SK and AM62-LP SK. 4 4 + * 5 5 + * Links: 6 6 + * AM625 SK: https://www.ti.com/tool/SK-AM62 7 7 + * AM62-LP SK: https://www.ti.com/tool/SK-AM62-LP 8 8 + * 9 9 + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ 10 10 + */ 11 11 + 12 12 + /dts-v1/; 13 13 + /plugin/; 14 14 + 15 15 + &{/} { 16 16 + hdmi_audio: sound-sii9022 { 17 17 + compatible = "simple-audio-card"; 18 18 + simple-audio-card,name = "AM62x-Sil9022-HDMI"; 19 19 + simple-audio-card,format = "i2s"; 20 20 + simple-audio-card,bitclock-master = <&hdmi_dailink_master>; 21 21 + simple-audio-card,frame-master = <&hdmi_dailink_master>; 22 22 + 23 23 + hdmi_dailink_master: simple-audio-card,cpu { 24 24 + sound-dai = <&mcasp1>; 25 25 + system-clock-direction-out; 26 26 + }; 27 27 + 28 28 + simple-audio-card,codec { 29 29 + sound-dai = <&sii9022>; 30 30 + }; 31 31 + }; 32 32 + }; 33 33 + 34 34 + &mcasp1 { 35 35 + auxclk-fs-ratio = <2177>; 36 36 + }; 37 37 + 38 38 + &codec_audio { 39 39 + status = "disabled"; 40 40 + };

+21 -27

arch/arm64/boot/dts/ti/k3-am64-main.dtsi

reviewed

··· 44 44 #size-cells = <1>; 45 45 ranges = <0x0 0x0 0x43000000 0x20000>; 46 46 47 47 + chipid@14 { 48 48 + compatible = "ti,am654-chipid"; 49 49 + reg = <0x00000014 0x4>; 50 50 + }; 51 51 + 47 52 serdes_ln_ctrl: mux-controller { 48 53 compatible = "mmio-mux"; 49 54 #mux-control-cells = <1>; 50 55 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ 56 56 + }; 57 57 + 58 58 + phy_gmii_sel: phy@4044 { 59 59 + compatible = "ti,am654-phy-gmii-sel"; 60 60 + reg = <0x4044 0x8>; 61 61 + #phy-cells = <1>; 62 62 + }; 63 63 + 64 64 + epwm_tbclk: clock-controller@4140 { 65 65 + compatible = "ti,am64-epwm-tbclk"; 66 66 + reg = <0x4130 0x4>; 67 67 + #clock-cells = <1>; 51 68 }; 52 69 }; 53 70 ··· 218 201 #pinctrl-cells = <1>; 219 202 pinctrl-single,register-width = <32>; 220 203 pinctrl-single,function-mask = <0xffffffff>; 221 221 - }; 222 222 - 223 223 - main_conf: syscon@43000000 { 224 224 - compatible = "syscon", "simple-mfd"; 225 225 - reg = <0x00 0x43000000 0x00 0x20000>; 226 226 - #address-cells = <1>; 227 227 - #size-cells = <1>; 228 228 - ranges = <0x00 0x00 0x43000000 0x20000>; 229 229 - 230 230 - chipid@14 { 231 231 - compatible = "ti,am654-chipid"; 232 232 - reg = <0x00000014 0x4>; 233 233 - }; 234 234 - 235 235 - phy_gmii_sel: phy@4044 { 236 236 - compatible = "ti,am654-phy-gmii-sel"; 237 237 - reg = <0x4044 0x8>; 238 238 - #phy-cells = <1>; 239 239 - }; 240 240 - 241 241 - epwm_tbclk: clock@4140 { 242 242 - compatible = "ti,am64-epwm-tbclk", "syscon"; 243 243 - reg = <0x4130 0x4>; 244 244 - #clock-cells = <1>; 245 245 - }; 246 204 }; 247 205 248 206 main_timer0: timer@2400000 { ··· 725 733 pinctrl-single,function-mask = <0x000107ff>; 726 734 }; 727 735 728 728 - usbss0: cdns-usb@f900000{ 736 736 + usbss0: cdns-usb@f900000 { 729 737 compatible = "ti,am64-usb"; 730 738 reg = <0x00 0xf900000 0x00 0x100>; 731 739 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; ··· 736 744 #address-cells = <2>; 737 745 #size-cells = <2>; 738 746 ranges; 739 739 - usb0: usb@f400000{ 747 747 + usb0: usb@f400000 { 740 748 compatible = "cdns,usb3"; 741 749 reg = <0x00 0xf400000 0x00 0x10000>, 742 750 <0x00 0xf410000 0x00 0x10000>, ··· 765 773 assigned-clock-parents = <&k3_clks 0 3>; 766 774 assigned-clock-rates = <60000000>; 767 775 clock-names = "fck"; 776 776 + status = "disabled"; 768 777 769 778 adc { 770 779 #io-channel-cells = <1>; ··· 795 802 assigned-clock-parents = <&k3_clks 75 7>; 796 803 assigned-clock-rates = <166666666>; 797 804 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 805 805 + status = "disabled"; 798 806 }; 799 807 }; 800 808

+1

arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi

reviewed

··· 181 181 }; 182 182 183 183 &ospi0 { 184 184 + status = "okay"; 184 185 pinctrl-names = "default"; 185 186 pinctrl-0 = <&ospi0_pins_default>; 186 187

+22

arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany. 4 4 + */ 5 5 + 6 6 + /dts-v1/; 7 7 + /plugin/; 8 8 + 9 9 + &sdhci1 { 10 10 + vmmc-supply = <&reg_sd>; 11 11 + no-sdio; 12 12 + status = "okay"; 13 13 + }; 14 14 + 15 15 + &main_gpio0 { 16 16 + line43-hog { 17 17 + gpio-hog; 18 18 + gpios = <43 0>; 19 19 + line-name = "MMC1_CTRL"; 20 20 + output-low; 21 21 + }; 22 22 + };

+22

arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany. 4 4 + */ 5 5 + 6 6 + /dts-v1/; 7 7 + /plugin/; 8 8 + 9 9 + &sdhci1 { 10 10 + mmc-pwrseq = <&wifi_pwrseq>; 11 11 + no-sd; 12 12 + status = "okay"; 13 13 + }; 14 14 + 15 15 + &main_gpio0 { 16 16 + line43-hog { 17 17 + gpio-hog; 18 18 + gpios = <43 0>; 19 19 + line-name = "MMC1_CTRL"; 20 20 + output-high; 21 21 + }; 22 22 + };

+3 -1

arch/arm64/boot/dts/ti/k3-am642-evm.dts

reviewed

··· 6 6 /dts-v1/; 7 7 8 8 #include <dt-bindings/phy/phy.h> 9 9 - #include <dt-bindings/mux/ti-serdes.h> 10 9 #include <dt-bindings/leds/common.h> 11 10 #include <dt-bindings/gpio/gpio.h> 12 11 #include <dt-bindings/net/ti-dp83867.h> 13 12 #include "k3-am642.dtsi" 13 13 + 14 14 + #include "k3-serdes.h" 14 15 15 16 / { 16 17 compatible = "ti,am642-evm", "ti,am642"; ··· 520 519 }; 521 520 522 521 &ospi0 { 522 522 + status = "okay"; 523 523 pinctrl-names = "default"; 524 524 pinctrl-0 = <&ospi0_pins_default>; 525 525

+2 -1

arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts

reviewed

··· 16 16 #include <dt-bindings/input/input.h> 17 17 #include <dt-bindings/leds/common.h> 18 18 #include <dt-bindings/leds/leds-pca9532.h> 19 19 - #include <dt-bindings/mux/ti-serdes.h> 20 19 #include <dt-bindings/phy/phy.h> 21 20 #include "k3-am642.dtsi" 22 21 #include "k3-am64-phycore-som.dtsi" 22 22 + 23 23 + #include "k3-serdes.h" 23 24 24 25 / { 25 26 compatible = "phytec,am642-phyboard-electra-rdk",

+3 -5

arch/arm64/boot/dts/ti/k3-am642-sk.dts

reviewed

··· 5 5 6 6 /dts-v1/; 7 7 8 8 - #include <dt-bindings/mux/ti-serdes.h> 9 8 #include <dt-bindings/phy/phy.h> 10 9 #include <dt-bindings/gpio/gpio.h> 11 10 #include <dt-bindings/net/ti-dp83867.h> 12 11 #include <dt-bindings/leds/common.h> 13 12 #include "k3-am642.dtsi" 13 13 + 14 14 + #include "k3-serdes.h" 14 15 15 16 / { 16 17 compatible = "ti,am642-sk", "ti,am642"; ··· 513 512 }; 514 513 }; 515 514 516 516 - &tscadc0 { 517 517 - status = "disabled"; 518 518 - }; 519 519 - 520 515 &ospi0 { 516 516 + status = "okay"; 521 517 pinctrl-names = "default"; 522 518 pinctrl-0 = <&ospi0_pins_default>; 523 519

+872

arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 4 + * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany. 5 5 + */ 6 6 + 7 7 + /dts-v1/; 8 8 + 9 9 + #include <dt-bindings/gpio/gpio.h> 10 10 + #include <dt-bindings/input/input.h> 11 11 + #include <dt-bindings/net/ti-dp83867.h> 12 12 + #include <dt-bindings/phy/phy.h> 13 13 + #include <dt-bindings/pwm/pwm.h> 14 14 + #include "k3-serdes.h" 15 15 + 16 16 + #include "k3-am642-tqma64xxl.dtsi" 17 17 + 18 18 + / { 19 19 + compatible = "tq,am642-tqma6442l-mbax4xxl", "tq,am642-tqma6442l", 20 20 + "ti,am642"; 21 21 + model = "TQ-Systems TQMa64xxL SoM on MBax4xxL carrier board"; 22 22 + 23 23 + aliases { 24 24 + ethernet0 = &cpsw_port1; 25 25 + i2c1 = &mcu_i2c0; 26 26 + mmc1 = &sdhci1; 27 27 + serial0 = &mcu_uart0; 28 28 + serial1 = &mcu_uart1; 29 29 + serial2 = &main_uart0; 30 30 + serial3 = &main_uart1; 31 31 + serial4 = &main_uart2; 32 32 + serial5 = &main_uart4; 33 33 + serial6 = &main_uart5; 34 34 + serial7 = &main_uart3; 35 35 + spi1 = &main_spi0; 36 36 + spi2 = &mcu_spi0; 37 37 + }; 38 38 + 39 39 + chosen { 40 40 + stdout-path = &main_uart0; 41 41 + }; 42 42 + 43 43 + gpio-keys { 44 44 + compatible = "gpio-keys"; 45 45 + pinctrl-names = "default"; 46 46 + pinctrl-0 = <&mcu_gpio_keys_pins>; 47 47 + 48 48 + user-button { 49 49 + label = "USER_BUTTON"; 50 50 + linux,code = <BTN_0>; 51 51 + gpios = <&mcu_gpio0 5 GPIO_ACTIVE_LOW>; 52 52 + }; 53 53 + }; 54 54 + 55 55 + gpio-leds { 56 56 + compatible = "gpio-leds"; 57 57 + pinctrl-names = "default"; 58 58 + pinctrl-0 = <&mcu_gpio_leds_pins>; 59 59 + 60 60 + led-0 { 61 61 + label = "led0"; 62 62 + gpios = <&mcu_gpio0 8 GPIO_ACTIVE_HIGH>; 63 63 + }; 64 64 + led-1 { 65 65 + label = "led1"; 66 66 + gpios = <&mcu_gpio0 9 GPIO_ACTIVE_HIGH>; 67 67 + }; 68 68 + }; 69 69 + 70 70 + fan0: pwm-fan { 71 71 + compatible = "pwm-fan"; 72 72 + pinctrl-names = "default"; 73 73 + pinctrl-0 = <&pwm_fan_pins>; 74 74 + fan-supply = <&reg_pwm_fan>; 75 75 + #cooling-cells = <2>; 76 76 + /* typical 25 kHz -> 40.000 nsec */ 77 77 + pwms = <&epwm5 0 40000 PWM_POLARITY_INVERTED>; 78 78 + cooling-levels = <0 32 64 128 196 240>; 79 79 + pulses-per-revolution = <2>; 80 80 + interrupt-parent = <&main_gpio1>; 81 81 + interrupts = <49 IRQ_TYPE_EDGE_FALLING>; 82 82 + status = "disabled"; 83 83 + }; 84 84 + 85 85 + wifi_pwrseq: pwrseq-wifi { 86 86 + compatible = "mmc-pwrseq-simple"; 87 87 + pinctrl-names = "default"; 88 88 + pinctrl-0 = <&main_mmc1_wifi_pwrseq_pins>; 89 89 + reset-gpios = <&main_gpio0 23 GPIO_ACTIVE_LOW>; 90 90 + }; 91 91 + 92 92 + reg_pwm_fan: regulator-pwm-fan { 93 93 + compatible = "regulator-fixed"; 94 94 + pinctrl-names = "default"; 95 95 + pinctrl-0 = <&pwm_fan_reg_pins>; 96 96 + regulator-name = "FAN_PWR"; 97 97 + regulator-min-microvolt = <12000000>; 98 98 + regulator-max-microvolt = <12000000>; 99 99 + gpio = <&main_gpio1 48 GPIO_ACTIVE_HIGH>; 100 100 + enable-active-high; 101 101 + }; 102 102 + 103 103 + reg_sd: regulator-sd { 104 104 + compatible = "regulator-fixed"; 105 105 + pinctrl-names = "default"; 106 106 + pinctrl-0 = <&main_mmc1_reg_pins>; 107 107 + regulator-name = "V_3V3_SD"; 108 108 + regulator-min-microvolt = <3300000>; 109 109 + regulator-max-microvolt = <3300000>; 110 110 + gpio = <&main_gpio1 43 GPIO_ACTIVE_HIGH>; 111 111 + enable-active-high; 112 112 + }; 113 113 + }; 114 114 + 115 115 + &cpsw3g { 116 116 + pinctrl-names = "default"; 117 117 + pinctrl-0 = <&cpsw_pins>; 118 118 + }; 119 119 + 120 120 + &cpsw_port1 { 121 121 + phy-mode = "rgmii-rxid"; 122 122 + phy-handle = <&cpsw3g_phy0>; 123 123 + }; 124 124 + 125 125 + &cpsw_port2 { 126 126 + status = "disabled"; 127 127 + }; 128 128 + 129 129 + &cpsw3g_mdio { 130 130 + pinctrl-names = "default"; 131 131 + pinctrl-0 = <&cpsw_mdio_pins>; 132 132 + status = "okay"; 133 133 + 134 134 + cpsw3g_phy0: ethernet-phy@0 { 135 135 + compatible = "ethernet-phy-ieee802.3-c22"; 136 136 + reg = <0>; 137 137 + reset-gpios = <&main_gpio0 44 GPIO_ACTIVE_LOW>; 138 138 + reset-assert-us = <1000>; 139 139 + reset-deassert-us = <1000>; 140 140 + ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 141 141 + ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 142 142 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 143 143 + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 144 144 + }; 145 145 + }; 146 146 + 147 147 + &epwm5 { 148 148 + pinctrl-names = "default"; 149 149 + pinctrl-0 = <&epwm5_pins>; 150 150 + status = "okay"; 151 151 + }; 152 152 + 153 153 + &main_gpio0 { 154 154 + pinctrl-names = "default"; 155 155 + pinctrl-0 = <&main_gpio0_digital_pins>, 156 156 + <&main_gpio0_hog_pins>; 157 157 + gpio-line-names = 158 158 + "", "", "", "", /* 0-3 */ 159 159 + "", "", "", "", /* 4-7 */ 160 160 + "", "", "", "", /* 8-11 */ 161 161 + "", "", "", "", /* 12-15 */ 162 162 + "", "", "", "", /* 16-19 */ 163 163 + "", "", "", "", /* 20-23 */ 164 164 + "", "", "EN_DIG_OUT_1", "STATUS_OUT_1", /* 24-27 */ 165 165 + "EN_DIG_OUT_2", "STATUS_OUT_2", "EN_SIG_OUT_3", "", /* 28-31 */ 166 166 + "", "", "STATUS_OUT_3", "EN_DIG_OUT_4", /* 32-35 */ 167 167 + "", "", "STATUS_OUT_4", "DIG_IN_1", /* 36-39 */ 168 168 + "DIG_IN_2", "DIG_IN_3", "DIG_IN_4"; /* 40- */ 169 169 + }; 170 170 + 171 171 + &main_gpio1 { 172 172 + pinctrl-names = "default"; 173 173 + pinctrl-0 = <&main_gpio1_hog_pins>; 174 174 + gpio-line-names = 175 175 + "", "", "", "", /* 0-3 */ 176 176 + "", "", "", "", /* 4-7 */ 177 177 + "", "", "", "", /* 8-11 */ 178 178 + "", "", "", "", /* 12-15 */ 179 179 + "", "", "", "", /* 16-19 */ 180 180 + "", "", "", "", /* 20-23 */ 181 181 + "", "", "", "", /* 24-27 */ 182 182 + "", "", "", "", /* 28-31 */ 183 183 + "", "", "", "", /* 32-35 */ 184 184 + "", "", "", "", /* 36-39 */ 185 185 + "", "", "", "", /* 40-43 */ 186 186 + "", "", "", "", /* 44-47 */ 187 187 + "", "", "", "", /* 48-51 */ 188 188 + "", "", "", "ADC_SYNC", /* 52-55 */ 189 189 + "", "", "ADC_RST#", "ADC_DATA_RDY", /* 56-59 */ 190 190 + "", "", "", "", /* 60-63 */ 191 191 + "", "", "", "ADC_INT#", /* 64-67 */ 192 192 + "BG95_PWRKEY", "BG95_RESET"; /* 68- */ 193 193 + 194 194 + line50-hog { 195 195 + /* See also usb0 */ 196 196 + gpio-hog; 197 197 + gpios = <50 0>; 198 198 + line-name = "USB0_VBUS_OC#"; 199 199 + input; 200 200 + }; 201 201 + 202 202 + line54-hog { 203 203 + gpio-hog; 204 204 + gpios = <54 0>; 205 205 + line-name = "PRG0_MDIO_SWITCH"; 206 206 + output-low; 207 207 + }; 208 208 + 209 209 + line70-hog { 210 210 + gpio-hog; 211 211 + gpios = <70 0>; 212 212 + line-name = "PHY_INT#"; 213 213 + input; 214 214 + }; 215 215 + }; 216 216 + 217 217 + &main_mcan0 { 218 218 + pinctrl-names = "default"; 219 219 + pinctrl-0 = <&main_mcan0_pins>; 220 220 + status = "okay"; 221 221 + }; 222 222 + 223 223 + &main_mcan1 { 224 224 + pinctrl-names = "default"; 225 225 + pinctrl-0 = <&main_mcan1_pins>; 226 226 + status = "okay"; 227 227 + }; 228 228 + 229 229 + &main_spi0 { 230 230 + pinctrl-names = "default"; 231 231 + pinctrl-0 = <&main_spi0_pins>; 232 232 + ti,pindir-d0-out-d1-in; 233 233 + status = "okay"; 234 234 + 235 235 + /* adc@0: NXP NAFE13388 */ 236 236 + }; 237 237 + 238 238 + /* UART/USB adapter port 1 */ 239 239 + &main_uart0 { 240 240 + pinctrl-names = "default"; 241 241 + pinctrl-0 = <&main_uart0_pins>; 242 242 + status = "okay"; 243 243 + }; 244 244 + 245 245 + /* 246 246 + * IOT Module - GNSS UART 247 247 + * 248 248 + * Note: We expect usage of a SYSFW that does not reserve UART1 for debug traces 249 249 + */ 250 250 + &main_uart1 { 251 251 + pinctrl-names = "default"; 252 252 + pinctrl-0 = <&main_uart1_pins>; 253 253 + status = "okay"; 254 254 + }; 255 255 + 256 256 + /* RS485 port */ 257 257 + &main_uart2 { 258 258 + pinctrl-names = "default"; 259 259 + pinctrl-0 = <&main_uart2_pins>; 260 260 + linux,rs485-enabled-at-boot-time; 261 261 + rs485-rts-active-low; 262 262 + status = "okay"; 263 263 + }; 264 264 + 265 265 + /* Bluetooth module */ 266 266 + &main_uart3 { 267 267 + pinctrl-names = "default"; 268 268 + pinctrl-0 = <&main_uart3_pins>; 269 269 + /* 270 270 + * Left disabled for now, until a way to deal with drivers and firmware 271 271 + * for the combined WLAN/BT module has been figured out 272 272 + */ 273 273 + }; 274 274 + 275 275 + /* IOT module - Main UART */ 276 276 + &main_uart4 { 277 277 + pinctrl-names = "default"; 278 278 + pinctrl-0 = <&main_uart4_pins>; 279 279 + status = "okay"; 280 280 + }; 281 281 + 282 282 + /* IOT module - DBG UART */ 283 283 + &main_uart5 { 284 284 + pinctrl-names = "default"; 285 285 + pinctrl-0 = <&main_uart5_pins>; 286 286 + status = "okay"; 287 287 + }; 288 288 + 289 289 + &main0_thermal { 290 290 + trips { 291 291 + main0_active0: trip-active0 { 292 292 + temperature = <40000>; 293 293 + hysteresis = <5000>; 294 294 + type = "active"; 295 295 + }; 296 296 + 297 297 + main0_active1: trip-active1 { 298 298 + temperature = <48000>; 299 299 + hysteresis = <3000>; 300 300 + type = "active"; 301 301 + }; 302 302 + 303 303 + main0_active2: trip-active2 { 304 304 + temperature = <60000>; 305 305 + hysteresis = <10000>; 306 306 + type = "active"; 307 307 + }; 308 308 + }; 309 309 + 310 310 + cooling-maps { 311 311 + map1 { 312 312 + trip = <&main0_active0>; 313 313 + cooling-device = <&fan0 1 1>; 314 314 + }; 315 315 + 316 316 + map2 { 317 317 + trip = <&main0_active1>; 318 318 + cooling-device = <&fan0 2 2>; 319 319 + }; 320 320 + 321 321 + map3 { 322 322 + trip = <&main0_active2>; 323 323 + cooling-device = <&fan0 3 3>; 324 324 + }; 325 325 + }; 326 326 + }; 327 327 + 328 328 + &main1_thermal { 329 329 + trips { 330 330 + main1_active0: trip-active0 { 331 331 + temperature = <40000>; 332 332 + hysteresis = <5000>; 333 333 + type = "active"; 334 334 + }; 335 335 + 336 336 + main1_active1: trip-active1 { 337 337 + temperature = <48000>; 338 338 + hysteresis = <3000>; 339 339 + type = "active"; 340 340 + }; 341 341 + 342 342 + main1_active2: trip-active2 { 343 343 + temperature = <60000>; 344 344 + hysteresis = <10000>; 345 345 + type = "active"; 346 346 + }; 347 347 + }; 348 348 + 349 349 + cooling-maps { 350 350 + map1 { 351 351 + trip = <&main1_active0>; 352 352 + cooling-device = <&fan0 1 1>; 353 353 + }; 354 354 + 355 355 + map2 { 356 356 + trip = <&main1_active1>; 357 357 + cooling-device = <&fan0 2 2>; 358 358 + }; 359 359 + 360 360 + map3 { 361 361 + trip = <&main1_active2>; 362 362 + cooling-device = <&fan0 3 3>; 363 363 + }; 364 364 + }; 365 365 + }; 366 366 + 367 367 + &mcu_gpio0 { 368 368 + pinctrl-names = "default"; 369 369 + pinctrl-0 = <&mcu_gpio0_pins>; 370 370 + }; 371 371 + 372 372 + &mcu_i2c0 { 373 373 + pinctrl-names = "default"; 374 374 + pinctrl-0 = <&mcu_i2c0_pins>; 375 375 + /* Left disabled: not functional without external pullup */ 376 376 + }; 377 377 + 378 378 + &mcu_spi0 { 379 379 + pinctrl-names = "default"; 380 380 + pinctrl-0 = <&mcu_spi0_pins>; 381 381 + ti,pindir-d0-out-d1-in; 382 382 + status = "okay"; 383 383 + }; 384 384 + 385 385 + /* UART/USB adapter port 2 */ 386 386 + &mcu_uart0 { 387 387 + pinctrl-names = "default"; 388 388 + pinctrl-0 = <&mcu_uart0_pins>; 389 389 + status = "okay"; 390 390 + }; 391 391 + 392 392 + /* Pin header */ 393 393 + &mcu_uart1 { 394 394 + pinctrl-names = "default"; 395 395 + pinctrl-0 = <&mcu_uart1_pins>; 396 396 + status = "okay"; 397 397 + }; 398 398 + 399 399 + &serdes_ln_ctrl { 400 400 + idle-states = <AM64_SERDES0_LANE0_USB>; 401 401 + }; 402 402 + 403 403 + &serdes0 { 404 404 + serdes0_usb_link: phy@0 { 405 405 + reg = <0>; 406 406 + #phy-cells = <0>; 407 407 + resets = <&serdes_wiz0 1>; 408 408 + cdns,num-lanes = <1>; 409 409 + cdns,phy-type = <PHY_TYPE_USB3>; 410 410 + }; 411 411 + }; 412 412 + 413 413 + &sdhci1 { 414 414 + pinctrl-names = "default"; 415 415 + pinctrl-0 = <&main_mmc1_pins>; 416 416 + bus-width = <4>; 417 417 + cd-gpios = <&main_gpio1 77 GPIO_ACTIVE_LOW>; 418 418 + disable-wp; 419 419 + no-mmc; 420 420 + ti,driver-strength-ohm = <50>; 421 421 + ti,fails-without-test-cd; 422 422 + /* Enabled by overlay */ 423 423 + status = "disabled"; 424 424 + }; 425 425 + 426 426 + &tscadc0 { 427 427 + status = "okay"; 428 428 + adc { 429 429 + ti,adc-channels = <0 1 2 3 4 5 6 7>; 430 430 + }; 431 431 + }; 432 432 + 433 433 + &usb0 { 434 434 + /* 435 435 + * The CDNS USB driver currently doesn't support overcurrent GPIOs, 436 436 + * so there is no overcurrent detection. The OC pin is configured 437 437 + * as a GPIO hog instead. 438 438 + */ 439 439 + pinctrl-names = "default"; 440 440 + pinctrl-0 = <&main_usb0_pins>; 441 441 + dr_mode = "otg"; 442 442 + maximum-speed = "super-speed"; 443 443 + phys = <&serdes0_usb_link>; 444 444 + phy-names = "cdns3,usb3-phy"; 445 445 + }; 446 446 + 447 447 + &usbss0 { 448 448 + ti,vbus-divider; 449 449 + }; 450 450 + 451 451 + &main_pmx0 { 452 452 + cpsw_pins: cpsw-pins { 453 453 + pinctrl-single,pins = < 454 454 + /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ 455 455 + AM64X_IOPAD(0x01cc, PIN_INPUT, 4) 456 456 + /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ 457 457 + AM64X_IOPAD(0x01d4, PIN_INPUT, 4) 458 458 + /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ 459 459 + AM64X_IOPAD(0x01d8, PIN_INPUT, 4) 460 460 + /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ 461 461 + AM64X_IOPAD(0x01f4, PIN_INPUT, 4) 462 462 + /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ 463 463 + AM64X_IOPAD(0x0188, PIN_INPUT, 4) 464 464 + /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ 465 465 + AM64X_IOPAD(0x0184, PIN_INPUT, 4) 466 466 + /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 467 467 + AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) 468 468 + /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 469 469 + AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) 470 470 + /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 471 471 + AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) 472 472 + /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 473 473 + AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) 474 474 + /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 475 475 + AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) 476 476 + /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 477 477 + AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) 478 478 + >; 479 479 + }; 480 480 + 481 481 + cpsw_mdio_pins: cpsw-mdio-pins { 482 482 + pinctrl-single,pins = < 483 483 + /* (R21) GPMC0_CSn3.GPIO0_44 - RESET_RGMII1# */ 484 484 + AM64X_IOPAD(0x00b4, PIN_OUTPUT, 7) 485 485 + 486 486 + /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 487 487 + AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) 488 488 + /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 489 489 + AM64X_IOPAD(0x01f8, PIN_INPUT, 4) 490 490 + >; 491 491 + }; 492 492 + 493 493 + epwm5_pins: epwm5-pins { 494 494 + pinctrl-single,pins = < 495 495 + /* (W19) GPMC0_WAIT0.EHRPWM5_B */ 496 496 + AM64X_IOPAD(0x0098, PIN_OUTPUT, 3) 497 497 + >; 498 498 + }; 499 499 + 500 500 + /* Digital IOs */ 501 501 + main_gpio0_digital_pins: main-gpio0-digital-pins { 502 502 + pinctrl-single,pins = < 503 503 + /* (W20) GPMC0_AD11.GPIO0_26 - EN_DIG_OUT_1 */ 504 504 + AM64X_IOPAD(0x0068, PIN_OUTPUT, 7) 505 505 + /* (W21) GPMC0_AD12.GPIO0_27 - STATUS_OUT_1 */ 506 506 + AM64X_IOPAD(0x006c, PIN_INPUT, 7) 507 507 + /* (V18) GPMC0_AD13.GPIO0_28 - EN_DIG_OUT_2 */ 508 508 + AM64X_IOPAD(0x0070, PIN_OUTPUT, 7) 509 509 + /* (Y21) GPMC0_AD14.GPIO0_29 - STATUS_OUT_2 */ 510 510 + AM64X_IOPAD(0x0074, PIN_INPUT, 7) 511 511 + /* (Y20) GPMC0_AD15.GPIO0_30 - EN_DIG_OUT_3 */ 512 512 + AM64X_IOPAD(0x0078, PIN_OUTPUT, 7) 513 513 + /* (T21) GPMC0_WEn.GPIO0_34 - STATUS_OUT_3 */ 514 514 + AM64X_IOPAD(0x008c, PIN_INPUT, 7) 515 515 + /* (P17) GPMC0_BE0n_CLE.GPIO0_35 - EN_DIG_OUT_4 */ 516 516 + AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) 517 517 + /* (Y18) GPMC0_WAIT1.GPIO0_38 - STATUS_OUT_4 */ 518 518 + AM64X_IOPAD(0x009c, PIN_INPUT, 7) 519 519 + /* (N16) GPMC0_WPn.GPIO0_39 - DIG_IN_1 */ 520 520 + AM64X_IOPAD(0x00a0, PIN_INPUT, 7) 521 521 + /* (N17) GPMC0_DIR.GPIO0_40 - DIG_IN_2 */ 522 522 + AM64X_IOPAD(0x00a4, PIN_INPUT, 7) 523 523 + /* (R19) GPMC0_CSn0.GPIO0_41 - DIG_IN_3 */ 524 524 + AM64X_IOPAD(0x00a8, PIN_INPUT, 7) 525 525 + /* (R20) GPMC0_CSn1.GPIO0_42 - DIG_IN_4 */ 526 526 + AM64X_IOPAD(0x00ac, PIN_INPUT, 7) 527 527 + >; 528 528 + }; 529 529 + 530 530 + main_gpio0_hog_pins: main-gpio0-hog-pins { 531 531 + pinctrl-single,pins = < 532 532 + /* (P19) GPMC0_CSn2.GPIO0_43 - MMC1_CTRL */ 533 533 + AM64X_IOPAD(0x00b0, PIN_OUTPUT, 7) 534 534 + >; 535 535 + }; 536 536 + 537 537 + main_gpio1_hog_pins: main-gpio1-hog-pins { 538 538 + pinctrl-single,pins = < 539 539 + /* (B15) SPI1_D0.GPIO1_50 - USB0_VBUS_OC# */ 540 540 + AM64X_IOPAD(0x0228, PIN_INPUT, 7) 541 541 + /* (B16) UART0_CTSn.GPIO1_54 - PRG0_MDIO_SWITCH */ 542 542 + AM64X_IOPAD(0x0238, PIN_OUTPUT, 7) 543 543 + /* (C19) EXTINTn.GPIO1_70 - PHY_INT# */ 544 544 + AM64X_IOPAD(0x0278, PIN_INPUT, 7) 545 545 + >; 546 546 + }; 547 547 + 548 548 + main_mcan0_pins: main-mcan0-pins { 549 549 + pinctrl-single,pins = < 550 550 + /* (B17) MCAN0_RX */ 551 551 + AM64X_IOPAD(0x0254, PIN_INPUT, 0) 552 552 + /* (A17) MCAN0_TX */ 553 553 + AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) 554 554 + >; 555 555 + }; 556 556 + 557 557 + main_mcan1_pins: main-mcan1-pins { 558 558 + pinctrl-single,pins = < 559 559 + /* (D17) MCAN1_RX */ 560 560 + AM64X_IOPAD(0x025c, PIN_INPUT, 0) 561 561 + /* (C17) MCAN1_TX */ 562 562 + AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) 563 563 + >; 564 564 + }; 565 565 + 566 566 + main_mmc1_pins: main-mmc1-pins { 567 567 + pinctrl-single,pins = < 568 568 + /* (J19) MMC1_CMD */ 569 569 + AM64X_IOPAD(0x0294, PIN_INPUT, 0) 570 570 + /* (L20) MMC1_CLK */ 571 571 + AM64X_IOPAD(0x028c, PIN_INPUT, 0) 572 572 + /* (K21) MMC1_DAT0 */ 573 573 + AM64X_IOPAD(0x0288, PIN_INPUT, 0) 574 574 + /* (L21) MMC1_DAT1 */ 575 575 + AM64X_IOPAD(0x0284, PIN_INPUT, 0) 576 576 + /* (K19) MMC1_DAT2 */ 577 577 + AM64X_IOPAD(0x0280, PIN_INPUT, 0) 578 578 + /* (K18) MMC1_DAT3 */ 579 579 + AM64X_IOPAD(0x027c, PIN_INPUT, 0) 580 580 + /* (D19) MMC1_SDCD.GPIO1_77 */ 581 581 + AM64X_IOPAD(0x0298, PIN_INPUT, 7) 582 582 + /* (#N/A) MMC1_CLKLB */ 583 583 + AM64X_IOPAD(0x0290, PIN_INPUT, 0) 584 584 + >; 585 585 + }; 586 586 + 587 587 + main_mmc1_reg_pins: main-mmc1-reg-pins { 588 588 + pinctrl-single,pins = < 589 589 + /* (C13) SPI0_CS1.GPIO1_43 - MMC1_SD_EN */ 590 590 + AM64X_IOPAD(0x020c, PIN_OUTPUT, 7) 591 591 + >; 592 592 + }; 593 593 + 594 594 + main_mmc1_wifi_pwrseq_pins: main-mmc1-wifi-pwrseq-pins { 595 595 + pinctrl-single,pins = < 596 596 + /* (V19) GPMC0_AD8.GPIO0_23 - WIFI-BT_EN */ 597 597 + AM64X_IOPAD(0x005c, PIN_OUTPUT, 7) 598 598 + >; 599 599 + }; 600 600 + 601 601 + main_spi0_pins: main-spi0-pins { 602 602 + pinctrl-single,pins = < 603 603 + /* (D13) SPI0_CLK */ 604 604 + AM64X_IOPAD(0x0210, PIN_OUTPUT, 0) 605 605 + /* (D12) SPI0_CS0 */ 606 606 + AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) 607 607 + /* (A13) SPI0_D0 */ 608 608 + AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) 609 609 + /* (A14) SPI0_D1 */ 610 610 + AM64X_IOPAD(0x0218, PIN_INPUT, 0) 611 611 + >; 612 612 + }; 613 613 + 614 614 + main_spi0_adc_pins: main-spi0-adc-pins { 615 615 + pinctrl-single,pins = < 616 616 + /* (A16) UART0_RTSn.GPIO1_55 - ADC_SYNC */ 617 617 + AM64X_IOPAD(0x023c, PIN_INPUT, 7) 618 618 + /* (D16) UART1_CTSn.GPIO1_58 - ADC_RST# */ 619 619 + AM64X_IOPAD(0x0248, PIN_OUTPUT, 7) 620 620 + /* (E16) UART1_RTSn.GPIO1_59 - ADC_DATA_RDY */ 621 621 + AM64X_IOPAD(0x024c, PIN_INPUT, 7) 622 622 + /* (B19) I2C1_SDA.GPIO1_67 - ADC_INT# */ 623 623 + AM64X_IOPAD(0x026c, PIN_INPUT, 7) 624 624 + >; 625 625 + }; 626 626 + 627 627 + main_uart0_pins: main-uart0-pins { 628 628 + pinctrl-single,pins = < 629 629 + /* (D15) UART0_RXD */ 630 630 + AM64X_IOPAD(0x0230, PIN_INPUT, 0) 631 631 + /* (C16) UART0_TXD */ 632 632 + AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) 633 633 + >; 634 634 + }; 635 635 + 636 636 + main_uart1_pins: main-uart1-pins { 637 637 + pinctrl-single,pins = < 638 638 + /* (E15) UART1_RXD */ 639 639 + AM64X_IOPAD(0x0240, PIN_INPUT, 0) 640 640 + /* (E14) UART1_TXD */ 641 641 + AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) 642 642 + >; 643 643 + }; 644 644 + 645 645 + main_uart2_pins: main-uart2-pins { 646 646 + pinctrl-single,pins = < 647 647 + /* (T18) GPMC0_AD2.UART2_RTSn */ 648 648 + AM64X_IOPAD(0x0044, PIN_OUTPUT, 2) 649 649 + /* (T20) GPMC0_AD0.UART2_RXD */ 650 650 + AM64X_IOPAD(0x003c, PIN_INPUT, 2) 651 651 + /* (U21) GPMC0_AD1.UART2_TXD */ 652 652 + AM64X_IOPAD(0x0040, PIN_OUTPUT, 2) 653 653 + >; 654 654 + }; 655 655 + 656 656 + main_uart3_pins: main-uart3-pins { 657 657 + pinctrl-single,pins = < 658 658 + /* (T17) GPMC0_AD9.UART3_CTSn */ 659 659 + AM64X_IOPAD(0x0060, PIN_INPUT, 2) 660 660 + /* (U19) GPMC0_AD5.UART3_RTSn */ 661 661 + AM64X_IOPAD(0x0050, PIN_OUTPUT, 2) 662 662 + /* (U20) GPMC0_AD3.UART3_RXD */ 663 663 + AM64X_IOPAD(0x0048, PIN_INPUT, 2) 664 664 + /* (U18) GPMC0_AD4.UART3_TXD */ 665 665 + AM64X_IOPAD(0x004c, PIN_OUTPUT, 2) 666 666 + >; 667 667 + }; 668 668 + 669 669 + main_uart4_pins: main-uart4-pins { 670 670 + pinctrl-single,pins = < 671 671 + /* (R16) GPMC0_AD10.UART4_CTSn */ 672 672 + AM64X_IOPAD(0x0064, PIN_INPUT, 2) 673 673 + /* (R17) GPMC0_CLK.UART4_RTSn */ 674 674 + AM64X_IOPAD(0x007c, PIN_OUTPUT, 2) 675 675 + /* (V20) GPMC0_AD6.UART4_RXD */ 676 676 + AM64X_IOPAD(0x0054, PIN_INPUT, 2) 677 677 + /* (V21) GPMC0_AD7.UART4_TXD */ 678 678 + AM64X_IOPAD(0x0058, PIN_OUTPUT, 2) 679 679 + 680 680 + /* Control GPIOs for IOT Module connected to UART4 */ 681 681 + /* (D18) ECAP0_IN_APWM_OUT.GPIO1_68 - BG95_PWRKEY */ 682 682 + AM64X_IOPAD(0x0270, PIN_OUTPUT, 7) 683 683 + /* (A19) EXT_REFCLK1.GPIO1_69 - BG95_RESET */ 684 684 + AM64X_IOPAD(0x0274, PIN_OUTPUT, 7) 685 685 + >; 686 686 + }; 687 687 + 688 688 + main_uart5_pins: main-uart5-pins { 689 689 + pinctrl-single,pins = < 690 690 + /* (P16) GPMC0_ADVn_ALE.UART5_RXD */ 691 691 + AM64X_IOPAD(0x0084, PIN_INPUT, 2) 692 692 + /* (R18) GPMC0_OEn_REn.UART5_TXD */ 693 693 + AM64X_IOPAD(0x0088, PIN_OUTPUT, 2) 694 694 + >; 695 695 + }; 696 696 + 697 697 + main_usb0_pins: main-usb0-pins { 698 698 + pinctrl-single,pins = < 699 699 + /* (E19) USB0_DRVVBUS */ 700 700 + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) 701 701 + >; 702 702 + }; 703 703 + 704 704 + pru_icssg1_mdio_pins: pru-icssg1-mdio-pins { 705 705 + pinctrl-single,pins = < 706 706 + /* (A15) SPI1_D1.GPIO1_51 - RESET_PRG1_RGMII1# */ 707 707 + AM64X_IOPAD(0x022c, PIN_OUTPUT, 7) 708 708 + /* (B14) SPI1_CS0.GPIO1_47 - RESET_PRG1_RGMII2# */ 709 709 + AM64X_IOPAD(0x021c, PIN_OUTPUT, 7) 710 710 + 711 711 + /* (Y6) PRG1_MDIO0_MDC */ 712 712 + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) 713 713 + /* (AA6) PRG1_MDIO0_MDIO */ 714 714 + AM64X_IOPAD(0x0158, PIN_INPUT, 0) 715 715 + >; 716 716 + }; 717 717 + 718 718 + pru_icssg1_rgmii1_pins: pru-icssg1-rgmii1-pins { 719 719 + pinctrl-single,pins = < 720 720 + /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ 721 721 + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) 722 722 + /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ 723 723 + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) 724 724 + /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ 725 725 + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) 726 726 + /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ 727 727 + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) 728 728 + /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ 729 729 + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) 730 730 + /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ 731 731 + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) 732 732 + /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ 733 733 + AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) 734 734 + /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ 735 735 + AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) 736 736 + /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ 737 737 + AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) 738 738 + /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ 739 739 + AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) 740 740 + /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ 741 741 + AM64X_IOPAD(0x00f8, PIN_OUTPUT, 2) 742 742 + /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ 743 743 + AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) 744 744 + >; 745 745 + }; 746 746 + 747 747 + pru_icssg1_rgmii2_pins: pru-icssg1-rgmii2-pins { 748 748 + pinctrl-single,pins = < 749 749 + /* (W11) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */ 750 750 + AM64X_IOPAD(0x0108, PIN_INPUT, 2) 751 751 + /* (V11) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */ 752 752 + AM64X_IOPAD(0x010c, PIN_INPUT, 2) 753 753 + /* (AA12) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */ 754 754 + AM64X_IOPAD(0x0110, PIN_INPUT, 2) 755 755 + /* (Y12) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */ 756 756 + AM64X_IOPAD(0x0114, PIN_INPUT, 2) 757 757 + /* (U11) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */ 758 758 + AM64X_IOPAD(0x0120, PIN_INPUT, 2) 759 759 + /* (W12) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */ 760 760 + AM64X_IOPAD(0x0118, PIN_INPUT, 2) 761 761 + /* (AA10) PRG1_PRU1_GPO11.PRG1_RGMII2_TD0 */ 762 762 + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) 763 763 + /* (V10) PRG1_PRU1_GPO12.PRG1_RGMII2_TD1 */ 764 764 + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) 765 765 + /* (U10) PRG1_PRU1_GPO13.PRG1_RGMII2_TD2 */ 766 766 + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) 767 767 + /* (AA11) PRG1_PRU1_GPO14.PRG1_RGMII2_TD3 */ 768 768 + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) 769 769 + /* (Y10) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */ 770 770 + AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) 771 771 + /* (Y11) PRG1_PRU1_GPO15.PRG1_RGMII2_TX_CTL */ 772 772 + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) 773 773 + >; 774 774 + }; 775 775 + 776 776 + pwm_fan_pins: pwm-fan-pins { 777 777 + pinctrl-single,pins = < 778 778 + /* (T19) GPMC0_BE1n.EHRPWM5_A */ 779 779 + AM64X_IOPAD(0x0094, PIN_OUTPUT, 3) 780 780 + /* (C14) SPI1_CLK.GPIO1_49 - FAN_RPM */ 781 781 + AM64X_IOPAD(0x0224, PIN_INPUT, 7) 782 782 + >; 783 783 + }; 784 784 + 785 785 + pwm_fan_reg_pins: pwm-fan-reg-pins { 786 786 + pinctrl-single,pins = < 787 787 + /* (D14) SPI1_CS1.GPIO1_48 - FAN_PWR */ 788 788 + AM64X_IOPAD(0x0220, PIN_OUTPUT, 7) 789 789 + >; 790 790 + }; 791 791 + }; 792 792 + 793 793 + &mcu_pmx0 { 794 794 + mcu_gpio_keys_pins: mcu-gpio-keys-pins { 795 795 + pinctrl-single,pins = < 796 796 + /* (A7) MCU_SPI1_CS0.MCU_GPIO0_5 */ 797 797 + AM64X_MCU_IOPAD(0x0014, PIN_INPUT, 7) 798 798 + >; 799 799 + }; 800 800 + 801 801 + mcu_gpio_leds_pins: mcu-gpio-leds-pins { 802 802 + pinctrl-single,pins = < 803 803 + /* (C7) MCU_SPI1_D0.MCU_GPIO0_8 */ 804 804 + AM64X_MCU_IOPAD(0x0020, PIN_OUTPUT, 7) 805 805 + /* (C8) MCU_SPI1_D1.MCU_GPIO0_9 */ 806 806 + AM64X_MCU_IOPAD(0x0024, PIN_OUTPUT, 7) 807 807 + >; 808 808 + }; 809 809 + 810 810 + mcu_gpio0_pins: mcu-gpio0-pins { 811 811 + pinctrl-single,pins = < 812 812 + /* (E8) MCU_UART0_RTSn.MCU_GPIO0_0 */ 813 813 + AM64X_MCU_IOPAD(0x0034, PIN_INPUT, 7) 814 814 + /* (D8) MCU_UART0_CTSn.MCU_GPIO0_1 */ 815 815 + AM64X_MCU_IOPAD(0x0030, PIN_INPUT, 7) 816 816 + /* (B7) MCU_SPI1_CS1.MCU_GPIO0_6 */ 817 817 + AM64X_MCU_IOPAD(0x0018, PIN_INPUT, 7) 818 818 + /* (D7) MCU_SPI1_CLK.MCU_GPIO0_7 */ 819 819 + AM64X_MCU_IOPAD(0x001c, PIN_INPUT, 7) 820 820 + /* (A11) MCU_I2C1_SCL.MCU_GPIO0_20 */ 821 821 + AM64X_MCU_IOPAD(0x0050, PIN_INPUT, 7) 822 822 + /* (B10) MCU_I2C1_SDA.MCU_GPIO0_21 */ 823 823 + AM64X_MCU_IOPAD(0x0054, PIN_INPUT, 7) 824 824 + >; 825 825 + }; 826 826 + 827 827 + mcu_i2c0_pins: mcu-i2c0-pins { 828 828 + pinctrl-single,pins = < 829 829 + /* (E9) MCU_I2C0_SCL */ 830 830 + AM64X_MCU_IOPAD(0x0048, PIN_INPUT, 0) 831 831 + /* (A10) MCU_I2C0_SDA */ 832 832 + AM64X_MCU_IOPAD(0x004c, PIN_INPUT, 0) 833 833 + >; 834 834 + }; 835 835 + 836 836 + mcu_spi0_pins: mcu-spi0-pins { 837 837 + pinctrl-single,pins = < 838 838 + /* (E6) MCU_SPI0_CLK */ 839 839 + AM64X_MCU_IOPAD(0x0008, PIN_OUTPUT, 0) 840 840 + /* (D6) MCU_SPI0_CS0 */ 841 841 + AM64X_MCU_IOPAD(0x0000, PIN_OUTPUT, 0) 842 842 + /* (C6) MCU_SPI0_CS1 */ 843 843 + AM64X_MCU_IOPAD(0x0004, PIN_OUTPUT, 0) 844 844 + /* (E7) MCU_SPI0_D0 */ 845 845 + AM64X_MCU_IOPAD(0x000c, PIN_OUTPUT, 0) 846 846 + /* (B6) MCU_SPI0_D1 */ 847 847 + AM64X_MCU_IOPAD(0x0010, PIN_INPUT, 0) 848 848 + >; 849 849 + }; 850 850 + 851 851 + mcu_uart0_pins: mcu-uart0-pins { 852 852 + pinctrl-single,pins = < 853 853 + /* (A9) MCU_UART0_RXD */ 854 854 + AM64X_MCU_IOPAD(0x0028, PIN_INPUT, 0) 855 855 + /* (A8) MCU_UART0_TXD */ 856 856 + AM64X_MCU_IOPAD(0x002c, PIN_OUTPUT, 0) 857 857 + >; 858 858 + }; 859 859 + 860 860 + mcu_uart1_pins: mcu-uart1-pins { 861 861 + pinctrl-single,pins = < 862 862 + /* (B8) MCU_UART1_CTSn */ 863 863 + AM64X_MCU_IOPAD(0x0040, PIN_INPUT, 0) 864 864 + /* (B9) MCU_UART1_RTSn */ 865 865 + AM64X_MCU_IOPAD(0x0044, PIN_OUTPUT, 0) 866 866 + /* (C9) MCU_UART1_RXD */ 867 867 + AM64X_MCU_IOPAD(0x0038, PIN_INPUT, 0) 868 868 + /* (D9) MCU_UART1_TXD */ 869 869 + AM64X_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) 870 870 + >; 871 871 + }; 872 872 + };

+253

arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 4 + * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany. 5 5 + */ 6 6 + 7 7 + #include "k3-am642.dtsi" 8 8 + 9 9 + / { 10 10 + aliases { 11 11 + i2c0 = &main_i2c0; 12 12 + mmc0 = &sdhci0; 13 13 + spi0 = &ospi0; 14 14 + }; 15 15 + 16 16 + memory@80000000 { 17 17 + device_type = "memory"; 18 18 + /* 1G RAM - default variant */ 19 19 + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; 20 20 + 21 21 + }; 22 22 + 23 23 + reserved-memory { 24 24 + #address-cells = <2>; 25 25 + #size-cells = <2>; 26 26 + ranges; 27 27 + 28 28 + secure_ddr: optee@9e800000 { 29 29 + reg = <0x00 0x9e800000 0x00 0x01800000>; 30 30 + alignment = <0x1000>; 31 31 + no-map; 32 32 + }; 33 33 + 34 34 + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 35 35 + compatible = "shared-dma-pool"; 36 36 + reg = <0x00 0xa0000000 0x00 0x100000>; 37 37 + no-map; 38 38 + }; 39 39 + 40 40 + main_r5fss0_core0_memory_region: r5f-memory@a0100000 { 41 41 + compatible = "shared-dma-pool"; 42 42 + reg = <0x00 0xa0100000 0x00 0xf00000>; 43 43 + no-map; 44 44 + }; 45 45 + 46 46 + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 47 47 + compatible = "shared-dma-pool"; 48 48 + reg = <0x00 0xa1000000 0x00 0x100000>; 49 49 + no-map; 50 50 + }; 51 51 + 52 52 + main_r5fss0_core1_memory_region: r5f-memory@a1100000 { 53 53 + compatible = "shared-dma-pool"; 54 54 + reg = <0x00 0xa1100000 0x00 0xf00000>; 55 55 + no-map; 56 56 + }; 57 57 + 58 58 + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { 59 59 + compatible = "shared-dma-pool"; 60 60 + reg = <0x00 0xa2000000 0x00 0x100000>; 61 61 + no-map; 62 62 + }; 63 63 + 64 64 + main_r5fss1_core0_memory_region: r5f-memory@a2100000 { 65 65 + compatible = "shared-dma-pool"; 66 66 + reg = <0x00 0xa2100000 0x00 0xf00000>; 67 67 + no-map; 68 68 + }; 69 69 + 70 70 + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { 71 71 + compatible = "shared-dma-pool"; 72 72 + reg = <0x00 0xa3000000 0x00 0x100000>; 73 73 + no-map; 74 74 + }; 75 75 + 76 76 + main_r5fss1_core1_memory_region: r5f-memory@a3100000 { 77 77 + compatible = "shared-dma-pool"; 78 78 + reg = <0x00 0xa3100000 0x00 0xf00000>; 79 79 + no-map; 80 80 + }; 81 81 + 82 82 + rtos_ipc_memory_region: ipc-memories@a5000000 { 83 83 + reg = <0x00 0xa5000000 0x00 0x00800000>; 84 84 + alignment = <0x1000>; 85 85 + no-map; 86 86 + }; 87 87 + }; 88 88 + }; 89 89 + 90 90 + &main_i2c0 { 91 91 + pinctrl-names = "default"; 92 92 + pinctrl-0 = <&main_i2c0_pins>; 93 93 + clock-frequency = <400000>; 94 94 + status = "okay"; 95 95 + 96 96 + tmp1075: temperature-sensor@4a { 97 97 + compatible = "ti,tmp1075"; 98 98 + reg = <0x4a>; 99 99 + }; 100 100 + 101 101 + eeprom0: eeprom@50 { 102 102 + compatible = "st,24c02", "atmel,24c02"; 103 103 + reg = <0x50>; 104 104 + pagesize = <16>; 105 105 + read-only; 106 106 + }; 107 107 + 108 108 + pcf85063: rtc@51 { 109 109 + compatible = "nxp,pcf85063a"; 110 110 + reg = <0x51>; 111 111 + quartz-load-femtofarads = <12500>; 112 112 + }; 113 113 + 114 114 + eeprom1: eeprom@54 { 115 115 + compatible = "st,24c64", "atmel,24c64"; 116 116 + reg = <0x54>; 117 117 + pagesize = <32>; 118 118 + }; 119 119 + }; 120 120 + 121 121 + &mailbox0_cluster2 { 122 122 + status = "okay"; 123 123 + 124 124 + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 125 125 + ti,mbox-rx = <0 0 2>; 126 126 + ti,mbox-tx = <1 0 2>; 127 127 + }; 128 128 + 129 129 + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 130 130 + ti,mbox-rx = <2 0 2>; 131 131 + ti,mbox-tx = <3 0 2>; 132 132 + }; 133 133 + }; 134 134 + 135 135 + &mailbox0_cluster4 { 136 136 + status = "okay"; 137 137 + 138 138 + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 139 139 + ti,mbox-rx = <0 0 2>; 140 140 + ti,mbox-tx = <1 0 2>; 141 141 + }; 142 142 + 143 143 + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 144 144 + ti,mbox-rx = <2 0 2>; 145 145 + ti,mbox-tx = <3 0 2>; 146 146 + }; 147 147 + }; 148 148 + 149 149 + &mailbox0_cluster6 { 150 150 + status = "okay"; 151 151 + 152 152 + mbox_m4_0: mbox-m4-0 { 153 153 + ti,mbox-rx = <0 0 2>; 154 154 + ti,mbox-tx = <1 0 2>; 155 155 + }; 156 156 + }; 157 157 + 158 158 + &main_r5fss0_core0 { 159 159 + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; 160 160 + memory-region = <&main_r5fss0_core0_dma_memory_region>, 161 161 + <&main_r5fss0_core0_memory_region>; 162 162 + }; 163 163 + 164 164 + &main_r5fss0_core1 { 165 165 + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; 166 166 + memory-region = <&main_r5fss0_core1_dma_memory_region>, 167 167 + <&main_r5fss0_core1_memory_region>; 168 168 + }; 169 169 + 170 170 + &main_r5fss1_core0 { 171 171 + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; 172 172 + memory-region = <&main_r5fss1_core0_dma_memory_region>, 173 173 + <&main_r5fss1_core0_memory_region>; 174 174 + }; 175 175 + 176 176 + &main_r5fss1_core1 { 177 177 + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; 178 178 + memory-region = <&main_r5fss1_core1_dma_memory_region>, 179 179 + <&main_r5fss1_core1_memory_region>; 180 180 + }; 181 181 + 182 182 + &ospi0 { 183 183 + status = "okay"; 184 184 + pinctrl-names = "default"; 185 185 + pinctrl-0 = <&ospi0_pins>; 186 186 + 187 187 + flash@0 { 188 188 + compatible = "jedec,spi-nor"; 189 189 + reg = <0>; 190 190 + spi-tx-bus-width = <8>; 191 191 + spi-rx-bus-width = <8>; 192 192 + spi-max-frequency = <84000000>; 193 193 + cdns,tshsl-ns = <60>; 194 194 + cdns,tsd2d-ns = <60>; 195 195 + cdns,tchsh-ns = <60>; 196 196 + cdns,tslch-ns = <60>; 197 197 + cdns,read-delay = <2>; 198 198 + 199 199 + partitions { 200 200 + compatible = "fixed-partitions"; 201 201 + #address-cells = <1>; 202 202 + #size-cells = <1>; 203 203 + 204 204 + /* Filled by bootloader */ 205 205 + }; 206 206 + }; 207 207 + }; 208 208 + 209 209 + &sdhci0 { 210 210 + non-removable; 211 211 + disable-wp; 212 212 + no-sdio; 213 213 + no-sd; 214 214 + ti,driver-strength-ohm = <50>; 215 215 + }; 216 216 + 217 217 + &main_pmx0 { 218 218 + main_i2c0_pins: main-i2c0-pins { 219 219 + pinctrl-single,pins = < 220 220 + /* (A18) I2C0_SCL */ 221 221 + AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) 222 222 + /* (B18) I2C0_SDA */ 223 223 + AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) 224 224 + >; 225 225 + }; 226 226 + 227 227 + ospi0_pins: ospi0-pins { 228 228 + pinctrl-single,pins = < 229 229 + /* (N20) OSPI0_CLK */ 230 230 + AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) 231 231 + /* (L19) OSPI0_CSn0 */ 232 232 + AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) 233 233 + /* (M19) OSPI0_D0 */ 234 234 + AM64X_IOPAD(0x000c, PIN_INPUT, 0) 235 235 + /* (M18) OSPI0_D1 */ 236 236 + AM64X_IOPAD(0x0010, PIN_INPUT, 0) 237 237 + /* (M20) OSPI0_D2 */ 238 238 + AM64X_IOPAD(0x0014, PIN_INPUT, 0) 239 239 + /* (M21) OSPI0_D3 */ 240 240 + AM64X_IOPAD(0x0018, PIN_INPUT, 0) 241 241 + /* (P21) OSPI0_D4 */ 242 242 + AM64X_IOPAD(0x001c, PIN_INPUT, 0) 243 243 + /* (P20) OSPI0_D5 */ 244 244 + AM64X_IOPAD(0x0020, PIN_INPUT, 0) 245 245 + /* (N18) OSPI0_D6 */ 246 246 + AM64X_IOPAD(0x0024, PIN_INPUT, 0) 247 247 + /* (M17) OSPI0_D7 */ 248 248 + AM64X_IOPAD(0x0028, PIN_INPUT, 0) 249 249 + /* (N19) OSPI0_DQS */ 250 250 + AM64X_IOPAD(0x0008, PIN_INPUT, 0) 251 251 + >; 252 252 + }; 253 253 + };

+1 -1

arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi

reviewed

··· 10 10 */ 11 11 12 12 &main_pmx0 { 13 13 - cp2102n_reset_pin_default: cp2102n-reset-pin-default { 13 13 + cp2102n_reset_pin_default: cp2102n-reset-default-pins { 14 14 pinctrl-single,pins = < 15 15 /* (AF12) GPIO1_24, used as cp2102 reset */ 16 16 AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)

+2 -4

arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi

reviewed

··· 582 582 ti,pindir-d0-out-d1-in; 583 583 }; 584 584 585 585 - &tscadc0 { 586 586 - status = "disabled"; 587 587 - }; 588 588 - 589 585 &tscadc1 { 586 586 + status = "okay"; 590 587 adc { 591 588 ti,adc-channels = <0 1 2 3 4 5>; 592 589 }; 593 590 }; 594 591 595 592 &ospi0 { 593 593 + status = "okay"; 596 594 pinctrl-names = "default"; 597 595 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 598 596

+18 -17

arch/arm64/boot/dts/ti/k3-am65-main.dtsi

reviewed

··· 502 502 reg = <0x000041e0 0x14>; 503 503 }; 504 504 505 505 - ehrpwm_tbclk: clock@4140 { 506 506 - compatible = "ti,am654-ehrpwm-tbclk", "syscon"; 505 505 + ehrpwm_tbclk: clock-controller@4140 { 506 506 + compatible = "ti,am654-ehrpwm-tbclk"; 507 507 reg = <0x4140 0x18>; 508 508 #clock-cells = <1>; 509 509 }; ··· 773 773 774 774 ringacc: ringacc@3c000000 { 775 775 compatible = "ti,am654-navss-ringacc"; 776 776 - reg = <0x0 0x3c000000 0x0 0x400000>, 777 777 - <0x0 0x38000000 0x0 0x400000>, 778 778 - <0x0 0x31120000 0x0 0x100>, 779 779 - <0x0 0x33000000 0x0 0x40000>; 780 780 - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 776 776 + reg = <0x0 0x3c000000 0x0 0x400000>, 777 777 + <0x0 0x38000000 0x0 0x400000>, 778 778 + <0x0 0x31120000 0x0 0x100>, 779 779 + <0x0 0x33000000 0x0 0x40000>, 780 780 + <0x0 0x31080000 0x0 0x40000>; 781 781 + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 781 782 ti,num-rings = <818>; 782 783 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 783 784 ti,sci = <&dmsc>; ··· 788 787 789 788 main_udmap: dma-controller@31150000 { 790 789 compatible = "ti,am654-navss-main-udmap"; 791 791 - reg = <0x0 0x31150000 0x0 0x100>, 792 792 - <0x0 0x34000000 0x0 0x100000>, 793 793 - <0x0 0x35000000 0x0 0x100000>; 790 790 + reg = <0x0 0x31150000 0x0 0x100>, 791 791 + <0x0 0x34000000 0x0 0x100000>, 792 792 + <0x0 0x35000000 0x0 0x100000>; 794 793 reg-names = "gcfg", "rchanrt", "tchanrt"; 795 794 msi-parent = <&inta_main_udmass>; 796 795 #dma-cells = <1>; ··· 1007 1006 1008 1007 dss: dss@4a00000 { 1009 1008 compatible = "ti,am65x-dss"; 1010 1010 - reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ 1011 1011 - <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ 1012 1012 - <0x0 0x04a06000 0x0 0x1000>, /* vid */ 1013 1013 - <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ 1014 1014 - <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ 1015 1015 - <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ 1016 1016 - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ 1009 1009 + reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ 1010 1010 + <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ 1011 1011 + <0x0 0x04a06000 0x0 0x1000>, /* vid */ 1012 1012 + <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ 1013 1013 + <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ 1014 1014 + <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ 1015 1015 + <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ 1017 1016 reg-names = "common", "vidl1", "vid", 1018 1017 "ovr1", "ovr2", "vp1", "vp2"; 1019 1018

+15 -9

arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi

reviewed

··· 112 112 dmas = <&mcu_udmap 0x7100>, 113 113 <&mcu_udmap 0x7101 >; 114 114 dma-names = "fifo0", "fifo1"; 115 115 + status = "disabled"; 115 116 116 117 adc { 117 118 #io-channel-cells = <1>; ··· 131 130 dmas = <&mcu_udmap 0x7102>, 132 131 <&mcu_udmap 0x7103>; 133 132 dma-names = "fifo0", "fifo1"; 133 133 + status = "disabled"; 134 134 135 135 adc { 136 136 #io-channel-cells = <1>; ··· 196 194 197 195 mcu_ringacc: ringacc@2b800000 { 198 196 compatible = "ti,am654-navss-ringacc"; 199 199 - reg = <0x0 0x2b800000 0x0 0x400000>, 200 200 - <0x0 0x2b000000 0x0 0x400000>, 201 201 - <0x0 0x28590000 0x0 0x100>, 202 202 - <0x0 0x2a500000 0x0 0x40000>; 203 203 - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 197 197 + reg = <0x0 0x2b800000 0x0 0x400000>, 198 198 + <0x0 0x2b000000 0x0 0x400000>, 199 199 + <0x0 0x28590000 0x0 0x100>, 200 200 + <0x0 0x2a500000 0x0 0x40000>, 201 201 + <0x0 0x28440000 0x0 0x40000>; 202 202 + reg-names = "rt", "fifos", "proxy_gcfg", 203 203 + "proxy_target", "cfg"; 204 204 ti,num-rings = <286>; 205 205 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 206 206 ti,sci = <&dmsc>; ··· 212 208 213 209 mcu_udmap: dma-controller@285c0000 { 214 210 compatible = "ti,am654-navss-mcu-udmap"; 215 215 - reg = <0x0 0x285c0000 0x0 0x100>, 216 216 - <0x0 0x2a800000 0x0 0x40000>, 217 217 - <0x0 0x2aa00000 0x0 0x40000>; 211 211 + reg = <0x0 0x285c0000 0x0 0x100>, 212 212 + <0x0 0x2a800000 0x0 0x40000>, 213 213 + <0x0 0x2aa00000 0x0 0x40000>; 218 214 reg-names = "gcfg", "rchanrt", "tchanrt"; 219 215 msi-parent = <&inta_main_udmass>; 220 216 #dma-cells = <1>; ··· 278 274 status = "disabled"; 279 275 }; 280 276 281 281 - fss: fss@47000000 { 277 277 + fss: bus@47000000 { 282 278 compatible = "simple-bus"; 283 279 #address-cells = <2>; 284 280 #size-cells = <2>; ··· 299 295 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 300 296 #address-cells = <1>; 301 297 #size-cells = <0>; 298 298 + status = "disabled"; 302 299 }; 303 300 304 301 ospi1: spi@47050000 { ··· 314 309 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 315 310 #address-cells = <1>; 316 311 #size-cells = <0>; 312 312 + status = "disabled"; 317 313 }; 318 314 }; 319 315

+4 -1

arch/arm64/boot/dts/ti/k3-am654-base-board.dts

reviewed

··· 192 192 >; 193 193 }; 194 194 195 195 - wkup_pca554_default: wkup-pca554-default { 195 195 + wkup_pca554_default: wkup-pca554-default-pins { 196 196 pinctrl-single,pins = < 197 197 AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ 198 198 >; ··· 478 478 }; 479 479 480 480 &tscadc0 { 481 481 + status = "okay"; 481 482 adc { 482 483 ti,adc-channels = <0 1 2 3 4 5 6 7>; 483 484 }; 484 485 }; 485 486 486 487 &tscadc1 { 488 488 + status = "okay"; 487 489 adc { 488 490 ti,adc-channels = <0 1 2 3 4 5 6 7>; 489 491 }; ··· 532 530 }; 533 531 534 532 &ospi0 { 533 533 + status = "okay"; 535 534 pinctrl-names = "default"; 536 535 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 537 536

+2 -2

arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts

reviewed

··· 33 33 >; 34 34 }; 35 35 36 36 - main_bkey_pcie_reset: main-bkey-pcie-reset { 36 36 + main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins { 37 37 pinctrl-single,pins = < 38 38 AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */ 39 39 >; ··· 46 46 >; 47 47 }; 48 48 49 49 - main_m2_pcie_mux_control: main-m2-pcie-mux-control { 49 49 + main_m2_pcie_mux_control: main-m2-pcie-mux-control-default-pins { 50 50 pinctrl-single,pins = < 51 51 AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */ 52 52 AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */

+143 -22

arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts

reviewed

··· 11 11 #include <dt-bindings/net/ti-dp83867.h> 12 12 #include <dt-bindings/phy/phy-cadence.h> 13 13 #include <dt-bindings/phy/phy.h> 14 14 - #include <dt-bindings/mux/ti-serdes.h> 14 14 + 15 15 + #include "k3-serdes.h" 15 16 16 17 / { 17 18 compatible = "ti,am68-sk", "ti,j721s2"; ··· 122 121 #phy-cells = <0>; 123 122 max-bitrate = <5000000>; 124 123 }; 124 124 + 125 125 + connector-hdmi { 126 126 + compatible = "hdmi-connector"; 127 127 + label = "hdmi"; 128 128 + type = "a"; 129 129 + pinctrl-names = "default"; 130 130 + pinctrl-0 = <&hdmi_hpd_pins_default>; 131 131 + ddc-i2c-bus = <&mcu_i2c1>; 132 132 + /* HDMI_HPD */ 133 133 + hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; 134 134 + 135 135 + port { 136 136 + hdmi_connector_in: endpoint { 137 137 + remote-endpoint = <&tfp410_out>; 138 138 + }; 139 139 + }; 140 140 + }; 141 141 + 142 142 + bridge-dvi { 143 143 + compatible = "ti,tfp410"; 144 144 + /* HDMI_PDn */ 145 145 + powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>; 146 146 + ti,deskew = <0>; 147 147 + 148 148 + ports { 149 149 + #address-cells = <1>; 150 150 + #size-cells = <0>; 151 151 + 152 152 + port@0 { 153 153 + reg = <0>; 154 154 + 155 155 + tfp410_in: endpoint { 156 156 + remote-endpoint = <&dpi_out0>; 157 157 + pclk-sample = <1>; 158 158 + }; 159 159 + }; 160 160 + 161 161 + port@1 { 162 162 + reg = <1>; 163 163 + 164 164 + tfp410_out: endpoint { 165 165 + remote-endpoint = <&hdmi_connector_in>; 166 166 + }; 167 167 + }; 168 168 + }; 169 169 + }; 125 170 }; 126 171 127 172 &main_pmx0 { ··· 248 201 J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */ 249 202 >; 250 203 }; 204 204 + 205 205 + dss_vout0_pins_default: dss-vout0-default-pins { 206 206 + pinctrl-single,pins = < 207 207 + J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */ 208 208 + J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */ 209 209 + J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */ 210 210 + J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */ 211 211 + J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */ 212 212 + J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */ 213 213 + J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */ 214 214 + J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */ 215 215 + J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */ 216 216 + J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */ 217 217 + J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */ 218 218 + J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */ 219 219 + J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */ 220 220 + J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */ 221 221 + J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */ 222 222 + J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */ 223 223 + J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */ 224 224 + J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */ 225 225 + J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */ 226 226 + J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */ 227 227 + J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */ 228 228 + J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */ 229 229 + J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */ 230 230 + J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */ 231 231 + J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */ 232 232 + J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */ 233 233 + J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */ 234 234 + J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */ 235 235 + >; 236 236 + }; 237 237 + 238 238 + hdmi_hpd_pins_default: hdmi-hpd-default-pins { 239 239 + pinctrl-single,pins = < 240 240 + J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */ 241 241 + >; 242 242 + }; 251 243 }; 252 244 253 245 &wkup_pmx2 { ··· 358 272 >; 359 273 }; 360 274 361 361 - mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-pins0-default { 275 275 + mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { 362 276 pinctrl-single,pins = < 363 277 J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ 364 278 J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ ··· 374 288 }; 375 289 376 290 &wkup_pmx3 { 377 377 - mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-pins1-default { 291 291 + mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-default-pins-1 { 378 292 pinctrl-single,pins = < 379 293 J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */ 380 294 >; ··· 382 296 }; 383 297 384 298 &main_gpio0 { 299 299 + status = "okay"; 385 300 pinctrl-names = "default"; 386 301 pinctrl-0 = <&rpi_header_gpio0_pins_default>; 387 302 }; 388 303 389 389 - &main_gpio2 { 390 390 - status = "disabled"; 391 391 - }; 392 392 - 393 393 - &main_gpio4 { 394 394 - status = "disabled"; 395 395 - }; 396 396 - 397 397 - &main_gpio6 { 398 398 - status = "disabled"; 399 399 - }; 400 400 - 401 304 &wkup_gpio0 { 305 305 + status = "okay"; 402 306 pinctrl-names = "default"; 403 307 pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>; 404 404 - }; 405 405 - 406 406 - &wkup_gpio1 { 407 407 - status = "disabled"; 408 308 }; 409 309 410 310 &wkup_uart0 { ··· 444 372 clock-frequency = <400000>; 445 373 }; 446 374 447 447 - &main_sdhci0 { 448 448 - /* Unused */ 449 449 - status = "disabled"; 375 375 + &mcu_i2c1 { 376 376 + status = "okay"; 377 377 + pinctrl-names = "default"; 378 378 + pinctrl-0 = <&mcu_i2c1_pins_default>; 379 379 + /* i2c1 is used for DVI DDC, so we need to use 100kHz */ 380 380 + clock-frequency = <100000>; 381 381 + 382 382 + exp2: gpio@20 { 383 383 + compatible = "ti,tca6408"; 384 384 + reg = <0x20>; 385 385 + gpio-controller; 386 386 + #gpio-cells = <2>; 387 387 + gpio-line-names = "HDMI_PDn","HDMI_LS_OE", 388 388 + "DP0_3V3_EN","eDP_ENABLE"; 389 389 + }; 450 390 }; 451 391 452 392 &main_sdhci1 { 453 393 /* SD card */ 394 394 + status = "okay"; 454 395 pinctrl-0 = <&main_mmc1_pins_default>; 455 396 pinctrl-names = "default"; 456 397 disable-wp; ··· 516 431 pinctrl-names = "default"; 517 432 pinctrl-0 = <&main_mcan7_pins_default>; 518 433 phys = <&transceiver4>; 434 434 + }; 435 435 + 436 436 + &dss { 437 437 + status = "okay"; 438 438 + pinctrl-names = "default"; 439 439 + pinctrl-0 = <&dss_vout0_pins_default>; 440 440 + /* 441 441 + * These clock assignments are chosen to enable the following outputs: 442 442 + * 443 443 + * VP0 - DisplayPort SST 444 444 + * VP1 - DPI0 445 445 + * VP2 - DSI 446 446 + * VP3 - DPI1 447 447 + */ 448 448 + assigned-clocks = <&k3_clks 158 2>, 449 449 + <&k3_clks 158 5>, 450 450 + <&k3_clks 158 14>, 451 451 + <&k3_clks 158 18>; 452 452 + assigned-clock-parents = <&k3_clks 158 3>, 453 453 + <&k3_clks 158 7>, 454 454 + <&k3_clks 158 16>, 455 455 + <&k3_clks 158 22>; 456 456 + }; 457 457 + 458 458 + &dss_ports { 459 459 + #address-cells = <1>; 460 460 + #size-cells = <0>; 461 461 + 462 462 + /* HDMI */ 463 463 + port@1 { 464 464 + reg = <1>; 465 465 + 466 466 + dpi_out0: endpoint { 467 467 + remote-endpoint = <&tfp410_in>; 468 468 + }; 469 469 + }; 519 470 };

+12

arch/arm64/boot/dts/ti/k3-am69-sk.dts

reviewed

··· 110 110 }; 111 111 112 112 &main_pmx0 { 113 113 + bootph-all; 113 114 main_uart8_pins_default: main-uart8-default-pins { 115 115 + bootph-all; 114 116 pinctrl-single,pins = < 115 117 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 116 118 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ ··· 127 125 }; 128 126 129 127 main_mmc1_pins_default: main-mmc1-default-pins { 128 128 + bootph-all; 130 129 pinctrl-single,pins = < 131 130 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 132 131 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ ··· 167 164 }; 168 165 169 166 &wkup_pmx2 { 167 167 + bootph-all; 170 168 wkup_uart0_pins_default: wkup-uart0-default-pins { 169 169 + bootph-all; 171 170 pinctrl-single,pins = < 172 171 J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ 173 172 J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ ··· 179 174 }; 180 175 181 176 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 177 177 + bootph-all; 182 178 pinctrl-single,pins = < 183 179 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ 184 180 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ ··· 187 181 }; 188 182 189 183 mcu_uart0_pins_default: mcu-uart0-default-pins { 184 184 + bootph-all; 190 185 pinctrl-single,pins = < 191 186 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ 192 187 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ ··· 256 249 }; 257 250 258 251 &wkup_i2c0 { 252 252 + bootph-all; 259 253 status = "okay"; 260 254 pinctrl-names = "default"; 261 255 pinctrl-0 = <&wkup_i2c0_pins_default>; ··· 276 268 }; 277 269 278 270 &mcu_uart0 { 271 271 + bootph-all; 279 272 status = "okay"; 280 273 pinctrl-names = "default"; 281 274 pinctrl-0 = <&mcu_uart0_pins_default>; ··· 290 281 }; 291 282 292 283 &main_uart8 { 284 284 + bootph-all; 293 285 status = "okay"; 294 286 pinctrl-names = "default"; 295 287 pinctrl-0 = <&main_uart8_pins_default>; ··· 317 307 }; 318 308 319 309 &main_sdhci0 { 310 310 + bootph-all; 320 311 /* eMMC */ 321 312 status = "okay"; 322 313 non-removable; ··· 326 315 }; 327 316 328 317 &main_sdhci1 { 318 318 + bootph-all; 329 319 /* SD card */ 330 320 status = "okay"; 331 321 pinctrl-0 = <&main_mmc1_pins_default>;

+7 -15

arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts

reviewed

··· 8 8 #include "k3-j7200-som-p0.dtsi" 9 9 #include <dt-bindings/gpio/gpio.h> 10 10 #include <dt-bindings/net/ti-dp83867.h> 11 11 - #include <dt-bindings/mux/ti-serdes.h> 12 11 #include <dt-bindings/phy/phy.h> 12 12 + 13 13 + #include "k3-serdes.h" 13 14 14 15 / { 15 16 compatible = "ti,j7200-evm", "ti,j7200"; ··· 240 239 pinctrl-0 = <&main_uart3_pins_default>; 241 240 }; 242 241 243 243 - &main_gpio2 { 244 244 - status = "disabled"; 245 245 - }; 246 246 - 247 247 - &main_gpio4 { 248 248 - status = "disabled"; 249 249 - }; 250 250 - 251 251 - &main_gpio6 { 252 252 - status = "disabled"; 242 242 + &main_gpio0 { 243 243 + status = "okay"; 253 244 }; 254 245 255 246 &wkup_gpio0 { 247 247 + status = "okay"; 256 248 pinctrl-names = "default"; 257 249 pinctrl-0 = <&wkup_gpio_pins_default>; 258 258 - }; 259 259 - 260 260 - &wkup_gpio1 { 261 261 - status = "disabled"; 262 250 }; 263 251 264 252 &mcu_cpsw { ··· 315 325 316 326 &main_sdhci0 { 317 327 /* eMMC */ 328 328 + status = "okay"; 318 329 non-removable; 319 330 ti,driver-strength-ohm = <50>; 320 331 disable-wp; ··· 323 332 324 333 &main_sdhci1 { 325 334 /* SD card */ 335 335 + status = "okay"; 326 336 pinctrl-0 = <&main_mmc1_pins_default>; 327 337 pinctrl-names = "default"; 328 338 vmmc-supply = <&vdd_mmc1>;

+1 -1

arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso

reviewed

··· 10 10 /plugin/; 11 11 12 12 #include <dt-bindings/gpio/gpio.h> 13 13 - #include <dt-bindings/mux/ti-serdes.h> 14 13 15 14 #include "k3-pinctrl.h" 15 15 + #include "k3-serdes.h" 16 16 17 17 &{/} { 18 18 aliases {

+15 -8

arch/arm64/boot/dts/ti/k3-j7200-main.dtsi

reviewed

··· 264 264 265 265 main_ringacc: ringacc@3c000000 { 266 266 compatible = "ti,am654-navss-ringacc"; 267 267 - reg = <0x00 0x3c000000 0x00 0x400000>, 268 268 - <0x00 0x38000000 0x00 0x400000>, 269 269 - <0x00 0x31120000 0x00 0x100>, 270 270 - <0x00 0x33000000 0x00 0x40000>; 271 271 - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 267 267 + reg = <0x00 0x3c000000 0x00 0x400000>, 268 268 + <0x00 0x38000000 0x00 0x400000>, 269 269 + <0x00 0x31120000 0x00 0x100>, 270 270 + <0x00 0x33000000 0x00 0x40000>, 271 271 + <0x00 0x31080000 0x00 0x40000>; 272 272 + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 272 273 ti,num-rings = <1024>; 273 274 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 274 275 ti,sci = <&dmsc>; ··· 279 278 280 279 main_udmap: dma-controller@31150000 { 281 280 compatible = "ti,j721e-navss-main-udmap"; 282 282 - reg = <0x00 0x31150000 0x00 0x100>, 283 283 - <0x00 0x34000000 0x00 0x100000>, 284 284 - <0x00 0x35000000 0x00 0x100000>; 281 281 + reg = <0x00 0x31150000 0x00 0x100>, 282 282 + <0x00 0x34000000 0x00 0x100000>, 283 283 + <0x00 0x35000000 0x00 0x100000>; 285 284 reg-names = "gcfg", "rchanrt", "tchanrt"; 286 285 msi-parent = <&main_udmass_inta>; 287 286 #dma-cells = <1>; ··· 655 654 mmc-hs200-1_8v; 656 655 mmc-hs400-1_8v; 657 656 dma-coherent; 657 657 + status = "disabled"; 658 658 }; 659 659 660 660 main_sdhci1: mmc@4fb0000 { ··· 679 677 ti,clkbuf-sel = <0x7>; 680 678 ti,trm-icp = <0x8>; 681 679 dma-coherent; 680 680 + status = "disabled"; 682 681 }; 683 682 684 683 serdes_wiz0: wiz@5060000 { ··· 833 830 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 834 831 clocks = <&k3_clks 105 0>; 835 832 clock-names = "gpio"; 833 833 + status = "disabled"; 836 834 }; 837 835 838 836 main_gpio2: gpio@610000 { ··· 851 847 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 852 848 clocks = <&k3_clks 107 0>; 853 849 clock-names = "gpio"; 850 850 + status = "disabled"; 854 851 }; 855 852 856 853 main_gpio4: gpio@620000 { ··· 869 864 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 870 865 clocks = <&k3_clks 109 0>; 871 866 clock-names = "gpio"; 867 867 + status = "disabled"; 872 868 }; 873 869 874 870 main_gpio6: gpio@630000 { ··· 887 881 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 888 882 clocks = <&k3_clks 111 0>; 889 883 clock-names = "gpio"; 884 884 + status = "disabled"; 890 885 }; 891 886 892 887 main_spi0: spi@2100000 {

+13 -8

arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi

reviewed

··· 297 297 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 298 298 clocks = <&k3_clks 113 0>; 299 299 clock-names = "gpio"; 300 300 + status = "disabled"; 300 301 }; 301 302 302 303 wkup_gpio1: gpio@42100000 { ··· 314 313 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 315 314 clocks = <&k3_clks 114 0>; 316 315 clock-names = "gpio"; 316 316 + status = "disabled"; 317 317 }; 318 318 319 319 mcu_navss: bus@28380000 { ··· 328 326 329 327 mcu_ringacc: ringacc@2b800000 { 330 328 compatible = "ti,am654-navss-ringacc"; 331 331 - reg = <0x00 0x2b800000 0x00 0x400000>, 332 332 - <0x00 0x2b000000 0x00 0x400000>, 333 333 - <0x00 0x28590000 0x00 0x100>, 334 334 - <0x00 0x2a500000 0x00 0x40000>; 335 335 - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 329 329 + reg = <0x00 0x2b800000 0x00 0x400000>, 330 330 + <0x00 0x2b000000 0x00 0x400000>, 331 331 + <0x00 0x28590000 0x00 0x100>, 332 332 + <0x00 0x2a500000 0x00 0x40000>, 333 333 + <0x00 0x28440000 0x00 0x40000>; 334 334 + reg-names = "rt", "fifos", "proxy_gcfg", 335 335 + "proxy_target", "cfg"; 336 336 ti,num-rings = <286>; 337 337 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 338 338 ti,sci = <&dmsc>; ··· 344 340 345 341 mcu_udmap: dma-controller@285c0000 { 346 342 compatible = "ti,j721e-navss-mcu-udmap"; 347 347 - reg = <0x00 0x285c0000 0x00 0x100>, 348 348 - <0x00 0x2a800000 0x00 0x40000>, 349 349 - <0x00 0x2aa00000 0x00 0x40000>; 343 343 + reg = <0x00 0x285c0000 0x00 0x100>, 344 344 + <0x00 0x2a800000 0x00 0x40000>, 345 345 + <0x00 0x2aa00000 0x00 0x40000>; 350 346 reg-names = "gcfg", "rchanrt", "tchanrt"; 351 347 msi-parent = <&main_udmass_inta>; 352 348 #dma-cells = <1>; ··· 548 544 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 549 545 #address-cells = <1>; 550 546 #size-cells = <0>; 547 547 + status = "disabled"; 551 548 }; 552 549 }; 553 550

+1

arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi

reviewed

··· 267 267 }; 268 268 269 269 &ospi0 { 270 270 + status = "okay"; 270 271 pinctrl-names = "default"; 271 272 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 272 273

+13 -50

arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts

reviewed

··· 563 563 564 564 &main_sdhci0 { 565 565 /* eMMC */ 566 566 + status = "okay"; 566 567 non-removable; 567 568 ti,driver-strength-ohm = <50>; 568 569 disable-wp; ··· 571 570 572 571 &main_sdhci1 { 573 572 /* SD Card */ 573 573 + status = "okay"; 574 574 vmmc-supply = <&vdd_mmc1>; 575 575 vqmmc-supply = <&vdd_sd_dv_alt>; 576 576 pinctrl-names = "default"; 577 577 pinctrl-0 = <&main_mmc1_pins_default>; 578 578 ti,driver-strength-ohm = <50>; 579 579 disable-wp; 580 580 - }; 581 581 - 582 582 - &main_sdhci2 { 583 583 - /* Unused */ 584 584 - status = "disabled"; 585 585 - }; 586 586 - 587 587 - &ospi0 { 588 588 - /* Unused */ 589 589 - status = "disabled"; 590 590 - }; 591 591 - 592 592 - &ospi1 { 593 593 - /* Unused */ 594 594 - status = "disabled"; 595 580 }; 596 581 597 582 &main_i2c0 { ··· 647 660 }; 648 661 }; 649 662 650 650 - &main_gpio2 { 651 651 - /* Unused */ 652 652 - status = "disabled"; 653 653 - }; 654 654 - 655 655 - &main_gpio3 { 656 656 - /* Unused */ 657 657 - status = "disabled"; 658 658 - }; 659 659 - 660 660 - &main_gpio4 { 661 661 - /* Unused */ 662 662 - status = "disabled"; 663 663 - }; 664 664 - 665 665 - &main_gpio5 { 666 666 - /* Unused */ 667 667 - status = "disabled"; 668 668 - }; 669 669 - 670 670 - &main_gpio6 { 671 671 - /* Unused */ 672 672 - status = "disabled"; 673 673 - }; 674 674 - 675 675 - &main_gpio7 { 676 676 - /* Unused */ 677 677 - status = "disabled"; 678 678 - }; 679 679 - 680 663 &wkup_gpio0 { 664 664 + status = "okay"; 681 665 pinctrl-names = "default"; 682 666 pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>, 683 667 <&mikro_bus_pins_default>; 684 668 }; 685 669 686 686 - &wkup_gpio1 { 687 687 - /* Unused */ 688 688 - status = "disabled"; 689 689 - }; 690 690 - 691 670 &main_gpio0 { 671 671 + status = "okay"; 692 672 pinctrl-names = "default"; 693 673 pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>; 674 674 + }; 675 675 + 676 676 + &main_gpio1 { 677 677 + status = "okay"; 694 678 }; 695 679 696 680 &usb_serdes_mux { ··· 747 789 }; 748 790 749 791 &tscadc0 { 792 792 + status = "okay"; 750 793 /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */ 751 794 adc { 752 795 ti,adc-channels = <0 1 2 3 4 5 6>; ··· 755 796 }; 756 797 757 798 &tscadc1 { 799 799 + status = "okay"; 758 800 /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */ 759 801 adc { 760 802 ti,adc-channels = <0>; ··· 972 1012 }; 973 1013 974 1014 &c66_0 { 1015 1015 + status = "okay"; 975 1016 mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; 976 1017 memory-region = <&c66_0_dma_memory_region>, 977 1018 <&c66_0_memory_region>; 978 1019 }; 979 1020 980 1021 &c66_1 { 1022 1022 + status = "okay"; 981 1023 mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; 982 1024 memory-region = <&c66_1_dma_memory_region>, 983 1025 <&c66_1_memory_region>; 984 1026 }; 985 1027 986 1028 &c71_0 { 1029 1029 + status = "okay"; 987 1030 mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; 988 1031 memory-region = <&c71_0_dma_memory_region>, 989 1032 <&c71_0_memory_region>;

+11 -31

arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts

reviewed

··· 469 469 pinctrl-0 = <&main_uart4_pins_default>; 470 470 }; 471 471 472 472 - &main_gpio2 { 473 473 - status = "disabled"; 474 474 - }; 475 475 - 476 476 - &main_gpio3 { 477 477 - status = "disabled"; 478 478 - }; 479 479 - 480 480 - &main_gpio4 { 481 481 - status = "disabled"; 482 482 - }; 483 483 - 484 484 - &main_gpio5 { 485 485 - status = "disabled"; 486 486 - }; 487 487 - 488 488 - &main_gpio6 { 489 489 - status = "disabled"; 490 490 - }; 491 491 - 492 492 - &main_gpio7 { 493 493 - status = "disabled"; 494 494 - }; 495 495 - 496 472 &wkup_gpio0 { 473 473 + status = "okay"; 497 474 pinctrl-names = "default"; 498 475 pinctrl-0 = <&wkup_gpio_pins_default>; 499 476 }; 500 477 501 501 - &wkup_gpio1 { 502 502 - status = "disabled"; 478 478 + &main_gpio0 { 479 479 + status = "okay"; 480 480 + }; 481 481 + 482 482 + &main_gpio1 { 483 483 + status = "okay"; 503 484 }; 504 485 505 486 &main_sdhci0 { 506 487 /* eMMC */ 488 488 + status = "okay"; 507 489 non-removable; 508 490 ti,driver-strength-ohm = <50>; 509 491 disable-wp; ··· 493 511 494 512 &main_sdhci1 { 495 513 /* SD/MMC */ 514 514 + status = "okay"; 496 515 vmmc-supply = <&vdd_mmc1>; 497 516 vqmmc-supply = <&vdd_sd_dv_alt>; 498 517 pinctrl-names = "default"; 499 518 pinctrl-0 = <&main_mmc1_pins_default>; 500 519 ti,driver-strength-ohm = <50>; 501 520 disable-wp; 502 502 - }; 503 503 - 504 504 - &main_sdhci2 { 505 505 - /* Unused */ 506 506 - status = "disabled"; 507 521 }; 508 522 509 523 &usb_serdes_mux { ··· 619 641 }; 620 642 621 643 &tscadc0 { 644 644 + status = "okay"; 622 645 adc { 623 646 ti,adc-channels = <0 1 2 3 4 5 6 7>; 624 647 }; 625 648 }; 626 649 627 650 &tscadc1 { 651 651 + status = "okay"; 628 652 adc { 629 653 ti,adc-channels = <0 1 2 3 4 5 6 7>; 630 654 };

+196

arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /** 3 3 + * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with 4 4 + * J721E board. 5 5 + * 6 6 + * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM 7 7 + * 8 8 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 9 9 + */ 10 10 + 11 11 + /dts-v1/; 12 12 + /plugin/; 13 13 + 14 14 + #include <dt-bindings/gpio/gpio.h> 15 15 + #include <dt-bindings/net/ti-dp83867.h> 16 16 + 17 17 + #include "k3-pinctrl.h" 18 18 + 19 19 + &{/} { 20 20 + aliases { 21 21 + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; 22 22 + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; 23 23 + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; 24 24 + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; 25 25 + }; 26 26 + }; 27 27 + 28 28 + &cpsw0 { 29 29 + status = "okay"; 30 30 + pinctrl-names = "default"; 31 31 + pinctrl-0 = <&rgmii1_default_pins 32 32 + &rgmii2_default_pins 33 33 + &rgmii3_default_pins 34 34 + &rgmii4_default_pins>; 35 35 + }; 36 36 + 37 37 + &cpsw0_port1 { 38 38 + status = "okay"; 39 39 + phy-handle = <&cpsw9g_phy12>; 40 40 + phy-mode = "rgmii-rxid"; 41 41 + mac-address = [00 00 00 00 00 00]; 42 42 + phys = <&cpsw0_phy_gmii_sel 1>; 43 43 + }; 44 44 + 45 45 + &cpsw0_port2 { 46 46 + status = "okay"; 47 47 + phy-handle = <&cpsw9g_phy15>; 48 48 + phy-mode = "rgmii-rxid"; 49 49 + mac-address = [00 00 00 00 00 00]; 50 50 + phys = <&cpsw0_phy_gmii_sel 2>; 51 51 + }; 52 52 + 53 53 + &cpsw0_port3 { 54 54 + status = "okay"; 55 55 + phy-handle = <&cpsw9g_phy0>; 56 56 + phy-mode = "rgmii-rxid"; 57 57 + mac-address = [00 00 00 00 00 00]; 58 58 + phys = <&cpsw0_phy_gmii_sel 3>; 59 59 + }; 60 60 + 61 61 + &cpsw0_port4 { 62 62 + status = "okay"; 63 63 + phy-handle = <&cpsw9g_phy3>; 64 64 + phy-mode = "rgmii-rxid"; 65 65 + mac-address = [00 00 00 00 00 00]; 66 66 + phys = <&cpsw0_phy_gmii_sel 4>; 67 67 + }; 68 68 + 69 69 + &cpsw9g_mdio { 70 70 + status = "okay"; 71 71 + pinctrl-names = "default"; 72 72 + pinctrl-0 = <&mdio0_default_pins>; 73 73 + bus_freq = <1000000>; 74 74 + #address-cells = <1>; 75 75 + #size-cells = <0>; 76 76 + 77 77 + cpsw9g_phy0: ethernet-phy@0 { 78 78 + reg = <0>; 79 79 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 80 80 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 81 81 + ti,min-output-impedance; 82 82 + }; 83 83 + cpsw9g_phy3: ethernet-phy@3 { 84 84 + reg = <3>; 85 85 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 86 86 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 87 87 + ti,min-output-impedance; 88 88 + }; 89 89 + cpsw9g_phy12: ethernet-phy@12 { 90 90 + reg = <12>; 91 91 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 92 92 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 93 93 + ti,min-output-impedance; 94 94 + }; 95 95 + cpsw9g_phy15: ethernet-phy@15 { 96 96 + reg = <15>; 97 97 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 98 98 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 99 99 + ti,min-output-impedance; 100 100 + }; 101 101 + }; 102 102 + 103 103 + &exp1 { 104 104 + p15-hog { 105 105 + /* P15 - EXP_MUX2 */ 106 106 + gpio-hog; 107 107 + gpios = <13 GPIO_ACTIVE_HIGH>; 108 108 + output-high; 109 109 + line-name = "EXP_MUX2"; 110 110 + }; 111 111 + 112 112 + p16-hog { 113 113 + /* P16 - EXP_MUX3 */ 114 114 + gpio-hog; 115 115 + gpios = <14 GPIO_ACTIVE_HIGH>; 116 116 + output-high; 117 117 + line-name = "EXP_MUX3"; 118 118 + }; 119 119 + }; 120 120 + 121 121 + &main_pmx0 { 122 122 + mdio0_default_pins: mdio0-default-pins { 123 123 + pinctrl-single,pins = < 124 124 + J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */ 125 125 + J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */ 126 126 + >; 127 127 + }; 128 128 + 129 129 + rgmii1_default_pins: rgmii1-default-pins { 130 130 + pinctrl-single,pins = < 131 131 + J721E_IOPAD(0x4, PIN_INPUT, 4) /* (AC23) PRG1_PRU0_GPO0.RGMII1_RD0 */ 132 132 + J721E_IOPAD(0x8, PIN_INPUT, 4) /* (AG22) PRG1_PRU0_GPO1.RGMII1_RD1 */ 133 133 + J721E_IOPAD(0xc, PIN_INPUT, 4) /* (AF22) PRG1_PRU0_GPO2.RGMII1_RD2 */ 134 134 + J721E_IOPAD(0x10, PIN_INPUT, 4) /* (AJ23) PRG1_PRU0_GPO3.RGMII1_RD3 */ 135 135 + J721E_IOPAD(0x1c, PIN_INPUT, 4) /* (AD22) PRG1_PRU0_GPO6.RGMII1_RXC */ 136 136 + J721E_IOPAD(0x14, PIN_INPUT, 4) /* (AH23) PRG1_PRU0_GPO4.RGMII1_RX_CTL */ 137 137 + J721E_IOPAD(0x30, PIN_OUTPUT, 4) /* (AF24) PRG1_PRU0_GPO11.RGMII1_TD0 */ 138 138 + J721E_IOPAD(0x34, PIN_OUTPUT, 4) /* (AJ24) PRG1_PRU0_GPO12.RGMII1_TD1 */ 139 139 + J721E_IOPAD(0x38, PIN_OUTPUT, 4) /* (AG24) PRG1_PRU0_GPO13.RGMII1_TD2 */ 140 140 + J721E_IOPAD(0x3c, PIN_OUTPUT, 4) /* (AD24) PRG1_PRU0_GPO14.RGMII1_TD3 */ 141 141 + J721E_IOPAD(0x44, PIN_OUTPUT, 4) /* (AE24) PRG1_PRU0_GPO16.RGMII1_TXC */ 142 142 + J721E_IOPAD(0x40, PIN_OUTPUT, 4) /* (AC24) PRG1_PRU0_GPO15.RGMII1_TX_CTL */ 143 143 + >; 144 144 + }; 145 145 + 146 146 + rgmii2_default_pins: rgmii2-default-pins { 147 147 + pinctrl-single,pins = < 148 148 + J721E_IOPAD(0x58, PIN_INPUT, 4) /* (AE22) PRG1_PRU1_GPO0.RGMII2_RD0 */ 149 149 + J721E_IOPAD(0x5c, PIN_INPUT, 4) /* (AG23) PRG1_PRU1_GPO1.RGMII2_RD1 */ 150 150 + J721E_IOPAD(0x60, PIN_INPUT, 4) /* (AF23) PRG1_PRU1_GPO2.RGMII2_RD2 */ 151 151 + J721E_IOPAD(0x64, PIN_INPUT, 4) /* (AD23) PRG1_PRU1_GPO3.RGMII2_RD3 */ 152 152 + J721E_IOPAD(0x70, PIN_INPUT, 4) /* (AE23) PRG1_PRU1_GPO6.RGMII2_RXC */ 153 153 + J721E_IOPAD(0x68, PIN_INPUT, 4) /* (AH24) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 154 154 + J721E_IOPAD(0x84, PIN_OUTPUT, 4) /* (AJ25) PRG1_PRU1_GPO11.RGMII2_TD0 */ 155 155 + J721E_IOPAD(0x88, PIN_OUTPUT, 4) /* (AH25) PRG1_PRU1_GPO12.RGMII2_TD1 */ 156 156 + J721E_IOPAD(0x8c, PIN_OUTPUT, 4) /* (AG25) PRG1_PRU1_GPO13.RGMII2_TD2 */ 157 157 + J721E_IOPAD(0x90, PIN_OUTPUT, 4) /* (AH26) PRG1_PRU1_GPO14.RGMII2_TD3 */ 158 158 + J721E_IOPAD(0x98, PIN_OUTPUT, 4) /* (AJ26) PRG1_PRU1_GPO16.RGMII2_TXC */ 159 159 + J721E_IOPAD(0x94, PIN_OUTPUT, 4) /* (AJ27) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 160 160 + >; 161 161 + }; 162 162 + 163 163 + rgmii3_default_pins: rgmii3-default-pins { 164 164 + pinctrl-single,pins = < 165 165 + J721E_IOPAD(0xb0, PIN_INPUT, 4) /* (AF28) PRG0_PRU0_GPO0.RGMII3_RD0 */ 166 166 + J721E_IOPAD(0xb4, PIN_INPUT, 4) /* (AE28) PRG0_PRU0_GPO1.RGMII3_RD1 */ 167 167 + J721E_IOPAD(0xb8, PIN_INPUT, 4) /* (AE27) PRG0_PRU0_GPO2.RGMII3_RD2 */ 168 168 + J721E_IOPAD(0xbc, PIN_INPUT, 4) /* (AD26) PRG0_PRU0_GPO3.RGMII3_RD3 */ 169 169 + J721E_IOPAD(0xc8, PIN_INPUT, 4) /* (AE26) PRG0_PRU0_GPO6.RGMII3_RXC */ 170 170 + J721E_IOPAD(0xc0, PIN_INPUT, 4) /* (AD25) PRG0_PRU0_GPO4.RGMII3_RX_CTL */ 171 171 + J721E_IOPAD(0xdc, PIN_OUTPUT, 4) /* (AJ28) PRG0_PRU0_GPO11.RGMII3_TD0 */ 172 172 + J721E_IOPAD(0xe0, PIN_OUTPUT, 4) /* (AH27) PRG0_PRU0_GPO12.RGMII3_TD1 */ 173 173 + J721E_IOPAD(0xe4, PIN_OUTPUT, 4) /* (AH29) PRG0_PRU0_GPO13.RGMII3_TD2 */ 174 174 + J721E_IOPAD(0xe8, PIN_OUTPUT, 4) /* (AG28) PRG0_PRU0_GPO14.RGMII3_TD3 */ 175 175 + J721E_IOPAD(0xf0, PIN_OUTPUT, 4) /* (AH28) PRG0_PRU0_GPO16.RGMII3_TXC */ 176 176 + J721E_IOPAD(0xec, PIN_OUTPUT, 4) /* (AG27) PRG0_PRU0_GPO15.RGMII3_TX_CTL */ 177 177 + >; 178 178 + }; 179 179 + 180 180 + rgmii4_default_pins: rgmii4-default-pins { 181 181 + pinctrl-single,pins = < 182 182 + J721E_IOPAD(0x100, PIN_INPUT, 4) /* (AE29) PRG0_PRU1_GPO0.RGMII4_RD0 */ 183 183 + J721E_IOPAD(0x104, PIN_INPUT, 4) /* (AD28) PRG0_PRU1_GPO1.RGMII4_RD1 */ 184 184 + J721E_IOPAD(0x108, PIN_INPUT, 4) /* (AD27) PRG0_PRU1_GPO2.RGMII4_RD2 */ 185 185 + J721E_IOPAD(0x10c, PIN_INPUT, 4) /* (AC25) PRG0_PRU1_GPO3.RGMII4_RD3 */ 186 186 + J721E_IOPAD(0x118, PIN_INPUT, 4) /* (AC26) PRG0_PRU1_GPO6.RGMII4_RXC */ 187 187 + J721E_IOPAD(0x110, PIN_INPUT, 4) /* (AD29) PRG0_PRU1_GPO4.RGMII4_RX_CTL */ 188 188 + J721E_IOPAD(0x12c, PIN_OUTPUT, 4) /* (AG26) PRG0_PRU1_GPO11.RGMII4_TD0 */ 189 189 + J721E_IOPAD(0x130, PIN_OUTPUT, 4) /* (AF27) PRG0_PRU1_GPO12.RGMII4_TD1 */ 190 190 + J721E_IOPAD(0x134, PIN_OUTPUT, 4) /* (AF26) PRG0_PRU1_GPO13.RGMII4_TD2 */ 191 191 + J721E_IOPAD(0x138, PIN_OUTPUT, 4) /* (AE25) PRG0_PRU1_GPO14.RGMII4_TD3 */ 192 192 + J721E_IOPAD(0x140, PIN_OUTPUT, 4) /* (AG29) PRG0_PRU1_GPO16.RGMII4_TXC */ 193 193 + J721E_IOPAD(0x13c, PIN_OUTPUT, 4) /* (AF29) PRG0_PRU1_GPO15.RGMII4_TX_CTL */ 194 194 + >; 195 195 + }; 196 196 + };

+1 -1

arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso

reviewed

··· 10 10 /plugin/; 11 11 12 12 #include <dt-bindings/gpio/gpio.h> 13 13 - #include <dt-bindings/mux/ti-serdes.h> 14 13 #include <dt-bindings/phy/phy.h> 15 14 #include <dt-bindings/phy/phy-cadence.h> 16 15 17 16 #include "k3-pinctrl.h" 17 17 + #include "k3-serdes.h" 18 18 19 19 &{/} { 20 20 aliases {

+32 -16

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

reviewed

··· 7 7 #include <dt-bindings/phy/phy.h> 8 8 #include <dt-bindings/phy/phy-ti.h> 9 9 #include <dt-bindings/mux/mux.h> 10 10 - #include <dt-bindings/mux/ti-serdes.h> 10 10 + 11 11 + #include "k3-serdes.h" 11 12 12 13 / { 13 14 cmn_refclk: clock-cmnrefclk { ··· 77 76 }; 78 77 79 78 ehrpwm_tbclk: clock-controller@4140 { 80 80 - compatible = "ti,am654-ehrpwm-tbclk", "syscon"; 79 79 + compatible = "ti,am654-ehrpwm-tbclk"; 81 80 reg = <0x4140 0x18>; 82 81 #clock-cells = <1>; 83 82 }; ··· 365 364 366 365 main_ringacc: ringacc@3c000000 { 367 366 compatible = "ti,am654-navss-ringacc"; 368 368 - reg = <0x0 0x3c000000 0x0 0x400000>, 369 369 - <0x0 0x38000000 0x0 0x400000>, 370 370 - <0x0 0x31120000 0x0 0x100>, 371 371 - <0x0 0x33000000 0x0 0x40000>; 372 372 - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 367 367 + reg = <0x0 0x3c000000 0x0 0x400000>, 368 368 + <0x0 0x38000000 0x0 0x400000>, 369 369 + <0x0 0x31120000 0x0 0x100>, 370 370 + <0x0 0x33000000 0x0 0x40000>, 371 371 + <0x0 0x31080000 0x0 0x40000>; 372 372 + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 373 373 ti,num-rings = <1024>; 374 374 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 375 375 ti,sci = <&dmsc>; ··· 380 378 381 379 main_udmap: dma-controller@31150000 { 382 380 compatible = "ti,j721e-navss-main-udmap"; 383 383 - reg = <0x0 0x31150000 0x0 0x100>, 384 384 - <0x0 0x34000000 0x0 0x100000>, 385 385 - <0x0 0x35000000 0x0 0x100000>; 381 381 + reg = <0x0 0x31150000 0x0 0x100>, 382 382 + <0x0 0x34000000 0x0 0x100000>, 383 383 + <0x0 0x35000000 0x0 0x100000>; 386 384 reg-names = "gcfg", "rchanrt", "tchanrt"; 387 385 msi-parent = <&main_udmass_inta>; 388 386 #dma-cells = <1>; ··· 662 660 assigned-clock-parents = <&k3_clks 293 13>; 663 661 }; 664 662 665 665 - wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 663 663 + wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div { 666 664 clocks = <&wiz1_refclk_dig>; 667 665 #clock-cells = <0>; 668 666 }; ··· 1340 1338 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 1341 1339 clocks = <&k3_clks 105 0>; 1342 1340 clock-names = "gpio"; 1341 1341 + status = "disabled"; 1343 1342 }; 1344 1343 1345 1344 main_gpio1: gpio@601000 { ··· 1357 1354 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 1358 1355 clocks = <&k3_clks 106 0>; 1359 1356 clock-names = "gpio"; 1357 1357 + status = "disabled"; 1360 1358 }; 1361 1359 1362 1360 main_gpio2: gpio@610000 { ··· 1375 1371 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 1376 1372 clocks = <&k3_clks 107 0>; 1377 1373 clock-names = "gpio"; 1374 1374 + status = "disabled"; 1378 1375 }; 1379 1376 1380 1377 main_gpio3: gpio@611000 { ··· 1392 1387 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 1393 1388 clocks = <&k3_clks 108 0>; 1394 1389 clock-names = "gpio"; 1390 1390 + status = "disabled"; 1395 1391 }; 1396 1392 1397 1393 main_gpio4: gpio@620000 { ··· 1410 1404 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 1411 1405 clocks = <&k3_clks 109 0>; 1412 1406 clock-names = "gpio"; 1407 1407 + status = "disabled"; 1413 1408 }; 1414 1409 1415 1410 main_gpio5: gpio@621000 { ··· 1427 1420 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 1428 1421 clocks = <&k3_clks 110 0>; 1429 1422 clock-names = "gpio"; 1423 1423 + status = "disabled"; 1430 1424 }; 1431 1425 1432 1426 main_gpio6: gpio@630000 { ··· 1445 1437 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1446 1438 clocks = <&k3_clks 111 0>; 1447 1439 clock-names = "gpio"; 1440 1440 + status = "disabled"; 1448 1441 }; 1449 1442 1450 1443 main_gpio7: gpio@631000 { ··· 1462 1453 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1463 1454 clocks = <&k3_clks 112 0>; 1464 1455 clock-names = "gpio"; 1456 1456 + status = "disabled"; 1465 1457 }; 1466 1458 1467 1459 main_sdhci0: mmc@4f80000 { ··· 1487 1477 ti,itap-del-sel-ddr52 = <0x3>; 1488 1478 ti,trm-icp = <0x8>; 1489 1479 dma-coherent; 1480 1480 + status = "disabled"; 1490 1481 }; 1491 1482 1492 1483 main_sdhci1: mmc@4fb0000 { ··· 1515 1504 ti,clkbuf-sel = <0x7>; 1516 1505 dma-coherent; 1517 1506 sdhci-caps-mask = <0x2 0x0>; 1507 1507 + status = "disabled"; 1518 1508 }; 1519 1509 1520 1510 main_sdhci2: mmc@4f98000 { ··· 1543 1531 ti,clkbuf-sel = <0x7>; 1544 1532 dma-coherent; 1545 1533 sdhci-caps-mask = <0x2 0x0>; 1534 1534 + status = "disabled"; 1546 1535 }; 1547 1536 1548 1537 usbss0: cdns-usb@4104000 { ··· 1774 1761 "vp1", "vp2", "vp3", "vp4", 1775 1762 "wb"; 1776 1763 1777 1777 - clocks = <&k3_clks 152 0>, 1778 1778 - <&k3_clks 152 1>, 1779 1779 - <&k3_clks 152 4>, 1780 1780 - <&k3_clks 152 9>, 1781 1781 - <&k3_clks 152 13>; 1764 1764 + clocks = <&k3_clks 152 0>, 1765 1765 + <&k3_clks 152 1>, 1766 1766 + <&k3_clks 152 4>, 1767 1767 + <&k3_clks 152 9>, 1768 1768 + <&k3_clks 152 13>; 1782 1769 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1783 1770 1784 1771 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; ··· 2121 2108 ti,sci-proc-ids = <0x03 0xff>; 2122 2109 resets = <&k3_reset 142 1>; 2123 2110 firmware-name = "j7-c66_0-fw"; 2111 2111 + status = "disabled"; 2124 2112 }; 2125 2113 2126 2114 c66_1: dsp@4d81800000 { ··· 2135 2121 ti,sci-proc-ids = <0x04 0xff>; 2136 2122 resets = <&k3_reset 143 1>; 2137 2123 firmware-name = "j7-c66_1-fw"; 2124 2124 + status = "disabled"; 2138 2125 }; 2139 2126 2140 2127 c71_0: dsp@64800000 { ··· 2148 2133 ti,sci-proc-ids = <0x30 0xff>; 2149 2134 resets = <&k3_reset 15 1>; 2150 2135 firmware-name = "j7-c71_0-fw"; 2136 2136 + status = "disabled"; 2151 2137 }; 2152 2138 2153 2139 icssg0: icssg@b000000 {

+16 -9

arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi

reviewed

··· 281 281 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 282 282 clocks = <&k3_clks 113 0>; 283 283 clock-names = "gpio"; 284 284 + status = "disabled"; 284 285 }; 285 286 286 287 wkup_gpio1: gpio@42100000 { ··· 298 297 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 299 298 clocks = <&k3_clks 114 0>; 300 299 clock-names = "gpio"; 300 300 + status = "disabled"; 301 301 }; 302 302 303 303 mcu_i2c0: i2c@40b00000 { ··· 337 335 status = "disabled"; 338 336 }; 339 337 340 340 - fss: fss@47000000 { 338 338 + fss: bus@47000000 { 341 339 compatible = "simple-bus"; 342 340 reg = <0x0 0x47000000 0x0 0x100>; 343 341 #address-cells = <2>; ··· 380 378 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 381 379 #address-cells = <1>; 382 380 #size-cells = <0>; 381 381 + status = "disabled"; 383 382 }; 384 383 385 384 ospi1: spi@47050000 { ··· 395 392 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 396 393 #address-cells = <1>; 397 394 #size-cells = <0>; 395 395 + status = "disabled"; 398 396 }; 399 397 }; 400 398 ··· 411 407 dmas = <&main_udmap 0x7400>, 412 408 <&main_udmap 0x7401>; 413 409 dma-names = "fifo0", "fifo1"; 410 410 + status = "disabled"; 414 411 415 412 adc { 416 413 #io-channel-cells = <1>; ··· 431 426 dmas = <&main_udmap 0x7402>, 432 427 <&main_udmap 0x7403>; 433 428 dma-names = "fifo0", "fifo1"; 429 429 + status = "disabled"; 434 430 435 431 adc { 436 432 #io-channel-cells = <1>; ··· 451 445 452 446 mcu_ringacc: ringacc@2b800000 { 453 447 compatible = "ti,am654-navss-ringacc"; 454 454 - reg = <0x0 0x2b800000 0x0 0x400000>, 455 455 - <0x0 0x2b000000 0x0 0x400000>, 456 456 - <0x0 0x28590000 0x0 0x100>, 457 457 - <0x0 0x2a500000 0x0 0x40000>; 458 458 - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 448 448 + reg = <0x0 0x2b800000 0x0 0x400000>, 449 449 + <0x0 0x2b000000 0x0 0x400000>, 450 450 + <0x0 0x28590000 0x0 0x100>, 451 451 + <0x0 0x2a500000 0x0 0x40000>, 452 452 + <0x0 0x28440000 0x0 0x40000>; 453 453 + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 459 454 ti,num-rings = <286>; 460 455 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 461 456 ti,sci = <&dmsc>; ··· 466 459 467 460 mcu_udmap: dma-controller@285c0000 { 468 461 compatible = "ti,j721e-navss-mcu-udmap"; 469 469 - reg = <0x0 0x285c0000 0x0 0x100>, 470 470 - <0x0 0x2a800000 0x0 0x40000>, 471 471 - <0x0 0x2aa00000 0x0 0x40000>; 462 462 + reg = <0x0 0x285c0000 0x0 0x100>, 463 463 + <0x0 0x2a800000 0x0 0x40000>, 464 464 + <0x0 0x2aa00000 0x0 0x40000>; 472 465 reg-names = "gcfg", "rchanrt", "tchanrt"; 473 466 msi-parent = <&main_udmass_inta>; 474 467 #dma-cells = <1>;

+9 -51

arch/arm64/boot/dts/ti/k3-j721e-sk.dts

reviewed

··· 582 582 pinctrl-0 = <&main_uart1_pins_default>; 583 583 }; 584 584 585 585 - &main_sdhci0 { 586 586 - /* Unused */ 587 587 - status = "disabled"; 588 588 - }; 589 589 - 590 585 &main_sdhci1 { 591 586 /* SD Card */ 587 587 + status = "okay"; 592 588 vmmc-supply = <&vdd_mmc1>; 593 589 vqmmc-supply = <&vdd_sd_dv_alt>; 594 590 pinctrl-names = "default"; ··· 593 597 disable-wp; 594 598 }; 595 599 596 596 - &main_sdhci2 { 597 597 - /* Unused */ 598 598 - status = "disabled"; 599 599 - }; 600 600 - 601 600 &ospi0 { 601 601 + status = "okay"; 602 602 pinctrl-names = "default"; 603 603 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 604 604 ··· 656 664 }; 657 665 }; 658 666 }; 659 659 - }; 660 660 - 661 661 - &ospi1 { 662 662 - /* Unused */ 663 663 - status = "disabled"; 664 667 }; 665 668 666 669 &main_i2c0 { ··· 731 744 }; 732 745 733 746 &main_gpio0 { 747 747 + status = "okay"; 734 748 pinctrl-names = "default"; 735 749 pinctrl-0 = <&rpi_header_gpio0_pins_default>; 736 750 }; 737 751 738 752 &main_gpio1 { 753 753 + status = "okay"; 739 754 pinctrl-names = "default"; 740 755 pinctrl-0 = <&rpi_header_gpio1_pins_default>; 741 756 }; 742 757 743 743 - &main_gpio2 { 744 744 - status = "disabled"; 745 745 - }; 746 746 - 747 747 - &main_gpio3 { 748 748 - status = "disabled"; 749 749 - }; 750 750 - 751 751 - &main_gpio4 { 752 752 - status = "disabled"; 753 753 - }; 754 754 - 755 755 - &main_gpio5 { 756 756 - status = "disabled"; 757 757 - }; 758 758 - 759 759 - &main_gpio6 { 760 760 - status = "disabled"; 761 761 - }; 762 762 - 763 763 - &main_gpio7 { 764 764 - status = "disabled"; 765 765 - }; 766 766 - 767 767 - &wkup_gpio1 { 768 768 - status = "disabled"; 758 758 + &wkup_gpio0 { 759 759 + status = "okay"; 769 760 }; 770 761 771 762 &usb_serdes_mux { ··· 826 861 maximum-speed = "super-speed"; 827 862 phys = <&serdes2_usb_link>; 828 863 phy-names = "cdns3,usb3-phy"; 829 829 - }; 830 830 - 831 831 - &tscadc0 { 832 832 - /* Unused */ 833 833 - status = "disabled"; 834 834 - }; 835 835 - 836 836 - &tscadc1 { 837 837 - /* Unused */ 838 838 - status = "disabled"; 839 864 }; 840 865 841 866 &mcu_cpsw { ··· 1053 1098 }; 1054 1099 1055 1100 &c66_0 { 1101 1101 + status = "okay"; 1056 1102 mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; 1057 1103 memory-region = <&c66_0_dma_memory_region>, 1058 1104 <&c66_0_memory_region>; 1059 1105 }; 1060 1106 1061 1107 &c66_1 { 1108 1108 + status = "okay"; 1062 1109 mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; 1063 1110 memory-region = <&c66_1_dma_memory_region>, 1064 1111 <&c66_1_memory_region>; 1065 1112 }; 1066 1113 1067 1114 &c71_0 { 1115 1115 + status = "okay"; 1068 1116 mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; 1069 1117 memory-region = <&c71_0_dma_memory_region>, 1070 1118 <&c71_0_memory_region>;

+4 -13

arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi

reviewed

··· 201 201 }; 202 202 }; 203 203 204 204 - &wkup_i2c0 { 205 205 - status = "okay"; 206 206 - pinctrl-names = "default"; 207 207 - pinctrl-0 = <&wkup_i2c0_pins_default>; 208 208 - clock-frequency = <400000>; 209 209 - 210 210 - eeprom@50 { 211 211 - /* CAV24C256WE-GT3 */ 212 212 - compatible = "atmel,24c256"; 213 213 - reg = <0x50>; 214 214 - }; 215 215 - }; 216 216 - 217 204 &ospi0 { 205 205 + status = "okay"; 218 206 pinctrl-names = "default"; 219 207 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 220 208 ··· 425 437 }; 426 438 427 439 &c66_0 { 440 440 + status = "okay"; 428 441 mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; 429 442 memory-region = <&c66_0_dma_memory_region>, 430 443 <&c66_0_memory_region>; 431 444 }; 432 445 433 446 &c66_1 { 447 447 + status = "okay"; 434 448 mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; 435 449 memory-region = <&c66_1_dma_memory_region>, 436 450 <&c66_1_memory_region>; 437 451 }; 438 452 439 453 &c71_0 { 454 454 + status = "okay"; 440 455 mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; 441 456 memory-region = <&c71_0_dma_memory_region>, 442 457 <&c71_0_memory_region>;

+65 -23

arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts

reviewed

··· 11 11 #include <dt-bindings/net/ti-dp83867.h> 12 12 #include <dt-bindings/phy/phy-cadence.h> 13 13 #include <dt-bindings/phy/phy.h> 14 14 - #include <dt-bindings/mux/ti-serdes.h> 14 14 + 15 15 + #include "k3-serdes.h" 15 16 16 17 / { 17 18 compatible = "ti,j721s2-evm", "ti,j721s2"; ··· 30 29 can0 = &main_mcan16; 31 30 can1 = &mcu_mcan0; 32 31 can2 = &mcu_mcan1; 32 32 + can3 = &main_mcan3; 33 33 + can4 = &main_mcan5; 33 34 }; 34 35 35 36 evm_12v0: fixedregulator-evm12v0 { ··· 112 109 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; 113 110 }; 114 111 112 112 + transceiver3: can-phy3 { 113 113 + compatible = "ti,tcan1043"; 114 114 + #phy-cells = <0>; 115 115 + max-bitrate = <5000000>; 116 116 + standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; 117 117 + enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; 118 118 + mux-states = <&mux0 1>; 119 119 + }; 120 120 + 121 121 + transceiver4: can-phy4 { 122 122 + compatible = "ti,tcan1042"; 123 123 + #phy-cells = <0>; 124 124 + max-bitrate = <5000000>; 125 125 + standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>; 126 126 + mux-states = <&mux1 1>; 127 127 + }; 115 128 }; 116 129 117 130 &main_pmx0 { ··· 169 150 main_usbss0_pins_default: main-usbss0-default-pins { 170 151 pinctrl-single,pins = < 171 152 J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ 153 153 + >; 154 154 + }; 155 155 + 156 156 + main_mcan3_pins_default: main-mcan3-default-pins { 157 157 + pinctrl-single,pins = < 158 158 + J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */ 159 159 + J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */ 160 160 + >; 161 161 + }; 162 162 + 163 163 + main_mcan5_pins_default: main-mcan5-default-pins { 164 164 + pinctrl-single,pins = < 165 165 + J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */ 166 166 + J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */ 172 167 >; 173 168 }; 174 169 }; ··· 282 249 J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ 283 250 >; 284 251 }; 252 252 + }; 285 253 254 254 + &wkup_pmx1 { 286 255 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 287 256 pinctrl-single,pins = < 288 288 - J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ 289 289 - J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ 290 290 - J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ 291 291 - J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ 292 292 - J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ 293 293 - J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ 294 294 - J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ 295 295 - J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ 296 296 - J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ 257 257 + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ 258 258 + J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ 259 259 + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ 260 260 + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ 261 261 + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ 262 262 + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ 263 263 + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ 264 264 + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ 297 265 >; 298 266 }; 299 267 }; 300 268 301 301 - &main_gpio2 { 302 302 - status = "disabled"; 269 269 + &main_gpio0 { 270 270 + status = "okay"; 303 271 }; 304 272 305 305 - &main_gpio4 { 306 306 - status = "disabled"; 307 307 - }; 308 308 - 309 309 - &main_gpio6 { 310 310 - status = "disabled"; 311 311 - }; 312 312 - 313 313 - &wkup_gpio1 { 314 314 - status = "disabled"; 273 273 + &wkup_gpio0 { 274 274 + status = "okay"; 315 275 }; 316 276 317 277 &wkup_uart0 { ··· 358 332 359 333 &main_sdhci0 { 360 334 /* eMMC */ 335 335 + status = "okay"; 361 336 non-removable; 362 337 ti,driver-strength-ohm = <50>; 363 338 disable-wp; ··· 366 339 367 340 &main_sdhci1 { 368 341 /* SD card */ 342 342 + status = "okay"; 369 343 pinctrl-0 = <&main_mmc1_pins_default>; 370 344 pinctrl-names = "default"; 371 345 disable-wp; ··· 435 407 pinctrl-names = "default"; 436 408 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 437 409 438 438 - flash@0{ 410 410 + flash@0 { 439 411 compatible = "jedec,spi-nor"; 440 412 reg = <0x0>; 441 413 spi-tx-bus-width = <1>; ··· 487 459 adc { 488 460 ti,adc-channels = <0 1 2 3 4 5 6 7>; 489 461 }; 462 462 + }; 463 463 + 464 464 + &main_mcan3 { 465 465 + status = "okay"; 466 466 + pinctrl-names = "default"; 467 467 + pinctrl-0 = <&main_mcan3_pins_default>; 468 468 + phys = <&transceiver3>; 469 469 + }; 470 470 + 471 471 + &main_mcan5 { 472 472 + status = "okay"; 473 473 + pinctrl-names = "default"; 474 474 + pinctrl-0 = <&main_mcan5_pins_default>; 475 475 + phys = <&transceiver4>; 490 476 };

+85

arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /** 3 3 + * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board. 4 4 + * 5 5 + * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM 6 6 + * 7 7 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 8 8 + */ 9 9 + 10 10 + /dts-v1/; 11 11 + /plugin/; 12 12 + 13 13 + #include <dt-bindings/gpio/gpio.h> 14 14 + #include <dt-bindings/net/ti-dp83867.h> 15 15 + 16 16 + #include "k3-pinctrl.h" 17 17 + 18 18 + &{/} { 19 19 + aliases { 20 20 + ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; 21 21 + }; 22 22 + }; 23 23 + 24 24 + &main_pmx0 { 25 25 + main_cpsw_mdio_default_pins: main-cpsw-mdio-default-pins { 26 26 + pinctrl-single,pins = < 27 27 + J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */ 28 28 + J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */ 29 29 + >; 30 30 + }; 31 31 + 32 32 + rgmii1_default_pins: rgmii1-default-pins { 33 33 + pinctrl-single,pins = < 34 34 + J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */ 35 35 + J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */ 36 36 + J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */ 37 37 + J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */ 38 38 + J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */ 39 39 + J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */ 40 40 + J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */ 41 41 + J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */ 42 42 + J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */ 43 43 + J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */ 44 44 + J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */ 45 45 + J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */ 46 46 + >; 47 47 + }; 48 48 + }; 49 49 + 50 50 + &exp1 { 51 51 + p15 { 52 52 + /* P15 - EXP_MUX2 */ 53 53 + gpio-hog; 54 54 + gpios = <13 GPIO_ACTIVE_HIGH>; 55 55 + output-high; 56 56 + line-name = "EXP_MUX2"; 57 57 + }; 58 58 + }; 59 59 + 60 60 + &main_cpsw { 61 61 + status = "okay"; 62 62 + pinctrl-names = "default"; 63 63 + pinctrl-0 = <&rgmii1_default_pins>; 64 64 + }; 65 65 + 66 66 + &main_cpsw_mdio { 67 67 + status = "okay"; 68 68 + pinctrl-names = "default"; 69 69 + pinctrl-0 = <&main_cpsw_mdio_default_pins>; 70 70 + #address-cells = <1>; 71 71 + #size-cells = <0>; 72 72 + 73 73 + main_cpsw_phy0: ethernet-phy@0 { 74 74 + reg = <0>; 75 75 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 76 76 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 77 77 + ti,min-output-impedance; 78 78 + }; 79 79 + }; 80 80 + 81 81 + &main_cpsw_port1 { 82 82 + status = "okay"; 83 83 + phy-mode = "rgmii-rxid"; 84 84 + phy-handle = <&main_cpsw_phy0>; 85 85 + };

+190 -2

arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi

reviewed

··· 51 51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 52 52 }; 53 53 54 54 + phy_gmii_sel_cpsw: phy@34 { 55 55 + compatible = "ti,am654-phy-gmii-sel"; 56 56 + reg = <0x34 0x4>; 57 57 + #phy-cells = <1>; 58 58 + }; 59 59 + 54 60 serdes_ln_ctrl: mux-controller@80 { 55 61 compatible = "mmio-mux"; 56 62 reg = <0x80 0x10>; ··· 64 58 mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ 65 59 <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ 66 60 }; 61 61 + 62 62 + ehrpwm_tbclk: clock-controller@140 { 63 63 + compatible = "ti,am654-ehrpwm-tbclk"; 64 64 + reg = <0x140 0x18>; 65 65 + #clock-cells = <1>; 66 66 + }; 67 67 + }; 68 68 + 69 69 + main_ehrpwm0: pwm@3000000 { 70 70 + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 71 71 + #pwm-cells = <3>; 72 72 + reg = <0x00 0x3000000 0x00 0x100>; 73 73 + power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 74 74 + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>; 75 75 + clock-names = "tbclk", "fck"; 76 76 + status = "disabled"; 77 77 + }; 78 78 + 79 79 + main_ehrpwm1: pwm@3010000 { 80 80 + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 81 81 + #pwm-cells = <3>; 82 82 + reg = <0x00 0x3010000 0x00 0x100>; 83 83 + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 84 84 + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>; 85 85 + clock-names = "tbclk", "fck"; 86 86 + status = "disabled"; 87 87 + }; 88 88 + 89 89 + main_ehrpwm2: pwm@3020000 { 90 90 + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 91 91 + #pwm-cells = <3>; 92 92 + reg = <0x00 0x3020000 0x00 0x100>; 93 93 + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 94 94 + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>; 95 95 + clock-names = "tbclk", "fck"; 96 96 + status = "disabled"; 97 97 + }; 98 98 + 99 99 + main_ehrpwm3: pwm@3030000 { 100 100 + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 101 101 + #pwm-cells = <3>; 102 102 + reg = <0x00 0x3030000 0x00 0x100>; 103 103 + power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 104 104 + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>; 105 105 + clock-names = "tbclk", "fck"; 106 106 + status = "disabled"; 107 107 + }; 108 108 + 109 109 + main_ehrpwm4: pwm@3040000 { 110 110 + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 111 111 + #pwm-cells = <3>; 112 112 + reg = <0x00 0x3040000 0x00 0x100>; 113 113 + power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 114 114 + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>; 115 115 + clock-names = "tbclk", "fck"; 116 116 + status = "disabled"; 117 117 + }; 118 118 + 119 119 + main_ehrpwm5: pwm@3050000 { 120 120 + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 121 121 + #pwm-cells = <3>; 122 122 + reg = <0x00 0x3050000 0x00 0x100>; 123 123 + power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 124 124 + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>; 125 125 + clock-names = "tbclk", "fck"; 126 126 + status = "disabled"; 67 127 }; 68 128 69 129 gic500: interrupt-controller@1800000 { ··· 579 507 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 580 508 clocks = <&k3_clks 111 0>; 581 509 clock-names = "gpio"; 510 510 + status = "disabled"; 582 511 }; 583 512 584 513 main_gpio2: gpio@610000 { ··· 596 523 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 597 524 clocks = <&k3_clks 112 0>; 598 525 clock-names = "gpio"; 526 526 + status = "disabled"; 599 527 }; 600 528 601 529 main_gpio4: gpio@620000 { ··· 613 539 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 614 540 clocks = <&k3_clks 113 0>; 615 541 clock-names = "gpio"; 542 542 + status = "disabled"; 616 543 }; 617 544 618 545 main_gpio6: gpio@630000 { ··· 630 555 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 631 556 clocks = <&k3_clks 114 0>; 632 557 clock-names = "gpio"; 558 558 + status = "disabled"; 633 559 }; 634 560 635 561 main_i2c0: i2c@2000000 { ··· 741 665 mmc-hs200-1_8v; 742 666 mmc-hs400-1_8v; 743 667 dma-coherent; 668 668 + status = "disabled"; 744 669 }; 745 670 746 671 main_sdhci1: mmc@4fb0000 { ··· 771 694 dma-coherent; 772 695 /* Masking support for SDR104 capability */ 773 696 sdhci-caps-mask = <0x00000003 0x00000000>; 697 697 + status = "disabled"; 774 698 }; 775 699 776 700 main_navss: bus@30000000 { ··· 1071 993 reg = <0x0 0x3c000000 0x0 0x400000>, 1072 994 <0x0 0x38000000 0x0 0x400000>, 1073 995 <0x0 0x31120000 0x0 0x100>, 1074 1074 - <0x0 0x33000000 0x0 0x40000>; 1075 1075 - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 996 996 + <0x0 0x33000000 0x0 0x40000>, 997 997 + <0x0 0x31080000 0x0 0x40000>; 998 998 + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 1076 999 ti,num-rings = <1024>; 1077 1000 ti,sci-rm-range-gp-rings = <0x1>; 1078 1001 ti,sci = <&sms>; ··· 1115 1036 interrupt-names = "cpts"; 1116 1037 ti,cpts-periodic-outputs = <6>; 1117 1038 ti,cpts-ext-ts-inputs = <8>; 1039 1039 + }; 1040 1040 + }; 1041 1041 + 1042 1042 + main_cpsw: ethernet@c200000 { 1043 1043 + compatible = "ti,j721e-cpsw-nuss"; 1044 1044 + reg = <0x00 0xc200000 0x00 0x200000>; 1045 1045 + reg-names = "cpsw_nuss"; 1046 1046 + ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>; 1047 1047 + #address-cells = <2>; 1048 1048 + #size-cells = <2>; 1049 1049 + dma-coherent; 1050 1050 + clocks = <&k3_clks 28 28>; 1051 1051 + clock-names = "fck"; 1052 1052 + power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; 1053 1053 + 1054 1054 + dmas = <&main_udmap 0xc640>, 1055 1055 + <&main_udmap 0xc641>, 1056 1056 + <&main_udmap 0xc642>, 1057 1057 + <&main_udmap 0xc643>, 1058 1058 + <&main_udmap 0xc644>, 1059 1059 + <&main_udmap 0xc645>, 1060 1060 + <&main_udmap 0xc646>, 1061 1061 + <&main_udmap 0xc647>, 1062 1062 + <&main_udmap 0x4640>; 1063 1063 + dma-names = "tx0", "tx1", "tx2", "tx3", 1064 1064 + "tx4", "tx5", "tx6", "tx7", 1065 1065 + "rx"; 1066 1066 + 1067 1067 + status = "disabled"; 1068 1068 + 1069 1069 + ethernet-ports { 1070 1070 + #address-cells = <1>; 1071 1071 + #size-cells = <0>; 1072 1072 + 1073 1073 + main_cpsw_port1: port@1 { 1074 1074 + reg = <1>; 1075 1075 + ti,mac-only; 1076 1076 + label = "port1"; 1077 1077 + phys = <&phy_gmii_sel_cpsw 1>; 1078 1078 + status = "disabled"; 1079 1079 + }; 1080 1080 + }; 1081 1081 + 1082 1082 + main_cpsw_mdio: mdio@f00 { 1083 1083 + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 1084 1084 + reg = <0x00 0xf00 0x00 0x100>; 1085 1085 + #address-cells = <1>; 1086 1086 + #size-cells = <0>; 1087 1087 + clocks = <&k3_clks 28 28>; 1088 1088 + clock-names = "fck"; 1089 1089 + bus_freq = <1000000>; 1090 1090 + status = "disabled"; 1091 1091 + }; 1092 1092 + 1093 1093 + cpts@3d000 { 1094 1094 + compatible = "ti,am65-cpts"; 1095 1095 + reg = <0x00 0x3d000 0x00 0x400>; 1096 1096 + clocks = <&k3_clks 28 3>; 1097 1097 + clock-names = "cpts"; 1098 1098 + interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1099 1099 + interrupt-names = "cpts"; 1100 1100 + ti,cpts-ext-ts-inputs = <4>; 1101 1101 + ti,cpts-periodic-outputs = <2>; 1118 1102 }; 1119 1103 }; 1120 1104 ··· 1648 1506 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; 1649 1507 clocks = <&k3_clks 346 1>; 1650 1508 status = "disabled"; 1509 1509 + }; 1510 1510 + 1511 1511 + dss: dss@4a00000 { 1512 1512 + compatible = "ti,j721e-dss"; 1513 1513 + reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1514 1514 + <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1515 1515 + <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1516 1516 + <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1517 1517 + <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1518 1518 + <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1519 1519 + <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1520 1520 + <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1521 1521 + <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1522 1522 + <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1523 1523 + <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1524 1524 + <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1525 1525 + <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1526 1526 + <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1527 1527 + <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1528 1528 + <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1529 1529 + <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1530 1530 + reg-names = "common_m", "common_s0", 1531 1531 + "common_s1", "common_s2", 1532 1532 + "vidl1", "vidl2","vid1","vid2", 1533 1533 + "ovr1", "ovr2", "ovr3", "ovr4", 1534 1534 + "vp1", "vp2", "vp3", "vp4", 1535 1535 + "wb"; 1536 1536 + clocks = <&k3_clks 158 0>, 1537 1537 + <&k3_clks 158 2>, 1538 1538 + <&k3_clks 158 5>, 1539 1539 + <&k3_clks 158 14>, 1540 1540 + <&k3_clks 158 18>; 1541 1541 + clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1542 1542 + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 1543 1543 + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1544 1544 + <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1545 1545 + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1546 1546 + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1547 1547 + interrupt-names = "common_m", 1548 1548 + "common_s0", 1549 1549 + "common_s1", 1550 1550 + "common_s2"; 1551 1551 + status = "disabled"; 1552 1552 + 1553 1553 + dss_ports: ports { 1554 1554 + }; 1651 1555 }; 1652 1556 };

+6 -3

arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi

reviewed

··· 323 323 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 324 324 clocks = <&k3_clks 115 0>; 325 325 clock-names = "gpio"; 326 326 + status = "disabled"; 326 327 }; 327 328 328 329 wkup_gpio1: gpio@42100000 { ··· 340 339 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 341 340 clocks = <&k3_clks 116 0>; 342 341 clock-names = "gpio"; 342 342 + status = "disabled"; 343 343 }; 344 344 345 345 wkup_i2c0: i2c@42120000 { ··· 442 440 status = "disabled"; 443 441 }; 444 442 445 445 - mcu_navss: bus@28380000{ 443 443 + mcu_navss: bus@28380000 { 446 444 compatible = "simple-mfd"; 447 445 #address-cells = <2>; 448 446 #size-cells = <2>; ··· 457 455 reg = <0x0 0x2b800000 0x0 0x400000>, 458 456 <0x0 0x2b000000 0x0 0x400000>, 459 457 <0x0 0x28590000 0x0 0x100>, 460 460 - <0x0 0x2a500000 0x0 0x40000>; 461 461 - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 458 458 + <0x0 0x2a500000 0x0 0x40000>, 459 459 + <0x0 0x28440000 0x0 0x40000>; 460 460 + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 462 461 ti,num-rings = <286>; 463 462 ti,sci-rm-range-gp-rings = <0x1>; 464 463 ti,sci = <&sms>;

+12 -3

arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi

reviewed

··· 31 31 }; 32 32 }; 33 33 34 34 + mux0: mux-controller { 35 35 + compatible = "gpio-mux"; 36 36 + #mux-state-cells = <1>; 37 37 + mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; 38 38 + }; 39 39 + 40 40 + mux1: mux-controller { 41 41 + compatible = "gpio-mux"; 42 42 + #mux-state-cells = <1>; 43 43 + mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; 44 44 + }; 45 45 + 34 46 transceiver0: can-phy0 { 35 47 /* standby pin has been grounded by default */ 36 48 compatible = "ti,tcan1042"; ··· 56 44 pinctrl-single,pins = < 57 45 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ 58 46 J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ 59 59 - J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ 60 60 - J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ 61 61 - J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ 62 47 J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ 63 48 J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ 64 49 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */

+63 -28

arch/arm64/boot/dts/ti/k3-j784s4-evm.dts

reviewed

··· 252 252 }; 253 253 254 254 &main_pmx0 { 255 255 + bootph-all; 255 256 main_uart8_pins_default: main-uart8-default-pins { 257 257 + bootph-all; 256 258 pinctrl-single,pins = < 257 259 J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ 258 260 J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ ··· 271 269 }; 272 270 273 271 main_mmc1_pins_default: main-mmc1-default-pins { 272 272 + bootph-all; 274 273 pinctrl-single,pins = < 275 274 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 276 275 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ ··· 292 289 }; 293 290 294 291 &wkup_pmx2 { 292 292 + bootph-all; 295 293 wkup_uart0_pins_default: wkup-uart0-default-pins { 294 294 + bootph-all; 296 295 pinctrl-single,pins = < 297 296 J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ 298 297 J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ ··· 304 299 }; 305 300 306 301 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 302 302 + bootph-all; 307 303 pinctrl-single,pins = < 308 304 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ 309 305 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ ··· 312 306 }; 313 307 314 308 mcu_uart0_pins_default: mcu-uart0-default-pins { 309 309 + bootph-all; 315 310 pinctrl-single,pins = < 316 311 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ 317 312 J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ ··· 347 340 348 341 mcu_adc0_pins_default: mcu-adc0-default-pins { 349 342 pinctrl-single,pins = < 350 350 - J784S4_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ 351 351 - J784S4_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ 352 352 - J784S4_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ 353 353 - J784S4_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ 354 354 - J784S4_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ 355 355 - J784S4_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ 356 356 - J784S4_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ 357 357 - J784S4_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ 343 343 + J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ 344 344 + J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ 345 345 + J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ 346 346 + J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ 347 347 + J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ 348 348 + J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ 349 349 + J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ 350 350 + J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ 358 351 >; 359 352 }; 360 353 361 354 mcu_adc1_pins_default: mcu-adc1-default-pins { 362 355 pinctrl-single,pins = < 363 363 - J784S4_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ 364 364 - J784S4_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ 365 365 - J784S4_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ 366 366 - J784S4_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ 367 367 - J784S4_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ 368 368 - J784S4_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ 369 369 - J784S4_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ 370 370 - J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ 356 356 + J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ 357 357 + J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ 358 358 + J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ 359 359 + J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ 360 360 + J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ 361 361 + J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ 362 362 + J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ 363 363 + J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ 371 364 >; 372 365 }; 373 366 }; 374 367 375 368 &wkup_pmx0 { 369 369 + bootph-all; 376 370 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 371 371 + bootph-all; 377 372 pinctrl-single,pins = < 378 373 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ 379 374 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ ··· 388 379 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ 389 380 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ 390 381 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ 391 391 - J784S4_WKUP_IOPAD(0x03c, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_CSn3.MCU_OSPI0_ECC_FAIL */ 392 392 - J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_CSn2.MCU_OSPI0_RESET_OUT0 */ 382 382 + >; 383 383 + }; 384 384 + }; 385 385 + 386 386 + &wkup_pmx1 { 387 387 + bootph-all; 388 388 + mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { 389 389 + bootph-all; 390 390 + pinctrl-single,pins = < 391 391 + J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ 392 392 + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ 393 393 >; 394 394 }; 395 395 396 396 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 397 397 + bootph-all; 397 398 pinctrl-single,pins = < 398 398 - J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ 399 399 - J784S4_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ 400 400 - J784S4_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ 401 401 - J784S4_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ 402 402 - J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ 403 403 - J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ 404 404 - J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ 405 405 - J784S4_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ 399 399 + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ 400 400 + J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ 401 401 + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ 402 402 + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ 403 403 + J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ 404 404 + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ 405 405 + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ 406 406 + J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ 406 407 >; 407 408 }; 408 409 }; ··· 425 406 }; 426 407 427 408 &wkup_i2c0 { 409 409 + bootph-all; 428 410 status = "okay"; 429 411 pinctrl-names = "default"; 430 412 pinctrl-0 = <&wkup_i2c0_pins_default>; ··· 439 419 }; 440 420 441 421 &mcu_uart0 { 422 422 + bootph-all; 442 423 status = "okay"; 443 424 pinctrl-names = "default"; 444 425 pinctrl-0 = <&mcu_uart0_pins_default>; 445 426 }; 446 427 447 428 &main_uart8 { 429 429 + bootph-all; 448 430 status = "okay"; 449 431 pinctrl-names = "default"; 450 432 pinctrl-0 = <&main_uart8_pins_default>; 451 433 }; 452 434 435 435 + &ufs_wrapper { 436 436 + status = "okay"; 437 437 + }; 438 438 + 453 439 &fss { 440 440 + bootph-all; 454 441 status = "okay"; 455 442 }; 456 443 457 444 &ospi0 { 445 445 + bootph-all; 458 446 status = "okay"; 459 447 pinctrl-names = "default"; 460 460 - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 448 448 + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; 461 449 462 450 flash@0 { 451 451 + bootph-all; 463 452 compatible = "jedec,spi-nor"; 464 453 reg = <0x0>; 465 454 spi-tx-bus-width = <8>; ··· 516 487 }; 517 488 518 489 partition@3fc0000 { 490 490 + bootph-all; 519 491 label = "ospi.phypattern"; 520 492 reg = <0x3fc0000 0x40000>; 521 493 }; ··· 525 495 }; 526 496 527 497 &ospi1 { 498 498 + bootph-all; 528 499 status = "okay"; 529 500 pinctrl-names = "default"; 530 501 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 531 502 532 532 - flash@0{ 503 503 + flash@0 { 504 504 + bootph-all; 533 505 compatible = "jedec,spi-nor"; 534 506 reg = <0x0>; 535 507 spi-tx-bus-width = <1>; ··· 579 547 }; 580 548 581 549 partition@3fc0000 { 550 550 + bootph-all; 582 551 label = "qspi.phypattern"; 583 552 reg = <0x3fc0000 0x40000>; 584 553 }; ··· 624 591 }; 625 592 626 593 &main_sdhci0 { 594 594 + bootph-all; 627 595 /* eMMC */ 628 596 status = "okay"; 629 597 non-removable; ··· 633 599 }; 634 600 635 601 &main_sdhci1 { 602 602 + bootph-all; 636 603 /* SD card */ 637 604 status = "okay"; 638 605 pinctrl-0 = <&main_mmc1_pins_default>;

+36 -5

arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi

reviewed

··· 60 60 #interrupt-cells = <1>; 61 61 ti,sci = <&sms>; 62 62 ti,sci-dev-id = <10>; 63 63 - ti,interrupt-ranges = <8 360 56>; 63 63 + ti,interrupt-ranges = <8 392 56>; 64 64 }; 65 65 66 66 main_pmx0: pinctrl@11c000 { ··· 618 618 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 619 619 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 620 620 clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; 621 621 - clock-names = "clk_ahb", "clk_xin"; 621 621 + clock-names = "clk_ahb", "clk_xin"; 622 622 assigned-clocks = <&k3_clks 140 2>; 623 623 assigned-clock-parents = <&k3_clks 140 3>; 624 624 bus-width = <8>; ··· 646 646 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 647 647 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 648 648 clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; 649 649 - clock-names = "clk_ahb", "clk_xin"; 649 649 + clock-names = "clk_ahb", "clk_xin"; 650 650 assigned-clocks = <&k3_clks 141 4>; 651 651 assigned-clock-parents = <&k3_clks 141 5>; 652 652 bus-width = <4>; ··· 670 670 }; 671 671 672 672 main_navss: bus@30000000 { 673 673 + bootph-all; 673 674 compatible = "simple-bus"; 674 675 #address-cells = <2>; 675 676 #size-cells = <2>; ··· 706 705 }; 707 706 708 707 secure_proxy_main: mailbox@32c00000 { 708 708 + bootph-all; 709 709 compatible = "ti,am654-secure-proxy"; 710 710 #mbox-cells = <1>; 711 711 reg-names = "target_data", "rt", "scfg"; ··· 968 966 reg = <0x00 0x3c000000 0x00 0x400000>, 969 967 <0x00 0x38000000 0x00 0x400000>, 970 968 <0x00 0x31120000 0x00 0x100>, 971 971 - <0x00 0x33000000 0x00 0x40000>; 972 972 - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 969 969 + <0x00 0x33000000 0x00 0x40000>, 970 970 + <0x00 0x31080000 0x00 0x40000>; 971 971 + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 973 972 ti,num-rings = <1024>; 974 973 ti,sci-rm-range-gp-rings = <0x1>; 975 974 ti,sci = <&sms>; ··· 1373 1370 status = "disabled"; 1374 1371 }; 1375 1372 1373 1373 + ufs_wrapper: ufs-wrapper@4e80000 { 1374 1374 + compatible = "ti,j721e-ufs"; 1375 1375 + reg = <0x00 0x4e80000 0x00 0x100>; 1376 1376 + power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>; 1377 1377 + clocks = <&k3_clks 387 3>; 1378 1378 + assigned-clocks = <&k3_clks 387 3>; 1379 1379 + assigned-clock-parents = <&k3_clks 387 6>; 1380 1380 + ranges; 1381 1381 + #address-cells = <2>; 1382 1382 + #size-cells = <2>; 1383 1383 + status = "disabled"; 1384 1384 + 1385 1385 + ufs@4e84000 { 1386 1386 + compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1387 1387 + reg = <0x00 0x4e84000 0x00 0x10000>; 1388 1388 + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1389 1389 + freq-table-hz = <250000000 250000000>, <19200000 19200000>, 1390 1390 + <19200000 19200000>; 1391 1391 + clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>; 1392 1392 + clock-names = "core_clk", "phy_clk", "ref_clk"; 1393 1393 + dma-coherent; 1394 1394 + }; 1395 1395 + }; 1396 1396 + 1376 1397 main_r5fss0: r5fss@5c00000 { 1377 1398 compatible = "ti,j721s2-r5fss"; 1378 1399 ti,cluster-mode = <1>; ··· 1527 1500 ti,sci-proc-ids = <0x30 0xff>; 1528 1501 resets = <&k3_reset 30 1>; 1529 1502 firmware-name = "j784s4-c71_0-fw"; 1503 1503 + status = "disabled"; 1530 1504 }; 1531 1505 1532 1506 c71_1: dsp@65800000 { ··· 1540 1512 ti,sci-proc-ids = <0x31 0xff>; 1541 1513 resets = <&k3_reset 33 1>; 1542 1514 firmware-name = "j784s4-c71_1-fw"; 1515 1515 + status = "disabled"; 1543 1516 }; 1544 1517 1545 1518 c71_2: dsp@66800000 { ··· 1553 1524 ti,sci-proc-ids = <0x32 0xff>; 1554 1525 resets = <&k3_reset 37 1>; 1555 1526 firmware-name = "j784s4-c71_2-fw"; 1527 1527 + status = "disabled"; 1556 1528 }; 1557 1529 1558 1530 c71_3: dsp@67800000 { ··· 1566 1536 ti,sci-proc-ids = <0x33 0xff>; 1567 1537 resets = <&k3_reset 40 1>; 1568 1538 firmware-name = "j784s4-c71_3-fw"; 1539 1539 + status = "disabled"; 1569 1540 }; 1570 1541 };

+14 -4

arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi

reviewed

··· 7 7 8 8 &cbass_mcu_wakeup { 9 9 sms: system-controller@44083000 { 10 10 + bootph-all; 10 11 compatible = "ti,k2g-sci"; 11 12 ti,host-id = <12>; 12 13 ··· 20 19 reg = <0x00 0x44083000 0x00 0x1000>; 21 20 22 21 k3_pds: power-controller { 22 22 + bootph-all; 23 23 compatible = "ti,sci-pm-domain"; 24 24 #power-domain-cells = <2>; 25 25 }; 26 26 27 27 k3_clks: clock-controller { 28 28 + bootph-all; 28 29 compatible = "ti,k2g-sci-clk"; 29 30 #clock-cells = <2>; 30 31 }; 31 32 32 33 k3_reset: reset-controller { 34 34 + bootph-all; 33 35 compatible = "ti,sci-reset"; 34 36 #reset-cells = <2>; 35 37 }; 36 38 }; 37 39 38 40 chipid@43000014 { 41 41 + bootph-all; 39 42 compatible = "ti,am654-chipid"; 40 43 reg = <0x00 0x43000014 0x00 0x4>; 41 44 }; ··· 112 107 #interrupt-cells = <1>; 113 108 ti,sci = <&sms>; 114 109 ti,sci-dev-id = <177>; 115 115 - ti,interrupt-ranges = <16 928 16>; 110 110 + ti,interrupt-ranges = <16 960 16>; 116 111 }; 117 112 118 113 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ ··· 166 161 }; 167 162 168 163 mcu_timer1: timer@40410000 { 164 164 + bootph-all; 169 165 compatible = "ti,am654-timer"; 170 166 reg = <0x00 0x40410000 0x00 0x400>; 171 167 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; ··· 447 441 status = "disabled"; 448 442 }; 449 443 450 450 - mcu_navss: bus@28380000{ 444 444 + mcu_navss: bus@28380000 { 445 445 + bootph-all; 451 446 compatible = "simple-bus"; 452 447 #address-cells = <2>; 453 448 #size-cells = <2>; ··· 458 451 dma-ranges; 459 452 460 453 mcu_ringacc: ringacc@2b800000 { 454 454 + bootph-all; 461 455 compatible = "ti,am654-navss-ringacc"; 462 456 reg = <0x00 0x2b800000 0x00 0x400000>, 463 457 <0x00 0x2b000000 0x00 0x400000>, 464 458 <0x00 0x28590000 0x00 0x100>, 465 465 - <0x00 0x2a500000 0x00 0x40000>; 466 466 - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 459 459 + <0x00 0x2a500000 0x00 0x40000>, 460 460 + <0x00 0x28440000 0x00 0x40000>; 461 461 + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 467 462 ti,num-rings = <286>; 468 463 ti,sci-rm-range-gp-rings = <0x1>; 469 464 ti,sci = <&sms>; ··· 474 465 }; 475 466 476 467 mcu_udmap: dma-controller@285c0000 { 468 468 + bootph-all; 477 469 compatible = "ti,j721e-navss-mcu-udmap"; 478 470 reg = <0x00 0x285c0000 0x00 0x100>, 479 471 <0x00 0x2a800000 0x00 0x40000>,

+2

arch/arm64/boot/dts/ti/k3-j784s4.dtsi

reviewed

··· 228 228 }; 229 229 230 230 cbass_main: bus@100000 { 231 231 + bootph-all; 231 232 compatible = "simple-bus"; 232 233 #address-cells = <2>; 233 234 #size-cells = <2>; ··· 264 263 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; 265 264 266 265 cbass_mcu_wakeup: bus@28380000 { 266 266 + bootph-all; 267 267 compatible = "simple-bus"; 268 268 #address-cells = <2>; 269 269 #size-cells = <2>;

+12

arch/arm64/boot/dts/ti/k3-pinctrl.h

reviewed

··· 11 11 #define PULLUDEN_SHIFT (16) 12 12 #define PULLTYPESEL_SHIFT (17) 13 13 #define RXACTIVE_SHIFT (18) 14 14 + #define DEBOUNCE_SHIFT (11) 14 15 15 16 #define PULL_DISABLE (1 << PULLUDEN_SHIFT) 16 17 #define PULL_ENABLE (0 << PULLUDEN_SHIFT) ··· 30 29 #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) 31 30 #define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) 32 31 32 32 + #define PIN_DEBOUNCE_DISABLE (0 << DEBOUNCE_SHIFT) 33 33 + #define PIN_DEBOUNCE_CONF1 (1 << DEBOUNCE_SHIFT) 34 34 + #define PIN_DEBOUNCE_CONF2 (2 << DEBOUNCE_SHIFT) 35 35 + #define PIN_DEBOUNCE_CONF3 (3 << DEBOUNCE_SHIFT) 36 36 + #define PIN_DEBOUNCE_CONF4 (4 << DEBOUNCE_SHIFT) 37 37 + #define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) 38 38 + #define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) 39 39 + 33 40 #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 34 41 #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 42 42 + 43 43 + #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 44 44 + #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 35 45 36 46 #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 37 47 #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))

+204

arch/arm64/boot/dts/ti/k3-serdes.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 2 + /* 3 3 + * This header provides constants for SERDES MUX for TI SoCs 4 4 + * 5 5 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 6 6 + */ 7 7 + 8 8 + #ifndef DTS_ARM64_TI_K3_SERDES_H 9 9 + #define DTS_ARM64_TI_K3_SERDES_H 10 10 + 11 11 + /* J721E */ 12 12 + 13 13 + #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 14 14 + #define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 15 15 + #define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 16 16 + #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 17 17 + 18 18 + #define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 19 19 + #define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 20 20 + #define J721E_SERDES0_LANE1_USB3_0 0x2 21 21 + #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 22 22 + 23 23 + #define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 24 24 + #define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 25 25 + #define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 26 26 + #define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 27 27 + 28 28 + #define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 29 29 + #define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 30 30 + #define J721E_SERDES1_LANE1_USB3_1 0x2 31 31 + #define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 32 32 + 33 33 + #define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 34 34 + #define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 35 35 + #define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 36 36 + #define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 37 37 + 38 38 + #define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 39 39 + #define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 40 40 + #define J721E_SERDES2_LANE1_USB3_1 0x2 41 41 + #define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 42 42 + 43 43 + #define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 44 44 + #define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 45 45 + #define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 46 46 + #define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 47 47 + 48 48 + #define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 49 49 + #define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 50 50 + #define J721E_SERDES3_LANE1_USB3_0 0x2 51 51 + #define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 52 52 + 53 53 + #define J721E_SERDES4_LANE0_EDP_LANE0 0x0 54 54 + #define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 55 55 + #define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 56 56 + #define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 57 57 + 58 58 + #define J721E_SERDES4_LANE1_EDP_LANE1 0x0 59 59 + #define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 60 60 + #define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 61 61 + #define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 62 62 + 63 63 + #define J721E_SERDES4_LANE2_EDP_LANE2 0x0 64 64 + #define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 65 65 + #define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 66 66 + #define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 67 67 + 68 68 + #define J721E_SERDES4_LANE3_EDP_LANE3 0x0 69 69 + #define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 70 70 + #define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 71 71 + #define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 72 72 + 73 73 + /* J7200 */ 74 74 + 75 75 + #define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 76 76 + #define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 77 77 + #define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 78 78 + #define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 79 79 + 80 80 + #define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 81 81 + #define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 82 82 + #define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 83 83 + #define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 84 84 + 85 85 + #define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 86 86 + #define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 87 87 + #define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 88 88 + #define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 89 89 + 90 90 + #define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 91 91 + #define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 92 92 + #define J7200_SERDES0_LANE3_USB 0x2 93 93 + #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 94 94 + 95 95 + /* AM64 */ 96 96 + 97 97 + #define AM64_SERDES0_LANE0_PCIE0 0x0 98 98 + #define AM64_SERDES0_LANE0_USB 0x1 99 99 + 100 100 + /* J721S2 */ 101 101 + 102 102 + #define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 103 103 + #define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 104 104 + #define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2 105 105 + #define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3 106 106 + 107 107 + #define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 108 108 + #define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 109 109 + #define J721S2_SERDES0_LANE1_USB 0x2 110 110 + #define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3 111 111 + 112 112 + #define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 113 113 + #define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 114 114 + #define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 115 115 + #define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 116 116 + 117 117 + #define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 118 118 + #define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 119 119 + #define J721S2_SERDES0_LANE3_USB 0x2 120 120 + #define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 121 121 + 122 122 + /* J784S4 */ 123 123 + 124 124 + #define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0 125 125 + #define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1 126 126 + #define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2 127 127 + #define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3 128 128 + 129 129 + #define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0 130 130 + #define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1 131 131 + #define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2 132 132 + #define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3 133 133 + 134 134 + #define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0 135 135 + #define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1 136 136 + #define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2 137 137 + #define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3 138 138 + 139 139 + #define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0 140 140 + #define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1 141 141 + #define J784S4_SERDES0_LANE3_USB 0x2 142 142 + #define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3 143 143 + 144 144 + #define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0 145 145 + #define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1 146 146 + #define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2 147 147 + #define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3 148 148 + 149 149 + #define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0 150 150 + #define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1 151 151 + #define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2 152 152 + #define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3 153 153 + 154 154 + #define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0 155 155 + #define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1 156 156 + #define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2 157 157 + #define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3 158 158 + 159 159 + #define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0 160 160 + #define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1 161 161 + #define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2 162 162 + #define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3 163 163 + 164 164 + #define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0 165 165 + #define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1 166 166 + #define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2 167 167 + #define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3 168 168 + 169 169 + #define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0 170 170 + #define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1 171 171 + #define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2 172 172 + #define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3 173 173 + 174 174 + #define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0 175 175 + #define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1 176 176 + #define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2 177 177 + #define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3 178 178 + 179 179 + #define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0 180 180 + #define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1 181 181 + #define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2 182 182 + #define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3 183 183 + 184 184 + #define J784S4_SERDES4_LANE0_EDP_LANE0 0x0 185 185 + #define J784S4_SERDES4_LANE0_QSGMII_LANE5 0x1 186 186 + #define J784S4_SERDES4_LANE0_IP3_UNUSED 0x2 187 187 + #define J784S4_SERDES4_LANE0_IP4_UNUSED 0x3 188 188 + 189 189 + #define J784S4_SERDES4_LANE1_EDP_LANE1 0x0 190 190 + #define J784S4_SERDES4_LANE1_QSGMII_LANE6 0x1 191 191 + #define J784S4_SERDES4_LANE1_IP3_UNUSED 0x2 192 192 + #define J784S4_SERDES4_LANE1_IP4_UNUSED 0x3 193 193 + 194 194 + #define J784S4_SERDES4_LANE2_EDP_LANE2 0x0 195 195 + #define J784S4_SERDES4_LANE2_QSGMII_LANE7 0x1 196 196 + #define J784S4_SERDES4_LANE2_IP3_UNUSED 0x2 197 197 + #define J784S4_SERDES4_LANE2_IP4_UNUSED 0x3 198 198 + 199 199 + #define J784S4_SERDES4_LANE3_EDP_LANE3 0x0 200 200 + #define J784S4_SERDES4_LANE3_QSGMII_LANE8 0x1 201 201 + #define J784S4_SERDES4_LANE3_USB 0x2 202 202 + #define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3 203 203 + 204 204 + #endif /* DTS_ARM64_TI_K3_SERDES_H */

+8

include/dt-bindings/mux/ti-serdes.h

reviewed

··· 6 6 #ifndef _DT_BINDINGS_MUX_TI_SERDES 7 7 #define _DT_BINDINGS_MUX_TI_SERDES 8 8 9 9 + /* 10 10 + * These bindings are deprecated, because they do not match the actual 11 11 + * concept of bindings but rather contain pure constants values used only 12 12 + * in DTS board files. 13 13 + * Instead include the header in the DTS source directory. 14 14 + */ 15 15 + #warning "These bindings are deprecated. Instead, use the header in the DTS source directory." 16 16 + 9 17 /* J721E */ 10 18 11 19 #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0