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cxl/pci: Check Mem_info_valid bit for each applicable DVSEC

In theory a device might set the mem_info_valid bit for a first range
after it is ready but before as second range has reached that state.
Therefore, the correct approach is to check the Mem_info_valid bit for
each applicable DVSEC range against HDM_COUNT, rather than only for the
DVSEC range 1. Consequently, let's move the check into the "for loop"
that handles each DVSEC range.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Yanfei Xu <yanfei.xu@intel.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20240828084231.1378789-4-yanfei.xu@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

authored by

Yanfei Xu and committed by
Dave Jiang 99bf0eeb 5c6e3d5a

+4 -4
+4 -4
drivers/cxl/core/pci.c
··· 324 324 if (!hdm_count || hdm_count > 2) 325 325 return -EINVAL; 326 326 327 - rc = cxl_dvsec_mem_range_valid(cxlds, 0); 328 - if (rc) 329 - return rc; 330 - 331 327 /* 332 328 * The current DVSEC values are moot if the memory capability is 333 329 * disabled, and they will remain moot after the HDM Decoder ··· 340 344 for (i = 0; i < hdm_count; i++) { 341 345 u64 base, size; 342 346 u32 temp; 347 + 348 + rc = cxl_dvsec_mem_range_valid(cxlds, i); 349 + if (rc) 350 + return rc; 343 351 344 352 rc = pci_read_config_dword( 345 353 pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp);