Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'usb-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB / Thunderbolt updates from Greg KH:
"Here is the big set of USB and Thunderbolt changes for 7.1-rc1.
Lots of little things in here, nothing major, just constant
improvements, updates, and new features. Highlights are:
- new USB power supply driver support.
These changes did touch outside of drivers/usb/ but got acks from
the relevant mantainers for them.
- dts file updates and conversions
- string function conversions into "safer" ones
- new device quirks
- xhci driver updates
- usb gadget driver minor fixes
- typec driver additions and updates
- small number of thunderbolt driver changes
- dwc3 driver updates and additions of new hardware support
- other minor driver updates
All of these have been in the linux-next tree for a while with no
reported issues"
* tag 'usb-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (176 commits)
usb: dwc3: starfive: Add JHB100 USB 2.0 DRD controller
dt-bindings: usb: dwc3: add support for StarFive JHB100
dt-bindings: usb: atmel,at91sam9rl-udc: convert to DT schema
dt-bindings: usb: atmel,at91rm9200-udc: convert to DT schema
dt-bindings: usb: generic-ehci: fix schema structure and add at91sam9g45 constraints
dt-bindings: usb: generic-ohci: add AT91RM9200 OHCI binding support
arm: dts: at91: remove unused #address-cells/#size-cells from sam9x60 udc node
drivers/usb/host: Fix spelling error 'seperate' -> 'separate'
usbip: tools: add hint when no exported devices are found
USB: serial: iuu_phoenix: fix iuutool author name
usb: gadget: f_ncm: validate minimum block_len in ncm_unwrap_ntb()
usb: gadget: f_phonet: fix skb frags[] overflow in pn_rx_complete()
usb: gadget: f_hid: Add missing error code
usb: typec: cros_ec_ucsi: Load driver from OF and ACPI definitions
dt-bindings: chrome: Add cros-ec-ucsi compatibility to typec binding
USB: of: Simplify with scoped for each OF child loop
usbip: validate number_of_packets in usbip_pack_ret_submit()
usb: gadget: renesas_usb3: validate endpoint index in standard request handlers
usb: core: config: reverse the size check of the SSP isoc endpoint descriptor
usb: typec: ucsi: Set usb mode on partner change
...
+4767
-1385
+2
-1
Documentation/ABI/testing/sysfs-class-power
+2
-1
Documentation/ABI/testing/sysfs-class-power
+15
-4
Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
+15
-4
Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
···
8
8
9
9
maintainers:
10
10
- Benson Leung <bleung@chromium.org>
11
-
- Prashant Malani <pmalani@chromium.org>
11
+
- Abhishek Pandit-Subedi <abhishekpandit@chromium.org>
12
+
- Andrei Kuchynski <akuchynski@chromium.org>
13
+
- Łukasz Bartosik <ukaszb@chromium.org>
14
+
- Jameson Thies <jthies@google.com>
12
15
13
16
description:
14
17
Chrome OS devices have an Embedded Controller(EC) which has access to
15
18
Type C port state. This node is intended to allow the host to read and
16
-
control the Type C ports. The node for this device should be under a
17
-
cros-ec node like google,cros-ec-spi.
19
+
control the Type C ports. This binding is compatible with both the
20
+
cros-ec-typec and cros-ec-ucsi drivers. The cros-ec-typec driver
21
+
supports the host command interface used by the Chrome OS EC with a
22
+
built-in Type-C port manager and external Type-C Port Controller
23
+
(TCPC). The cros-ec-ucsi driver supports the USB Type-C Connector
24
+
System Software (UCSI) interface used by the Chrome OS EC when the
25
+
platform has a separate power delivery controller (PDC). The node for
26
+
this device should be under a cros-ec node like google,cros-ec-spi.
18
27
19
28
properties:
20
29
compatible:
21
-
const: google,cros-ec-typec
30
+
enum:
31
+
- google,cros-ec-typec
32
+
- google,cros-ec-ucsi
22
33
23
34
'#address-cells':
24
35
const: 1
+37
-2
Documentation/devicetree/bindings/connector/usb-connector.yaml
+37
-2
Documentation/devicetree/bindings/connector/usb-connector.yaml
···
300
300
$ref: /schemas/types.yaml#/definitions/uint8-array
301
301
maxItems: 4
302
302
303
+
sink-load-step:
304
+
description: Indicates the preferred load step slew rate in mA/usec for
305
+
the port (in sink mode). This property is defined in "6.5.13.7" of
306
+
"USB Power Delivery Specification Revision 3.1 Version 1.8".
307
+
$ref: /schemas/types.yaml#/definitions/uint32
308
+
enum: [150, 500]
309
+
default: 150
310
+
311
+
sink-load-characteristics:
312
+
description: Indicates the port's (in sink mode) preferred load
313
+
characteristics. Users can leverage SINK_LOAD_CHAR() defined in
314
+
dt-bindings/usb/pd.h to populate this field. This property is defined in
315
+
"6.5.13.8" of "USB Power Delivery Specification Revision 3.1 Version 1.8".
316
+
$ref: /schemas/types.yaml#/definitions/uint16
317
+
318
+
sink-compliance:
319
+
description: Represents the types of sources the sink device has been tested
320
+
and certified with. This property is defined in "6.5.13.9" of
321
+
"USB Power Delivery Specification Revision 3.1 Version 1.8"
322
+
Bit 0 when set indicates it has been tested on LPS compliant source
323
+
Bit 1 when set indicates it has been tested on PS1 compliant source
324
+
Bit 2 when set indicates it has been tested on PS2 compliant source
325
+
$ref: /schemas/types.yaml#/definitions/uint8
326
+
maximum: 7
327
+
328
+
charging-adapter-pdp-milliwatt:
329
+
description: This corresponds to the Power Delivery Profile rating of the
330
+
charging adapter shipped or recommended for use with the connector port.
331
+
This property is a requirement to infer the USB PD property
332
+
"SPR Sink Operational PDP" given in "6.5.13.14" of
333
+
"USB Power Delivery Specification Revision 3.1 Version 1.8".
334
+
minimum: 0
335
+
maximum: 100000
336
+
303
337
dependencies:
304
338
pd-disable: [typec-power-opmode]
305
339
sink-vdos-v1: [ sink-vdos ]
···
365
331
"Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
366
332
Sink Capabilities Message, the order of each entry(PDO) should follow the
367
333
PD spec chapter 6.4.1. Required for power sink and power dual role. User
368
-
can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined
369
-
in dt-bindings/usb/pd.h.
334
+
can specify the sink PDO array via
335
+
PDO_FIXED/BATT/VAR/PPS_APDO/SPR_AVS_SNK_APDO() defined in
336
+
dt-bindings/usb/pd.h.
370
337
minItems: 1
371
338
maxItems: 7
372
339
$ref: /schemas/types.yaml#/definitions/uint32-array
+15
-1
Documentation/devicetree/bindings/mfd/maxim,max77759.yaml
+15
-1
Documentation/devicetree/bindings/mfd/maxim,max77759.yaml
···
16
16
The MAX77759 includes Battery Charger, Fuel Gauge, temperature sensors, USB
17
17
Type-C Port Controller (TCPC), NVMEM, and a GPIO expander.
18
18
19
+
allOf:
20
+
- $ref: /schemas/power/supply/power-supply.yaml#
21
+
19
22
properties:
20
23
compatible:
21
24
const: maxim,max77759
···
40
37
nvmem-0:
41
38
$ref: /schemas/nvmem/maxim,max77759-nvmem.yaml
42
39
40
+
chgin-otg-regulator:
41
+
type: object
42
+
description: Provides Boost for sourcing VBUS.
43
+
$ref: /schemas/regulator/regulator.yaml#
44
+
unevaluatedProperties: false
45
+
43
46
required:
44
47
- compatible
45
48
- interrupts
46
49
- reg
47
50
48
-
additionalProperties: false
51
+
unevaluatedProperties: false
49
52
50
53
examples:
51
54
- |
···
68
59
69
60
interrupt-controller;
70
61
#interrupt-cells = <2>;
62
+
power-supplies = <&maxtcpci>;
63
+
64
+
chgin-otg-regulator {
65
+
regulator-name = "chgin-otg";
66
+
};
71
67
72
68
gpio {
73
69
compatible = "maxim,max77759-gpio";
+76
Documentation/devicetree/bindings/usb/atmel,at91rm9200-udc.yaml
+76
Documentation/devicetree/bindings/usb/atmel,at91rm9200-udc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/usb/atmel,at91rm9200-udc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Atmel AT91 USB Device Controller (UDC)
8
+
9
+
maintainers:
10
+
- Nicolas Ferre <nicolas.ferre@microchip.com>
11
+
- Alexandre Belloni <alexandre.belloni@bootlin.com>
12
+
13
+
description:
14
+
The Atmel AT91 USB Device Controller provides USB gadget (device-mode)
15
+
functionality on AT91 SoCs. It requires a peripheral clock and an AHB
16
+
clock for operation and may optionally control VBUS power through a GPIO.
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- atmel,at91rm9200-udc
22
+
- atmel,at91sam9260-udc
23
+
- atmel,at91sam9261-udc
24
+
- atmel,at91sam9263-udc
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
interrupts:
30
+
maxItems: 1
31
+
32
+
clocks:
33
+
maxItems: 2
34
+
35
+
clock-names:
36
+
items:
37
+
- const: pclk
38
+
- const: hclk
39
+
40
+
atmel,vbus-gpio:
41
+
description: GPIO used to enable or control VBUS power for the USB bus.
42
+
maxItems: 1
43
+
44
+
atmel,matrix:
45
+
$ref: /schemas/types.yaml#/definitions/phandle
46
+
description: Phandle to the Atmel bus matrix controller.
47
+
48
+
atmel,pullup-gpio:
49
+
description:
50
+
GPIO controlling the USB D+ pull-up resistor used to signal device
51
+
connection to the host.
52
+
maxItems: 1
53
+
54
+
required:
55
+
- compatible
56
+
- reg
57
+
- interrupts
58
+
- clocks
59
+
- clock-names
60
+
61
+
additionalProperties: false
62
+
63
+
examples:
64
+
- |
65
+
#include <dt-bindings/interrupt-controller/irq.h>
66
+
#include <dt-bindings/clock/at91.h>
67
+
#include <dt-bindings/gpio/gpio.h>
68
+
gadget@fffa4000 {
69
+
compatible = "atmel,at91rm9200-udc";
70
+
reg = <0xfffa4000 0x4000>;
71
+
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
72
+
clocks = <&udc_clk>, <&udpck>;
73
+
clock-names = "pclk", "hclk";
74
+
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
75
+
};
76
+
...
+74
Documentation/devicetree/bindings/usb/atmel,at91sam9rl-udc.yaml
+74
Documentation/devicetree/bindings/usb/atmel,at91sam9rl-udc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/usb/atmel,at91sam9rl-udc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Atmel High-Speed USB Device Controller (USBA)
8
+
9
+
maintainers:
10
+
- Nicolas Ferre <nicolas.ferre@microchip.com>
11
+
- Alexandre Belloni <alexandre.belloni@bootlin.com>
12
+
13
+
description:
14
+
The Atmel High-Speed USB Device Controller (USBA) provides USB 2.0
15
+
high-speed gadget functionality on several Atmel and Microchip SoCs.
16
+
The controller requires a peripheral clock and a host clock for operation
17
+
and may optionally use a GPIO to detect VBUS presence.
18
+
19
+
properties:
20
+
compatible:
21
+
oneOf:
22
+
- enum:
23
+
- atmel,at91sam9rl-udc
24
+
- atmel,at91sam9g45-udc
25
+
- atmel,sama5d3-udc
26
+
- items:
27
+
- const: microchip,lan9662-udc
28
+
- const: atmel,sama5d3-udc
29
+
- const: microchip,sam9x60-udc
30
+
31
+
reg:
32
+
maxItems: 2
33
+
34
+
interrupts:
35
+
maxItems: 1
36
+
37
+
clocks:
38
+
maxItems: 2
39
+
40
+
clock-names:
41
+
minItems: 2
42
+
maxItems: 2
43
+
items:
44
+
enum: [pclk, hclk]
45
+
46
+
atmel,vbus-gpio:
47
+
description: GPIO used to detect the presence of VBUS, indicating that
48
+
the USB cable is connected.
49
+
maxItems: 1
50
+
51
+
required:
52
+
- compatible
53
+
- reg
54
+
- interrupts
55
+
- clocks
56
+
- clock-names
57
+
58
+
unevaluatedProperties: false
59
+
60
+
examples:
61
+
- |
62
+
#include <dt-bindings/interrupt-controller/irq.h>
63
+
#include <dt-bindings/clock/at91.h>
64
+
#include <dt-bindings/gpio/gpio.h>
65
+
gadget@fff78000 {
66
+
compatible = "atmel,at91sam9g45-udc";
67
+
reg = <0x00600000 0x80000
68
+
0xfff78000 0x400>;
69
+
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
70
+
clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
71
+
clock-names = "pclk", "hclk";
72
+
atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>;
73
+
};
74
+
...
-125
Documentation/devicetree/bindings/usb/atmel-usb.txt
-125
Documentation/devicetree/bindings/usb/atmel-usb.txt
···
1
-
Atmel SOC USB controllers
2
-
3
-
OHCI
4
-
5
-
Required properties:
6
-
- compatible: Should be "atmel,at91rm9200-ohci" for USB controllers
7
-
used in host mode.
8
-
- reg: Address and length of the register set for the device
9
-
- interrupts: Should contain ohci interrupt
10
-
- clocks: Should reference the peripheral, host and system clocks
11
-
- clock-names: Should contain three strings
12
-
"ohci_clk" for the peripheral clock
13
-
"hclk" for the host clock
14
-
"uhpck" for the system clock
15
-
- num-ports: Number of ports.
16
-
- atmel,vbus-gpio: If present, specifies a gpio that needs to be
17
-
activated for the bus to be powered.
18
-
- atmel,oc-gpio: If present, specifies a gpio that needs to be
19
-
activated for the overcurrent detection.
20
-
21
-
usb0: ohci@500000 {
22
-
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
23
-
reg = <0x00500000 0x100000>;
24
-
clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
25
-
clock-names = "ohci_clk", "hclk", "uhpck";
26
-
interrupts = <20 4>;
27
-
num-ports = <2>;
28
-
};
29
-
30
-
EHCI
31
-
32
-
Required properties:
33
-
- compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers
34
-
used in host mode.
35
-
- reg: Address and length of the register set for the device
36
-
- interrupts: Should contain ehci interrupt
37
-
- clocks: Should reference the peripheral and the UTMI clocks
38
-
- clock-names: Should contain two strings
39
-
"ehci_clk" for the peripheral clock
40
-
"usb_clk" for the UTMI clock
41
-
42
-
Optional properties:
43
-
- phy_type : For multi port host USB controllers, should be one of
44
-
"utmi", or "hsic".
45
-
46
-
usb1: ehci@800000 {
47
-
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
48
-
reg = <0x00800000 0x100000>;
49
-
interrupts = <22 4>;
50
-
clocks = <&utmi>, <&uhphs_clk>;
51
-
clock-names = "usb_clk", "ehci_clk";
52
-
};
53
-
54
-
AT91 USB device controller
55
-
56
-
Required properties:
57
-
- compatible: Should be one of the following
58
-
"atmel,at91rm9200-udc"
59
-
"atmel,at91sam9260-udc"
60
-
"atmel,at91sam9261-udc"
61
-
"atmel,at91sam9263-udc"
62
-
- reg: Address and length of the register set for the device
63
-
- interrupts: Should contain macb interrupt
64
-
- clocks: Should reference the peripheral and the AHB clocks
65
-
- clock-names: Should contain two strings
66
-
"pclk" for the peripheral clock
67
-
"hclk" for the AHB clock
68
-
69
-
Optional properties:
70
-
- atmel,vbus-gpio: If present, specifies a gpio that needs to be
71
-
activated for the bus to be powered.
72
-
73
-
usb1: gadget@fffa4000 {
74
-
compatible = "atmel,at91rm9200-udc";
75
-
reg = <0xfffa4000 0x4000>;
76
-
interrupts = <10 4>;
77
-
clocks = <&udc_clk>, <&udpck>;
78
-
clock-names = "pclk", "hclk";
79
-
atmel,vbus-gpio = <&pioC 5 0>;
80
-
};
81
-
82
-
Atmel High-Speed USB device controller
83
-
84
-
Required properties:
85
-
- compatible: Should be one of the following
86
-
"atmel,at91sam9rl-udc"
87
-
"atmel,at91sam9g45-udc"
88
-
"atmel,sama5d3-udc"
89
-
"microchip,sam9x60-udc"
90
-
"microchip,lan9662-udc"
91
-
For "microchip,lan9662-udc" the fallback "atmel,sama5d3-udc"
92
-
is required.
93
-
- reg: Address and length of the register set for the device
94
-
- interrupts: Should contain usba interrupt
95
-
- clocks: Should reference the peripheral and host clocks
96
-
- clock-names: Should contain two strings
97
-
"pclk" for the peripheral clock
98
-
"hclk" for the host clock
99
-
100
-
Deprecated property:
101
-
- ep childnode: To specify the number of endpoints and their properties.
102
-
103
-
Optional properties:
104
-
- atmel,vbus-gpio: If present, specifies a gpio that allows to detect whether
105
-
vbus is present (USB is connected).
106
-
107
-
Deprecated child node properties:
108
-
- name: Name of the endpoint.
109
-
- reg: Num of the endpoint.
110
-
- atmel,fifo-size: Size of the fifo.
111
-
- atmel,nb-banks: Number of banks.
112
-
- atmel,can-dma: Boolean to specify if the endpoint support DMA.
113
-
- atmel,can-isoc: Boolean to specify if the endpoint support ISOC.
114
-
115
-
usb2: gadget@fff78000 {
116
-
#address-cells = <1>;
117
-
#size-cells = <0>;
118
-
compatible = "atmel,at91sam9rl-udc";
119
-
reg = <0x00600000 0x80000
120
-
0xfff78000 0x400>;
121
-
interrupts = <27 4 0>;
122
-
clocks = <&utmi>, <&udphs_clk>;
123
-
clock-names = "hclk", "pclk";
124
-
atmel,vbus-gpio = <&pioB 19 0>;
125
-
};
+1
Documentation/devicetree/bindings/usb/cdns,usb3.yaml
+1
Documentation/devicetree/bindings/usb/cdns,usb3.yaml
+79
Documentation/devicetree/bindings/usb/corechips,sl6341.yaml
+79
Documentation/devicetree/bindings/usb/corechips,sl6341.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/usb/corechips,sl6341.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Corechips SL6341 USB 2.0/3.0 Hub Controller
8
+
9
+
maintainers:
10
+
- Alexey Charkov <alchark@flipper.net>
11
+
12
+
allOf:
13
+
- $ref: usb-hub.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
enum:
18
+
- usb3431,6241
19
+
- usb3431,6341
20
+
21
+
reg: true
22
+
23
+
peer-hub: true
24
+
25
+
reset-gpios:
26
+
description: GPIO controlling the RSTN pin.
27
+
28
+
vdd1v1-supply:
29
+
description:
30
+
The regulator that provides 1.1V core power to the hub.
31
+
32
+
vdd3v3-supply:
33
+
description:
34
+
The regulator that provides 3.3V IO power to the hub.
35
+
36
+
ports:
37
+
$ref: /schemas/graph.yaml#/properties/ports
38
+
39
+
patternProperties:
40
+
'^port@':
41
+
$ref: /schemas/graph.yaml#/properties/port
42
+
43
+
properties:
44
+
reg:
45
+
minimum: 1
46
+
maximum: 4
47
+
48
+
required:
49
+
- compatible
50
+
- reg
51
+
- vdd1v1-supply
52
+
53
+
unevaluatedProperties: false
54
+
55
+
examples:
56
+
- |
57
+
#include <dt-bindings/gpio/gpio.h>
58
+
usb {
59
+
#address-cells = <1>;
60
+
#size-cells = <0>;
61
+
62
+
/* 2.0 hub */
63
+
hub_2_0: hub@1 {
64
+
compatible = "usb3431,6241";
65
+
reg = <1>;
66
+
peer-hub = <&hub_3_0>;
67
+
reset-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
68
+
vdd1v1-supply = <&vdd1v1_hub>;
69
+
};
70
+
71
+
/* 3.0 hub */
72
+
hub_3_0: hub@2 {
73
+
compatible = "usb3431,6341";
74
+
reg = <2>;
75
+
peer-hub = <&hub_2_0>;
76
+
reset-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
77
+
vdd1v1-supply = <&vdd1v1_hub>;
78
+
};
79
+
};
+2
Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
+2
Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
+33
-13
Documentation/devicetree/bindings/usb/generic-ehci.yaml
+33
-13
Documentation/devicetree/bindings/usb/generic-ehci.yaml
···
9
9
maintainers:
10
10
- Greg Kroah-Hartman <gregkh@linuxfoundation.org>
11
11
12
-
allOf:
13
-
- $ref: usb-hcd.yaml
14
-
- if:
15
-
properties:
16
-
compatible:
17
-
not:
18
-
contains:
19
-
const: ibm,usb-ehci-440epx
20
-
then:
21
-
properties:
22
-
reg:
23
-
maxItems: 1
24
-
25
12
properties:
26
13
compatible:
27
14
oneOf:
···
153
166
- compatible
154
167
- reg
155
168
- interrupts
169
+
170
+
allOf:
171
+
- $ref: usb-hcd.yaml
172
+
- if:
173
+
properties:
174
+
compatible:
175
+
not:
176
+
contains:
177
+
const: ibm,usb-ehci-440epx
178
+
then:
179
+
properties:
180
+
reg:
181
+
maxItems: 1
182
+
- if:
183
+
properties:
184
+
compatible:
185
+
contains:
186
+
const: atmel,at91sam9g45-ehci
187
+
then:
188
+
properties:
189
+
clock-names:
190
+
items:
191
+
- const: usb_clk
192
+
- const: ehci_clk
193
+
194
+
phy_type:
195
+
enum:
196
+
- utmi
197
+
- hsic
198
+
199
+
required:
200
+
- clocks
201
+
- clock-names
156
202
157
203
unevaluatedProperties: false
158
204
+41
Documentation/devicetree/bindings/usb/generic-ohci.yaml
+41
Documentation/devicetree/bindings/usb/generic-ohci.yaml
···
55
55
- ti,ohci-omap3
56
56
- items:
57
57
- enum:
58
+
- atmel,at91rm9200-ohci
58
59
- cavium,octeon-6335-ohci
59
60
- nintendo,hollywood-usb-ohci
60
61
- nxp,ohci-nxp
···
138
137
The associated ISP1301 device. Necessary for the UDC controller for
139
138
connecting to the USB physical layer.
140
139
140
+
atmel,vbus-gpio:
141
+
description:
142
+
GPIO used to control or sense the USB VBUS power. Each entry
143
+
represents a VBUS-related GPIO; count and order may vary by hardware.
144
+
Entries follow standard GPIO specifier format. A value of 0 indicates
145
+
an unused or unavailable VBUS signal.
146
+
minItems: 1
147
+
maxItems: 3
148
+
149
+
atmel,oc-gpio:
150
+
description:
151
+
GPIO used to signal USB overcurrent condition. Each entry represents
152
+
an OC detection GPIO; count and order may vary by hardware. Entries
153
+
follow standard GPIO specifier format. A value of 0 indicates an
154
+
unused or unavailable OC signal.
155
+
minItems: 1
156
+
maxItems: 3
157
+
141
158
required:
142
159
- compatible
143
160
- reg
···
163
144
164
145
allOf:
165
146
- $ref: usb-hcd.yaml
147
+
- if:
148
+
properties:
149
+
compatible:
150
+
contains:
151
+
const: atmel,at91rm9200-ohci
152
+
then:
153
+
properties:
154
+
clock-names:
155
+
items:
156
+
- const: ohci_clk
157
+
- const: hclk
158
+
- const: uhpck
159
+
160
+
required:
161
+
- clocks
162
+
- clock-names
163
+
164
+
else:
165
+
properties:
166
+
atmel,vbus-gpio: false
167
+
atmel,oc-gpio: false
168
+
166
169
- if:
167
170
not:
168
171
properties:
+8
Documentation/devicetree/bindings/usb/maxim,max33359.yaml
+8
Documentation/devicetree/bindings/usb/maxim,max33359.yaml
···
32
32
description:
33
33
Properties for usb c connector.
34
34
35
+
vbus-supply:
36
+
description: Regulator to control sourcing Vbus.
37
+
35
38
required:
36
39
- compatible
37
40
- reg
···
56
53
reg = <0x25>;
57
54
interrupt-parent = <&gpa8>;
58
55
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
56
+
vbus-supply = <&chgin_otg_reg>;
59
57
60
58
connector {
61
59
compatible = "usb-c-connector";
···
79
75
PDO_FIXED(9000, 2000, 0)>;
80
76
sink-bc12-completion-time-ms = <500>;
81
77
pd-revision = /bits/ 8 <0x03 0x01 0x01 0x08>;
78
+
sink-load-step = <150>;
79
+
sink-load-characteristics = /bits/ 16 <SINK_LOAD_CHAR(0, 1, 1, 2)>;
80
+
sink-compliance = /bits/ 8 <(COMPLIANCE_LPS | COMPLIANCE_PS1)>;
81
+
charging-adapter-pdp-milliwatt = <18000>;
82
82
};
83
83
};
84
84
};
-23
Documentation/devicetree/bindings/usb/maxim,max3421.txt
-23
Documentation/devicetree/bindings/usb/maxim,max3421.txt
···
1
-
Maxim Integrated SPI-based USB 2.0 host controller MAX3421E
2
-
3
-
Required properties:
4
-
- compatible: Should be "maxim,max3421"
5
-
- spi-max-frequency: maximum frequency for this device must not exceed 26 MHz.
6
-
- reg: chip select number to which this device is connected.
7
-
- maxim,vbus-en-pin: <GPOUTx ACTIVE_LEVEL>
8
-
GPOUTx is the number (1-8) of the GPOUT pin of MAX3421E to drive Vbus.
9
-
ACTIVE_LEVEL is 0 or 1.
10
-
- interrupts: the interrupt line description for the interrupt controller.
11
-
The driver configures MAX3421E for active low level triggered interrupts,
12
-
configure your interrupt line accordingly.
13
-
14
-
Example:
15
-
16
-
usb@0 {
17
-
compatible = "maxim,max3421";
18
-
reg = <0>;
19
-
maxim,vbus-en-pin = <3 1>;
20
-
spi-max-frequency = <26000000>;
21
-
interrupt-parent = <&PIC>;
22
-
interrupts = <42>;
23
-
};
+67
Documentation/devicetree/bindings/usb/maxim,max3421.yaml
+67
Documentation/devicetree/bindings/usb/maxim,max3421.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/usb/maxim,max3421.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MAXIM MAX3421e USB Peripheral/Host Controller
8
+
9
+
maintainers:
10
+
- David Mosberger <davidm@egauge.net>
11
+
12
+
description: |
13
+
The controller provides USB2.0 compliant with Full Speed or Low Speed when in
14
+
the host mode. At peripheral, it operates at Full Speed. At both cases, it
15
+
uses a SPI interface.
16
+
Datasheet at:
17
+
https://www.analog.com/media/en/technical-documentation/data-sheets/max3421e.pdf
18
+
19
+
properties:
20
+
compatible:
21
+
const: maxim,max3421
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
spi-max-frequency:
30
+
maximum: 26000000
31
+
32
+
maxim,vbus-en-pin:
33
+
$ref: /schemas/types.yaml#/definitions/uint32-array
34
+
description:
35
+
One of eight GPOUT pins to control external VBUS power and the polarity
36
+
of the active level. It's an array of GPIO number and the active level of it.
37
+
minItems: 2
38
+
maxItems: 2
39
+
40
+
required:
41
+
- compatible
42
+
- reg
43
+
- interrupts
44
+
- maxim,vbus-en-pin
45
+
46
+
allOf:
47
+
- $ref: /schemas/spi/spi-peripheral-props.yaml#
48
+
49
+
unevaluatedProperties: false
50
+
51
+
examples:
52
+
- |
53
+
#include <dt-bindings/gpio/gpio.h>
54
+
#include <dt-bindings/interrupt-controller/irq.h>
55
+
spi {
56
+
#address-cells = <1>;
57
+
#size-cells = <0>;
58
+
59
+
usb@0 {
60
+
compatible = "maxim,max3421";
61
+
reg = <0>;
62
+
maxim,vbus-en-pin = <3 1>;
63
+
spi-max-frequency = <26000000>;
64
+
interrupt-parent = <&gpio>;
65
+
interrupts = <42>;
66
+
};
67
+
};
+3
Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
+3
Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
+123
Documentation/devicetree/bindings/usb/nxp,imx-dwc3.yaml
+123
Documentation/devicetree/bindings/usb/nxp,imx-dwc3.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
# Copyright 2026 NXP
3
+
%YAML 1.2
4
+
---
5
+
$id: http://devicetree.org/schemas/usb/nxp,imx-dwc3.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
+
8
+
title: NXP i.MX Soc USB Controller
9
+
10
+
maintainers:
11
+
- Xu Yang <xu.yang_2@nxp.com>
12
+
13
+
properties:
14
+
compatible:
15
+
oneOf:
16
+
- items:
17
+
- enum:
18
+
- nxp,imx94-dwc3
19
+
- nxp,imx95-dwc3
20
+
- const: nxp,imx8mp-dwc3
21
+
- const: nxp,imx8mp-dwc3
22
+
23
+
reg:
24
+
items:
25
+
- description: DWC3 core registers
26
+
- description: HSIO Block Control registers
27
+
- description: Wrapper registers of dwc3 core
28
+
29
+
reg-names:
30
+
items:
31
+
- const: core
32
+
- const: blkctl
33
+
- const: glue
34
+
35
+
interrupts:
36
+
items:
37
+
- description: DWC3 controller interrupt
38
+
- description: Wakeup interrupt from glue logic
39
+
40
+
interrupt-names:
41
+
items:
42
+
- const: dwc_usb3
43
+
- const: wakeup
44
+
45
+
iommus:
46
+
maxItems: 1
47
+
48
+
clocks:
49
+
items:
50
+
- description: System hsio root clock
51
+
- description: SoC Bus Clock for AHB/AXI/Native
52
+
- description: Reference clock for generating ITP when UTMI/ULPI PHY is suspended
53
+
- description: Suspend clock used for usb wakeup logic
54
+
55
+
clock-names:
56
+
items:
57
+
- const: hsio
58
+
- const: bus_early
59
+
- const: ref
60
+
- const: suspend
61
+
62
+
fsl,permanently-attached:
63
+
type: boolean
64
+
description:
65
+
Indicates if the device attached to a downstream port is
66
+
permanently attached
67
+
68
+
fsl,disable-port-power-control:
69
+
type: boolean
70
+
description:
71
+
Indicates whether the host controller implementation includes port
72
+
power control. Defines Bit 3 in capability register (HCCPARAMS)
73
+
74
+
fsl,over-current-active-low:
75
+
type: boolean
76
+
description:
77
+
Over current signal polarity is active low
78
+
79
+
fsl,power-active-low:
80
+
type: boolean
81
+
description:
82
+
Power pad (PWR) polarity is active low
83
+
84
+
power-domains:
85
+
maxItems: 1
86
+
87
+
required:
88
+
- compatible
89
+
- reg
90
+
- clocks
91
+
- clock-names
92
+
- interrupts
93
+
- power-domains
94
+
95
+
allOf:
96
+
- $ref: snps,dwc3-common.yaml#
97
+
98
+
unevaluatedProperties: false
99
+
100
+
examples:
101
+
- |
102
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
103
+
104
+
usb@4c100000 {
105
+
compatible = "nxp,imx94-dwc3", "nxp,imx8mp-dwc3";
106
+
reg = <0x4c100000 0x10000>,
107
+
<0x4c010010 0x04>,
108
+
<0x4c1f0000 0x20>;
109
+
reg-names = "core", "blkctl", "glue";
110
+
clocks = <&scmi_clk 74>, //IMX94_CLK_HSIO
111
+
<&scmi_clk 74>, //IMX94_CLK_HSIO
112
+
<&scmi_clk 2>, //IMX94_CLK_24M
113
+
<&scmi_clk 1>; //IMX94_CLK_32K
114
+
clock-names = "hsio", "bus_early", "ref", "suspend";
115
+
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
116
+
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>;
117
+
interrupt-names = "dwc_usb3", "wakeup";
118
+
power-domains = <&scmi_devpd 13>; //IMX94_PD_HSIO_TOP
119
+
phys = <&usb3_phy>, <&usb3_phy>;
120
+
phy-names = "usb2-phy", "usb3-phy";
121
+
snps,gfladj-refclk-lpm-sel-quirk;
122
+
snps,parkmode-disable-ss-quirk;
123
+
};
+4
Documentation/devicetree/bindings/usb/nxp,ptn5110.yaml
+4
Documentation/devicetree/bindings/usb/nxp,ptn5110.yaml
-36
Documentation/devicetree/bindings/usb/ohci-st.txt
-36
Documentation/devicetree/bindings/usb/ohci-st.txt
···
1
-
ST USB OHCI controller
2
-
3
-
Required properties:
4
-
5
-
- compatible : must be "st,st-ohci-300x"
6
-
- reg : physical base addresses of the controller and length of memory mapped
7
-
region
8
-
- interrupts : one OHCI controller interrupt should be described here
9
-
- clocks : phandle list of usb clocks
10
-
- clock-names : should be "ic" for interconnect clock and "clk48"
11
-
See: Documentation/devicetree/bindings/clock/clock-bindings.txt
12
-
13
-
- phys : phandle for the PHY device
14
-
- phy-names : should be "usb"
15
-
16
-
- resets : phandle to the powerdown and reset controller for the USB IP
17
-
- reset-names : should be "power" and "softreset".
18
-
See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
19
-
See: Documentation/devicetree/bindings/reset/reset.txt
20
-
21
-
Example:
22
-
23
-
ohci0: usb@fe1ffc00 {
24
-
compatible = "st,st-ohci-300x";
25
-
reg = <0xfe1ffc00 0x100>;
26
-
interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
27
-
clocks = <&clk_s_a1_ls 0>,
28
-
<&clockgen_b0 0>;
29
-
clock-names = "ic", "clk48";
30
-
phys = <&usb2_phy>;
31
-
phy-names = "usb";
32
-
33
-
resets = <&powerdown STIH416_USB0_POWERDOWN>,
34
-
<&softreset STIH416_USB0_SOFTRESET>;
35
-
reset-names = "power", "softreset";
36
-
};
-80
Documentation/devicetree/bindings/usb/omap-usb.txt
-80
Documentation/devicetree/bindings/usb/omap-usb.txt
···
1
-
OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS
2
-
3
-
OMAP MUSB GLUE
4
-
- compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5
-
- ti,hwmods : must be "usb_otg_hs"
6
-
- multipoint : Should be "1" indicating the musb controller supports
7
-
multipoint. This is a MUSB configuration-specific setting.
8
-
- num-eps : Specifies the number of endpoints. This is also a
9
-
MUSB configuration-specific setting. Should be set to "16"
10
-
- ram-bits : Specifies the ram address size. Should be set to "12"
11
-
- interface-type : This is a board specific setting to describe the type of
12
-
interface between the controller and the phy. It should be "0" or "1"
13
-
specifying ULPI and UTMI respectively.
14
-
- mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
15
-
represents PERIPHERAL.
16
-
- power : Should be "50". This signifies the controller can supply up to
17
-
100mA when operating in host mode.
18
-
- usb-phy : the phandle for the PHY device
19
-
- phys : the phandle for the PHY device (used by generic PHY framework)
20
-
- phy-names : the names of the PHY corresponding to the PHYs present in the
21
-
*phy* phandle.
22
-
23
-
Optional properties:
24
-
- ctrl-module : phandle of the control module this glue uses to write to
25
-
mailbox
26
-
27
-
SOC specific device node entry
28
-
usb_otg_hs: usb_otg_hs@4a0ab000 {
29
-
compatible = "ti,omap4-musb";
30
-
ti,hwmods = "usb_otg_hs";
31
-
multipoint = <1>;
32
-
num-eps = <16>;
33
-
ram-bits = <12>;
34
-
ctrl-module = <&omap_control_usb>;
35
-
phys = <&usb2_phy>;
36
-
phy-names = "usb2-phy";
37
-
};
38
-
39
-
Board specific device node entry
40
-
&usb_otg_hs {
41
-
interface-type = <1>;
42
-
mode = <3>;
43
-
power = <50>;
44
-
};
45
-
46
-
OMAP DWC3 GLUE
47
-
- compatible : Should be
48
-
* "ti,dwc3" for OMAP5 and DRA7
49
-
* "ti,am437x-dwc3" for AM437x
50
-
- ti,hwmods : Should be "usb_otg_ss"
51
-
- reg : Address and length of the register set for the device.
52
-
- interrupts : The irq number of this device that is used to interrupt the
53
-
MPU
54
-
- #address-cells, #size-cells : Must be present if the device has sub-nodes
55
-
- utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID.
56
-
It should be set to "1" for HW mode and "2" for SW mode.
57
-
- ranges: the child address space are mapped 1:1 onto the parent address space
58
-
59
-
Optional Properties:
60
-
- extcon : phandle for the extcon device omap dwc3 uses to detect
61
-
connect/disconnect events.
62
-
- vbus-supply : phandle to the regulator device tree node if needed.
63
-
64
-
Sub-nodes:
65
-
The dwc3 core should be added as subnode to omap dwc3 glue.
66
-
- dwc3 :
67
-
The binding details of dwc3 can be found in:
68
-
Documentation/devicetree/bindings/usb/snps,dwc3.yaml
69
-
70
-
omap_dwc3 {
71
-
compatible = "ti,dwc3";
72
-
ti,hwmods = "usb_otg_ss";
73
-
reg = <0x4a020000 0x1ff>;
74
-
interrupts = <0 93 4>;
75
-
#address-cells = <1>;
76
-
#size-cells = <1>;
77
-
utmi-mode = <2>;
78
-
ranges;
79
-
};
80
-
+37
-4
Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
+37
-4
Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
···
24
24
compatible:
25
25
items:
26
26
- enum:
27
+
- qcom,eliza-dwc3
27
28
- qcom,glymur-dwc3
28
29
- qcom,glymur-dwc3-mp
29
30
- qcom,ipq4019-dwc3
···
154
153
155
154
wakeup-source: true
156
155
157
-
# Required child node:
158
-
159
156
required:
160
157
- compatible
161
158
- reg
···
174
175
then:
175
176
properties:
176
177
clocks:
178
+
minItems: 3
177
179
maxItems: 3
178
180
clock-names:
179
181
items:
···
203
203
compatible:
204
204
contains:
205
205
enum:
206
+
- qcom,ipq5424-dwc3
206
207
- qcom,ipq9574-dwc3
207
208
- qcom,kaanapali-dwc3
208
209
- qcom,msm8953-dwc3
···
223
222
then:
224
223
properties:
225
224
clocks:
225
+
minItems: 5
226
226
maxItems: 5
227
227
clock-names:
228
228
items:
···
266
264
then:
267
265
properties:
268
266
clocks:
267
+
minItems: 4
269
268
maxItems: 4
270
269
clock-names:
271
270
items:
···
286
283
then:
287
284
properties:
288
285
clocks:
286
+
minItems: 4
289
287
maxItems: 4
290
288
clock-names:
291
289
items:
···
307
303
then:
308
304
properties:
309
305
clocks:
306
+
minItems: 9
310
307
maxItems: 9
311
308
clock-names:
312
309
items:
···
351
346
compatible:
352
347
contains:
353
348
enum:
349
+
- qcom,eliza-dwc3
354
350
- qcom,milos-dwc3
355
351
- qcom,qcm2290-dwc3
356
352
- qcom,qcs615-dwc3
357
353
- qcom,sar2130p-dwc3
358
354
- qcom,sc8180x-dwc3
359
355
- qcom,sc8180x-dwc3-mp
356
+
- qcom,sm4250-dwc3
360
357
- qcom,sm6115-dwc3
361
358
- qcom,sm6125-dwc3
359
+
- qcom,sm6375-dwc3
362
360
- qcom,sm8150-dwc3
363
361
- qcom,sm8250-dwc3
364
362
- qcom,sm8450-dwc3
···
371
363
properties:
372
364
clocks:
373
365
minItems: 6
366
+
maxItems: 6
374
367
clock-names:
375
368
items:
376
369
- const: cfg_noc
···
413
404
then:
414
405
properties:
415
406
clocks:
407
+
minItems: 7
416
408
maxItems: 7
417
409
clock-names:
418
410
items:
···
456
446
- qcom,msm8996-dwc3
457
447
- qcom,qcs404-dwc3
458
448
- qcom,sdm660-dwc3
449
+
- qcom,sm4250-dwc3
459
450
- qcom,sm6115-dwc3
460
451
- qcom,sm6125-dwc3
461
452
then:
···
483
472
then:
484
473
properties:
485
474
interrupts:
475
+
minItems: 4
486
476
maxItems: 4
487
477
interrupt-names:
488
478
items:
489
479
- const: dwc_usb3
490
480
- const: pwr_event
481
+
- const: dp_hs_phy_irq
482
+
- const: dm_hs_phy_irq
483
+
484
+
- if:
485
+
properties:
486
+
compatible:
487
+
contains:
488
+
enum:
489
+
- qcom,ipq5424-dwc3
490
+
- qcom,ipq9574-dwc3
491
+
then:
492
+
properties:
493
+
interrupts:
494
+
minItems: 5
495
+
maxItems: 5
496
+
interrupt-names:
497
+
items:
498
+
- const: dwc_usb3
499
+
- const: pwr_event
500
+
- const: qusb2_phy
491
501
- const: dp_hs_phy_irq
492
502
- const: dm_hs_phy_irq
493
503
···
532
500
- const: pwr_event
533
501
- const: dp_hs_phy_irq
534
502
- const: dm_hs_phy_irq
535
-
- const: ss_phy_irq
503
+
- enum: [hs_phy_irq, ss_phy_irq]
536
504
537
505
- if:
538
506
properties:
539
507
compatible:
540
508
contains:
541
509
enum:
510
+
- qcom,eliza-dwc3
542
511
- qcom,ipq4019-dwc3
543
512
- qcom,ipq8064-dwc3
544
513
- qcom,kaanapali-dwc3
···
556
523
- qcom,sdx55-dwc3
557
524
- qcom,sdx65-dwc3
558
525
- qcom,sdx75-dwc3
559
-
- qcom,sm4250-dwc3
560
526
- qcom,sm6350-dwc3
527
+
- qcom,sm6375-dwc3
561
528
- qcom,sm8150-dwc3
562
529
- qcom,sm8250-dwc3
563
530
- qcom,sm8350-dwc3
+63
Documentation/devicetree/bindings/usb/renesas,upd720201-pci.yaml
+63
Documentation/devicetree/bindings/usb/renesas,upd720201-pci.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/usb/renesas,upd720201-pci.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: UPD720201/UPD720202 USB 3.0 xHCI Host Controller (PCIe)
8
+
9
+
maintainers:
10
+
- Neil Armstrong <neil.armstrong@linaro.org>
11
+
12
+
description:
13
+
UPD720201 USB 3.0 xHCI Host Controller via PCIe x1 Gen2 interface.
14
+
The UPD720202 supports up to two downstream ports, while UPD720201
15
+
supports up to four downstream USB 3.0 rev1.0 ports.
16
+
17
+
properties:
18
+
compatible:
19
+
enum:
20
+
- pci1912,0014 # UPD720201
21
+
- pci1912,0015 # UPD720202
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
avdd33-supply:
27
+
description: +3.3 V power supply for analog circuit
28
+
29
+
vdd10-supply:
30
+
description: +1.05 V power supply
31
+
32
+
vdd33-supply:
33
+
description: +3.3 V power supply
34
+
35
+
required:
36
+
- compatible
37
+
- reg
38
+
- avdd33-supply
39
+
- vdd10-supply
40
+
- vdd33-supply
41
+
42
+
allOf:
43
+
- $ref: usb-xhci.yaml
44
+
45
+
additionalProperties: true
46
+
47
+
examples:
48
+
- |
49
+
pcie@0 {
50
+
reg = <0x0 0x1000>;
51
+
ranges = <0x02000000 0x0 0x100000 0x10000000 0x0 0x0>;
52
+
#address-cells = <3>;
53
+
#size-cells = <2>;
54
+
device_type = "pci";
55
+
56
+
usb-controller@0 {
57
+
compatible = "pci1912,0014";
58
+
reg = <0x0 0x0 0x0 0x0 0x0>;
59
+
avdd33-supply = <&avdd33_reg>;
60
+
vdd10-supply = <&vdd10_reg>;
61
+
vdd33-supply = <&vdd33_reg>;
62
+
};
63
+
};
+14
-4
Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml
+14
-4
Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml
···
18
18
19
19
properties:
20
20
compatible:
21
-
enum:
22
-
- richtek,rt1711h
23
-
- richtek,rt1715
21
+
oneOf:
22
+
- enum:
23
+
- richtek,rt1711h
24
+
- richtek,rt1715
25
+
- items:
26
+
- enum:
27
+
- hynetek,husb311
28
+
- const: richtek,rt1711h
29
+
- items:
30
+
- enum:
31
+
- etekmicro,et7304
32
+
- const: richtek,rt1715
24
33
description:
25
-
RT1711H support PD20, RT1715 support PD30 except Fast Role Swap.
34
+
RT1711H support PD20, ET7304 and RT1715 support PD30 except Fast Role Swap.
35
+
HUSB311 is a rebrand of RT1711H which is pin and register compatible.
26
36
27
37
reg:
28
38
maxItems: 1
+5
-1
Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
+5
-1
Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
···
27
27
28
28
properties:
29
29
compatible:
30
-
const: spacemit,k1-dwc3
30
+
enum:
31
+
- spacemit,k1-dwc3
32
+
- spacemit,k3-dwc3
31
33
32
34
reg:
33
35
maxItems: 1
···
44
42
maxItems: 1
45
43
46
44
phys:
45
+
minItems: 1
47
46
items:
48
47
- description: phandle to USB2/HS PHY
49
48
- description: phandle to USB3/SS PHY
50
49
51
50
phy-names:
51
+
minItems: 1
52
52
items:
53
53
- const: usb2-phy
54
54
- const: usb3-phy
+85
Documentation/devicetree/bindings/usb/st,st-ohci-300x.yaml
+85
Documentation/devicetree/bindings/usb/st,st-ohci-300x.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/usb/st,st-ohci-300x.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: STMicroelectronics USB OHCI Controller
8
+
9
+
maintainers:
10
+
- Peter Griffin <peter.griffin@linaro.org>
11
+
12
+
description:
13
+
The STMicroelectronics USB Open Host Controller Interface (OHCI)
14
+
compliant USB host controller found in ST platforms. The controller
15
+
provides full- and low-speed USB host functionality and interfaces
16
+
with an external USB PHY. It requires dedicated clock, reset, and
17
+
interrupt resources for proper operation.
18
+
19
+
allOf:
20
+
- $ref: /schemas/usb/usb-hcd.yaml#
21
+
22
+
properties:
23
+
compatible:
24
+
const: st,st-ohci-300x
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
interrupts:
30
+
maxItems: 1
31
+
32
+
clocks:
33
+
maxItems: 2
34
+
35
+
clock-names:
36
+
items:
37
+
- const: ic
38
+
- const: clk48
39
+
40
+
phys:
41
+
maxItems: 1
42
+
43
+
phy-names:
44
+
items:
45
+
- const: usb
46
+
47
+
resets:
48
+
maxItems: 2
49
+
50
+
reset-names:
51
+
items:
52
+
- const: power
53
+
- const: softreset
54
+
55
+
required:
56
+
- compatible
57
+
- reg
58
+
- interrupts
59
+
- clocks
60
+
- clock-names
61
+
- phys
62
+
- phy-names
63
+
- resets
64
+
- reset-names
65
+
66
+
unevaluatedProperties: false
67
+
68
+
examples:
69
+
- |
70
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
71
+
#include <dt-bindings/reset/stih407-resets.h>
72
+
usb@fe1ffc00 {
73
+
compatible = "st,st-ohci-300x";
74
+
reg = <0xfe1ffc00 0x100>;
75
+
interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
76
+
clocks = <&clk_s_a1_ls 0>,
77
+
<&clockgen_b0 0>;
78
+
clock-names = "ic", "clk48";
79
+
phys = <&usb2_phy>;
80
+
phy-names = "usb";
81
+
resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
82
+
<&softreset STIH407_USB2_PORT0_SOFTRESET>;
83
+
reset-names = "power", "softreset";
84
+
};
85
+
...
+64
Documentation/devicetree/bindings/usb/starfive,jhb100-dwc3.yaml
+64
Documentation/devicetree/bindings/usb/starfive,jhb100-dwc3.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/usb/starfive,jhb100-dwc3.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: StarFive JHB100 DWC3 USB SoC Controller
8
+
9
+
maintainers:
10
+
- Minda Chen <minda.chen@starfivetech.com>
11
+
12
+
description:
13
+
The USB DRD controller on JHB100 BMC SoC.
14
+
15
+
allOf:
16
+
- $ref: snps,dwc3-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: starfive,jhb100-dwc3
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
clocks:
29
+
items:
30
+
- description: USB main enable clk
31
+
- description: DWC3 bus early clock
32
+
- description: DWC3 ref clock
33
+
34
+
clock-names:
35
+
items:
36
+
- const: main
37
+
- const: bus_early
38
+
- const: ref
39
+
40
+
resets:
41
+
maxItems: 1
42
+
43
+
required:
44
+
- compatible
45
+
- reg
46
+
- clocks
47
+
- clock-names
48
+
- interrupts
49
+
50
+
unevaluatedProperties: false
51
+
52
+
examples:
53
+
- |
54
+
usb@11800000 {
55
+
compatible = "starfive,jhb100-dwc3";
56
+
reg = <0x11800000 0x10000>;
57
+
clocks = <&usbcrg 9>,
58
+
<&usbcrg 5>,
59
+
<&usbcrg 6>;
60
+
clock-names = "main", "bus_early", "ref";
61
+
resets = <&usbcrg 4>;
62
+
interrupts = <105>;
63
+
dr_mode = "host";
64
+
};
+62
Documentation/devicetree/bindings/usb/terminus,fe11.yaml
+62
Documentation/devicetree/bindings/usb/terminus,fe11.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/usb/terminus,fe11.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Terminus FE1.1/1.1S USB 2.0 Hub Controller
8
+
9
+
maintainers:
10
+
- Yixun Lan <dlan@kernel.org>
11
+
12
+
allOf:
13
+
- $ref: usb-hub.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
enum:
18
+
- usb1a40,0101
19
+
20
+
reg: true
21
+
22
+
reset-gpios:
23
+
description:
24
+
GPIO controlling the RESET#.
25
+
26
+
vdd-supply:
27
+
description:
28
+
Regulator supply to the hub, one of 3.3V or 5V can be chosen.
29
+
30
+
ports:
31
+
$ref: /schemas/graph.yaml#/properties/ports
32
+
33
+
patternProperties:
34
+
'^port@':
35
+
$ref: /schemas/graph.yaml#/properties/port
36
+
37
+
properties:
38
+
reg:
39
+
minimum: 1
40
+
maximum: 4
41
+
42
+
required:
43
+
- compatible
44
+
- reg
45
+
- vdd-supply
46
+
47
+
unevaluatedProperties: false
48
+
49
+
examples:
50
+
- |
51
+
#include <dt-bindings/gpio/gpio.h>
52
+
usb {
53
+
#address-cells = <1>;
54
+
#size-cells = <0>;
55
+
56
+
hub@1 {
57
+
compatible = "usb1a40,0101";
58
+
reg = <1>;
59
+
reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
60
+
vdd-supply = <&vcc_5v>;
61
+
};
62
+
};
+100
Documentation/devicetree/bindings/usb/ti,dwc3.yaml
+100
Documentation/devicetree/bindings/usb/ti,dwc3.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/usb/ti,dwc3.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Texas Instruments OMAP DWC3 USB Glue Layer
8
+
9
+
maintainers:
10
+
- Felipe Balbi <balbi@ti.com>
11
+
12
+
description:
13
+
Texas Instruments glue layer for Synopsys DesignWare USB3 (DWC3)
14
+
controller on OMAP and AM43xx SoCs. Manages SoC-specific integration
15
+
including register mapping, interrupt routing, UTMI/PIPE interface mode
16
+
selection (HW/SW), and child DWC3 core instantiation via address space
17
+
translation. Supports both legacy single-instance and multi-instance
18
+
(numbered) configurations.
19
+
20
+
properties:
21
+
compatible:
22
+
enum:
23
+
- ti,dwc3
24
+
- ti,am437x-dwc3
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
interrupts:
30
+
maxItems: 1
31
+
32
+
utmi-mode:
33
+
$ref: /schemas/types.yaml#/definitions/uint32
34
+
description:
35
+
Controls the source of UTMI/PIPE status for VBUS and OTG ID.
36
+
1 for HW mode, 2 for SW mode.
37
+
enum: [1, 2]
38
+
39
+
"#address-cells":
40
+
const: 1
41
+
42
+
"#size-cells":
43
+
const: 1
44
+
45
+
ranges: true
46
+
47
+
extcon:
48
+
$ref: /schemas/types.yaml#/definitions/phandle
49
+
description:
50
+
Phandle for the extcon device used to detect connect/
51
+
disconnect events.
52
+
53
+
vbus-supply:
54
+
description: Phandle to the regulator device tree node if needed.
55
+
56
+
patternProperties:
57
+
"^usb@[0-9a-f]+$":
58
+
type: object
59
+
$ref: snps,dwc3.yaml#
60
+
unevaluatedProperties: false
61
+
62
+
required:
63
+
- reg
64
+
- compatible
65
+
- interrupts
66
+
- "#address-cells"
67
+
- "#size-cells"
68
+
- utmi-mode
69
+
- ranges
70
+
71
+
unevaluatedProperties: false
72
+
73
+
examples:
74
+
- |
75
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
76
+
omap_dwc3_1@0 {
77
+
compatible = "ti,dwc3";
78
+
reg = <0x0 0x10000>;
79
+
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
80
+
#address-cells = <1>;
81
+
#size-cells = <1>;
82
+
utmi-mode = <2>;
83
+
ranges = <0 0 0x20000>;
84
+
85
+
usb@10000 {
86
+
compatible = "snps,dwc3";
87
+
reg = <0x10000 0x17000>;
88
+
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
89
+
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
90
+
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
91
+
interrupt-names = "peripheral", "host", "otg";
92
+
phys = <&usb2_phy1>, <&usb3_phy1>;
93
+
phy-names = "usb2-phy", "usb3-phy";
94
+
maximum-speed = "super-speed";
95
+
dr_mode = "otg";
96
+
snps,dis_u3_susphy_quirk;
97
+
snps,dis_u2_susphy_quirk;
98
+
};
99
+
};
100
+
...
+120
Documentation/devicetree/bindings/usb/ti,omap4-musb.yaml
+120
Documentation/devicetree/bindings/usb/ti,omap4-musb.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/usb/ti,omap4-musb.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Texas Instruments OMAP MUSB USB OTG Controller
8
+
9
+
maintainers:
10
+
- Felipe Balbi <balbi@ti.com>
11
+
12
+
description:
13
+
Texas Instruments glue layer for the Mentor Graphics MUSB OTG controller.
14
+
Handles SoC-specific integration including PHY interface bridging(ULPI/
15
+
UTMI), interrupt aggregation, DMA engine coordination (internal/
16
+
external), VBUS/session control via control module mailbox, and
17
+
clock/reset management. Provides fixed hardware configuration parameters
18
+
to the generic MUSB core driver.
19
+
20
+
properties:
21
+
compatible:
22
+
enum:
23
+
- ti,omap3-musb
24
+
- ti,omap4-musb
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
interrupts:
30
+
minItems: 1
31
+
maxItems: 2
32
+
33
+
interrupt-names:
34
+
minItems: 1
35
+
items:
36
+
- const: mc
37
+
- const: dma
38
+
39
+
multipoint:
40
+
$ref: /schemas/types.yaml#/definitions/uint32
41
+
description:
42
+
Indicates the MUSB controller supports multipoint. This is a MUSB
43
+
configuration-specific setting.
44
+
const: 1
45
+
46
+
num-eps:
47
+
$ref: /schemas/types.yaml#/definitions/uint32
48
+
description:
49
+
Specifies the number of endpoints. This is a MUSB configuration
50
+
specific setting.
51
+
const: 16
52
+
53
+
ram-bits:
54
+
description: Specifies the RAM address size.
55
+
const: 12
56
+
57
+
interface-type:
58
+
$ref: /schemas/types.yaml#/definitions/uint32
59
+
description:
60
+
Describes the type of interface between the controller and the PHY.
61
+
0 for ULPI, 1 for UTMI.
62
+
enum: [0, 1]
63
+
64
+
mode:
65
+
$ref: /schemas/types.yaml#/definitions/uint32
66
+
description: 1 for HOST, 2 for PERIPHERAL, 3 for OTG.
67
+
enum: [1, 2, 3]
68
+
69
+
power:
70
+
$ref: /schemas/types.yaml#/definitions/uint32
71
+
description:
72
+
Indicates the maximum current the controller can supply when
73
+
operating in host mode. A value of 50 corresponds to 100 mA, and a
74
+
value of 150 corresponds to 300 mA.
75
+
enum: [50, 150]
76
+
77
+
phys:
78
+
maxItems: 1
79
+
80
+
phy-names:
81
+
const: usb2-phy
82
+
83
+
usb-phy:
84
+
$ref: /schemas/types.yaml#/definitions/phandle-array
85
+
description: Phandle for the PHY device.
86
+
deprecated: true
87
+
88
+
ctrl-module:
89
+
$ref: /schemas/types.yaml#/definitions/phandle
90
+
description:
91
+
Phandle of the control module this glue uses to write to mailbox.
92
+
93
+
required:
94
+
- reg
95
+
- compatible
96
+
- interrupts
97
+
- interrupt-names
98
+
99
+
unevaluatedProperties: false
100
+
101
+
examples:
102
+
- |
103
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
104
+
usb@4a0ab000 {
105
+
compatible = "ti,omap4-musb";
106
+
reg = <0x4a0ab000 0x1000>;
107
+
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
108
+
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
109
+
interrupt-names = "mc", "dma";
110
+
multipoint = <1>;
111
+
num-eps = <16>;
112
+
ram-bits = <12>;
113
+
ctrl-module = <&omap_control_usb>;
114
+
phys = <&usb2_phy>;
115
+
phy-names = "usb2-phy";
116
+
interface-type = <1>;
117
+
mode = <3>;
118
+
power = <50>;
119
+
};
120
+
...
+17
-6
Documentation/devicetree/bindings/usb/ti,usb8041.yaml
+17
-6
Documentation/devicetree/bindings/usb/ti,usb8041.yaml
···
11
11
12
12
allOf:
13
13
- $ref: usb-device.yaml#
14
+
- $ref: usb-hub.yaml#
14
15
15
16
properties:
16
17
compatible:
···
31
30
description:
32
31
VDD power supply to the hub
33
32
34
-
peer-hub:
35
-
$ref: /schemas/types.yaml#/definitions/phandle
36
-
description:
37
-
phandle to the peer hub on the controller.
33
+
peer-hub: true
34
+
35
+
patternProperties:
36
+
'^.*@[1-9a-f][0-9a-f]*$':
37
+
description: The hard wired USB devices
38
+
type: object
39
+
$ref: /schemas/usb/usb-device.yaml
40
+
additionalProperties: true
38
41
39
42
required:
40
43
- compatible
41
44
- reg
42
-
- peer-hub
43
45
44
-
additionalProperties: false
46
+
unevaluatedProperties: false
45
47
46
48
examples:
47
49
- |
···
60
56
compatible = "usb451,8142";
61
57
reg = <1>;
62
58
peer-hub = <&hub_3_0>;
59
+
#address-cells = <1>;
60
+
#size-cells = <0>;
63
61
reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
62
+
63
+
hub@1 {
64
+
compatible = "usb123,4567";
65
+
reg = <1>;
66
+
};
64
67
};
65
68
66
69
/* 3.0 hub on port 2 */
+6
Documentation/devicetree/bindings/vendor-prefixes.yaml
+6
Documentation/devicetree/bindings/vendor-prefixes.yaml
···
365
365
description: CORERIVER Semiconductor Co.,Ltd.
366
366
"^corpro,.*":
367
367
description: Chengdu Corpro Technology Co., Ltd.
368
+
"^corechips,.*":
369
+
description: Shenzhen Corechips Microelectronics Co., Ltd.
368
370
"^cortina,.*":
369
371
description: Cortina Systems, Inc.
370
372
"^cosmic,.*":
···
549
547
description: ESTeem Wireless Modems
550
548
"^eswin,.*":
551
549
description: Beijing ESWIN Technology Group Co. Ltd.
550
+
"^etekmicro,.*":
551
+
description: Wuxi ETEK Micro-Electronics Co.,Ltd.
552
552
"^ettus,.*":
553
553
description: NI Ettus Research
554
554
"^eukrea,.*":
···
755
751
description: Hycon Technology Corp.
756
752
"^hydis,.*":
757
753
description: Hydis Technologies
754
+
"^hynetek,.*":
755
+
description: Hynetek Semiconductor Co., Ltd.
758
756
"^hynitron,.*":
759
757
description: Shanghai Hynitron Microelectronics Co. Ltd.
760
758
"^hynix,.*":
+9
-2
MAINTAINERS
+9
-2
MAINTAINERS
···
15816
15816
F: drivers/nvmem/max77759-nvmem.c
15817
15817
F: include/linux/mfd/max77759.h
15818
15818
15819
+
MAXIM MAX77759 BATTERY CHARGER DRIVER
15820
+
M: Amit Sunil Dhamne <amitsd@google.com>
15821
+
L: linux-kernel@vger.kernel.org
15822
+
S: Maintained
15823
+
F: drivers/power/supply/max77759_charger.c
15824
+
15819
15825
MAXIM MAX77802 PMIC REGULATOR DEVICE DRIVER
15820
15826
M: Javier Martinez Canillas <javier@dowhile0.org>
15821
15827
L: linux-kernel@vger.kernel.org
···
25492
25486
F: drivers/reset/starfive/reset-starfive-jh71*
25493
25487
F: include/dt-bindings/reset/starfive?jh71*.h
25494
25488
25495
-
STARFIVE JH71X0 USB DRIVERS
25489
+
STARFIVE USB DRIVERS
25496
25490
M: Minda Chen <minda.chen@starfivetech.com>
25497
25491
S: Maintained
25498
25492
F: Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
25493
+
F: Documentation/devicetree/bindings/usb/starfive,jhb100-dwc3.yaml
25499
25494
F: drivers/usb/cdns3/cdns3-starfive.c
25500
25495
25501
25496
STARFIVE JH71XX PMU CONTROLLER DRIVER
···
26543
26536
F: include/uapi/linux/thp7312.h
26544
26537
26545
26538
THUNDERBOLT DMA TRAFFIC TEST DRIVER
26546
-
M: Isaac Hazan <isaac.hazan@intel.com>
26539
+
M: Mika Westerberg <westeri@kernel.org>
26547
26540
L: linux-usb@vger.kernel.org
26548
26541
S: Maintained
26549
26542
F: drivers/thunderbolt/dma_test.c
+85
-10
drivers/mfd/max77759.c
+85
-10
drivers/mfd/max77759.c
···
201
201
* - SYSUVLO_INT
202
202
* - FSHIP_NOT_RD
203
203
* - CHGR_INT: charger
204
-
* - CHG_INT
205
-
* - CHG_INT2
204
+
* - INT1
205
+
* - AICL
206
+
* - CHGIN
207
+
* - WCIN
208
+
* - CHG
209
+
* - BAT
210
+
* - INLIM
211
+
* - THM2
212
+
* - BYP
213
+
* - INT2
214
+
* - INSEL
215
+
* - SYS_UVLO1
216
+
* - SYS_UVLO2
217
+
* - BAT_OILO
218
+
* - CHG_STA_CC
219
+
* - CHG_STA_CV
220
+
* - CHG_STA_TO
221
+
* - CHG_STA_DONE
206
222
*/
207
223
enum {
208
224
MAX77759_INT_MAXQ,
···
244
228
};
245
229
246
230
enum {
247
-
MAX77759_CHARGER_INT_1,
248
-
MAX77759_CHARGER_INT_2,
231
+
MAX77759_CHGR_INT1_AICL,
232
+
MAX77759_CHGR_INT1_CHGIN,
233
+
MAX77759_CHGR_INT1_WCIN,
234
+
MAX77759_CHGR_INT1_CHG,
235
+
MAX77759_CHGR_INT1_BAT,
236
+
MAX77759_CHGR_INT1_INLIM,
237
+
MAX77759_CHGR_INT1_THM2,
238
+
MAX77759_CHGR_INT1_BYP,
239
+
MAX77759_CHGR_INT2_INSEL,
240
+
MAX77759_CHGR_INT2_SYS_UVLO1,
241
+
MAX77759_CHGR_INT2_SYS_UVLO2,
242
+
MAX77759_CHGR_INT2_BAT_OILO,
243
+
MAX77759_CHGR_INT2_CHG_STA_CC,
244
+
MAX77759_CHGR_INT2_CHG_STA_CV,
245
+
MAX77759_CHGR_INT2_CHG_STA_TO,
246
+
MAX77759_CHGR_INT2_CHG_STA_DONE,
249
247
};
250
248
251
249
static const struct regmap_irq max77759_pmic_irqs[] = {
···
286
256
};
287
257
288
258
static const struct regmap_irq max77759_chgr_irqs[] = {
289
-
REGMAP_IRQ_REG(MAX77759_CHARGER_INT_1, 0, GENMASK(7, 0)),
290
-
REGMAP_IRQ_REG(MAX77759_CHARGER_INT_2, 1, GENMASK(7, 0)),
259
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_AICL, 0,
260
+
MAX77759_CHGR_REG_CHG_INT_AICL),
261
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHGIN, 0,
262
+
MAX77759_CHGR_REG_CHG_INT_CHGIN),
263
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_WCIN, 0,
264
+
MAX77759_CHGR_REG_CHG_INT_WCIN),
265
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHG, 0,
266
+
MAX77759_CHGR_REG_CHG_INT_CHG),
267
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BAT, 0,
268
+
MAX77759_CHGR_REG_CHG_INT_BAT),
269
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_INLIM, 0,
270
+
MAX77759_CHGR_REG_CHG_INT_INLIM),
271
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_THM2, 0,
272
+
MAX77759_CHGR_REG_CHG_INT_THM2),
273
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BYP, 0,
274
+
MAX77759_CHGR_REG_CHG_INT_BYP),
275
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_INSEL, 1,
276
+
MAX77759_CHGR_REG_CHG_INT2_INSEL),
277
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO1, 1,
278
+
MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1),
279
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO2, 1,
280
+
MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2),
281
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_BAT_OILO, 1,
282
+
MAX77759_CHGR_REG_CHG_INT2_BAT_OILO),
283
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CC, 1,
284
+
MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC),
285
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CV, 1,
286
+
MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV),
287
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_TO, 1,
288
+
MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO),
289
+
REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_DONE, 1,
290
+
MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE),
291
291
};
292
292
293
293
static const struct regmap_irq_chip max77759_pmic_irq_chip = {
···
357
297
.num_irqs = ARRAY_SIZE(max77759_topsys_irqs),
358
298
};
359
299
360
-
static const struct regmap_irq_chip max77759_chrg_irq_chip = {
300
+
static const struct regmap_irq_chip max77759_chgr_irq_chip = {
361
301
.name = "max77759-chgr",
362
302
.domain_suffix = "CHGR",
363
303
.status_base = MAX77759_CHGR_REG_CHG_INT,
364
304
.mask_base = MAX77759_CHGR_REG_CHG_INT_MASK,
305
+
.ack_base = MAX77759_CHGR_REG_CHG_INT,
365
306
.num_regs = 2,
366
307
.irqs = max77759_chgr_irqs,
367
308
.num_irqs = ARRAY_SIZE(max77759_chgr_irqs),
···
386
325
};
387
326
388
327
static const struct resource max77759_charger_resources[] = {
389
-
DEFINE_RES_IRQ_NAMED(MAX77759_CHARGER_INT_1, "INT1"),
390
-
DEFINE_RES_IRQ_NAMED(MAX77759_CHARGER_INT_2, "INT2"),
328
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_AICL, "AICL"),
329
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_CHGIN, "CHGIN"),
330
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_WCIN, "WCIN"),
331
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_CHG, "CHG"),
332
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_BAT, "BAT"),
333
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_INLIM, "INLIM"),
334
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_THM2, "THM2"),
335
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_BYP, "BYP"),
336
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_INSEL, "INSEL"),
337
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_SYS_UVLO1, "SYS_UVLO1"),
338
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_SYS_UVLO2, "SYS_UVLO2"),
339
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_BAT_OILO, "BAT_OILO"),
340
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_CC, "CHG_STA_CC"),
341
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_CV, "CHG_STA_CV"),
342
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_TO, "CHG_STA_TO"),
343
+
DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_DONE, "CHG_STA_DONE"),
391
344
};
392
345
393
346
static const struct mfd_cell max77759_cells[] = {
···
642
567
max77759->regmap_charger,
643
568
MAX77759_INT_CHGR,
644
569
parent,
645
-
&max77759_chrg_irq_chip,
570
+
&max77759_chgr_irq_chip,
646
571
&irq_chip_data);
647
572
if (ret)
648
573
return ret;
+11
drivers/power/supply/Kconfig
+11
drivers/power/supply/Kconfig
···
642
642
help
643
643
Say Y to enable support for the Maxim MAX77705 battery charger.
644
644
645
+
config CHARGER_MAX77759
646
+
tristate "Maxim MAX77759 battery charger driver"
647
+
depends on MFD_MAX77759 && REGULATOR
648
+
default MFD_MAX77759
649
+
help
650
+
Say M or Y here to enable the MAX77759 battery charger. MAX77759
651
+
charger is a function of the MAX77759 PMIC. This is a dual input
652
+
switch-mode charger. This driver supports buck and OTG boost modes.
653
+
654
+
If built as a module, it will be called max77759_charger.
655
+
645
656
config CHARGER_MAX77976
646
657
tristate "Maxim MAX77976 battery charger driver"
647
658
depends on I2C
+1
drivers/power/supply/Makefile
+1
drivers/power/supply/Makefile
+774
drivers/power/supply/max77759_charger.c
+774
drivers/power/supply/max77759_charger.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* max77759_charger.c - Battery charger driver for MAX77759 charger device.
4
+
*
5
+
* Copyright 2025 Google LLC.
6
+
*/
7
+
8
+
#include <linux/bitfield.h>
9
+
#include <linux/cleanup.h>
10
+
#include <linux/device.h>
11
+
#include <linux/devm-helpers.h>
12
+
#include <linux/interrupt.h>
13
+
#include <linux/irq.h>
14
+
#include <linux/linear_range.h>
15
+
#include <linux/mfd/max77759.h>
16
+
#include <linux/module.h>
17
+
#include <linux/mod_devicetable.h>
18
+
#include <linux/mutex.h>
19
+
#include <linux/of.h>
20
+
#include <linux/platform_device.h>
21
+
#include <linux/power_supply.h>
22
+
#include <linux/regmap.h>
23
+
#include <linux/regulator/driver.h>
24
+
#include <linux/string_choices.h>
25
+
#include <linux/workqueue.h>
26
+
27
+
/* Default values for Fast Charge Current & Float Voltage */
28
+
#define CHG_CC_DEFAULT_UA 2266770
29
+
#define CHG_FV_DEFAULT_MV 4300
30
+
31
+
#define MAX_NUM_RETRIES 3
32
+
#define PSY_WORK_RETRY_DELAY_MS 10
33
+
34
+
#define FOREACH_IRQ(S) \
35
+
S(AICL), \
36
+
S(CHGIN), \
37
+
S(CHG), \
38
+
S(INLIM), \
39
+
S(BAT_OILO), \
40
+
S(CHG_STA_CC), \
41
+
S(CHG_STA_CV), \
42
+
S(CHG_STA_TO), \
43
+
S(CHG_STA_DONE)
44
+
45
+
#define GENERATE_ENUM(e) e
46
+
#define GENERATE_STRING(s) #s
47
+
48
+
enum {
49
+
FOREACH_IRQ(GENERATE_ENUM)
50
+
};
51
+
52
+
static const char *const chgr_irqs_str[] = {
53
+
FOREACH_IRQ(GENERATE_STRING)
54
+
};
55
+
56
+
#define NUM_IRQS ARRAY_SIZE(chgr_irqs_str)
57
+
58
+
/* Fast charge current limits (in uA) */
59
+
static const struct linear_range chgcc_limit_ranges[] = {
60
+
LINEAR_RANGE(133330, 0x0, 0x2, 0),
61
+
LINEAR_RANGE(200000, 0x3, 0x3C, 66670),
62
+
};
63
+
64
+
/* Charge Termination Voltage Limits (in mV) */
65
+
static const struct linear_range chg_cv_prm_ranges[] = {
66
+
LINEAR_RANGE(3800, 0x38, 0x39, 100),
67
+
LINEAR_RANGE(4000, 0x0, 0x32, 10),
68
+
};
69
+
70
+
/* USB input current limits (in uA) */
71
+
static const struct linear_range chgin_ilim_ranges[] = {
72
+
LINEAR_RANGE(100000, 0x3, 0x7F, 25000),
73
+
};
74
+
75
+
struct max77759_charger {
76
+
struct device *dev;
77
+
struct regmap *regmap;
78
+
struct power_supply *psy;
79
+
struct regulator_dev *chgin_otg_rdev;
80
+
struct notifier_block nb;
81
+
struct power_supply *tcpm_psy;
82
+
struct delayed_work psy_work;
83
+
struct mutex retry_lock; /* Protects psy_work_retry_cnt */
84
+
u32 psy_work_retry_cnt;
85
+
int irqs[NUM_IRQS];
86
+
struct mutex lock; /* protects the state below */
87
+
enum max77759_chgr_mode mode;
88
+
};
89
+
90
+
static inline int unlock_prot_regs(struct max77759_charger *chg, bool unlock)
91
+
{
92
+
return regmap_update_bits(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_06,
93
+
MAX77759_CHGR_REG_CHG_CNFG_06_CHGPROT, unlock
94
+
? MAX77759_CHGR_REG_CHG_CNFG_06_CHGPROT : 0);
95
+
}
96
+
97
+
static int charger_input_valid(struct max77759_charger *chg)
98
+
{
99
+
u32 val;
100
+
int ret;
101
+
102
+
ret = regmap_read(chg->regmap, MAX77759_CHGR_REG_CHG_INT_OK, &val);
103
+
if (ret)
104
+
return ret;
105
+
106
+
return (val & MAX77759_CHGR_REG_CHG_INT_CHG) &&
107
+
(val & MAX77759_CHGR_REG_CHG_INT_CHGIN);
108
+
}
109
+
110
+
static int get_online(struct max77759_charger *chg)
111
+
{
112
+
u32 val;
113
+
int ret;
114
+
115
+
ret = charger_input_valid(chg);
116
+
if (ret <= 0)
117
+
return ret;
118
+
119
+
ret = regmap_read(chg->regmap, MAX77759_CHGR_REG_CHG_DETAILS_02, &val);
120
+
if (ret)
121
+
return ret;
122
+
123
+
guard(mutex)(&chg->lock);
124
+
125
+
return (val & MAX77759_CHGR_REG_CHG_DETAILS_02_CHGIN_STS) &&
126
+
(chg->mode == MAX77759_CHGR_MODE_CHG_BUCK_ON);
127
+
}
128
+
129
+
static int get_status(struct max77759_charger *chg)
130
+
{
131
+
u32 val;
132
+
int ret;
133
+
134
+
ret = regmap_read(chg->regmap, MAX77759_CHGR_REG_CHG_DETAILS_01, &val);
135
+
if (ret)
136
+
return ret;
137
+
138
+
switch (FIELD_GET(MAX77759_CHGR_REG_CHG_DETAILS_01_CHG_DTLS, val)) {
139
+
case MAX77759_CHGR_CHG_DTLS_PREQUAL:
140
+
case MAX77759_CHGR_CHG_DTLS_CC:
141
+
case MAX77759_CHGR_CHG_DTLS_CV:
142
+
case MAX77759_CHGR_CHG_DTLS_TO:
143
+
return POWER_SUPPLY_STATUS_CHARGING;
144
+
case MAX77759_CHGR_CHG_DTLS_DONE:
145
+
return POWER_SUPPLY_STATUS_FULL;
146
+
case MAX77759_CHGR_CHG_DTLS_TIMER_FAULT:
147
+
case MAX77759_CHGR_CHG_DTLS_SUSP_BATT_THM:
148
+
case MAX77759_CHGR_CHG_DTLS_OFF_WDOG_TIMER:
149
+
case MAX77759_CHGR_CHG_DTLS_SUSP_JEITA:
150
+
return POWER_SUPPLY_STATUS_NOT_CHARGING;
151
+
case MAX77759_CHGR_CHG_DTLS_OFF:
152
+
return POWER_SUPPLY_STATUS_DISCHARGING;
153
+
default:
154
+
break;
155
+
}
156
+
157
+
return POWER_SUPPLY_STATUS_UNKNOWN;
158
+
}
159
+
160
+
static int get_charge_type(struct max77759_charger *chg)
161
+
{
162
+
u32 val;
163
+
int ret;
164
+
165
+
ret = regmap_read(chg->regmap, MAX77759_CHGR_REG_CHG_DETAILS_01, &val);
166
+
if (ret)
167
+
return ret;
168
+
169
+
switch (FIELD_GET(MAX77759_CHGR_REG_CHG_DETAILS_01_CHG_DTLS, val)) {
170
+
case MAX77759_CHGR_CHG_DTLS_PREQUAL:
171
+
return POWER_SUPPLY_CHARGE_TYPE_TRICKLE;
172
+
case MAX77759_CHGR_CHG_DTLS_CC:
173
+
case MAX77759_CHGR_CHG_DTLS_CV:
174
+
return POWER_SUPPLY_CHARGE_TYPE_FAST;
175
+
case MAX77759_CHGR_CHG_DTLS_TO:
176
+
return POWER_SUPPLY_CHARGE_TYPE_STANDARD;
177
+
case MAX77759_CHGR_CHG_DTLS_DONE:
178
+
case MAX77759_CHGR_CHG_DTLS_TIMER_FAULT:
179
+
case MAX77759_CHGR_CHG_DTLS_SUSP_BATT_THM:
180
+
case MAX77759_CHGR_CHG_DTLS_OFF_WDOG_TIMER:
181
+
case MAX77759_CHGR_CHG_DTLS_SUSP_JEITA:
182
+
case MAX77759_CHGR_CHG_DTLS_OFF:
183
+
return POWER_SUPPLY_CHARGE_TYPE_NONE;
184
+
default:
185
+
break;
186
+
}
187
+
188
+
return POWER_SUPPLY_CHARGE_TYPE_UNKNOWN;
189
+
}
190
+
191
+
static int get_chg_health(struct max77759_charger *chg)
192
+
{
193
+
u32 val;
194
+
int ret;
195
+
196
+
ret = regmap_read(chg->regmap, MAX77759_CHGR_REG_CHG_DETAILS_00, &val);
197
+
if (ret)
198
+
return ret;
199
+
200
+
switch (FIELD_GET(MAX77759_CHGR_REG_CHG_DETAILS_00_CHGIN_DTLS, val)) {
201
+
case MAX77759_CHGR_CHGIN_DTLS_VBUS_UNDERVOLTAGE:
202
+
case MAX77759_CHGR_CHGIN_DTLS_VBUS_MARGINAL_VOLTAGE:
203
+
return POWER_SUPPLY_HEALTH_UNDERVOLTAGE;
204
+
case MAX77759_CHGR_CHGIN_DTLS_VBUS_OVERVOLTAGE:
205
+
return POWER_SUPPLY_HEALTH_OVERVOLTAGE;
206
+
case MAX77759_CHGR_CHGIN_DTLS_VBUS_VALID:
207
+
return POWER_SUPPLY_HEALTH_GOOD;
208
+
default:
209
+
break;
210
+
}
211
+
212
+
return POWER_SUPPLY_HEALTH_UNKNOWN;
213
+
}
214
+
215
+
static int get_batt_health(struct max77759_charger *chg)
216
+
{
217
+
u32 val;
218
+
int ret;
219
+
220
+
ret = regmap_read(chg->regmap, MAX77759_CHGR_REG_CHG_DETAILS_01, &val);
221
+
if (ret)
222
+
return ret;
223
+
224
+
switch (FIELD_GET(MAX77759_CHGR_REG_CHG_DETAILS_01_BAT_DTLS, val)) {
225
+
case MAX77759_CHGR_BAT_DTLS_NO_BATT_CHG_SUSP:
226
+
return POWER_SUPPLY_HEALTH_NO_BATTERY;
227
+
case MAX77759_CHGR_BAT_DTLS_DEAD_BATTERY:
228
+
return POWER_SUPPLY_HEALTH_DEAD;
229
+
case MAX77759_CHGR_BAT_DTLS_BAT_CHG_TIMER_FAULT:
230
+
return POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE;
231
+
case MAX77759_CHGR_BAT_DTLS_BAT_OKAY:
232
+
case MAX77759_CHGR_BAT_DTLS_BAT_ONLY_MODE:
233
+
return POWER_SUPPLY_HEALTH_GOOD;
234
+
case MAX77759_CHGR_BAT_DTLS_BAT_UNDERVOLTAGE:
235
+
return POWER_SUPPLY_HEALTH_UNDERVOLTAGE;
236
+
case MAX77759_CHGR_BAT_DTLS_BAT_OVERVOLTAGE:
237
+
return POWER_SUPPLY_HEALTH_OVERVOLTAGE;
238
+
case MAX77759_CHGR_BAT_DTLS_BAT_OVERCURRENT:
239
+
return POWER_SUPPLY_HEALTH_OVERCURRENT;
240
+
default:
241
+
break;
242
+
}
243
+
244
+
return POWER_SUPPLY_HEALTH_UNKNOWN;
245
+
}
246
+
247
+
static int get_health(struct max77759_charger *chg)
248
+
{
249
+
int ret;
250
+
251
+
ret = get_online(chg);
252
+
if (ret < 0)
253
+
return ret;
254
+
255
+
if (ret) {
256
+
ret = get_chg_health(chg);
257
+
if (ret < 0 || ret != POWER_SUPPLY_HEALTH_GOOD)
258
+
return ret;
259
+
}
260
+
261
+
return get_batt_health(chg);
262
+
}
263
+
264
+
static int get_fast_charge_current(struct max77759_charger *chg)
265
+
{
266
+
u32 regval, val;
267
+
int ret;
268
+
269
+
ret = regmap_read(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_02, ®val);
270
+
if (ret)
271
+
return ret;
272
+
273
+
regval = FIELD_GET(MAX77759_CHGR_REG_CHG_CNFG_02_CHGCC, regval);
274
+
ret = linear_range_get_value_array(chgcc_limit_ranges,
275
+
ARRAY_SIZE(chgcc_limit_ranges),
276
+
regval, &val);
277
+
return ret ? ret : val;
278
+
}
279
+
280
+
static int set_fast_charge_current_limit(struct max77759_charger *chg,
281
+
u32 cc_max_ua)
282
+
{
283
+
bool found;
284
+
u32 regval;
285
+
286
+
linear_range_get_selector_high_array(chgcc_limit_ranges,
287
+
ARRAY_SIZE(chgcc_limit_ranges),
288
+
cc_max_ua, ®val, &found);
289
+
if (!found)
290
+
return -EINVAL;
291
+
292
+
return regmap_update_bits(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_02,
293
+
MAX77759_CHGR_REG_CHG_CNFG_02_CHGCC, regval);
294
+
}
295
+
296
+
static int get_float_voltage(struct max77759_charger *chg)
297
+
{
298
+
u32 regval, val;
299
+
int ret;
300
+
301
+
ret = regmap_read(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_04, ®val);
302
+
if (ret)
303
+
return ret;
304
+
305
+
regval = FIELD_GET(MAX77759_CHGR_REG_CHG_CNFG_04_CHG_CV_PRM, regval);
306
+
ret = linear_range_get_value_array(chg_cv_prm_ranges,
307
+
ARRAY_SIZE(chg_cv_prm_ranges),
308
+
regval, &val);
309
+
310
+
return ret ? ret : val;
311
+
}
312
+
313
+
static int set_float_voltage_limit(struct max77759_charger *chg, u32 fv_mv)
314
+
{
315
+
u32 regval;
316
+
bool found;
317
+
318
+
linear_range_get_selector_high_array(chg_cv_prm_ranges,
319
+
ARRAY_SIZE(chg_cv_prm_ranges),
320
+
fv_mv, ®val, &found);
321
+
if (!found)
322
+
return -EINVAL;
323
+
324
+
return regmap_update_bits(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_04,
325
+
MAX77759_CHGR_REG_CHG_CNFG_04_CHG_CV_PRM,
326
+
regval);
327
+
}
328
+
329
+
static int get_input_current_limit(struct max77759_charger *chg)
330
+
{
331
+
u32 regval, val;
332
+
int ret;
333
+
334
+
ret = regmap_read(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_09, ®val);
335
+
if (ret)
336
+
return ret;
337
+
338
+
regval = FIELD_GET(MAX77759_CHGR_REG_CHG_CNFG_09_CHGIN_ILIM, regval);
339
+
regval = umax(regval, chgin_ilim_ranges[0].min_sel);
340
+
341
+
ret = linear_range_get_value_array(chgin_ilim_ranges,
342
+
ARRAY_SIZE(chgin_ilim_ranges),
343
+
regval, &val);
344
+
345
+
return ret ? ret : val;
346
+
}
347
+
348
+
static int set_input_current_limit(struct max77759_charger *chg, int ilim_ua)
349
+
{
350
+
u32 regval;
351
+
352
+
if (ilim_ua < 0)
353
+
return -EINVAL;
354
+
355
+
linear_range_get_selector_within(chgin_ilim_ranges, ilim_ua, ®val);
356
+
357
+
return regmap_update_bits(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_09,
358
+
MAX77759_CHGR_REG_CHG_CNFG_09_CHGIN_ILIM,
359
+
regval);
360
+
}
361
+
362
+
static const enum power_supply_property max77759_charger_props[] = {
363
+
POWER_SUPPLY_PROP_ONLINE,
364
+
POWER_SUPPLY_PROP_PRESENT,
365
+
POWER_SUPPLY_PROP_STATUS,
366
+
POWER_SUPPLY_PROP_CHARGE_TYPE,
367
+
POWER_SUPPLY_PROP_HEALTH,
368
+
POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX,
369
+
POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX,
370
+
POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
371
+
};
372
+
373
+
static int max77759_charger_get_property(struct power_supply *psy,
374
+
enum power_supply_property psp,
375
+
union power_supply_propval *pval)
376
+
{
377
+
struct max77759_charger *chg = power_supply_get_drvdata(psy);
378
+
int ret;
379
+
380
+
switch (psp) {
381
+
case POWER_SUPPLY_PROP_ONLINE:
382
+
ret = get_online(chg);
383
+
break;
384
+
case POWER_SUPPLY_PROP_PRESENT:
385
+
ret = charger_input_valid(chg);
386
+
break;
387
+
case POWER_SUPPLY_PROP_STATUS:
388
+
ret = get_status(chg);
389
+
break;
390
+
case POWER_SUPPLY_PROP_CHARGE_TYPE:
391
+
ret = get_charge_type(chg);
392
+
break;
393
+
case POWER_SUPPLY_PROP_HEALTH:
394
+
ret = get_health(chg);
395
+
break;
396
+
case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX:
397
+
ret = get_fast_charge_current(chg);
398
+
break;
399
+
case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX:
400
+
ret = get_float_voltage(chg);
401
+
break;
402
+
case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
403
+
ret = get_input_current_limit(chg);
404
+
break;
405
+
default:
406
+
ret = -EINVAL;
407
+
}
408
+
409
+
pval->intval = ret;
410
+
return ret < 0 ? ret : 0;
411
+
}
412
+
413
+
static const struct power_supply_desc max77759_charger_desc = {
414
+
.name = "max77759-charger",
415
+
.type = POWER_SUPPLY_TYPE_USB,
416
+
.properties = max77759_charger_props,
417
+
.num_properties = ARRAY_SIZE(max77759_charger_props),
418
+
.get_property = max77759_charger_get_property,
419
+
};
420
+
421
+
static int charger_set_mode(struct max77759_charger *chg,
422
+
enum max77759_chgr_mode mode)
423
+
{
424
+
int ret;
425
+
426
+
guard(mutex)(&chg->lock);
427
+
428
+
if (chg->mode == mode)
429
+
return 0;
430
+
431
+
if ((mode == MAX77759_CHGR_MODE_CHG_BUCK_ON ||
432
+
mode == MAX77759_CHGR_MODE_OTG_BOOST_ON) &&
433
+
chg->mode != MAX77759_CHGR_MODE_OFF) {
434
+
dev_err(chg->dev, "Invalid mode transition from %d to %d\n",
435
+
chg->mode, mode);
436
+
return -EINVAL;
437
+
}
438
+
439
+
ret = regmap_update_bits(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_00,
440
+
MAX77759_CHGR_REG_CHG_CNFG_00_MODE, mode);
441
+
if (ret)
442
+
return ret;
443
+
444
+
chg->mode = mode;
445
+
return 0;
446
+
}
447
+
448
+
static int enable_chgin_otg(struct regulator_dev *rdev)
449
+
{
450
+
struct max77759_charger *chg = rdev_get_drvdata(rdev);
451
+
452
+
return charger_set_mode(chg, MAX77759_CHGR_MODE_OTG_BOOST_ON);
453
+
}
454
+
455
+
static int disable_chgin_otg(struct regulator_dev *rdev)
456
+
{
457
+
struct max77759_charger *chg = rdev_get_drvdata(rdev);
458
+
459
+
return charger_set_mode(chg, MAX77759_CHGR_MODE_OFF);
460
+
}
461
+
462
+
static int chgin_otg_status(struct regulator_dev *rdev)
463
+
{
464
+
struct max77759_charger *chg = rdev_get_drvdata(rdev);
465
+
466
+
guard(mutex)(&chg->lock);
467
+
468
+
return chg->mode == MAX77759_CHGR_MODE_OTG_BOOST_ON;
469
+
}
470
+
471
+
static const struct regulator_ops chgin_otg_reg_ops = {
472
+
.enable = enable_chgin_otg,
473
+
.disable = disable_chgin_otg,
474
+
.is_enabled = chgin_otg_status,
475
+
};
476
+
477
+
static const struct regulator_desc chgin_otg_reg_desc = {
478
+
.name = "chgin-otg",
479
+
.of_match = of_match_ptr("chgin-otg-regulator"),
480
+
.owner = THIS_MODULE,
481
+
.ops = &chgin_otg_reg_ops,
482
+
.fixed_uV = 5000000,
483
+
.n_voltages = 1,
484
+
};
485
+
486
+
static irqreturn_t irq_handler(int irq, void *data)
487
+
{
488
+
struct max77759_charger *chg = data;
489
+
490
+
power_supply_changed(chg->psy);
491
+
492
+
return IRQ_HANDLED;
493
+
}
494
+
495
+
static irqreturn_t bat_oilo_irq_handler(int irq, void *data)
496
+
{
497
+
struct max77759_charger *chg = data;
498
+
499
+
dev_warn_ratelimited(chg->dev,
500
+
"Battery over-current threshold crossed\n");
501
+
502
+
return irq_handler(irq, data);
503
+
}
504
+
505
+
static int max77759_init_irqhandler(struct max77759_charger *chg)
506
+
{
507
+
struct device *dev = chg->dev;
508
+
irq_handler_t thread_fn;
509
+
char *name;
510
+
int i, ret;
511
+
512
+
for (i = 0; i < ARRAY_SIZE(chgr_irqs_str); i++) {
513
+
ret = platform_get_irq_byname(to_platform_device(dev),
514
+
chgr_irqs_str[i]);
515
+
if (ret < 0)
516
+
return dev_err_probe(dev, ret,
517
+
"Failed to get irq resource for %s\n",
518
+
chgr_irqs_str[i]);
519
+
520
+
chg->irqs[i] = ret;
521
+
name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", dev_name(dev),
522
+
chgr_irqs_str[i]);
523
+
if (!name)
524
+
return dev_err_probe(dev, -ENOMEM,
525
+
"Failed to allocate space for irqname: %s\n",
526
+
chgr_irqs_str[i]);
527
+
528
+
if (i == BAT_OILO)
529
+
thread_fn = bat_oilo_irq_handler;
530
+
else
531
+
thread_fn = irq_handler;
532
+
533
+
ret = devm_request_threaded_irq(dev, chg->irqs[i], NULL,
534
+
thread_fn, 0, name, chg);
535
+
if (ret)
536
+
return dev_err_probe(dev, ret,
537
+
"Unable to register irq handler for %s\n",
538
+
chgr_irqs_str[i]);
539
+
}
540
+
541
+
return 0;
542
+
}
543
+
544
+
static int max77759_charger_init(struct max77759_charger *chg)
545
+
{
546
+
struct power_supply_battery_info *info;
547
+
u32 regval, fast_chg_curr, fv;
548
+
int ret;
549
+
550
+
ret = regmap_read(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_00, ®val);
551
+
if (ret)
552
+
return ret;
553
+
554
+
chg->mode = FIELD_GET(MAX77759_CHGR_REG_CHG_CNFG_00_MODE, regval);
555
+
ret = charger_set_mode(chg, MAX77759_CHGR_MODE_OFF);
556
+
if (ret)
557
+
return ret;
558
+
559
+
if (power_supply_get_battery_info(chg->psy, &info)) {
560
+
fv = CHG_FV_DEFAULT_MV;
561
+
fast_chg_curr = CHG_CC_DEFAULT_UA;
562
+
} else {
563
+
fv = info->constant_charge_voltage_max_uv / 1000;
564
+
fast_chg_curr = info->constant_charge_current_max_ua;
565
+
}
566
+
567
+
ret = set_fast_charge_current_limit(chg, fast_chg_curr);
568
+
if (ret)
569
+
return ret;
570
+
571
+
ret = set_float_voltage_limit(chg, fv);
572
+
if (ret)
573
+
return ret;
574
+
575
+
ret = unlock_prot_regs(chg, true);
576
+
if (ret)
577
+
return ret;
578
+
579
+
/* Disable wireless charging input */
580
+
ret = regmap_update_bits(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_12,
581
+
MAX77759_CHGR_REG_CHG_CNFG_12_WCINSEL, 0);
582
+
if (ret)
583
+
goto relock;
584
+
585
+
ret = regmap_update_bits(chg->regmap, MAX77759_CHGR_REG_CHG_CNFG_18,
586
+
MAX77759_CHGR_REG_CHG_CNFG_18_WDTEN, 0);
587
+
if (ret)
588
+
goto relock;
589
+
590
+
return unlock_prot_regs(chg, false);
591
+
592
+
relock:
593
+
(void)unlock_prot_regs(chg, false);
594
+
return ret;
595
+
}
596
+
597
+
static void psy_work_item(struct work_struct *work)
598
+
{
599
+
struct max77759_charger *chg =
600
+
container_of(work, struct max77759_charger, psy_work.work);
601
+
union power_supply_propval current_limit, online;
602
+
int ret;
603
+
604
+
ret = power_supply_get_property(chg->tcpm_psy,
605
+
POWER_SUPPLY_PROP_CURRENT_MAX,
606
+
¤t_limit);
607
+
if (ret) {
608
+
dev_err(chg->dev,
609
+
"Failed to get CURRENT_MAX psy property, ret=%d\n",
610
+
ret);
611
+
goto err;
612
+
}
613
+
614
+
ret = power_supply_get_property(chg->tcpm_psy, POWER_SUPPLY_PROP_ONLINE,
615
+
&online);
616
+
if (ret) {
617
+
dev_err(chg->dev,
618
+
"Failed to get ONLINE psy property, ret=%d\n",
619
+
ret);
620
+
goto err;
621
+
}
622
+
623
+
if (online.intval && current_limit.intval) {
624
+
ret = set_input_current_limit(chg, current_limit.intval);
625
+
if (ret) {
626
+
dev_err(chg->dev,
627
+
"Unable to set current limit, ret=%d\n", ret);
628
+
goto err;
629
+
}
630
+
631
+
charger_set_mode(chg, MAX77759_CHGR_MODE_CHG_BUCK_ON);
632
+
} else {
633
+
charger_set_mode(chg, MAX77759_CHGR_MODE_OFF);
634
+
}
635
+
636
+
scoped_guard(mutex, &chg->retry_lock) {
637
+
if (chg->psy_work_retry_cnt)
638
+
dev_dbg(chg->dev,
639
+
"chg psy_work succeeded after %u tries\n",
640
+
chg->psy_work_retry_cnt);
641
+
chg->psy_work_retry_cnt = 0;
642
+
}
643
+
644
+
return;
645
+
646
+
err:
647
+
charger_set_mode(chg, MAX77759_CHGR_MODE_OFF);
648
+
scoped_guard(mutex, &chg->retry_lock) {
649
+
if (chg->psy_work_retry_cnt >= MAX_NUM_RETRIES) {
650
+
dev_err(chg->dev, "chg psy work failed, giving up\n");
651
+
return;
652
+
}
653
+
654
+
++chg->psy_work_retry_cnt;
655
+
dev_dbg(chg->dev, "Retrying %u/%u chg psy_work\n",
656
+
chg->psy_work_retry_cnt, MAX_NUM_RETRIES);
657
+
schedule_delayed_work(&chg->psy_work,
658
+
msecs_to_jiffies(PSY_WORK_RETRY_DELAY_MS));
659
+
}
660
+
}
661
+
662
+
static int psy_changed(struct notifier_block *nb, unsigned long evt, void *data)
663
+
{
664
+
struct max77759_charger *chg = container_of(nb, struct max77759_charger,
665
+
nb);
666
+
static const char *psy_name = "tcpm-source";
667
+
struct power_supply *psy = data;
668
+
669
+
if (!strnstr(psy->desc->name, psy_name, strlen(psy_name)) ||
670
+
evt != PSY_EVENT_PROP_CHANGED)
671
+
return NOTIFY_OK;
672
+
673
+
chg->tcpm_psy = psy;
674
+
scoped_guard(mutex, &chg->retry_lock)
675
+
chg->psy_work_retry_cnt = 0;
676
+
677
+
schedule_delayed_work(&chg->psy_work, 0);
678
+
679
+
return NOTIFY_OK;
680
+
}
681
+
682
+
static void max_tcpci_unregister_psy_notifier(void *nb)
683
+
{
684
+
power_supply_unreg_notifier(nb);
685
+
}
686
+
687
+
static int max77759_charger_probe(struct platform_device *pdev)
688
+
{
689
+
struct regulator_config chgin_otg_reg_cfg;
690
+
struct power_supply_config psy_cfg;
691
+
struct device *dev = &pdev->dev;
692
+
struct max77759_charger *chg;
693
+
int ret;
694
+
695
+
device_set_of_node_from_dev(dev, dev->parent);
696
+
chg = devm_kzalloc(dev, sizeof(*chg), GFP_KERNEL);
697
+
if (!chg)
698
+
return -ENOMEM;
699
+
700
+
platform_set_drvdata(pdev, chg);
701
+
chg->dev = dev;
702
+
chg->regmap = dev_get_regmap(dev->parent, "charger");
703
+
if (!chg->regmap)
704
+
return dev_err_probe(dev, -ENODEV, "Missing regmap\n");
705
+
706
+
ret = devm_mutex_init(dev, &chg->lock);
707
+
if (ret)
708
+
return dev_err_probe(dev, ret, "Failed to initialize lock\n");
709
+
710
+
ret = devm_mutex_init(dev, &chg->retry_lock);
711
+
if (ret)
712
+
return dev_err_probe(dev, ret,
713
+
"Failed to initialize retry_lock\n");
714
+
715
+
psy_cfg.fwnode = dev_fwnode(dev);
716
+
psy_cfg.drv_data = chg;
717
+
chg->psy = devm_power_supply_register(dev, &max77759_charger_desc,
718
+
&psy_cfg);
719
+
if (IS_ERR(chg->psy))
720
+
return dev_err_probe(dev, PTR_ERR(chg->psy),
721
+
"Failed to register psy\n");
722
+
723
+
ret = max77759_charger_init(chg);
724
+
if (ret)
725
+
return dev_err_probe(dev, ret,
726
+
"Failed to initialize max77759 charger\n");
727
+
728
+
chgin_otg_reg_cfg.dev = dev;
729
+
chgin_otg_reg_cfg.driver_data = chg;
730
+
chgin_otg_reg_cfg.of_node = dev_of_node(dev);
731
+
chg->chgin_otg_rdev = devm_regulator_register(dev, &chgin_otg_reg_desc,
732
+
&chgin_otg_reg_cfg);
733
+
if (IS_ERR(chg->chgin_otg_rdev))
734
+
return dev_err_probe(dev, PTR_ERR(chg->chgin_otg_rdev),
735
+
"Failed to register chgin otg regulator\n");
736
+
737
+
ret = devm_delayed_work_autocancel(dev, &chg->psy_work, psy_work_item);
738
+
if (ret)
739
+
return dev_err_probe(dev, ret, "Failed to initialize psy work\n");
740
+
741
+
chg->nb.notifier_call = psy_changed;
742
+
ret = power_supply_reg_notifier(&chg->nb);
743
+
if (ret)
744
+
return dev_err_probe(dev, ret,
745
+
"Unable to register psy notifier\n");
746
+
747
+
ret = devm_add_action_or_reset(dev, max_tcpci_unregister_psy_notifier,
748
+
&chg->nb);
749
+
if (ret)
750
+
return dev_err_probe(dev, ret,
751
+
"Failed to add devm action to unregister psy notifier\n");
752
+
753
+
return max77759_init_irqhandler(chg);
754
+
}
755
+
756
+
static const struct platform_device_id max77759_charger_id[] = {
757
+
{ .name = "max77759-charger", },
758
+
{ }
759
+
};
760
+
MODULE_DEVICE_TABLE(platform, max77759_charger_id);
761
+
762
+
static struct platform_driver max77759_charger_driver = {
763
+
.driver = {
764
+
.name = "max77759-charger",
765
+
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
766
+
},
767
+
.probe = max77759_charger_probe,
768
+
.id_table = max77759_charger_id,
769
+
};
770
+
module_platform_driver(max77759_charger_driver);
771
+
772
+
MODULE_AUTHOR("Amit Sunil Dhamne <amitsd@google.com>");
773
+
MODULE_DESCRIPTION("Maxim MAX77759 charger driver");
774
+
MODULE_LICENSE("GPL");
+2
drivers/power/supply/power_supply_sysfs.c
+2
drivers/power/supply/power_supply_sysfs.c
···
70
70
[POWER_SUPPLY_USB_TYPE_PD] = "PD",
71
71
[POWER_SUPPLY_USB_TYPE_PD_DRP] = "PD_DRP",
72
72
[POWER_SUPPLY_USB_TYPE_PD_PPS] = "PD_PPS",
73
+
[POWER_SUPPLY_USB_TYPE_PD_SPR_AVS] = "PD_SPR_AVS",
74
+
[POWER_SUPPLY_USB_TYPE_PD_PPS_SPR_AVS] = "PD_PPS_SPR_AVS",
73
75
[POWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID] = "BrickID",
74
76
};
75
77
+3
-12
drivers/thunderbolt/dma_port.c
+3
-12
drivers/thunderbolt/dma_port.c
···
55
55
struct tb_switch *sw;
56
56
u8 port;
57
57
u32 base;
58
-
u8 *buf;
58
+
u8 buf[];
59
59
};
60
60
61
61
/*
···
209
209
if (port < 0)
210
210
return NULL;
211
211
212
-
dma = kzalloc_obj(*dma);
212
+
dma = kzalloc_flex(*dma, buf, MAIL_DATA_DWORDS);
213
213
if (!dma)
214
214
return NULL;
215
-
216
-
dma->buf = kmalloc_array(MAIL_DATA_DWORDS, sizeof(u32), GFP_KERNEL);
217
-
if (!dma->buf) {
218
-
kfree(dma);
219
-
return NULL;
220
-
}
221
215
222
216
dma->sw = sw;
223
217
dma->port = port;
···
226
232
*/
227
233
void dma_port_free(struct tb_dma_port *dma)
228
234
{
229
-
if (dma) {
230
-
kfree(dma->buf);
231
-
kfree(dma);
232
-
}
235
+
kfree(dma);
233
236
}
234
237
235
238
static int dma_port_wait_for_completion(struct tb_dma_port *dma,
+7
-21
drivers/thunderbolt/path.c
+7
-21
drivers/thunderbolt/path.c
···
150
150
num_hops++;
151
151
}
152
152
153
-
path = kzalloc_obj(*path);
153
+
path = kzalloc_flex(*path, hops, num_hops);
154
154
if (!path)
155
155
return NULL;
156
156
157
+
path->path_length = num_hops;
158
+
157
159
path->name = name;
158
160
path->tb = src->sw->tb;
159
-
path->path_length = num_hops;
160
161
path->activated = true;
161
162
path->alloc_hopid = alloc_hopid;
162
-
163
-
path->hops = kzalloc_objs(*path->hops, num_hops);
164
-
if (!path->hops) {
165
-
kfree(path);
166
-
return NULL;
167
-
}
168
163
169
164
tb_dbg(path->tb, "discovering %s path starting from %llx:%u\n",
170
165
path->name, tb_route(src->sw), src->port);
···
240
245
size_t num_hops;
241
246
int i, ret;
242
247
243
-
path = kzalloc_obj(*path);
244
-
if (!path)
245
-
return NULL;
246
-
247
248
first_port = last_port = NULL;
248
249
i = 0;
249
250
tb_for_each_port_on_path(src, dst, in_port) {
···
250
259
}
251
260
252
261
/* Check that src and dst are reachable */
253
-
if (first_port != src || last_port != dst) {
254
-
kfree(path);
262
+
if (first_port != src || last_port != dst)
255
263
return NULL;
256
-
}
257
264
258
265
/* Each hop takes two ports */
259
266
num_hops = i / 2;
260
267
261
-
path->hops = kzalloc_objs(*path->hops, num_hops);
262
-
if (!path->hops) {
263
-
kfree(path);
268
+
path = kzalloc_flex(*path, hops, num_hops);
269
+
if (!path)
264
270
return NULL;
265
-
}
266
271
272
+
path->path_length = num_hops;
267
273
path->alloc_hopid = true;
268
274
269
275
in_hopid = src_hopid;
···
327
339
}
328
340
329
341
path->tb = tb;
330
-
path->path_length = num_hops;
331
342
path->name = name;
332
343
333
344
return path;
···
359
372
}
360
373
}
361
374
362
-
kfree(path->hops);
363
375
kfree(path);
364
376
}
365
377
+7
drivers/thunderbolt/quirks.c
+7
drivers/thunderbolt/quirks.c
···
23
23
24
24
static void quirk_clx_disable(struct tb_switch *sw)
25
25
{
26
+
if (tb_switch_is_titan_ridge(sw) && sw->nvm && sw->nvm->major >= 0x65)
27
+
return;
28
+
26
29
sw->quirks |= QUIRK_NO_CLX;
27
30
tb_sw_dbg(sw, "disabling CL states\n");
28
31
}
···
64
61
/* Dell WD19TB supports self-authentication on unplug */
65
62
{ 0x0000, 0x0000, 0x00d4, 0xb070, quirk_force_power_link },
66
63
{ 0x0000, 0x0000, 0x00d4, 0xb071, quirk_force_power_link },
64
+
65
+
/* Intel Titan Ridge CLx is unstable on early firmware versions */
66
+
{ 0x8086, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE, 0x0000, 0x0000,
67
+
quirk_clx_disable },
67
68
/*
68
69
* Intel Goshen Ridge NVM 27 and before report wrong number of
69
70
* DP buffers.
+26
-4
drivers/thunderbolt/switch.c
+26
-4
drivers/thunderbolt/switch.c
···
347
347
return ret;
348
348
}
349
349
350
-
static int tb_switch_nvm_add(struct tb_switch *sw)
350
+
static int tb_switch_nvm_init(struct tb_switch *sw)
351
351
{
352
352
struct tb_nvm *nvm;
353
353
int ret;
···
364
364
ret = tb_nvm_read_version(nvm);
365
365
if (ret)
366
366
goto err_nvm;
367
+
368
+
sw->nvm = nvm;
369
+
return 0;
370
+
371
+
err_nvm:
372
+
tb_sw_dbg(sw, "NVM upgrade disabled\n");
373
+
sw->no_nvm_upgrade = true;
374
+
if (!IS_ERR(nvm))
375
+
tb_nvm_free(nvm);
376
+
377
+
return ret;
378
+
}
379
+
380
+
static int tb_switch_nvm_add(struct tb_switch *sw)
381
+
{
382
+
struct tb_nvm *nvm = sw->nvm;
383
+
int ret;
384
+
385
+
if (!nvm)
386
+
return 0;
367
387
368
388
/*
369
389
* If the switch is in safe-mode the only accessible portion of
···
403
383
goto err_nvm;
404
384
}
405
385
406
-
sw->nvm = nvm;
407
386
return 0;
408
387
409
388
err_nvm:
410
389
tb_sw_dbg(sw, "NVM upgrade disabled\n");
411
390
sw->no_nvm_upgrade = true;
412
-
if (!IS_ERR(nvm))
413
-
tb_nvm_free(nvm);
391
+
tb_nvm_free(nvm);
414
392
415
393
return ret;
416
394
}
···
3328
3310
dev_err(&sw->dev, "failed to add DMA port\n");
3329
3311
return ret;
3330
3312
}
3313
+
3314
+
ret = tb_switch_nvm_init(sw);
3315
+
if (ret)
3316
+
return ret;
3331
3317
3332
3318
if (!sw->safe_mode) {
3333
3319
tb_switch_credits_init(sw);
+3
-2
drivers/thunderbolt/tb.h
+3
-2
drivers/thunderbolt/tb.h
···
419
419
* @activated: Is the path active
420
420
* @clear_fc: Clear all flow control from the path config space entries
421
421
* when deactivating this path
422
-
* @hops: Path hops
423
422
* @path_length: How many hops the path uses
424
423
* @alloc_hopid: Does this path consume port HopID
424
+
* @hops: Path hops
425
425
*
426
426
* A path consists of a number of hops (see &struct tb_path_hop). To
427
427
* establish a PCIe tunnel two paths have to be created between the two
···
440
440
bool drop_packages;
441
441
bool activated;
442
442
bool clear_fc;
443
-
struct tb_path_hop *hops;
444
443
int path_length;
445
444
bool alloc_hopid;
445
+
446
+
struct tb_path_hop hops[] __counted_by(path_length);
446
447
};
447
448
448
449
/* HopIDs 0-7 are reserved by the Thunderbolt protocol */
+2
-8
drivers/thunderbolt/tunnel.c
+2
-8
drivers/thunderbolt/tunnel.c
···
180
180
{
181
181
struct tb_tunnel *tunnel;
182
182
183
-
tunnel = kzalloc_obj(*tunnel);
183
+
tunnel = kzalloc_flex(*tunnel, paths, npaths);
184
184
if (!tunnel)
185
185
return NULL;
186
186
187
-
tunnel->paths = kzalloc_objs(tunnel->paths[0], npaths);
188
-
if (!tunnel->paths) {
189
-
kfree(tunnel);
190
-
return NULL;
191
-
}
187
+
tunnel->npaths = npaths;
192
188
193
189
INIT_LIST_HEAD(&tunnel->list);
194
190
tunnel->tb = tb;
195
-
tunnel->npaths = npaths;
196
191
tunnel->type = type;
197
192
kref_init(&tunnel->kref);
198
193
···
214
219
tb_path_free(tunnel->paths[i]);
215
220
}
216
221
217
-
kfree(tunnel->paths);
218
222
kfree(tunnel);
219
223
}
220
224
+3
-2
drivers/thunderbolt/tunnel.h
+3
-2
drivers/thunderbolt/tunnel.h
···
37
37
* @src_port: Source port of the tunnel
38
38
* @dst_port: Destination port of the tunnel. For discovered incomplete
39
39
* tunnels may be %NULL or null adapter port instead.
40
-
* @paths: All paths required by the tunnel
41
40
* @npaths: Number of paths in @paths
42
41
* @pre_activate: Optional tunnel specific initialization called before
43
42
* activation. Can touch hardware.
···
68
69
* @dprx_work: Worker that is scheduled to poll completion of DPRX capabilities read
69
70
* @callback: Optional callback called when DP tunnel is fully activated
70
71
* @callback_data: Optional data for @callback
72
+
* @paths: All paths required by the tunnel
71
73
*/
72
74
struct tb_tunnel {
73
75
struct kref kref;
74
76
struct tb *tb;
75
77
struct tb_port *src_port;
76
78
struct tb_port *dst_port;
77
-
struct tb_path **paths;
78
79
size_t npaths;
79
80
int (*pre_activate)(struct tb_tunnel *tunnel);
80
81
int (*activate)(struct tb_tunnel *tunnel, bool activate);
···
106
107
struct delayed_work dprx_work;
107
108
void (*callback)(struct tb_tunnel *tunnel, void *data);
108
109
void *callback_data;
110
+
111
+
struct tb_path *paths[] __counted_by(npaths);
109
112
};
110
113
111
114
struct tb_tunnel *tb_tunnel_discover_pci(struct tb *tb, struct tb_port *down,
+30
-44
drivers/usb/chipidea/core.c
+30
-44
drivers/usb/chipidea/core.c
···
544
544
if (ret == IRQ_HANDLED)
545
545
return ret;
546
546
}
547
-
}
548
547
549
-
/*
550
-
* Handle id change interrupt, it indicates device/host function
551
-
* switch.
552
-
*/
553
-
if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
554
-
ci->id_event = true;
555
-
/* Clear ID change irq status */
556
-
hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
557
-
ci_otg_queue_work(ci);
558
-
return IRQ_HANDLED;
559
-
}
548
+
/*
549
+
* Handle id change interrupt, it indicates device/host function
550
+
* switch.
551
+
*/
552
+
if ((otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
553
+
ci->id_event = true;
554
+
/* Clear ID change irq status */
555
+
hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
556
+
}
560
557
561
-
/*
562
-
* Handle vbus change interrupt, it indicates device connection
563
-
* and disconnection events.
564
-
*/
565
-
if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
566
-
ci->b_sess_valid_event = true;
567
-
/* Clear BSV irq */
568
-
hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
569
-
ci_otg_queue_work(ci);
570
-
return IRQ_HANDLED;
558
+
/*
559
+
* Handle vbus change interrupt, it indicates device connection
560
+
* and disconnection events.
561
+
*/
562
+
if ((otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
563
+
ci->b_sess_valid_event = true;
564
+
/* Clear BSV irq */
565
+
hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
566
+
}
567
+
568
+
if (ci->id_event || ci->b_sess_valid_event) {
569
+
ci_otg_queue_work(ci);
570
+
return IRQ_HANDLED;
571
+
}
571
572
}
572
573
573
574
/* Handle device/host interrupt */
···
619
618
struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
620
619
struct ci_hdrc_cable *cable;
621
620
622
-
if (role == USB_ROLE_HOST) {
623
-
cable = &ci->platdata->id_extcon;
624
-
cable->changed = true;
625
-
cable->connected = true;
626
-
cable = &ci->platdata->vbus_extcon;
627
-
cable->changed = true;
628
-
cable->connected = false;
629
-
} else if (role == USB_ROLE_DEVICE) {
630
-
cable = &ci->platdata->id_extcon;
631
-
cable->changed = true;
632
-
cable->connected = false;
633
-
cable = &ci->platdata->vbus_extcon;
634
-
cable->changed = true;
635
-
cable->connected = true;
636
-
} else {
637
-
cable = &ci->platdata->id_extcon;
638
-
cable->changed = true;
639
-
cable->connected = false;
640
-
cable = &ci->platdata->vbus_extcon;
641
-
cable->changed = true;
642
-
cable->connected = false;
643
-
}
621
+
cable = &ci->platdata->id_extcon;
622
+
cable->changed = true;
623
+
cable->connected = (role == USB_ROLE_HOST);
624
+
625
+
cable = &ci->platdata->vbus_extcon;
626
+
cable->changed = true;
627
+
cable->connected = (role == USB_ROLE_DEVICE);
644
628
645
629
ci_irq(ci);
646
630
return 0;
+5
-2
drivers/usb/chipidea/otg.c
+5
-2
drivers/usb/chipidea/otg.c
···
130
130
131
131
void ci_handle_vbus_change(struct ci_hdrc *ci)
132
132
{
133
+
if (ci->role != CI_ROLE_GADGET)
134
+
return;
135
+
133
136
if (!ci->is_otg) {
134
137
if (ci->platdata->flags & CI_HDRC_FORCE_VBUS_ACTIVE_ALWAYS)
135
138
usb_gadget_vbus_connect(&ci->gadget);
···
190
187
191
188
ci_role_stop(ci);
192
189
193
-
if (role == CI_ROLE_GADGET &&
194
-
IS_ERR(ci->platdata->vbus_extcon.edev))
190
+
if (role == CI_ROLE_GADGET && !ci->role_switch &&
191
+
IS_ERR(ci->platdata->vbus_extcon.edev))
195
192
/*
196
193
* Wait vbus lower than OTGSC_BSV before connecting
197
194
* to host. If connecting status is from an external
+46
-7
drivers/usb/class/cdc-acm.c
+46
-7
drivers/usb/class/cdc-acm.c
···
114
114
int retval;
115
115
116
116
retval = usb_autopm_get_interface(acm->control);
117
+
#define VENDOR_CLASS_DATA_IFACE BIT(9) /* data interface uses vendor-specific class */
118
+
#define ALWAYS_POLL_CTRL BIT(10) /* keep ctrl URB active even without an open TTY */
117
119
if (retval)
118
120
return retval;
119
121
···
712
710
set_bit(TTY_NO_WRITE_SPLIT, &tty->flags);
713
711
acm->control->needs_remote_wakeup = 1;
714
712
715
-
acm->ctrlurb->dev = acm->dev;
716
-
retval = usb_submit_urb(acm->ctrlurb, GFP_KERNEL);
717
-
if (retval) {
718
-
dev_err(&acm->control->dev,
719
-
"%s - usb_submit_urb(ctrl irq) failed\n", __func__);
720
-
goto error_submit_urb;
713
+
if (!(acm->quirks & ALWAYS_POLL_CTRL)) {
714
+
acm->ctrlurb->dev = acm->dev;
715
+
retval = usb_submit_urb(acm->ctrlurb, GFP_KERNEL);
716
+
if (retval) {
717
+
dev_err(&acm->control->dev,
718
+
"%s - usb_submit_urb(ctrl irq) failed\n", __func__);
719
+
goto error_submit_urb;
720
+
}
721
721
}
722
722
723
723
acm_tty_set_termios(tty, NULL);
···
792
788
793
789
acm_unpoison_urbs(acm);
794
790
791
+
if (acm->quirks & ALWAYS_POLL_CTRL) {
792
+
acm->ctrlurb->dev = acm->dev;
793
+
if (usb_submit_urb(acm->ctrlurb, GFP_KERNEL))
794
+
dev_dbg(&acm->control->dev,
795
+
"ctrl polling restart failed after port close\n");
796
+
/* port_shutdown() cleared DTR/RTS; restore them */
797
+
acm_set_control(acm, USB_CDC_CTRL_DTR | USB_CDC_CTRL_RTS);
798
+
}
795
799
}
796
800
797
801
static void acm_tty_cleanup(struct tty_struct *tty)
···
1340
1328
dev_dbg(&intf->dev,
1341
1329
"Your device has switched interfaces.\n");
1342
1330
swap(control_interface, data_interface);
1331
+
} else if (quirks & VENDOR_CLASS_DATA_IFACE) {
1332
+
dev_dbg(&intf->dev,
1333
+
"Vendor-specific data interface class, continuing.\n");
1343
1334
} else {
1344
1335
return -EINVAL;
1345
1336
}
···
1537
1522
acm->line.bDataBits = 8;
1538
1523
acm_set_line(acm, &acm->line);
1539
1524
1525
+
if (quirks & ALWAYS_POLL_CTRL)
1526
+
acm_set_control(acm, USB_CDC_CTRL_DTR | USB_CDC_CTRL_RTS);
1527
+
1540
1528
if (!acm->combined_interfaces) {
1541
1529
rv = usb_driver_claim_interface(&acm_driver, data_interface, acm);
1542
1530
if (rv)
···
1560
1542
}
1561
1543
1562
1544
dev_info(&intf->dev, "ttyACM%d: USB ACM device\n", minor);
1545
+
1546
+
if (acm->quirks & ALWAYS_POLL_CTRL) {
1547
+
acm->ctrlurb->dev = acm->dev;
1548
+
if (usb_submit_urb(acm->ctrlurb, GFP_KERNEL))
1549
+
dev_warn(&intf->dev,
1550
+
"failed to start persistent ctrl polling\n");
1551
+
}
1563
1552
1564
1553
return 0;
1565
1554
···
1694
1669
1695
1670
acm_unpoison_urbs(acm);
1696
1671
1697
-
if (tty_port_initialized(&acm->port)) {
1672
+
if (tty_port_initialized(&acm->port) || (acm->quirks & ALWAYS_POLL_CTRL)) {
1698
1673
rv = usb_submit_urb(acm->ctrlurb, GFP_ATOMIC);
1699
1674
1700
1675
for (;;) {
···
2040
2015
2041
2016
/* CH343 supports CAP_BRK, but doesn't advertise it */
2042
2017
{ USB_DEVICE(0x1a86, 0x55d3), .driver_info = MISSING_CAP_BRK, },
2018
+
2019
+
/*
2020
+
* Lenovo Yoga Book 9 14IAH10 (83KJ) — INGENIC 17EF:6161 touchscreen
2021
+
* composite device. The CDC ACM control interface (0) uses a standard
2022
+
* Union descriptor, but the data interface (1) is declared as vendor-
2023
+
* specific class (0xff) with no CDC data descriptors, so cdc-acm would
2024
+
* normally reject it. The firmware also requires continuous polling of
2025
+
* the notification endpoint (EP 0x82) to suppress a 20-second watchdog
2026
+
* reset; ALWAYS_POLL_CTRL keeps the ctrlurb active even when no TTY is
2027
+
* open. Match only the control interface by class to avoid probing the
2028
+
* vendor-specific data interface.
2029
+
*/
2030
+
{ USB_DEVICE_INTERFACE_CLASS(0x17ef, 0x6161, USB_CLASS_COMM),
2031
+
.driver_info = VENDOR_CLASS_DATA_IFACE | ALWAYS_POLL_CTRL },
2043
2032
2044
2033
/* control interfaces without any protocol set */
2045
2034
{ USB_INTERFACE_INFO(USB_CLASS_COMM, USB_CDC_SUBCLASS_ACM,
+2
-2
drivers/usb/core/config.c
+2
-2
drivers/usb/core/config.c
···
54
54
* follows the SuperSpeed Endpoint Companion descriptor
55
55
*/
56
56
desc = (struct usb_ssp_isoc_ep_comp_descriptor *) buffer;
57
-
if (desc->bDescriptorType != USB_DT_SSP_ISOC_ENDPOINT_COMP ||
58
-
size < USB_DT_SSP_ISOC_EP_COMP_SIZE) {
57
+
if (size < USB_DT_SSP_ISOC_EP_COMP_SIZE ||
58
+
desc->bDescriptorType != USB_DT_SSP_ISOC_ENDPOINT_COMP) {
59
59
dev_notice(ddev, "Invalid SuperSpeedPlus isoc endpoint companion"
60
60
"for config %d interface %d altsetting %d ep %d.\n",
61
61
cfgno, inum, asnum, ep->desc.bEndpointAddress);
-8
drivers/usb/core/endpoint.c
-8
drivers/usb/core/endpoint.c
···
26
26
#define to_ep_device(_dev) \
27
27
container_of(_dev, struct ep_device, dev)
28
28
29
-
struct ep_attribute {
30
-
struct attribute attr;
31
-
ssize_t (*show)(struct usb_device *,
32
-
struct usb_endpoint_descriptor *, char *);
33
-
};
34
-
#define to_ep_attribute(_attr) \
35
-
container_of(_attr, struct ep_attribute, attr)
36
-
37
29
#define usb_ep_attr(field, format_string) \
38
30
static ssize_t field##_show(struct device *dev, \
39
31
struct device_attribute *attr, \
+11
-9
drivers/usb/core/message.c
+11
-9
drivers/usb/core/message.c
···
1063
1063
}
1064
1064
EXPORT_SYMBOL_GPL(usb_string);
1065
1065
1066
-
/* one UTF-8-encoded 16-bit character has at most three bytes */
1066
+
/* one 16-bit character, when UTF-8-encoded, has at most three bytes */
1067
1067
#define MAX_USB_STRING_SIZE (127 * 3 + 1)
1068
1068
1069
1069
/**
···
1084
1084
return NULL;
1085
1085
1086
1086
buf = kmalloc(MAX_USB_STRING_SIZE, GFP_NOIO);
1087
-
if (buf) {
1088
-
len = usb_string(udev, index, buf, MAX_USB_STRING_SIZE);
1089
-
if (len > 0) {
1090
-
smallbuf = kmalloc(++len, GFP_NOIO);
1091
-
if (!smallbuf)
1092
-
return buf;
1093
-
memcpy(smallbuf, buf, len);
1094
-
}
1087
+
if (!buf)
1088
+
return NULL;
1089
+
1090
+
len = usb_string(udev, index, buf, MAX_USB_STRING_SIZE);
1091
+
if (len <= 0) {
1095
1092
kfree(buf);
1093
+
return NULL;
1096
1094
}
1095
+
1096
+
smallbuf = krealloc(buf, len + 1, GFP_NOIO);
1097
+
if (unlikely(!smallbuf))
1098
+
return buf;
1097
1099
return smallbuf;
1098
1100
}
1099
1101
EXPORT_SYMBOL_GPL(usb_cache_string);
+2
-6
drivers/usb/core/of.c
+2
-6
drivers/usb/core/of.c
···
79
79
static bool usb_of_has_devices_or_graph(const struct usb_device *hub)
80
80
{
81
81
const struct device_node *np = hub->dev.of_node;
82
-
struct device_node *child;
83
82
84
83
if (of_graph_is_present(np))
85
84
return true;
86
85
87
-
for_each_child_of_node(np, child) {
88
-
if (of_property_present(child, "reg")) {
89
-
of_node_put(child);
86
+
for_each_child_of_node_scoped(np, child)
87
+
if (of_property_present(child, "reg"))
90
88
return true;
91
-
}
92
-
}
93
89
94
90
return false;
95
91
}
+18
-3
drivers/usb/core/port.c
+18
-3
drivers/usb/core/port.c
···
21
21
22
22
static const struct attribute_group *port_dev_group[];
23
23
24
+
static bool usb_port_allow_power_off(struct usb_device *hdev,
25
+
struct usb_hub *hub,
26
+
struct usb_port *port_dev)
27
+
{
28
+
if (hub_is_port_power_switchable(hub))
29
+
return true;
30
+
31
+
if (!IS_ENABLED(CONFIG_ACPI))
32
+
return false;
33
+
34
+
return port_dev->connect_type == USB_PORT_CONNECT_TYPE_HARD_WIRED &&
35
+
usb_acpi_power_manageable(hdev, port_dev->portnum - 1);
36
+
}
37
+
24
38
static ssize_t early_stop_show(struct device *dev,
25
39
struct device_attribute *attr, char *buf)
26
40
{
···
155
141
usb_disconnect(&port_dev->child);
156
142
157
143
rc = usb_hub_set_port_power(hdev, hub, port1, !disabled);
144
+
msleep(2 * hub_power_on_good_delay(hub));
158
145
159
146
if (disabled) {
160
147
usb_clear_port_feature(hdev, port1, USB_PORT_FEAT_C_CONNECTION);
···
820
805
device_enable_async_suspend(&port_dev->dev);
821
806
822
807
/*
823
-
* Keep hidden the ability to enable port-poweroff if the hub
824
-
* does not support power switching.
808
+
* Keep hidden the ability to enable port-poweroff if neither the
809
+
* USB hub nor platform firmware can manage downstream port power.
825
810
*/
826
-
if (!hub_is_port_power_switchable(hub))
811
+
if (!usb_port_allow_power_off(hdev, hub, port_dev))
827
812
return 0;
828
813
829
814
/* Attempt to let userspace take over the policy. */
+12
drivers/usb/dwc3/Kconfig
+12
drivers/usb/dwc3/Kconfig
···
150
150
functionality.
151
151
Say 'Y' or 'M' if you have one such device.
152
152
153
+
config USB_DWC3_IMX
154
+
tristate "NXP iMX Platform"
155
+
depends on OF && COMMON_CLK
156
+
depends on (ARCH_MXC && ARM64) || COMPILE_TEST
157
+
default USB_DWC3
158
+
help
159
+
NXP iMX SoC use DesignWare Core IP for USB2/3
160
+
functionality.
161
+
This driver also handles the wakeup feature outside
162
+
of DesignWare Core.
163
+
Say 'Y' or 'M' if you have one such device.
164
+
153
165
config USB_DWC3_XILINX
154
166
tristate "Xilinx Platforms"
155
167
depends on (ARCH_ZYNQMP || COMPILE_TEST) && OF
+1
drivers/usb/dwc3/Makefile
+1
drivers/usb/dwc3/Makefile
···
55
55
obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o
56
56
obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom-legacy.o
57
57
obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o
58
+
obj-$(CONFIG_USB_DWC3_IMX) += dwc3-imx.o
58
59
obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o
59
60
obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o
60
61
obj-$(CONFIG_USB_DWC3_RTK) += dwc3-rtk.o
+27
-2
drivers/usb/dwc3/core.c
+27
-2
drivers/usb/dwc3/core.c
···
782
782
return 0;
783
783
}
784
784
785
+
static void dwc3_ulpi_setup(struct dwc3 *dwc)
786
+
{
787
+
int index;
788
+
u32 reg;
789
+
790
+
/* Don't do anything if there is no ULPI PHY */
791
+
if (!dwc->ulpi)
792
+
return;
793
+
794
+
if (dwc->enable_usb2_transceiver_delay) {
795
+
for (index = 0; index < dwc->num_usb2_ports; index++) {
796
+
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));
797
+
reg |= DWC3_GUSB2PHYCFG_XCVRDLY;
798
+
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
799
+
}
800
+
}
801
+
}
802
+
785
803
/**
786
804
* dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
787
805
* @dwc: Pointer to our controller context structure
···
1381
1363
dwc->ulpi_ready = true;
1382
1364
}
1383
1365
1366
+
dwc3_ulpi_setup(dwc);
1367
+
1384
1368
if (!dwc->phys_ready) {
1385
1369
ret = dwc3_core_get_phy(dwc);
1386
1370
if (ret)
···
1694
1674
struct device *tmpdev;
1695
1675
u16 gsbuscfg0_reqinfo;
1696
1676
int ret;
1677
+
1678
+
if (properties->needs_full_reinit)
1679
+
dwc->needs_full_reinit = true;
1697
1680
1698
1681
dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED;
1699
1682
···
2502
2479
dwc3_core_exit(dwc);
2503
2480
break;
2504
2481
case DWC3_GCTL_PRTCAP_HOST:
2505
-
if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2482
+
if (!PMSG_IS_AUTO(msg) &&
2483
+
(!device_may_wakeup(dwc->dev) || dwc->needs_full_reinit)) {
2506
2484
dwc3_core_exit(dwc);
2507
2485
break;
2508
2486
}
···
2566
2542
dwc3_gadget_resume(dwc);
2567
2543
break;
2568
2544
case DWC3_GCTL_PRTCAP_HOST:
2569
-
if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2545
+
if (!PMSG_IS_AUTO(msg) &&
2546
+
(!device_may_wakeup(dwc->dev) || dwc->needs_full_reinit)) {
2570
2547
ret = dwc3_core_init_for_resume(dwc);
2571
2548
if (ret)
2572
2549
return ret;
+8
-1
drivers/usb/dwc3/core.h
+8
-1
drivers/usb/dwc3/core.h
···
302
302
#define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
303
303
#define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
304
304
#define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
305
+
#define DWC3_GUSB2PHYCFG_XCVRDLY BIT(9)
305
306
#define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
306
307
#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
307
308
#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
···
1120
1119
* @usb3_lpm_capable: set if hadrware supports Link Power Management
1121
1120
* @usb2_lpm_disable: set to disable usb2 lpm for host
1122
1121
* @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget
1122
+
* @needs_full_reinit: set to indicate the core may lose power and need full
1123
+
* initialization during system pm
1123
1124
* @disable_scramble_quirk: set if we enable the disable scramble quirk
1124
1125
* @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
1125
1126
* @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
···
1152
1149
* VBUS with an external supply.
1153
1150
* @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
1154
1151
* instances in park mode.
1155
-
* @parkmode_disable_hs_quirk: set if we need to disable all HishSpeed
1152
+
* @parkmode_disable_hs_quirk: set if we need to disable all HighSpeed
1156
1153
* instances in park mode.
1157
1154
* @gfladj_refclk_lpm_sel: set if we need to enable SOF/ITP counter
1158
1155
* running based on ref_clk
···
1164
1161
* 3 - Reserved
1165
1162
* @dis_metastability_quirk: set to disable metastability quirk.
1166
1163
* @dis_split_quirk: set to disable split boundary.
1164
+
* @enable_usb2_transceiver_delay: Set to insert a delay before the
1165
+
* assertion of the TxValid signal during a HS Chirp.
1167
1166
* @sys_wakeup: set if the device may do system wakeup.
1168
1167
* @wakeup_configured: set if the device is configured for remote wakeup.
1169
1168
* @suspended: set to track suspend event due to U3/L2.
···
1378
1373
unsigned usb3_lpm_capable:1;
1379
1374
unsigned usb2_lpm_disable:1;
1380
1375
unsigned usb2_gadget_lpm_disable:1;
1376
+
unsigned needs_full_reinit:1;
1381
1377
1382
1378
unsigned disable_scramble_quirk:1;
1383
1379
unsigned u2exit_lfps_quirk:1;
···
1409
1403
unsigned dis_metastability_quirk:1;
1410
1404
1411
1405
unsigned dis_split_quirk:1;
1406
+
unsigned enable_usb2_transceiver_delay:1;
1412
1407
unsigned async_callbacks:1;
1413
1408
unsigned sys_wakeup:1;
1414
1409
unsigned wakeup_configured:1;
+24
-1
drivers/usb/dwc3/dwc3-generic-plat.c
+24
-1
drivers/usb/dwc3/dwc3-generic-plat.c
···
12
12
#include <linux/reset.h>
13
13
#include <linux/regmap.h>
14
14
#include <linux/mfd/syscon.h>
15
+
#include <linux/regulator/consumer.h>
16
+
#include <linux/usb/otg.h>
15
17
#include "glue.h"
16
18
17
19
#define EIC7700_HSP_BUS_FILTER_EN BIT(0)
···
68
66
69
67
regmap_write(regmap, hsp_usb_axi_lp, EIC7700_HSP_AXI_LP_XM_CSYSREQ |
70
68
EIC7700_HSP_AXI_LP_XS_CSYSREQ);
69
+
return 0;
70
+
}
71
+
72
+
static int dwc3_spacemit_k1_init(struct dwc3_generic *dwc3g)
73
+
{
74
+
struct device *dev = dwc3g->dev;
75
+
76
+
if (usb_get_dr_mode(dev) == USB_DR_MODE_HOST) {
77
+
int ret = devm_regulator_get_enable_optional(dev, "vbus");
78
+
79
+
if (ret && ret != -ENODEV)
80
+
return dev_err_probe(dev, ret, "failed to enable VBUS\n");
81
+
}
82
+
71
83
return 0;
72
84
}
73
85
···
217
201
dwc3_generic_runtime_idle)
218
202
};
219
203
204
+
static const struct dwc3_generic_config spacemit_k1_dwc3 = {
205
+
.init = dwc3_spacemit_k1_init,
206
+
.properties = DWC3_DEFAULT_PROPERTIES,
207
+
};
208
+
220
209
static const struct dwc3_generic_config fsl_ls1028_dwc3 = {
221
210
.properties.gsbuscfg0_reqinfo = 0x2222,
222
211
};
···
232
211
};
233
212
234
213
static const struct of_device_id dwc3_generic_of_match[] = {
235
-
{ .compatible = "spacemit,k1-dwc3", },
214
+
{ .compatible = "spacemit,k1-dwc3", &spacemit_k1_dwc3},
215
+
{ .compatible = "spacemit,k3-dwc3", },
236
216
{ .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3},
237
217
{ .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3},
218
+
{ .compatible = "starfive,jhb100-dwc3", },
238
219
{ /* sentinel */ }
239
220
};
240
221
MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
+448
drivers/usb/dwc3/dwc3-imx.c
+448
drivers/usb/dwc3/dwc3-imx.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* dwc3-imx.c - NXP i.MX Soc USB3 Specific Glue layer
4
+
*
5
+
* Copyright 2026 NXP
6
+
*/
7
+
8
+
#include <linux/clk.h>
9
+
#include <linux/interrupt.h>
10
+
#include <linux/io.h>
11
+
#include <linux/kernel.h>
12
+
#include <linux/module.h>
13
+
#include <linux/of_platform.h>
14
+
#include <linux/platform_device.h>
15
+
#include <linux/pm_runtime.h>
16
+
17
+
#include "core.h"
18
+
#include "glue.h"
19
+
20
+
/* USB wakeup registers */
21
+
#define USB_WAKEUP_CTRL 0x00
22
+
23
+
/* Global wakeup interrupt enable, also used to clear interrupt */
24
+
#define USB_WAKEUP_EN BIT(31)
25
+
/* Wakeup from connect or disconnect, only for superspeed */
26
+
#define USB_WAKEUP_SS_CONN BIT(5)
27
+
/* 0 select vbus_valid, 1 select sessvld */
28
+
#define USB_WAKEUP_VBUS_SRC_SESS_VAL BIT(4)
29
+
/* Enable signal for wake up from u3 state */
30
+
#define USB_WAKEUP_U3_EN BIT(3)
31
+
/* Enable signal for wake up from id change */
32
+
#define USB_WAKEUP_ID_EN BIT(2)
33
+
/* Enable signal for wake up from vbus change */
34
+
#define USB_WAKEUP_VBUS_EN BIT(1)
35
+
/* Enable signal for wake up from dp/dm change */
36
+
#define USB_WAKEUP_DPDM_EN BIT(0)
37
+
38
+
#define USB_WAKEUP_EN_MASK GENMASK(5, 0)
39
+
40
+
/* USB glue registers */
41
+
#define USB_CTRL0 0x00
42
+
#define USB_CTRL1 0x04
43
+
44
+
#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
45
+
#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
46
+
#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
47
+
48
+
#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
49
+
#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
50
+
51
+
struct dwc3_imx {
52
+
struct dwc3 dwc;
53
+
struct device *dev;
54
+
void __iomem *blkctl_base;
55
+
void __iomem *glue_base;
56
+
struct clk *hsio_clk;
57
+
struct clk *suspend_clk;
58
+
int irq;
59
+
bool pm_suspended;
60
+
bool wakeup_pending;
61
+
unsigned permanent_attached:1;
62
+
unsigned disable_pwr_ctrl:1;
63
+
unsigned overcur_active_low:1;
64
+
unsigned power_active_low:1;
65
+
};
66
+
67
+
#define to_dwc3_imx(d) container_of((d), struct dwc3_imx, dwc)
68
+
69
+
static void dwc3_imx_get_property(struct dwc3_imx *dwc_imx)
70
+
{
71
+
struct device *dev = dwc_imx->dev;
72
+
73
+
dwc_imx->permanent_attached =
74
+
device_property_read_bool(dev, "fsl,permanently-attached");
75
+
dwc_imx->disable_pwr_ctrl =
76
+
device_property_read_bool(dev, "fsl,disable-port-power-control");
77
+
dwc_imx->overcur_active_low =
78
+
device_property_read_bool(dev, "fsl,over-current-active-low");
79
+
dwc_imx->power_active_low =
80
+
device_property_read_bool(dev, "fsl,power-active-low");
81
+
}
82
+
83
+
static void dwc3_imx_configure_glue(struct dwc3_imx *dwc_imx)
84
+
{
85
+
u32 value;
86
+
87
+
if (!dwc_imx->glue_base)
88
+
return;
89
+
90
+
value = readl(dwc_imx->glue_base + USB_CTRL0);
91
+
92
+
if (dwc_imx->permanent_attached)
93
+
value |= USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED;
94
+
else
95
+
value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
96
+
97
+
if (dwc_imx->disable_pwr_ctrl)
98
+
value &= ~USB_CTRL0_PORTPWR_EN;
99
+
else
100
+
value |= USB_CTRL0_PORTPWR_EN;
101
+
102
+
writel(value, dwc_imx->glue_base + USB_CTRL0);
103
+
104
+
value = readl(dwc_imx->glue_base + USB_CTRL1);
105
+
if (dwc_imx->overcur_active_low)
106
+
value |= USB_CTRL1_OC_POLARITY;
107
+
else
108
+
value &= ~USB_CTRL1_OC_POLARITY;
109
+
110
+
if (dwc_imx->power_active_low)
111
+
value |= USB_CTRL1_PWR_POLARITY;
112
+
else
113
+
value &= ~USB_CTRL1_PWR_POLARITY;
114
+
115
+
writel(value, dwc_imx->glue_base + USB_CTRL1);
116
+
}
117
+
118
+
static void dwc3_imx_wakeup_enable(struct dwc3_imx *dwc_imx, pm_message_t msg)
119
+
{
120
+
struct dwc3 *dwc = &dwc_imx->dwc;
121
+
u32 val;
122
+
123
+
val = readl(dwc_imx->blkctl_base + USB_WAKEUP_CTRL);
124
+
125
+
if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && dwc->xhci) {
126
+
val |= USB_WAKEUP_EN | USB_WAKEUP_DPDM_EN;
127
+
if (PMSG_IS_AUTO(msg))
128
+
val |= USB_WAKEUP_SS_CONN | USB_WAKEUP_U3_EN;
129
+
} else {
130
+
val |= USB_WAKEUP_EN | USB_WAKEUP_VBUS_EN |
131
+
USB_WAKEUP_VBUS_SRC_SESS_VAL;
132
+
}
133
+
134
+
writel(val, dwc_imx->blkctl_base + USB_WAKEUP_CTRL);
135
+
}
136
+
137
+
static void dwc3_imx_wakeup_disable(struct dwc3_imx *dwc_imx)
138
+
{
139
+
u32 val;
140
+
141
+
val = readl(dwc_imx->blkctl_base + USB_WAKEUP_CTRL);
142
+
val &= ~(USB_WAKEUP_EN | USB_WAKEUP_EN_MASK);
143
+
writel(val, dwc_imx->blkctl_base + USB_WAKEUP_CTRL);
144
+
}
145
+
146
+
static irqreturn_t dwc3_imx_interrupt(int irq, void *data)
147
+
{
148
+
struct dwc3_imx *dwc_imx = data;
149
+
struct dwc3 *dwc = &dwc_imx->dwc;
150
+
151
+
if (!dwc_imx->pm_suspended)
152
+
return IRQ_HANDLED;
153
+
154
+
disable_irq_nosync(dwc_imx->irq);
155
+
dwc_imx->wakeup_pending = true;
156
+
157
+
if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && dwc->xhci)
158
+
pm_runtime_resume(&dwc->xhci->dev);
159
+
else if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE)
160
+
pm_runtime_get(dwc->dev);
161
+
162
+
return IRQ_HANDLED;
163
+
}
164
+
165
+
static void dwc3_imx_pre_set_role(struct dwc3 *dwc, enum usb_role role)
166
+
{
167
+
if (role == USB_ROLE_HOST)
168
+
/*
169
+
* For xhci host, we need disable dwc core auto
170
+
* suspend, because during this auto suspend delay(5s),
171
+
* xhci host RUN_STOP is cleared and wakeup is not
172
+
* enabled, if device is inserted, xhci host can't
173
+
* response the connection.
174
+
*/
175
+
pm_runtime_dont_use_autosuspend(dwc->dev);
176
+
else
177
+
pm_runtime_use_autosuspend(dwc->dev);
178
+
}
179
+
180
+
static struct dwc3_glue_ops dwc3_imx_glue_ops = {
181
+
.pre_set_role = dwc3_imx_pre_set_role,
182
+
};
183
+
184
+
static const struct property_entry dwc3_imx_properties[] = {
185
+
PROPERTY_ENTRY_BOOL("xhci-missing-cas-quirk"),
186
+
PROPERTY_ENTRY_BOOL("xhci-skip-phy-init-quirk"),
187
+
{},
188
+
};
189
+
190
+
static const struct software_node dwc3_imx_swnode = {
191
+
.properties = dwc3_imx_properties,
192
+
};
193
+
194
+
static int dwc3_imx_probe(struct platform_device *pdev)
195
+
{
196
+
struct device *dev = &pdev->dev;
197
+
struct dwc3_imx *dwc_imx;
198
+
struct dwc3 *dwc;
199
+
struct resource *res;
200
+
const char *irq_name;
201
+
struct dwc3_probe_data probe_data = {};
202
+
int ret, irq;
203
+
204
+
dwc_imx = devm_kzalloc(dev, sizeof(*dwc_imx), GFP_KERNEL);
205
+
if (!dwc_imx)
206
+
return -ENOMEM;
207
+
208
+
platform_set_drvdata(pdev, dwc_imx);
209
+
dwc_imx->dev = dev;
210
+
211
+
dwc3_imx_get_property(dwc_imx);
212
+
213
+
dwc_imx->blkctl_base = devm_platform_ioremap_resource_byname(pdev, "blkctl");
214
+
if (IS_ERR(dwc_imx->blkctl_base))
215
+
return PTR_ERR(dwc_imx->blkctl_base);
216
+
217
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "glue");
218
+
if (!res) {
219
+
dev_warn(dev, "Base address for glue layer missing\n");
220
+
} else {
221
+
dwc_imx->glue_base = devm_ioremap_resource(dev, res);
222
+
if (IS_ERR(dwc_imx->glue_base))
223
+
return PTR_ERR(dwc_imx->glue_base);
224
+
}
225
+
226
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
227
+
if (!res)
228
+
return dev_err_probe(dev, -ENODEV, "missing core memory resource\n");
229
+
230
+
dwc_imx->hsio_clk = devm_clk_get_enabled(dev, "hsio");
231
+
if (IS_ERR(dwc_imx->hsio_clk))
232
+
return dev_err_probe(dev, PTR_ERR(dwc_imx->hsio_clk),
233
+
"Failed to get hsio clk\n");
234
+
235
+
dwc_imx->suspend_clk = devm_clk_get_enabled(dev, "suspend");
236
+
if (IS_ERR(dwc_imx->suspend_clk))
237
+
return dev_err_probe(dev, PTR_ERR(dwc_imx->suspend_clk),
238
+
"Failed to get suspend clk\n");
239
+
240
+
irq = platform_get_irq_byname(pdev, "wakeup");
241
+
if (irq < 0)
242
+
return irq;
243
+
dwc_imx->irq = irq;
244
+
245
+
irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s:wakeup", dev_name(dev));
246
+
if (!irq_name)
247
+
return dev_err_probe(dev, -ENOMEM, "failed to create irq_name\n");
248
+
249
+
ret = devm_request_threaded_irq(dev, irq, NULL, dwc3_imx_interrupt,
250
+
IRQF_ONESHOT | IRQF_NO_AUTOEN,
251
+
irq_name, dwc_imx);
252
+
if (ret)
253
+
return dev_err_probe(dev, ret, "failed to request IRQ #%d\n", irq);
254
+
255
+
ret = device_add_software_node(dev, &dwc3_imx_swnode);
256
+
if (ret)
257
+
return dev_err_probe(dev, ret, "failed to add software node\n");
258
+
259
+
dwc3_imx_configure_glue(dwc_imx);
260
+
261
+
dwc = &dwc_imx->dwc;
262
+
dwc->dev = dev;
263
+
dwc->glue_ops = &dwc3_imx_glue_ops;
264
+
265
+
probe_data.res = res;
266
+
probe_data.dwc = dwc;
267
+
probe_data.properties = DWC3_DEFAULT_PROPERTIES;
268
+
probe_data.properties.needs_full_reinit = true;
269
+
270
+
ret = dwc3_core_probe(&probe_data);
271
+
if (ret) {
272
+
device_remove_software_node(dev);
273
+
return ret;
274
+
}
275
+
276
+
device_set_wakeup_capable(dev, true);
277
+
return 0;
278
+
}
279
+
280
+
static void dwc3_imx_remove(struct platform_device *pdev)
281
+
{
282
+
struct device *dev = &pdev->dev;
283
+
struct dwc3 *dwc = dev_get_drvdata(dev);
284
+
285
+
dwc3_core_remove(dwc);
286
+
device_remove_software_node(dev);
287
+
}
288
+
289
+
static void dwc3_imx_suspend(struct dwc3_imx *dwc_imx, pm_message_t msg)
290
+
{
291
+
if (dwc_imx->pm_suspended)
292
+
return;
293
+
294
+
if (PMSG_IS_AUTO(msg) || device_may_wakeup(dwc_imx->dev))
295
+
dwc3_imx_wakeup_enable(dwc_imx, msg);
296
+
297
+
enable_irq(dwc_imx->irq);
298
+
dwc_imx->pm_suspended = true;
299
+
}
300
+
301
+
static void dwc3_imx_resume(struct dwc3_imx *dwc_imx, pm_message_t msg)
302
+
{
303
+
struct dwc3 *dwc = &dwc_imx->dwc;
304
+
305
+
if (!dwc_imx->pm_suspended)
306
+
return;
307
+
308
+
dwc_imx->pm_suspended = false;
309
+
if (!dwc_imx->wakeup_pending)
310
+
disable_irq_nosync(dwc_imx->irq);
311
+
312
+
dwc3_imx_wakeup_disable(dwc_imx);
313
+
314
+
/* Upon power loss any previous configuration is lost, restore it */
315
+
dwc3_imx_configure_glue(dwc_imx);
316
+
317
+
if (dwc_imx->wakeup_pending) {
318
+
dwc_imx->wakeup_pending = false;
319
+
if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE)
320
+
pm_runtime_put_autosuspend(dwc->dev);
321
+
else
322
+
/*
323
+
* Add wait for xhci switch from suspend
324
+
* clock to normal clock to detect connection.
325
+
*/
326
+
usleep_range(9000, 10000);
327
+
}
328
+
}
329
+
330
+
static int dwc3_imx_runtime_suspend(struct device *dev)
331
+
{
332
+
struct dwc3 *dwc = dev_get_drvdata(dev);
333
+
struct dwc3_imx *dwc_imx = to_dwc3_imx(dwc);
334
+
int ret;
335
+
336
+
ret = dwc3_runtime_suspend(dwc);
337
+
if (ret)
338
+
return ret;
339
+
340
+
dwc3_imx_suspend(dwc_imx, PMSG_AUTO_SUSPEND);
341
+
return 0;
342
+
}
343
+
344
+
static int dwc3_imx_runtime_resume(struct device *dev)
345
+
{
346
+
struct dwc3 *dwc = dev_get_drvdata(dev);
347
+
struct dwc3_imx *dwc_imx = to_dwc3_imx(dwc);
348
+
349
+
dwc3_imx_resume(dwc_imx, PMSG_AUTO_RESUME);
350
+
return dwc3_runtime_resume(dwc);
351
+
}
352
+
353
+
static int dwc3_imx_runtime_idle(struct device *dev)
354
+
{
355
+
return dwc3_runtime_idle(dev_get_drvdata(dev));
356
+
}
357
+
358
+
static int dwc3_imx_pm_suspend(struct device *dev)
359
+
{
360
+
struct dwc3 *dwc = dev_get_drvdata(dev);
361
+
struct dwc3_imx *dwc_imx = to_dwc3_imx(dwc);
362
+
int ret;
363
+
364
+
ret = dwc3_pm_suspend(dwc);
365
+
if (ret)
366
+
return ret;
367
+
368
+
dwc3_imx_suspend(dwc_imx, PMSG_SUSPEND);
369
+
370
+
if (device_may_wakeup(dev)) {
371
+
enable_irq_wake(dwc_imx->irq);
372
+
device_set_out_band_wakeup(dev);
373
+
} else {
374
+
clk_disable_unprepare(dwc_imx->suspend_clk);
375
+
}
376
+
377
+
clk_disable_unprepare(dwc_imx->hsio_clk);
378
+
379
+
return 0;
380
+
}
381
+
382
+
static int dwc3_imx_pm_resume(struct device *dev)
383
+
{
384
+
struct dwc3 *dwc = dev_get_drvdata(dev);
385
+
struct dwc3_imx *dwc_imx = to_dwc3_imx(dwc);
386
+
int ret;
387
+
388
+
if (device_may_wakeup(dwc_imx->dev)) {
389
+
disable_irq_wake(dwc_imx->irq);
390
+
} else {
391
+
ret = clk_prepare_enable(dwc_imx->suspend_clk);
392
+
if (ret)
393
+
return ret;
394
+
}
395
+
396
+
ret = clk_prepare_enable(dwc_imx->hsio_clk);
397
+
if (ret) {
398
+
clk_disable_unprepare(dwc_imx->suspend_clk);
399
+
return ret;
400
+
}
401
+
402
+
dwc3_imx_resume(dwc_imx, PMSG_RESUME);
403
+
404
+
ret = dwc3_pm_resume(dwc);
405
+
if (ret)
406
+
return ret;
407
+
408
+
return 0;
409
+
}
410
+
411
+
static void dwc3_imx_complete(struct device *dev)
412
+
{
413
+
dwc3_pm_complete(dev_get_drvdata(dev));
414
+
}
415
+
416
+
static int dwc3_imx_prepare(struct device *dev)
417
+
{
418
+
return dwc3_pm_prepare(dev_get_drvdata(dev));
419
+
}
420
+
421
+
static const struct dev_pm_ops dwc3_imx_dev_pm_ops = {
422
+
SYSTEM_SLEEP_PM_OPS(dwc3_imx_pm_suspend, dwc3_imx_pm_resume)
423
+
RUNTIME_PM_OPS(dwc3_imx_runtime_suspend, dwc3_imx_runtime_resume,
424
+
dwc3_imx_runtime_idle)
425
+
.complete = pm_sleep_ptr(dwc3_imx_complete),
426
+
.prepare = pm_sleep_ptr(dwc3_imx_prepare),
427
+
};
428
+
429
+
static const struct of_device_id dwc3_imx_of_match[] = {
430
+
{ .compatible = "nxp,imx8mp-dwc3", },
431
+
{},
432
+
};
433
+
MODULE_DEVICE_TABLE(of, dwc3_imx_of_match);
434
+
435
+
static struct platform_driver dwc3_imx_driver = {
436
+
.probe = dwc3_imx_probe,
437
+
.remove = dwc3_imx_remove,
438
+
.driver = {
439
+
.name = "imx-dwc3",
440
+
.pm = pm_ptr(&dwc3_imx_dev_pm_ops),
441
+
.of_match_table = dwc3_imx_of_match,
442
+
},
443
+
};
444
+
445
+
module_platform_driver(dwc3_imx_driver);
446
+
447
+
MODULE_LICENSE("GPL");
448
+
MODULE_DESCRIPTION("DesignWare USB3 i.MX Glue Layer");
+2
-2
drivers/usb/dwc3/dwc3-qcom.c
+2
-2
drivers/usb/dwc3/dwc3-qcom.c
···
526
526
int irq;
527
527
528
528
irq = platform_get_irq_byname_optional(pdev, "dp_hs_phy_1");
529
-
if (irq <= 0)
529
+
if (irq < 0)
530
530
return 1;
531
531
532
532
for (port_num = 2; port_num <= DWC3_QCOM_MAX_PORTS; port_num++) {
533
533
sprintf(irq_name, "dp_hs_phy_%d", port_num);
534
534
535
535
irq = platform_get_irq_byname_optional(pdev, irq_name);
536
-
if (irq <= 0)
536
+
if (irq < 0)
537
537
return port_num - 1;
538
538
}
539
539
+1
-1
drivers/usb/dwc3/gadget.c
+1
-1
drivers/usb/dwc3/gadget.c
+3
drivers/usb/dwc3/glue.h
+3
drivers/usb/dwc3/glue.h
···
12
12
/**
13
13
* dwc3_properties: DWC3 core properties
14
14
* @gsbuscfg0_reqinfo: Value to be programmed in the GSBUSCFG0.REQINFO field
15
+
* @needs_full_reinit: indicate the controller may not remain power during system
16
+
* pm and need full initialization
15
17
*/
16
18
struct dwc3_properties {
17
19
u32 gsbuscfg0_reqinfo;
20
+
unsigned needs_full_reinit:1;
18
21
};
19
22
20
23
#define DWC3_DEFAULT_PROPERTIES ((struct dwc3_properties){ \
+25
drivers/usb/dwc3/ulpi.c
+25
drivers/usb/dwc3/ulpi.c
···
10
10
#include <linux/delay.h>
11
11
#include <linux/time64.h>
12
12
#include <linux/ulpi/regs.h>
13
+
#include <linux/ulpi/driver.h>
13
14
14
15
#include "core.h"
15
16
#include "io.h"
17
+
18
+
#define USB_VENDOR_MICROCHIP 0x0424
16
19
17
20
#define DWC3_ULPI_ADDR(a) \
18
21
((a >= ULPI_EXT_VENDOR_SPECIFIC) ? \
···
86
83
.write = dwc3_ulpi_write,
87
84
};
88
85
86
+
static void dwc3_ulpi_detect_config(struct dwc3 *dwc)
87
+
{
88
+
struct ulpi *ulpi = dwc->ulpi;
89
+
90
+
switch (ulpi->id.vendor) {
91
+
case USB_VENDOR_MICROCHIP:
92
+
switch (ulpi->id.product) {
93
+
case 0x0009:
94
+
/* Microchip USB3340 ULPI PHY */
95
+
dwc->enable_usb2_transceiver_delay = true;
96
+
break;
97
+
default:
98
+
break;
99
+
}
100
+
break;
101
+
default:
102
+
break;
103
+
}
104
+
}
105
+
89
106
int dwc3_ulpi_init(struct dwc3 *dwc)
90
107
{
91
108
/* Register the interface */
···
114
91
dev_err(dwc->dev, "failed to register ULPI interface");
115
92
return PTR_ERR(dwc->ulpi);
116
93
}
94
+
95
+
dwc3_ulpi_detect_config(dwc);
117
96
118
97
return 0;
119
98
}
+12
-5
drivers/usb/gadget/function/f_hid.c
+12
-5
drivers/usb/gadget/function/f_hid.c
···
106
106
struct list_head report_list;
107
107
108
108
struct device dev;
109
-
struct cdev cdev;
109
+
struct cdev *cdev;
110
110
struct usb_function func;
111
111
112
112
struct usb_ep *in_ep;
···
749
749
750
750
static int f_hidg_open(struct inode *inode, struct file *fd)
751
751
{
752
+
struct kobject *parent = inode->i_cdev->kobj.parent;
752
753
struct f_hidg *hidg =
753
-
container_of(inode->i_cdev, struct f_hidg, cdev);
754
+
container_of(parent, struct f_hidg, dev.kobj);
754
755
755
756
fd->private_data = hidg;
756
757
···
1277
1276
}
1278
1277
1279
1278
/* create char device */
1280
-
cdev_init(&hidg->cdev, &f_hidg_fops);
1281
-
status = cdev_device_add(&hidg->cdev, &hidg->dev);
1279
+
hidg->cdev = cdev_alloc();
1280
+
if (!hidg->cdev) {
1281
+
status = -ENOMEM;
1282
+
goto fail_free_all;
1283
+
}
1284
+
hidg->cdev->ops = &f_hidg_fops;
1285
+
1286
+
status = cdev_device_add(hidg->cdev, &hidg->dev);
1282
1287
if (status)
1283
1288
goto fail_free_all;
1284
1289
···
1586
1579
{
1587
1580
struct f_hidg *hidg = func_to_hidg(f);
1588
1581
1589
-
cdev_device_del(&hidg->cdev, &hidg->dev);
1582
+
cdev_device_del(hidg->cdev, &hidg->dev);
1590
1583
destroy_workqueue(hidg->workqueue);
1591
1584
usb_free_all_descriptors(f);
1592
1585
}
+3
-3
drivers/usb/gadget/function/f_midi2.c
+3
-3
drivers/usb/gadget/function/f_midi2.c
···
1541
1541
return err;
1542
1542
midi2->card = card;
1543
1543
1544
-
strcpy(card->driver, "f_midi2");
1545
-
strcpy(card->shortname, "MIDI 2.0 Gadget");
1546
-
strcpy(card->longname, "MIDI 2.0 Gadget");
1544
+
strscpy(card->driver, "f_midi2");
1545
+
strscpy(card->shortname, "MIDI 2.0 Gadget");
1546
+
strscpy(card->longname, "MIDI 2.0 Gadget");
1547
1547
1548
1548
id = 0;
1549
1549
for (i = 0; i < midi2->num_eps; i++) {
+2
-2
drivers/usb/gadget/function/f_ncm.c
+2
-2
drivers/usb/gadget/function/f_ncm.c
···
1210
1210
1211
1211
block_len = get_ncm(&tmp, opts->block_length);
1212
1212
/* (d)wBlockLength */
1213
-
if (block_len > ntb_max) {
1214
-
INFO(port->func.config->cdev, "OUT size exceeded\n");
1213
+
if ((block_len < opts->nth_size + opts->ndp_size) || (block_len > ntb_max)) {
1214
+
INFO(port->func.config->cdev, "Bad block length: %#X\n", block_len);
1215
1215
goto err;
1216
1216
}
1217
1217
+9
drivers/usb/gadget/function/f_phonet.c
+9
drivers/usb/gadget/function/f_phonet.c
···
333
333
if (unlikely(!skb))
334
334
break;
335
335
336
+
if (unlikely(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS)) {
337
+
/* Frame count from host exceeds frags[] capacity */
338
+
dev_kfree_skb_any(skb);
339
+
if (fp->rx.skb == skb)
340
+
fp->rx.skb = NULL;
341
+
dev->stats.rx_length_errors++;
342
+
break;
343
+
}
344
+
336
345
if (skb->len == 0) { /* First fragment */
337
346
skb->protocol = htons(ETH_P_PHONET);
338
347
skb_reset_mac_header(skb);
+1
-1
drivers/usb/gadget/function/u_serial.c
+1
-1
drivers/usb/gadget/function/u_serial.c
···
1086
1086
if (!cons)
1087
1087
return -ENOMEM;
1088
1088
1089
-
strcpy(cons->console.name, "ttyGS");
1089
+
strscpy(cons->console.name, "ttyGS");
1090
1090
cons->console.write = gs_console_write;
1091
1091
cons->console.device = gs_console_device;
1092
1092
cons->console.flags = CON_PRINTBUFFER;
+4
drivers/usb/gadget/udc/bdc/bdc_ep.c
+4
drivers/usb/gadget/udc/bdc/bdc_ep.c
···
1647
1647
u8 ep_num;
1648
1648
1649
1649
ep_num = (le32_to_cpu(sreport->offset[3])>>4) & 0x1f;
1650
+
if (ep_num >= bdc->num_eps) {
1651
+
dev_err(bdc->dev, "xsf for invalid ep %u\n", ep_num);
1652
+
return;
1653
+
}
1650
1654
ep = bdc->bdc_ep_array[ep_num];
1651
1655
if (!ep || !(ep->flags & BDC_EP_ENABLED)) {
1652
1656
dev_err(bdc->dev, "xsf for ep not enabled\n");
+3
-2
drivers/usb/gadget/udc/core.c
+3
-2
drivers/usb/gadget/udc/core.c
···
1266
1266
* @speed: The maximum speed to allowed to run
1267
1267
*
1268
1268
* This call is issued by the UDC Class driver before calling
1269
-
* usb_gadget_udc_start() in order to make sure that we don't try to
1270
-
* connect on speeds the gadget driver doesn't support.
1269
+
* usb_gadget_udc_start_locked() in order to make sure that
1270
+
* we don't try to connect on speeds the gadget driver
1271
+
* doesn't support.
1271
1272
*/
1272
1273
static inline void usb_gadget_udc_set_speed(struct usb_udc *udc,
1273
1274
enum usb_device_speed speed)
+53
-15
drivers/usb/gadget/udc/pxa27x_udc.c
+53
-15
drivers/usb/gadget/udc/pxa27x_udc.c
···
1462
1462
return 0;
1463
1463
}
1464
1464
1465
-
static void udc_enable(struct pxa_udc *udc);
1465
+
static int udc_enable(struct pxa_udc *udc);
1466
1466
static void udc_disable(struct pxa_udc *udc);
1467
1467
1468
1468
/**
···
1519
1519
static int pxa_udc_pullup(struct usb_gadget *_gadget, int is_active)
1520
1520
{
1521
1521
struct pxa_udc *udc = to_gadget_udc(_gadget);
1522
+
int ret;
1522
1523
1523
1524
if (!udc->gpiod && !udc->udc_command)
1524
1525
return -EOPNOTSUPP;
1525
1526
1526
1527
dplus_pullup(udc, is_active);
1527
1528
1528
-
if (should_enable_udc(udc))
1529
-
udc_enable(udc);
1529
+
if (should_enable_udc(udc)) {
1530
+
ret = udc_enable(udc);
1531
+
if (ret) {
1532
+
dplus_pullup(udc, !is_active);
1533
+
return ret;
1534
+
}
1535
+
}
1530
1536
if (should_disable_udc(udc))
1531
1537
udc_disable(udc);
1532
1538
return 0;
···
1551
1545
static int pxa_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
1552
1546
{
1553
1547
struct pxa_udc *udc = to_gadget_udc(_gadget);
1548
+
int ret;
1554
1549
1555
1550
udc->vbus_sensed = is_active;
1556
-
if (should_enable_udc(udc))
1557
-
udc_enable(udc);
1551
+
if (should_enable_udc(udc)) {
1552
+
ret = udc_enable(udc);
1553
+
if (ret) {
1554
+
udc->vbus_sensed = !is_active;
1555
+
return ret;
1556
+
}
1557
+
}
1558
1558
if (should_disable_udc(udc))
1559
1559
udc_disable(udc);
1560
1560
···
1703
1691
* Enables the udc device : enables clocks, udc interrupts, control endpoint
1704
1692
* interrupts, sets usb as UDC client and setups endpoints.
1705
1693
*/
1706
-
static void udc_enable(struct pxa_udc *udc)
1694
+
static int udc_enable(struct pxa_udc *udc)
1707
1695
{
1708
-
if (udc->enabled)
1709
-
return;
1696
+
int ret;
1710
1697
1711
-
clk_enable(udc->clk);
1698
+
if (udc->enabled)
1699
+
return 0;
1700
+
1701
+
ret = clk_enable(udc->clk);
1702
+
if (ret) {
1703
+
dev_err(udc->dev, "clk_enable failed: %d\n", ret);
1704
+
return ret;
1705
+
}
1712
1706
udc_writel(udc, UDCICR0, 0);
1713
1707
udc_writel(udc, UDCICR1, 0);
1714
1708
udc_clear_mask_UDCCR(udc, UDCCR_UDE);
···
1744
1726
pio_irq_enable(&udc->pxa_ep[0]);
1745
1727
1746
1728
udc->enabled = 1;
1729
+
1730
+
return 0;
1747
1731
}
1748
1732
1749
1733
/**
···
1781
1761
}
1782
1762
}
1783
1763
1784
-
if (should_enable_udc(udc))
1785
-
udc_enable(udc);
1764
+
if (should_enable_udc(udc)) {
1765
+
retval = udc_enable(udc);
1766
+
if (retval)
1767
+
goto fail_enable;
1768
+
}
1786
1769
return 0;
1787
1770
1771
+
fail_enable:
1772
+
if (!IS_ERR_OR_NULL(udc->transceiver))
1773
+
otg_set_peripheral(udc->transceiver->otg, NULL);
1788
1774
fail:
1789
1775
udc->driver = NULL;
1790
1776
return retval;
···
2456
2430
goto err_add_gadget;
2457
2431
2458
2432
pxa_init_debugfs(udc);
2459
-
if (should_enable_udc(udc))
2460
-
udc_enable(udc);
2433
+
if (should_enable_udc(udc)) {
2434
+
retval = udc_enable(udc);
2435
+
if (retval)
2436
+
goto err_enable;
2437
+
}
2461
2438
return 0;
2462
2439
2440
+
err_enable:
2441
+
usb_del_gadget_udc(&udc->gadget);
2442
+
pxa_cleanup_debugfs(udc);
2463
2443
err_add_gadget:
2464
2444
if (!IS_ERR_OR_NULL(udc->transceiver))
2465
2445
usb_unregister_notifier(udc->transceiver, &pxa27x_udc_phy);
···
2541
2509
{
2542
2510
struct pxa_udc *udc = platform_get_drvdata(_dev);
2543
2511
struct pxa_ep *ep;
2512
+
int ret;
2544
2513
2545
2514
ep = &udc->pxa_ep[0];
2546
2515
udc_ep_writel(ep, UDCCSR, udc->udccsr0 & (UDCCSR0_FST | UDCCSR0_DME));
2547
2516
2548
2517
dplus_pullup(udc, udc->pullup_resume);
2549
-
if (should_enable_udc(udc))
2550
-
udc_enable(udc);
2518
+
if (should_enable_udc(udc)) {
2519
+
ret = udc_enable(udc);
2520
+
if (ret) {
2521
+
dplus_pullup(udc, !udc->pullup_resume);
2522
+
return ret;
2523
+
}
2524
+
}
2551
2525
/*
2552
2526
* We do not handle OTG yet.
2553
2527
*
+6
-1
drivers/usb/gadget/udc/renesas_usb3.c
+6
-1
drivers/usb/gadget/udc/renesas_usb3.c
···
1669
1669
break;
1670
1670
case USB_RECIP_ENDPOINT:
1671
1671
num = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
1672
+
if (num >= usb3->num_usb3_eps) {
1673
+
stall = true;
1674
+
break;
1675
+
}
1672
1676
usb3_ep = usb3_get_ep(usb3, num);
1673
1677
if (usb3_ep->halt)
1674
1678
status |= 1 << USB_ENDPOINT_HALT;
···
1785
1781
struct renesas_usb3_ep *usb3_ep;
1786
1782
struct renesas_usb3_request *usb3_req;
1787
1783
1788
-
if (le16_to_cpu(ctrl->wValue) != USB_ENDPOINT_HALT)
1784
+
if ((le16_to_cpu(ctrl->wValue) != USB_ENDPOINT_HALT) ||
1785
+
(num >= usb3->num_usb3_eps))
1789
1786
return true; /* stall */
1790
1787
1791
1788
usb3_ep = usb3_get_ep(usb3, num);
+1
-1
drivers/usb/gadget/udc/snps_udc_core.c
+1
-1
drivers/usb/gadget/udc/snps_udc_core.c
···
3151
3151
tmp, dev->phys_addr, dev->chiprev,
3152
3152
(dev->chiprev == UDC_HSA0_REV) ?
3153
3153
"A0" : "B1");
3154
-
strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3154
+
strscpy(tmp, UDC_DRIVER_VERSION_STRING);
3155
3155
if (dev->chiprev == UDC_HSA0_REV) {
3156
3156
dev_err(dev->dev, "chip revision is A0; too old\n");
3157
3157
retval = -ENODEV;
-9
drivers/usb/host/ehci-orion.c
-9
drivers/usb/host/ehci-orion.c
···
12
12
#include <linux/clk.h>
13
13
#include <linux/platform_data/usb-ehci-orion.h>
14
14
#include <linux/of.h>
15
-
#include <linux/phy/phy.h>
16
15
#include <linux/usb.h>
17
16
#include <linux/usb/hcd.h>
18
17
#include <linux/io.h>
···
59
60
60
61
struct orion_ehci_hcd {
61
62
struct clk *clk;
62
-
struct phy *phy;
63
63
};
64
64
65
65
static struct hc_driver __read_mostly ehci_orion_hc_driver;
···
272
274
err = clk_prepare_enable(priv->clk);
273
275
if (err)
274
276
goto err_put_hcd;
275
-
}
276
-
277
-
priv->phy = devm_phy_optional_get(&pdev->dev, "usb");
278
-
if (IS_ERR(priv->phy)) {
279
-
err = PTR_ERR(priv->phy);
280
-
if (err != -ENOSYS)
281
-
goto err_dis_clk;
282
277
}
283
278
284
279
/*
+3
-12
drivers/usb/host/fhci-hcd.c
+3
-12
drivers/usb/host/fhci-hcd.c
···
426
426
}
427
427
428
428
/* allocate the private part of the URB */
429
-
urb_priv = kzalloc_obj(*urb_priv, mem_flags);
429
+
urb_priv = kzalloc_flex(*urb_priv, tds, size, mem_flags);
430
430
if (!urb_priv)
431
431
return -ENOMEM;
432
432
433
-
/* allocate the private part of the URB */
434
-
urb_priv->tds = kzalloc_objs(*urb_priv->tds, size, mem_flags);
435
-
if (!urb_priv->tds) {
436
-
kfree(urb_priv);
437
-
return -ENOMEM;
438
-
}
433
+
urb_priv->num_of_tds = size;
439
434
440
435
spin_lock_irqsave(&fhci->lock, flags);
441
436
···
439
444
goto err;
440
445
441
446
/* fill the private part of the URB */
442
-
urb_priv->num_of_tds = size;
443
-
444
447
urb->status = -EINPROGRESS;
445
448
urb->actual_length = 0;
446
449
urb->error_count = 0;
···
446
453
447
454
fhci_queue_urb(fhci, urb);
448
455
err:
449
-
if (ret) {
450
-
kfree(urb_priv->tds);
456
+
if (ret)
451
457
kfree(urb_priv);
452
-
}
453
458
spin_unlock_irqrestore(&fhci->lock, flags);
454
459
return ret;
455
460
}
+2
-1
drivers/usb/host/fhci.h
+2
-1
drivers/usb/host/fhci.h
+7
-3
drivers/usb/host/xhci-debugfs.c
+7
-3
drivers/usb/host/xhci-debugfs.c
···
700
700
seq_printf(s, "port[%d] available bw: %d%%.\n", i,
701
701
ctx->bytes[i]);
702
702
err_out:
703
+
if (ret == -EIO) {
704
+
seq_puts(s, "Get Port Bandwidth failed\n");
705
+
ret = 0;
706
+
}
703
707
pm_runtime_put_sync(dev);
704
708
xhci_free_port_bw_ctx(xhci, ctx);
705
709
return ret;
···
714
710
int ret;
715
711
struct xhci_hcd *xhci = (struct xhci_hcd *)s->private;
716
712
717
-
ret = xhci_port_bw_show(xhci, USB_SPEED_SUPER, s);
713
+
ret = xhci_port_bw_show(xhci, DEV_PORT_SPEED(XDEV_SS), s);
718
714
return ret;
719
715
}
720
716
···
723
719
int ret;
724
720
struct xhci_hcd *xhci = (struct xhci_hcd *)s->private;
725
721
726
-
ret = xhci_port_bw_show(xhci, USB_SPEED_HIGH, s);
722
+
ret = xhci_port_bw_show(xhci, DEV_PORT_SPEED(XDEV_HS), s);
727
723
return ret;
728
724
}
729
725
···
732
728
int ret;
733
729
struct xhci_hcd *xhci = (struct xhci_hcd *)s->private;
734
730
735
-
ret = xhci_port_bw_show(xhci, USB_SPEED_FULL, s);
731
+
ret = xhci_port_bw_show(xhci, DEV_PORT_SPEED(XDEV_FS), s);
736
732
return ret;
737
733
}
738
734
+178
-205
drivers/usb/host/xhci-hub.c
+178
-205
drivers/usb/host/xhci-hub.c
···
375
375
376
376
}
377
377
378
-
static unsigned int xhci_port_speed(unsigned int port_status)
378
+
static unsigned int xhci_port_speed(int portsc)
379
379
{
380
-
if (DEV_LOWSPEED(port_status))
380
+
if (DEV_LOWSPEED(portsc))
381
381
return USB_PORT_STAT_LOW_SPEED;
382
-
if (DEV_HIGHSPEED(port_status))
382
+
if (DEV_HIGHSPEED(portsc))
383
383
return USB_PORT_STAT_HIGH_SPEED;
384
384
/*
385
385
* FIXME: Yes, we should check for full speed, but the core uses that as
···
429
429
430
430
/**
431
431
* xhci_port_state_to_neutral() - Clean up read portsc value back into writeable
432
-
* @state: u32 port value read from portsc register to be cleanup up
432
+
* @portsc: u32 port value read from portsc register to be cleanup up
433
433
*
434
-
* Given a port state, this function returns a value that would result in the
434
+
* Given a portsc, this function returns a value that would result in the
435
435
* port being in the same state, if the value was written to the port status
436
436
* control register.
437
437
* Save Read Only (RO) bits and save read/write bits where
···
442
442
* changing port state.
443
443
*/
444
444
445
-
u32 xhci_port_state_to_neutral(u32 state)
445
+
u32 xhci_port_state_to_neutral(u32 portsc)
446
446
{
447
447
/* Save read-only status and port state */
448
-
return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
448
+
return (portsc & XHCI_PORT_RO) | (portsc & XHCI_PORT_RWS);
449
449
}
450
450
EXPORT_SYMBOL_GPL(xhci_port_state_to_neutral);
451
451
···
577
577
hcd->self.busnum, port->hcd_portnum + 1, portsc);
578
578
}
579
579
580
-
static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
581
-
u16 wIndex, struct xhci_port *port, u32 port_status)
580
+
static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, struct xhci_port *port,
581
+
u32 portsc)
582
582
{
583
583
char *port_change_bit;
584
584
u32 status;
···
621
621
return;
622
622
}
623
623
/* Change bits are all write 1 to clear */
624
-
xhci_portsc_writel(port, port_status | status);
625
-
port_status = xhci_portsc_readl(port);
624
+
xhci_portsc_writel(port, portsc | status);
625
+
portsc = xhci_portsc_readl(port);
626
626
627
627
xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
628
-
wIndex + 1, port_change_bit, port_status);
628
+
port->hcd_portnum + 1, port_change_bit, portsc);
629
629
}
630
630
631
631
struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
···
675
675
spin_lock_irqsave(&xhci->lock, *flags);
676
676
}
677
677
678
-
static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
679
-
u16 test_mode, u16 wIndex)
678
+
static void xhci_port_set_test_mode(struct xhci_hcd *xhci, u16 test_mode, int portnum)
680
679
{
681
680
u32 temp;
682
681
struct xhci_port *port;
683
682
684
683
/* xhci only supports test mode for usb2 ports */
685
-
port = xhci->usb2_rhub.ports[wIndex];
684
+
port = xhci->usb2_rhub.ports[portnum];
686
685
temp = readl(&port->port_reg->portpmsc);
687
686
temp |= test_mode << PORT_TEST_MODE_SHIFT;
688
687
writel(temp, &port->port_reg->portpmsc);
···
690
691
xhci_start(xhci);
691
692
}
692
693
693
-
static int xhci_enter_test_mode(struct xhci_hcd *xhci,
694
-
u16 test_mode, u16 wIndex, unsigned long *flags)
694
+
static int xhci_enter_test_mode(struct xhci_hcd *xhci, u16 test_mode, int portnum,
695
+
unsigned long *flags)
695
696
__must_hold(&xhci->lock)
696
697
{
697
698
int i, retval;
···
725
726
/* Disable runtime PM for test mode */
726
727
pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
727
728
/* Set PORTPMSC.PTC field to enter selected test mode */
728
-
/* Port is selected by wIndex. port_id = wIndex + 1 */
729
-
xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
730
-
test_mode, wIndex + 1);
731
-
xhci_port_set_test_mode(xhci, test_mode, wIndex);
729
+
xhci_dbg(xhci, "Enter Test Mode: %u, Port_id=%d\n", test_mode, portnum + 1);
730
+
xhci_port_set_test_mode(xhci, test_mode, portnum);
732
731
return retval;
733
732
}
734
733
···
850
853
}
851
854
852
855
/* Updates Link Status for super Speed port */
853
-
static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
854
-
u32 *status, u32 status_reg)
856
+
static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, u32 *status, u32 portsc)
855
857
{
856
-
u32 pls = status_reg & PORT_PLS_MASK;
858
+
u32 pls = portsc & PORT_PLS_MASK;
857
859
858
-
/* When the CAS bit is set then warm reset
859
-
* should be performed on port
860
+
/*
861
+
* CAS indicates that a warm reset is required, it may be set in any
862
+
* link state and is only present on roothubs.
860
863
*/
861
-
if (status_reg & PORT_CAS) {
862
-
/* The CAS bit can be set while the port is
863
-
* in any link state.
864
-
* Only roothubs have CAS bit, so we
865
-
* pretend to be in compliance mode
866
-
* unless we're already in compliance
867
-
* or the inactive state.
864
+
if (portsc & PORT_CAS) {
865
+
/*
866
+
* If not already in Compliance or Inactive state,
867
+
* report Compliance Mode so the hub logic triggers a warm reset.
868
868
*/
869
-
if (pls != USB_SS_PORT_LS_COMP_MOD &&
870
-
pls != USB_SS_PORT_LS_SS_INACTIVE) {
869
+
if (pls != XDEV_COMP_MODE && pls != XDEV_INACTIVE)
871
870
pls = USB_SS_PORT_LS_COMP_MOD;
872
-
}
873
-
/* Return also connection bit -
874
-
* hub state machine resets port
875
-
* when this bit is set.
876
-
*/
877
-
pls |= USB_PORT_STAT_CONNECTION;
878
-
} else {
879
-
/*
880
-
* Resume state is an xHCI internal state. Do not report it to
881
-
* usb core, instead, pretend to be U3, thus usb core knows
882
-
* it's not ready for transfer.
883
-
*/
884
-
if (pls == XDEV_RESUME) {
885
-
*status |= USB_SS_PORT_LS_U3;
886
-
return;
887
-
}
888
871
872
+
/* Signal a connection change to force a reset */
873
+
*status |= USB_PORT_STAT_CONNECTION;
874
+
} else if (pls == XDEV_RESUME) {
889
875
/*
890
-
* If CAS bit isn't set but the Port is already at
891
-
* Compliance Mode, fake a connection so the USB core
892
-
* notices the Compliance state and resets the port.
893
-
* This resolves an issue generated by the SN65LVPE502CP
894
-
* in which sometimes the port enters compliance mode
895
-
* caused by a delay on the host-device negotiation.
876
+
* Resume is an internal xHCI-only state and must not be exposed
877
+
* to usbcore. Report it as U3 so transfers are blocked.
896
878
*/
897
-
if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
898
-
(pls == USB_SS_PORT_LS_COMP_MOD))
899
-
pls |= USB_PORT_STAT_CONNECTION;
879
+
pls = USB_SS_PORT_LS_U3;
880
+
} else if (pls == XDEV_COMP_MODE) {
881
+
/*
882
+
* Some hardware may enter Compliance Mode without CAS.
883
+
* Fake a connection event so usbcore notices and resets the port.
884
+
*/
885
+
if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
886
+
*status |= USB_PORT_STAT_CONNECTION;
900
887
}
901
888
902
889
/* update status field */
···
894
913
* the compliance mode timer is deleted. A port won't enter
895
914
* compliance mode if it has previously entered U0.
896
915
*/
897
-
static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
898
-
u16 wIndex)
916
+
static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 portsc, int portnum)
899
917
{
900
918
u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
901
-
bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
919
+
bool port_in_u0 = ((portsc & PORT_PLS_MASK) == XDEV_U0);
902
920
903
921
if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
904
922
return;
905
923
906
924
if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
907
-
xhci->port_status_u0 |= 1 << wIndex;
925
+
xhci->port_status_u0 |= 1 << portnum;
908
926
if (xhci->port_status_u0 == all_ports_seen_u0) {
909
927
timer_delete_sync(&xhci->comp_mode_recovery_timer);
910
928
xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
···
921
941
struct xhci_bus_state *bus_state;
922
942
struct xhci_hcd *xhci;
923
943
struct usb_hcd *hcd;
924
-
u32 wIndex;
944
+
int portnum;
925
945
926
946
hcd = port->rhub->hcd;
927
947
bus_state = &port->rhub->bus_state;
928
948
xhci = hcd_to_xhci(hcd);
929
-
wIndex = port->hcd_portnum;
949
+
portnum = port->hcd_portnum;
930
950
931
951
if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
932
952
return -EINVAL;
···
934
954
/* did port event handler already start resume timing? */
935
955
if (!port->resume_timestamp) {
936
956
/* If not, maybe we are in a host initiated resume? */
937
-
if (test_bit(wIndex, &bus_state->resuming_ports)) {
957
+
if (test_bit(portnum, &bus_state->resuming_ports)) {
938
958
/* Host initiated resume doesn't time the resume
939
959
* signalling using resume_done[].
940
960
* It manually sets RESUME state, sleeps 20ms
···
948
968
unsigned long timeout = jiffies +
949
969
msecs_to_jiffies(USB_RESUME_TIMEOUT);
950
970
951
-
set_bit(wIndex, &bus_state->resuming_ports);
971
+
set_bit(portnum, &bus_state->resuming_ports);
952
972
port->resume_timestamp = timeout;
953
973
mod_timer(&hcd->rh_timer, timeout);
954
-
usb_hcd_start_port_resume(&hcd->self, wIndex);
974
+
usb_hcd_start_port_resume(&hcd->self, portnum);
955
975
}
956
976
/* Has resume been signalled for USB_RESUME_TIME yet? */
957
977
} else if (time_after_eq(jiffies, port->resume_timestamp)) {
958
978
int time_left;
959
979
960
980
xhci_dbg(xhci, "resume USB2 port %d-%d\n",
961
-
hcd->self.busnum, wIndex + 1);
981
+
hcd->self.busnum, portnum + 1);
962
982
963
983
port->resume_timestamp = 0;
964
-
clear_bit(wIndex, &bus_state->resuming_ports);
984
+
clear_bit(portnum, &bus_state->resuming_ports);
965
985
966
986
reinit_completion(&port->rexit_done);
967
987
port->rexit_active = true;
···
985
1005
int port_status = xhci_portsc_readl(port);
986
1006
987
1007
xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
988
-
hcd->self.busnum, wIndex + 1, port_status);
1008
+
hcd->self.busnum, portnum + 1, port_status);
989
1009
/*
990
1010
* keep rexit_active set if U0 transition failed so we
991
1011
* know to report PORT_STAT_SUSPEND status back to
···
994
1014
*/
995
1015
}
996
1016
997
-
usb_hcd_end_port_resume(&hcd->self, wIndex);
998
-
bus_state->port_c_suspend |= 1 << wIndex;
999
-
bus_state->suspended_ports &= ~(1 << wIndex);
1017
+
usb_hcd_end_port_resume(&hcd->self, portnum);
1018
+
bus_state->port_c_suspend |= 1 << portnum;
1019
+
bus_state->suspended_ports &= ~(1 << portnum);
1000
1020
}
1001
1021
1002
1022
return 0;
1003
1023
}
1004
1024
1005
-
static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
1025
+
static u32 xhci_get_ext_port_status(u32 portsc, u32 port_li)
1006
1026
{
1007
1027
u32 ext_stat = 0;
1008
1028
int speed_id;
1009
1029
1010
1030
/* only support rx and tx lane counts of 1 in usb3.1 spec */
1011
-
speed_id = DEV_PORT_SPEED(raw_port_status);
1031
+
speed_id = DEV_PORT_SPEED(portsc);
1012
1032
ext_stat |= speed_id; /* bits 3:0, RX speed id */
1013
1033
ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
1014
1034
···
1133
1153
* - Stop the Synopsys redriver Compliance Mode polling.
1134
1154
* - Drop and reacquire the xHCI lock, in order to wait for port resume.
1135
1155
*/
1136
-
static u32 xhci_get_port_status(struct usb_hcd *hcd,
1137
-
struct xhci_bus_state *bus_state,
1138
-
u16 wIndex, u32 raw_port_status,
1139
-
unsigned long *flags)
1156
+
static u32 xhci_get_port_status(struct usb_hcd *hcd, struct xhci_bus_state *bus_state,
1157
+
int portnum, u32 portsc, unsigned long *flags)
1140
1158
__releases(&xhci->lock)
1141
1159
__acquires(&xhci->lock)
1142
1160
{
···
1143
1165
struct xhci_port *port;
1144
1166
1145
1167
rhub = xhci_get_rhub(hcd);
1146
-
port = rhub->ports[wIndex];
1168
+
port = rhub->ports[portnum];
1147
1169
1148
1170
/* common wPortChange bits */
1149
-
if (raw_port_status & PORT_CSC)
1171
+
if (portsc & PORT_CSC)
1150
1172
status |= USB_PORT_STAT_C_CONNECTION << 16;
1151
-
if (raw_port_status & PORT_PEC)
1173
+
if (portsc & PORT_PEC)
1152
1174
status |= USB_PORT_STAT_C_ENABLE << 16;
1153
-
if ((raw_port_status & PORT_OCC))
1175
+
if (portsc & PORT_OCC)
1154
1176
status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1155
-
if ((raw_port_status & PORT_RC))
1177
+
if (portsc & PORT_RC)
1156
1178
status |= USB_PORT_STAT_C_RESET << 16;
1157
1179
1158
1180
/* common wPortStatus bits */
1159
-
if (raw_port_status & PORT_CONNECT) {
1181
+
if (portsc & PORT_CONNECT) {
1160
1182
status |= USB_PORT_STAT_CONNECTION;
1161
-
status |= xhci_port_speed(raw_port_status);
1183
+
status |= xhci_port_speed(portsc);
1162
1184
}
1163
-
if (raw_port_status & PORT_PE)
1185
+
if (portsc & PORT_PE)
1164
1186
status |= USB_PORT_STAT_ENABLE;
1165
-
if (raw_port_status & PORT_OC)
1187
+
if (portsc & PORT_OC)
1166
1188
status |= USB_PORT_STAT_OVERCURRENT;
1167
-
if (raw_port_status & PORT_RESET)
1189
+
if (portsc & PORT_RESET)
1168
1190
status |= USB_PORT_STAT_RESET;
1169
1191
1170
1192
/* USB2 and USB3 specific bits, including Port Link State */
1171
1193
if (hcd->speed >= HCD_USB3)
1172
-
xhci_get_usb3_port_status(port, &status, raw_port_status);
1194
+
xhci_get_usb3_port_status(port, &status, portsc);
1173
1195
else
1174
-
xhci_get_usb2_port_status(port, &status, raw_port_status,
1175
-
flags);
1196
+
xhci_get_usb2_port_status(port, &status, portsc, flags);
1176
1197
1177
-
if (bus_state->port_c_suspend & (1 << wIndex))
1198
+
if (bus_state->port_c_suspend & (1 << portnum))
1178
1199
status |= USB_PORT_STAT_C_SUSPEND << 16;
1179
1200
1180
1201
return status;
···
1185
1208
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1186
1209
int max_ports;
1187
1210
unsigned long flags;
1188
-
u32 temp, status;
1211
+
u32 portsc, portpmsc, status;
1189
1212
int retval = 0;
1190
1213
struct xhci_bus_state *bus_state;
1191
-
u16 link_state = 0;
1192
-
u16 wake_mask = 0;
1193
-
u16 timeout = 0;
1194
-
u16 test_mode = 0;
1214
+
u16 link_state;
1215
+
u16 wake_mask;
1216
+
u8 timeout;
1217
+
u8 test_mode;
1218
+
u8 desc_type;
1195
1219
struct xhci_hub *rhub;
1196
1220
struct xhci_port **ports;
1197
1221
struct xhci_port *port;
1198
-
int portnum1;
1222
+
int portnum;
1199
1223
1200
1224
rhub = xhci_get_rhub(hcd);
1201
1225
ports = rhub->ports;
1202
1226
max_ports = rhub->num_ports;
1203
1227
bus_state = &rhub->bus_state;
1204
-
portnum1 = wIndex & 0xff;
1205
1228
1206
1229
spin_lock_irqsave(&xhci->lock, flags);
1207
1230
switch (typeReq) {
···
1210
1233
memset(buf, 0, 4);
1211
1234
break;
1212
1235
case GetHubDescriptor:
1236
+
desc_type = (wValue & 0xff00) >> 8;
1213
1237
/* Check to make sure userspace is asking for the USB 3.0 hub
1214
1238
* descriptor for the USB 3.0 roothub. If not, we stall the
1215
1239
* endpoint, like external hubs do.
1216
1240
*/
1217
1241
if (hcd->speed >= HCD_USB3 &&
1218
-
(wLength < USB_DT_SS_HUB_SIZE ||
1219
-
wValue != (USB_DT_SS_HUB << 8))) {
1242
+
(wLength < USB_DT_SS_HUB_SIZE || desc_type != USB_DT_SS_HUB)) {
1220
1243
xhci_dbg(xhci, "Wrong hub descriptor type for "
1221
1244
"USB 3.0 roothub.\n");
1222
1245
goto error;
···
1225
1248
(struct usb_hub_descriptor *) buf);
1226
1249
break;
1227
1250
case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1228
-
if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1251
+
desc_type = (wValue & 0xff00) >> 8;
1252
+
if (desc_type != USB_DT_BOS)
1229
1253
goto error;
1230
1254
1231
1255
if (hcd->speed < HCD_USB3)
···
1236
1258
spin_unlock_irqrestore(&xhci->lock, flags);
1237
1259
return retval;
1238
1260
case GetPortStatus:
1239
-
if (!portnum1 || portnum1 > max_ports)
1261
+
portnum = (wIndex & 0xff) - 1;
1262
+
if (!in_range(portnum, 0, max_ports))
1240
1263
goto error;
1241
1264
1242
-
wIndex--;
1243
-
port = ports[portnum1 - 1];
1244
-
temp = xhci_portsc_readl(port);
1245
-
if (temp == ~(u32)0) {
1265
+
port = ports[portnum];
1266
+
portsc = xhci_portsc_readl(port);
1267
+
if (portsc == ~(u32)0) {
1246
1268
xhci_hc_died(xhci);
1247
1269
retval = -ENODEV;
1248
1270
break;
1249
1271
}
1250
-
trace_xhci_get_port_status(port, temp);
1251
-
status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1252
-
&flags);
1272
+
trace_xhci_get_port_status(port, portsc);
1273
+
status = xhci_get_port_status(hcd, bus_state, portnum, portsc, &flags);
1253
1274
if (status == 0xffffffff)
1254
1275
goto error;
1255
1276
1256
1277
xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1257
-
hcd->self.busnum, portnum1, temp, status);
1278
+
hcd->self.busnum, portnum + 1, portsc, status);
1258
1279
1259
1280
put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1260
1281
/* if USB 3.1 extended port status return additional 4 bytes */
1261
-
if (wValue == 0x02) {
1282
+
if (wValue == HUB_EXT_PORT_STATUS) {
1262
1283
u32 port_li;
1263
1284
1264
1285
if (hcd->speed < HCD_USB31 || wLength != 8) {
···
1266
1289
break;
1267
1290
}
1268
1291
port_li = readl(&port->port_reg->portli);
1269
-
status = xhci_get_ext_port_status(temp, port_li);
1292
+
status = xhci_get_ext_port_status(portsc, port_li);
1270
1293
put_unaligned_le32(status, &buf[4]);
1271
1294
}
1272
1295
break;
1273
1296
case SetPortFeature:
1274
-
if (wValue == USB_PORT_FEAT_LINK_STATE)
1275
-
link_state = (wIndex & 0xff00) >> 3;
1276
-
if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1277
-
wake_mask = wIndex & 0xff00;
1278
-
if (wValue == USB_PORT_FEAT_TEST)
1279
-
test_mode = (wIndex & 0xff00) >> 8;
1280
-
/* The MSB of wIndex is the U1/U2 timeout */
1281
-
timeout = (wIndex & 0xff00) >> 8;
1282
-
1283
-
wIndex &= 0xff;
1284
-
if (!portnum1 || portnum1 > max_ports)
1297
+
portnum = (wIndex & 0xff) - 1;
1298
+
if (!in_range(portnum, 0, max_ports))
1285
1299
goto error;
1286
1300
1287
-
port = ports[portnum1 - 1];
1288
-
wIndex--;
1289
-
temp = xhci_portsc_readl(port);
1290
-
if (temp == ~(u32)0) {
1301
+
port = ports[portnum];
1302
+
portsc = xhci_portsc_readl(port);
1303
+
if (portsc == ~(u32)0) {
1291
1304
xhci_hc_died(xhci);
1292
1305
retval = -ENODEV;
1293
1306
break;
1294
1307
}
1295
-
temp = xhci_port_state_to_neutral(temp);
1308
+
portsc = xhci_port_state_to_neutral(portsc);
1296
1309
/* FIXME: What new port features do we need to support? */
1297
1310
switch (wValue) {
1298
1311
case USB_PORT_FEAT_SUSPEND:
1299
-
temp = xhci_portsc_readl(port);
1300
-
if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1312
+
portsc = xhci_portsc_readl(port);
1313
+
if ((portsc & PORT_PLS_MASK) != XDEV_U0) {
1301
1314
/* Resume the port to U0 first */
1302
1315
xhci_set_link_state(xhci, port, XDEV_U0);
1303
1316
spin_unlock_irqrestore(&xhci->lock, flags);
···
1298
1331
* a port unless the port reports that it is in the
1299
1332
* enabled (PED = ‘1’,PLS < ‘3’) state.
1300
1333
*/
1301
-
temp = xhci_portsc_readl(port);
1302
-
if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1303
-
|| (temp & PORT_PLS_MASK) >= XDEV_U3) {
1334
+
portsc = xhci_portsc_readl(port);
1335
+
if ((portsc & PORT_PE) == 0 || (portsc & PORT_RESET) ||
1336
+
(portsc & PORT_PLS_MASK) >= XDEV_U3) {
1304
1337
xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1305
-
hcd->self.busnum, portnum1);
1338
+
hcd->self.busnum, portnum + 1);
1306
1339
goto error;
1307
1340
}
1308
1341
···
1321
1354
msleep(10); /* wait device to enter */
1322
1355
spin_lock_irqsave(&xhci->lock, flags);
1323
1356
1324
-
temp = xhci_portsc_readl(port);
1325
-
bus_state->suspended_ports |= 1 << wIndex;
1357
+
portsc = xhci_portsc_readl(port);
1358
+
bus_state->suspended_ports |= 1 << portnum;
1326
1359
break;
1327
1360
case USB_PORT_FEAT_LINK_STATE:
1328
-
temp = xhci_portsc_readl(port);
1361
+
link_state = (wIndex & 0xff00) >> 3;
1362
+
portsc = xhci_portsc_readl(port);
1329
1363
/* Disable port */
1330
1364
if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1331
1365
xhci_dbg(xhci, "Disable port %d-%d\n",
1332
-
hcd->self.busnum, portnum1);
1333
-
temp = xhci_port_state_to_neutral(temp);
1366
+
hcd->self.busnum, portnum + 1);
1367
+
portsc = xhci_port_state_to_neutral(portsc);
1334
1368
/*
1335
1369
* Clear all change bits, so that we get a new
1336
1370
* connection event.
1337
1371
*/
1338
-
temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1339
-
PORT_OCC | PORT_RC | PORT_PLC |
1340
-
PORT_CEC;
1341
-
xhci_portsc_writel(port, temp | PORT_PE);
1342
-
temp = xhci_portsc_readl(port);
1372
+
portsc |= PORT_CSC | PORT_PEC | PORT_WRC |
1373
+
PORT_OCC | PORT_RC | PORT_PLC |
1374
+
PORT_CEC;
1375
+
xhci_portsc_writel(port, portsc | PORT_PE);
1376
+
portsc = xhci_portsc_readl(port);
1343
1377
break;
1344
1378
}
1345
1379
1346
1380
/* Put link in RxDetect (enable port) */
1347
1381
if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1348
1382
xhci_dbg(xhci, "Enable port %d-%d\n",
1349
-
hcd->self.busnum, portnum1);
1350
-
xhci_set_link_state(xhci, port, link_state);
1351
-
temp = xhci_portsc_readl(port);
1383
+
hcd->self.busnum, portnum + 1);
1384
+
xhci_set_link_state(xhci, port, XDEV_RXDETECT);
1385
+
portsc = xhci_portsc_readl(port);
1352
1386
break;
1353
1387
}
1354
1388
···
1373
1405
break;
1374
1406
}
1375
1407
1376
-
if ((temp & PORT_CONNECT)) {
1408
+
if ((portsc & PORT_CONNECT)) {
1377
1409
xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1378
1410
goto error;
1379
1411
}
1380
1412
1381
1413
xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n",
1382
-
hcd->self.busnum, portnum1);
1383
-
xhci_set_link_state(xhci, port, link_state);
1414
+
hcd->self.busnum, portnum + 1);
1415
+
xhci_set_link_state(xhci, port, XDEV_COMP_MODE);
1384
1416
1385
-
temp = xhci_portsc_readl(port);
1417
+
portsc = xhci_portsc_readl(port);
1386
1418
break;
1387
1419
}
1388
1420
/* Port must be enabled */
1389
-
if (!(temp & PORT_PE)) {
1421
+
if (!(portsc & PORT_PE)) {
1390
1422
retval = -ENODEV;
1391
1423
break;
1392
1424
}
1393
1425
/* Can't set port link state above '3' (U3) */
1394
1426
if (link_state > USB_SS_PORT_LS_U3) {
1395
1427
xhci_warn(xhci, "Cannot set port %d-%d link state %d\n",
1396
-
hcd->self.busnum, portnum1, link_state);
1428
+
hcd->self.busnum, portnum + 1, link_state);
1397
1429
goto error;
1398
1430
}
1399
1431
···
1405
1437
* completion
1406
1438
*/
1407
1439
if (link_state == USB_SS_PORT_LS_U0) {
1408
-
u32 pls = temp & PORT_PLS_MASK;
1440
+
u32 pls = portsc & PORT_PLS_MASK;
1409
1441
bool wait_u0 = false;
1410
1442
1411
1443
/* already in U0 */
···
1418
1450
reinit_completion(&port->u3exit_done);
1419
1451
}
1420
1452
if (pls <= XDEV_U3) /* U1, U2, U3 */
1421
-
xhci_set_link_state(xhci, port, USB_SS_PORT_LS_U0);
1453
+
xhci_set_link_state(xhci, port, XDEV_U0);
1422
1454
if (!wait_u0) {
1423
1455
if (pls > XDEV_U3)
1424
1456
goto error;
···
1428
1460
if (!wait_for_completion_timeout(&port->u3exit_done,
1429
1461
msecs_to_jiffies(500)))
1430
1462
xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n",
1431
-
hcd->self.busnum, portnum1);
1463
+
hcd->self.busnum, portnum + 1);
1432
1464
spin_lock_irqsave(&xhci->lock, flags);
1433
-
temp = xhci_portsc_readl(port);
1465
+
portsc = xhci_portsc_readl(port);
1434
1466
break;
1435
1467
}
1436
1468
···
1444
1476
xhci_stop_device(xhci, port->slot_id, 1);
1445
1477
spin_lock_irqsave(&xhci->lock, flags);
1446
1478
}
1447
-
xhci_set_link_state(xhci, port, USB_SS_PORT_LS_U3);
1479
+
xhci_set_link_state(xhci, port, XDEV_U3);
1448
1480
spin_unlock_irqrestore(&xhci->lock, flags);
1449
1481
while (retries--) {
1450
1482
usleep_range(4000, 8000);
1451
-
temp = xhci_portsc_readl(port);
1452
-
if ((temp & PORT_PLS_MASK) == XDEV_U3)
1483
+
portsc = xhci_portsc_readl(port);
1484
+
if ((portsc & PORT_PLS_MASK) == XDEV_U3)
1453
1485
break;
1454
1486
}
1455
1487
spin_lock_irqsave(&xhci->lock, flags);
1456
-
temp = xhci_portsc_readl(port);
1457
-
bus_state->suspended_ports |= 1 << wIndex;
1488
+
portsc = xhci_portsc_readl(port);
1489
+
bus_state->suspended_ports |= 1 << portnum;
1458
1490
}
1459
1491
break;
1460
1492
case USB_PORT_FEAT_POWER:
···
1467
1499
xhci_set_port_power(xhci, port, true, &flags);
1468
1500
break;
1469
1501
case USB_PORT_FEAT_RESET:
1470
-
temp = (temp | PORT_RESET);
1471
-
xhci_portsc_writel(port, temp);
1502
+
portsc |= PORT_RESET;
1503
+
xhci_portsc_writel(port, portsc);
1472
1504
1473
-
temp = xhci_portsc_readl(port);
1505
+
portsc = xhci_portsc_readl(port);
1474
1506
xhci_dbg(xhci, "set port reset, actual port %d-%d status = 0x%x\n",
1475
-
hcd->self.busnum, portnum1, temp);
1507
+
hcd->self.busnum, portnum + 1, portsc);
1476
1508
break;
1477
1509
case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1510
+
wake_mask = wIndex & 0xff00;
1478
1511
xhci_set_remote_wake_mask(xhci, port, wake_mask);
1479
-
temp = xhci_portsc_readl(port);
1512
+
portsc = xhci_portsc_readl(port);
1480
1513
xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status = 0x%x\n",
1481
-
hcd->self.busnum, portnum1, temp);
1514
+
hcd->self.busnum, portnum + 1, portsc);
1482
1515
break;
1483
1516
case USB_PORT_FEAT_BH_PORT_RESET:
1484
-
temp |= PORT_WR;
1485
-
xhci_portsc_writel(port, temp);
1486
-
temp = xhci_portsc_readl(port);
1517
+
portsc |= PORT_WR;
1518
+
xhci_portsc_writel(port, portsc);
1519
+
portsc = xhci_portsc_readl(port);
1487
1520
break;
1488
1521
case USB_PORT_FEAT_U1_TIMEOUT:
1489
1522
if (hcd->speed < HCD_USB3)
1490
1523
goto error;
1491
-
temp = readl(&port->port_reg->portpmsc);
1492
-
temp &= ~PORT_U1_TIMEOUT_MASK;
1493
-
temp |= PORT_U1_TIMEOUT(timeout);
1494
-
writel(temp, &port->port_reg->portpmsc);
1524
+
1525
+
timeout = (wIndex & 0xff00) >> 8;
1526
+
portpmsc = readl(&port->port_reg->portpmsc);
1527
+
portpmsc &= ~PORT_U1_TIMEOUT_MASK;
1528
+
portpmsc |= PORT_U1_TIMEOUT(timeout);
1529
+
writel(portpmsc, &port->port_reg->portpmsc);
1495
1530
break;
1496
1531
case USB_PORT_FEAT_U2_TIMEOUT:
1497
1532
if (hcd->speed < HCD_USB3)
1498
1533
goto error;
1499
-
temp = readl(&port->port_reg->portpmsc);
1500
-
temp &= ~PORT_U2_TIMEOUT_MASK;
1501
-
temp |= PORT_U2_TIMEOUT(timeout);
1502
-
writel(temp, &port->port_reg->portpmsc);
1534
+
1535
+
timeout = (wIndex & 0xff00) >> 8;
1536
+
portpmsc = readl(&port->port_reg->portpmsc);
1537
+
portpmsc &= ~PORT_U2_TIMEOUT_MASK;
1538
+
portpmsc |= PORT_U2_TIMEOUT(timeout);
1539
+
writel(portpmsc, &port->port_reg->portpmsc);
1503
1540
break;
1504
1541
case USB_PORT_FEAT_TEST:
1505
1542
/* 4.19.6 Port Test Modes (USB2 Test Mode) */
1506
1543
if (hcd->speed != HCD_USB2)
1507
1544
goto error;
1545
+
1546
+
test_mode = (wIndex & 0xff00) >> 8;
1508
1547
if (test_mode > USB_TEST_FORCE_ENABLE ||
1509
1548
test_mode < USB_TEST_J)
1510
1549
goto error;
1511
-
retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1512
-
&flags);
1550
+
retval = xhci_enter_test_mode(xhci, test_mode, portnum, &flags);
1513
1551
break;
1514
1552
default:
1515
1553
goto error;
1516
1554
}
1517
1555
/* unblock any posted writes */
1518
-
temp = xhci_portsc_readl(port);
1556
+
portsc = xhci_portsc_readl(port);
1519
1557
break;
1520
1558
case ClearPortFeature:
1521
-
if (!portnum1 || portnum1 > max_ports)
1559
+
portnum = (wIndex & 0xff) - 1;
1560
+
if (!in_range(portnum, 0, max_ports))
1522
1561
goto error;
1523
1562
1524
-
port = ports[portnum1 - 1];
1525
-
1526
-
wIndex--;
1527
-
temp = xhci_portsc_readl(port);
1528
-
if (temp == ~(u32)0) {
1563
+
port = ports[portnum];
1564
+
portsc = xhci_portsc_readl(port);
1565
+
if (portsc == ~(u32)0) {
1529
1566
xhci_hc_died(xhci);
1530
1567
retval = -ENODEV;
1531
1568
break;
1532
1569
}
1533
1570
/* FIXME: What new port features do we need to support? */
1534
-
temp = xhci_port_state_to_neutral(temp);
1571
+
portsc = xhci_port_state_to_neutral(portsc);
1535
1572
switch (wValue) {
1536
1573
case USB_PORT_FEAT_SUSPEND:
1537
-
temp = xhci_portsc_readl(port);
1574
+
portsc = xhci_portsc_readl(port);
1538
1575
xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1539
-
xhci_dbg(xhci, "PORTSC %04x\n", temp);
1540
-
if (temp & PORT_RESET)
1576
+
xhci_dbg(xhci, "PORTSC %04x\n", portsc);
1577
+
if (portsc & PORT_RESET)
1541
1578
goto error;
1542
-
if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1543
-
if ((temp & PORT_PE) == 0)
1579
+
if ((portsc & PORT_PLS_MASK) == XDEV_U3) {
1580
+
if ((portsc & PORT_PE) == 0)
1544
1581
goto error;
1545
1582
1546
-
set_bit(wIndex, &bus_state->resuming_ports);
1547
-
usb_hcd_start_port_resume(&hcd->self, wIndex);
1583
+
set_bit(portnum, &bus_state->resuming_ports);
1584
+
usb_hcd_start_port_resume(&hcd->self, portnum);
1548
1585
xhci_set_link_state(xhci, port, XDEV_RESUME);
1549
1586
spin_unlock_irqrestore(&xhci->lock, flags);
1550
1587
msleep(USB_RESUME_TIMEOUT);
1551
1588
spin_lock_irqsave(&xhci->lock, flags);
1552
1589
xhci_set_link_state(xhci, port, XDEV_U0);
1553
-
clear_bit(wIndex, &bus_state->resuming_ports);
1554
-
usb_hcd_end_port_resume(&hcd->self, wIndex);
1590
+
clear_bit(portnum, &bus_state->resuming_ports);
1591
+
usb_hcd_end_port_resume(&hcd->self, portnum);
1555
1592
}
1556
-
bus_state->port_c_suspend |= 1 << wIndex;
1593
+
bus_state->port_c_suspend |= 1 << portnum;
1557
1594
1558
1595
if (!port->slot_id) {
1559
1596
xhci_dbg(xhci, "slot_id is zero\n");
···
1567
1594
xhci_ring_device(xhci, port->slot_id);
1568
1595
break;
1569
1596
case USB_PORT_FEAT_C_SUSPEND:
1570
-
bus_state->port_c_suspend &= ~(1 << wIndex);
1597
+
bus_state->port_c_suspend &= ~(1 << portnum);
1571
1598
fallthrough;
1572
1599
case USB_PORT_FEAT_C_RESET:
1573
1600
case USB_PORT_FEAT_C_BH_PORT_RESET:
···
1576
1603
case USB_PORT_FEAT_C_ENABLE:
1577
1604
case USB_PORT_FEAT_C_PORT_LINK_STATE:
1578
1605
case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1579
-
xhci_clear_port_change_bit(xhci, wValue, wIndex, port, temp);
1606
+
xhci_clear_port_change_bit(xhci, wValue, port, portsc);
1580
1607
break;
1581
1608
case USB_PORT_FEAT_ENABLE:
1582
1609
xhci_disable_port(xhci, port);
+68
-65
drivers/usb/host/xhci-mem.c
+68
-65
drivers/usb/host/xhci-mem.c
···
129
129
ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |= cpu_to_le32(LINK_TOGGLE);
130
130
}
131
131
132
+
void xhci_ring_init(struct xhci_hcd *xhci, struct xhci_ring *ring)
133
+
{
134
+
xhci_initialize_ring_segments(xhci, ring);
135
+
xhci_initialize_ring_info(ring);
136
+
trace_xhci_ring_alloc(ring);
137
+
}
138
+
132
139
/*
133
140
* Link the src ring segments to the dst ring.
134
141
* Set Toggle Cycle for the new ring if needed.
···
396
389
if (ret)
397
390
goto fail;
398
391
399
-
xhci_initialize_ring_segments(xhci, ring);
400
-
xhci_initialize_ring_info(ring);
401
-
trace_xhci_ring_alloc(ring);
402
392
return ring;
403
393
404
394
fail:
···
672
668
cur_ring = stream_info->stream_rings[cur_stream];
673
669
if (!cur_ring)
674
670
goto cleanup_rings;
671
+
672
+
xhci_ring_init(xhci, cur_ring);
675
673
cur_ring->stream_id = cur_stream;
676
674
cur_ring->trb_address_map = &stream_info->trb_address_map;
677
675
/* Set deq ptr, cycle bit, and stream context type */
···
936
930
* that tt_info, then free the child first. Recursive.
937
931
* We can't rely on udev at this point to find child-parent relationships.
938
932
*/
939
-
static void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id)
933
+
void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id)
940
934
{
941
935
struct xhci_virt_device *vdev;
942
936
struct list_head *tt_list_head;
···
994
988
if (!dev->out_ctx)
995
989
goto fail;
996
990
997
-
xhci_dbg(xhci, "Slot %d output ctx = 0x%pad (dma)\n", slot_id, &dev->out_ctx->dma);
991
+
xhci_dbg(xhci, "Slot %d output ctx = %pad (dma)\n", slot_id, &dev->out_ctx->dma);
998
992
999
993
/* Allocate the (input) device context for address device command */
1000
994
dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
1001
995
if (!dev->in_ctx)
1002
996
goto fail;
1003
997
1004
-
xhci_dbg(xhci, "Slot %d input ctx = 0x%pad (dma)\n", slot_id, &dev->in_ctx->dma);
998
+
xhci_dbg(xhci, "Slot %d input ctx = %pad (dma)\n", slot_id, &dev->in_ctx->dma);
1005
999
1006
1000
/* Initialize the cancellation and bandwidth list for each ep */
1007
1001
for (i = 0; i < 31; i++) {
···
1016
1010
dev->eps[0].ring = xhci_ring_alloc(xhci, 2, TYPE_CTRL, 0, flags);
1017
1011
if (!dev->eps[0].ring)
1018
1012
goto fail;
1013
+
1014
+
xhci_ring_init(xhci, dev->eps[0].ring);
1019
1015
1020
1016
dev->udev = udev;
1021
1017
···
1500
1492
1501
1493
virt_dev->eps[ep_index].skip = false;
1502
1494
ep_ring = virt_dev->eps[ep_index].new_ring;
1495
+
xhci_ring_init(xhci, ep_ring);
1503
1496
1504
1497
/* Fill the endpoint context */
1505
1498
ep_ctx->ep_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
···
1904
1895
}
1905
1896
EXPORT_SYMBOL_GPL(xhci_remove_secondary_interrupter);
1906
1897
1898
+
/* Cleanup roothub bandwidth data */
1899
+
void xhci_rh_bw_cleanup(struct xhci_hcd *xhci)
1900
+
{
1901
+
struct xhci_root_port_bw_info *rh_bw;
1902
+
struct xhci_tt_bw_info *tt_info, *tt_next;
1903
+
struct list_head *eps, *ep, *ep_next;
1904
+
1905
+
for (int i = 0; i < xhci->max_ports; i++) {
1906
+
rh_bw = &xhci->rh_bw[i];
1907
+
1908
+
/* Clear and free all TT bandwidth entries */
1909
+
list_for_each_entry_safe(tt_info, tt_next, &rh_bw->tts, tt_list) {
1910
+
list_del(&tt_info->tt_list);
1911
+
kfree(tt_info);
1912
+
}
1913
+
1914
+
/* Clear per-interval endpoint lists */
1915
+
for (int j = 0; j < XHCI_MAX_INTERVAL; j++) {
1916
+
eps = &rh_bw->bw_table.interval_bw[j].endpoints;
1917
+
1918
+
list_for_each_safe(ep, ep_next, eps)
1919
+
list_del_init(ep);
1920
+
}
1921
+
}
1922
+
}
1923
+
1907
1924
void xhci_mem_cleanup(struct xhci_hcd *xhci)
1908
1925
{
1909
1926
struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1910
-
int i, j;
1927
+
int i;
1911
1928
1912
1929
cancel_delayed_work_sync(&xhci->cmd_timer);
1913
1930
···
1951
1916
xhci->cmd_ring = NULL;
1952
1917
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring");
1953
1918
xhci_cleanup_command_queue(xhci);
1954
-
1955
-
for (i = 0; i < xhci->max_ports && xhci->rh_bw; i++) {
1956
-
struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1957
-
for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1958
-
struct list_head *ep = &bwt->interval_bw[j].endpoints;
1959
-
while (!list_empty(ep))
1960
-
list_del_init(ep->next);
1961
-
}
1962
-
}
1963
1919
1964
1920
for (i = xhci->max_slots; i > 0; i--)
1965
1921
xhci_free_virt_devices_depth_first(xhci, i);
···
1985
1959
1986
1960
scratchpad_free(xhci);
1987
1961
1988
-
if (!xhci->rh_bw)
1989
-
goto no_bw;
1962
+
if (xhci->rh_bw)
1963
+
xhci_rh_bw_cleanup(xhci);
1990
1964
1991
-
for (i = 0; i < xhci->max_ports; i++) {
1992
-
struct xhci_tt_bw_info *tt, *n;
1993
-
list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1994
-
list_del(&tt->tt_list);
1995
-
kfree(tt);
1996
-
}
1997
-
}
1998
-
1999
-
no_bw:
2000
1965
xhci->cmd_ring_reserved_trbs = 0;
2001
1966
xhci->usb2_rhub.num_ports = 0;
2002
1967
xhci->usb3_rhub.num_ports = 0;
···
2009
1992
xhci->port_caps = NULL;
2010
1993
xhci->interrupters = NULL;
2011
1994
2012
-
xhci->page_size = 0;
2013
1995
xhci->usb2_rhub.bus_state.bus_suspended = 0;
2014
1996
xhci->usb3_rhub.bus_state.bus_suspended = 0;
2015
1997
}
···
2165
2149
/* FIXME: Should we disable ports not in the Extended Capabilities? */
2166
2150
}
2167
2151
2168
-
static void xhci_create_rhub_port_array(struct xhci_hcd *xhci,
2169
-
struct xhci_hub *rhub, gfp_t flags)
2152
+
static void xhci_create_rhub_port_array(struct xhci_hcd *xhci, struct xhci_hub *rhub,
2153
+
unsigned int max_ports, gfp_t flags)
2170
2154
{
2171
2155
int port_index = 0;
2172
2156
int i;
2173
2157
struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2174
2158
2175
-
if (!rhub->num_ports)
2159
+
if (!rhub->num_ports) {
2160
+
xhci_info(xhci, "USB%u root hub has no ports\n", rhub->maj_rev);
2176
2161
return;
2162
+
}
2163
+
2164
+
/*
2165
+
* Place limits on the number of roothub ports so that the hub
2166
+
* descriptors aren't longer than the USB core will allocate.
2167
+
*/
2168
+
if (rhub->num_ports > max_ports) {
2169
+
xhci->usb3_rhub.num_ports = max_ports;
2170
+
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Limiting USB%u root hub ports to %u",
2171
+
rhub->maj_rev, max_ports);
2172
+
}
2173
+
2177
2174
rhub->ports = kcalloc_node(rhub->num_ports, sizeof(*rhub->ports),
2178
2175
flags, dev_to_node(dev));
2179
2176
if (!rhub->ports)
···
2282
2253
"Found %u USB 2.0 ports and %u USB 3.0 ports.",
2283
2254
xhci->usb2_rhub.num_ports, xhci->usb3_rhub.num_ports);
2284
2255
2285
-
/* Place limits on the number of roothub ports so that the hub
2286
-
* descriptors aren't longer than the USB core will allocate.
2287
-
*/
2288
-
if (xhci->usb3_rhub.num_ports > USB_SS_MAXPORTS) {
2289
-
xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2290
-
"Limiting USB 3.0 roothub ports to %u.",
2291
-
USB_SS_MAXPORTS);
2292
-
xhci->usb3_rhub.num_ports = USB_SS_MAXPORTS;
2293
-
}
2294
-
if (xhci->usb2_rhub.num_ports > USB_MAXCHILDREN) {
2295
-
xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2296
-
"Limiting USB 2.0 roothub ports to %u.",
2297
-
USB_MAXCHILDREN);
2298
-
xhci->usb2_rhub.num_ports = USB_MAXCHILDREN;
2299
-
}
2300
-
2301
-
if (!xhci->usb2_rhub.num_ports)
2302
-
xhci_info(xhci, "USB2 root hub has no ports\n");
2303
-
2304
-
if (!xhci->usb3_rhub.num_ports)
2305
-
xhci_info(xhci, "USB3 root hub has no ports\n");
2306
-
2307
-
xhci_create_rhub_port_array(xhci, &xhci->usb2_rhub, flags);
2308
-
xhci_create_rhub_port_array(xhci, &xhci->usb3_rhub, flags);
2256
+
xhci_create_rhub_port_array(xhci, &xhci->usb2_rhub, USB_MAXCHILDREN, flags);
2257
+
xhci_create_rhub_port_array(xhci, &xhci->usb3_rhub, USB_SS_MAXPORTS, flags);
2309
2258
2310
2259
return 0;
2311
2260
}
···
2369
2362
if (!ir)
2370
2363
return NULL;
2371
2364
2365
+
xhci_ring_init(xhci, ir->event_ring);
2366
+
2372
2367
spin_lock_irq(&xhci->lock);
2373
2368
if (!intr_num) {
2374
2369
/* Find available secondary interrupter, interrupter 0 is reserved for primary */
···
2412
2403
struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2413
2404
dma_addr_t dma;
2414
2405
2406
+
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Starting %s", __func__);
2407
+
2415
2408
/*
2416
2409
* xHCI section 5.4.6 - Device Context array must be
2417
2410
* "physically contiguous and 64-byte (cache line) aligned".
···
2424
2413
2425
2414
xhci->dcbaa->dma = dma;
2426
2415
xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2427
-
"Device context base array address = 0x%pad (DMA), %p (virt)",
2416
+
"Device context base array address = %pad (DMA), %p (virt)",
2428
2417
&xhci->dcbaa->dma, xhci->dcbaa);
2429
2418
2430
2419
/*
···
2485
2474
goto fail;
2486
2475
2487
2476
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Allocated command ring at %p", xhci->cmd_ring);
2488
-
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%pad",
2489
-
&xhci->cmd_ring->first_seg->dma);
2490
-
2491
-
/*
2492
-
* Reserve one command ring TRB for disabling LPM.
2493
-
* Since the USB core grabs the shared usb_bus bandwidth mutex before
2494
-
* disabling LPM, we only need to reserve one TRB for all devices.
2495
-
*/
2496
-
xhci->cmd_ring_reserved_trbs++;
2497
2477
2498
2478
/* Allocate and set up primary interrupter 0 with an event ring. */
2499
2479
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Allocating primary event ring");
···
2503
2501
if (xhci_setup_port_arrays(xhci, flags))
2504
2502
goto fail;
2505
2503
2504
+
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished %s", __func__);
2506
2505
return 0;
2507
2506
2508
2507
fail:
+1
-1
drivers/usb/host/xhci-mvebu.c
+1
-1
drivers/usb/host/xhci-mvebu.c
+4
-5
drivers/usb/host/xhci-ring.c
+4
-5
drivers/usb/host/xhci-ring.c
···
755
755
}
756
756
757
757
if ((ep->ep_state & SET_DEQ_PENDING)) {
758
-
xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
758
+
xhci_warn(xhci, "Set TR Deq already pending, don't submit for %pad\n",
759
759
&addr);
760
760
return -EBUSY;
761
761
}
···
763
763
/* This function gets called from contexts where it cannot sleep */
764
764
cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
765
765
if (!cmd) {
766
-
xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
766
+
xhci_warn(xhci, "Can't alloc Set TR Deq cmd %pad\n", &addr);
767
767
return -ENOMEM;
768
768
}
769
769
···
3208
3208
/*
3209
3209
* Clear the op reg interrupt status first,
3210
3210
* so we can receive interrupts from other MSI-X interrupters.
3211
-
* Write 1 to clear the interrupt status.
3211
+
* USBSTS bits are write 1 to clear.
3212
3212
*/
3213
-
status |= STS_EINT;
3214
-
writel(status, &xhci->op_regs->status);
3213
+
writel(STS_EINT, &xhci->op_regs->status);
3215
3214
3216
3215
/* This is the handler of the primary interrupter */
3217
3216
xhci_handle_events(xhci, xhci->interrupters[0], false);
+8
-4
drivers/usb/host/xhci-tegra.c
+8
-4
drivers/usb/host/xhci-tegra.c
···
1357
1357
1358
1358
dev_dbg(tegra->dev, "host mode %s\n", str_on_off(tegra->host_mode));
1359
1359
1360
-
mutex_lock(&tegra->lock);
1361
-
1362
1360
if (tegra->host_mode)
1363
1361
phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_HOST);
1364
1362
else
1365
1363
phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_NONE);
1366
-
1367
-
mutex_unlock(&tegra->lock);
1368
1364
1369
1365
tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion(tegra->padctl,
1370
1366
tegra->otg_usb2_port);
···
2562
2566
.smi_intr = XUSB_CFG_ARU_SMI_INTR,
2563
2567
},
2564
2568
};
2569
+
#if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) || IS_ENABLED(CONFIG_ARCH_TEGRA_132_SOC)
2565
2570
MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
2571
+
#endif
2566
2572
2567
2573
static const char * const tegra210_supply_names[] = {
2568
2574
"dvddio-pex",
···
2602
2604
.smi_intr = XUSB_CFG_ARU_SMI_INTR,
2603
2605
},
2604
2606
};
2607
+
#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
2605
2608
MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
2609
+
#endif
2606
2610
2607
2611
static const char * const tegra186_supply_names[] = {
2608
2612
};
2613
+
#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
2609
2614
MODULE_FIRMWARE("nvidia/tegra186/xusb.bin");
2615
+
#endif
2610
2616
2611
2617
static const struct tegra_xusb_phy_type tegra186_phy_types[] = {
2612
2618
{ .name = "usb3", .num = 3, },
···
2683
2681
},
2684
2682
.lpm_support = true,
2685
2683
};
2684
+
#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
2686
2685
MODULE_FIRMWARE("nvidia/tegra194/xusb.bin");
2686
+
#endif
2687
2687
2688
2688
static const struct tegra_xusb_soc_ops tegra234_ops = {
2689
2689
.mbox_reg_readl = &bar2_readl,
+123
-108
drivers/usb/host/xhci.c
+123
-108
drivers/usb/host/xhci.c
···
536
536
writel(dev_notf, &xhci->op_regs->dev_notification);
537
537
}
538
538
539
-
/*
540
-
* Initialize memory for HCD and xHC (one-time init).
541
-
*
542
-
* Program the PAGESIZE register, initialize the device context array, create
543
-
* device contexts (?), set up a command ring segment (or two?), create event
544
-
* ring (one for now).
545
-
*/
546
-
static int xhci_init(struct usb_hcd *hcd)
539
+
/* Setup basic xHCI registers */
540
+
static void xhci_init(struct usb_hcd *hcd)
547
541
{
548
542
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
549
-
int retval;
550
543
551
544
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Starting %s", __func__);
552
-
spin_lock_init(&xhci->lock);
553
-
554
-
INIT_LIST_HEAD(&xhci->cmd_list);
555
-
INIT_DELAYED_WORK(&xhci->cmd_timer, xhci_handle_command_timeout);
556
-
init_completion(&xhci->cmd_ring_stop_completion);
557
-
xhci_hcd_page_size(xhci);
558
-
memset(xhci->devs, 0, MAX_HC_SLOTS * sizeof(*xhci->devs));
559
-
560
-
retval = xhci_mem_init(xhci, GFP_KERNEL);
561
-
if (retval)
562
-
return retval;
563
545
564
546
/* Set the Number of Device Slots Enabled to the maximum supported value */
565
547
xhci_enable_max_dev_slots(xhci);
566
548
549
+
/* Initialize the Command ring */
550
+
xhci_ring_init(xhci, xhci->cmd_ring);
551
+
/*
552
+
* Reserve one command ring TRB for disabling LPM.
553
+
* Since the USB core grabs the shared usb_bus bandwidth mutex before
554
+
* disabling LPM, we only need to reserve one TRB for all devices.
555
+
*/
556
+
xhci->cmd_ring_reserved_trbs = 1;
567
557
/* Set the address in the Command Ring Control register */
568
558
xhci_set_cmd_ring_deq(xhci);
569
559
···
567
577
xhci_set_dev_notifications(xhci);
568
578
569
579
/* Initialize the Primary interrupter */
580
+
xhci_ring_init(xhci, xhci->interrupters[0]->event_ring);
570
581
xhci_add_interrupter(xhci, 0);
571
582
xhci->interrupters[0]->isoc_bei_interval = AVOID_BEI_INTERVAL_MAX;
572
583
···
578
587
}
579
588
580
589
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished %s", __func__);
581
-
return 0;
582
590
}
583
591
584
592
/*-------------------------------------------------------------------------*/
···
957
967
*/
958
968
int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
959
969
{
960
-
int rc = 0;
970
+
int err;
961
971
unsigned int delay = XHCI_MAX_HALT_USEC * 2;
962
972
struct usb_hcd *hcd = xhci_to_hcd(xhci);
963
973
u32 command;
964
-
u32 res;
974
+
u32 usbsts;
965
975
966
976
if (!hcd->state)
967
977
return 0;
···
1007
1017
/* Some chips from Fresco Logic need an extraordinary delay */
1008
1018
delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1009
1019
1010
-
if (xhci_handshake(&xhci->op_regs->status,
1011
-
STS_HALT, STS_HALT, delay)) {
1012
-
xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1013
-
spin_unlock_irq(&xhci->lock);
1014
-
return -ETIMEDOUT;
1020
+
err = xhci_handshake(&xhci->op_regs->status, STS_HALT, STS_HALT, delay);
1021
+
if (err) {
1022
+
xhci_warn(xhci, "Clearing Run/Stop bit failed %d\n", err);
1023
+
goto handshake_error;
1015
1024
}
1016
1025
xhci_clear_command_ring(xhci);
1017
1026
···
1021
1032
command = readl(&xhci->op_regs->command);
1022
1033
command |= CMD_CSS;
1023
1034
writel(command, &xhci->op_regs->command);
1035
+
1036
+
err = xhci_handshake(&xhci->op_regs->status, STS_SAVE, 0, 20 * USEC_PER_MSEC);
1037
+
usbsts = readl(&xhci->op_regs->status);
1024
1038
xhci->broken_suspend = 0;
1025
-
if (xhci_handshake(&xhci->op_regs->status,
1026
-
STS_SAVE, 0, 20 * 1000)) {
1027
-
/*
1028
-
* AMD SNPS xHC 3.0 occasionally does not clear the
1029
-
* SSS bit of USBSTS and when driver tries to poll
1030
-
* to see if the xHC clears BIT(8) which never happens
1031
-
* and driver assumes that controller is not responding
1032
-
* and times out. To workaround this, its good to check
1033
-
* if SRE and HCE bits are not set (as per xhci
1034
-
* Section 5.4.2) and bypass the timeout.
1035
-
*/
1036
-
res = readl(&xhci->op_regs->status);
1037
-
if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1038
-
(((res & STS_SRE) == 0) &&
1039
-
((res & STS_HCE) == 0))) {
1040
-
xhci->broken_suspend = 1;
1041
-
} else {
1042
-
xhci_warn(xhci, "WARN: xHC save state timeout\n");
1043
-
spin_unlock_irq(&xhci->lock);
1044
-
return -ETIMEDOUT;
1039
+
if (err) {
1040
+
/*
1041
+
* AMD SNPS xHC 3.0 occasionally does not clear the
1042
+
* SSS bit of USBSTS and when driver tries to poll
1043
+
* to see if the xHC clears BIT(8) which never happens
1044
+
* and driver assumes that controller is not responding
1045
+
* and times out. To workaround this, its good to check
1046
+
* if SRE and HCE bits are not set (as per xhci
1047
+
* Section 5.4.2) and bypass the timeout.
1048
+
*/
1049
+
if (!(xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND)) {
1050
+
xhci_warn(xhci, "Controller Save State failed %d\n", err);
1051
+
goto handshake_error;
1045
1052
}
1053
+
1054
+
if (usbsts & (STS_SRE | STS_HCE)) {
1055
+
xhci_warn(xhci, "Controller Save State failed, USBSTS 0x%08x\n", usbsts);
1056
+
goto handshake_error;
1057
+
}
1058
+
1059
+
xhci_dbg(xhci, "SNPS broken suspend, save state unreliable\n");
1060
+
xhci->broken_suspend = 1;
1061
+
} else if (usbsts & STS_SRE) {
1062
+
xhci_warn(xhci, "Suspend Save Error (SRE), USBSTS 0x%08x\n", usbsts);
1046
1063
}
1047
1064
spin_unlock_irq(&xhci->lock);
1048
1065
···
1064
1069
__func__);
1065
1070
}
1066
1071
1067
-
return rc;
1072
+
return 0;
1073
+
1074
+
handshake_error:
1075
+
spin_unlock_irq(&xhci->lock);
1076
+
return -ETIMEDOUT;
1068
1077
}
1069
1078
EXPORT_SYMBOL_GPL(xhci_suspend);
1070
1079
···
1082
1083
{
1083
1084
u32 command, temp = 0;
1084
1085
struct usb_hcd *hcd = xhci_to_hcd(xhci);
1086
+
struct xhci_segment *seg;
1085
1087
int retval = 0;
1086
-
bool comp_timer_running = false;
1087
1088
bool pending_portevent = false;
1088
1089
bool suspended_usb3_devs = false;
1090
+
bool reset_registers = false;
1089
1091
1090
1092
if (!hcd->state)
1091
1093
return 0;
···
1105
1105
1106
1106
spin_lock_irq(&xhci->lock);
1107
1107
1108
-
if (xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1109
-
power_lost = true;
1110
-
1111
-
if (!power_lost) {
1108
+
if (power_lost || xhci->broken_suspend || xhci->quirks & XHCI_RESET_ON_RESUME) {
1109
+
xhci_dbg(xhci, "HC state lost, performing host controller reset\n");
1110
+
reset_registers = true;
1111
+
} else {
1112
+
xhci_dbg(xhci, "HC state intact, continuing without reset\n");
1112
1113
/*
1113
1114
* Some controllers might lose power during suspend, so wait
1114
1115
* for controller not ready bit to clear, just as in xHC init.
···
1142
1141
spin_unlock_irq(&xhci->lock);
1143
1142
return -ETIMEDOUT;
1144
1143
}
1145
-
}
1146
1144
1147
-
temp = readl(&xhci->op_regs->status);
1148
-
1149
-
/* re-initialize the HC on Restore Error, or Host Controller Error */
1150
-
if ((temp & (STS_SRE | STS_HCE)) &&
1151
-
!(xhci->xhc_state & XHCI_STATE_REMOVING)) {
1152
-
if (!power_lost)
1145
+
/* re-initialize the HC on Restore Error, or Host Controller Error */
1146
+
temp = readl(&xhci->op_regs->status);
1147
+
if ((temp & (STS_SRE | STS_HCE)) && !(xhci->xhc_state & XHCI_STATE_REMOVING)) {
1153
1148
xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1154
-
power_lost = true;
1149
+
reset_registers = true;
1150
+
}
1155
1151
}
1156
1152
1157
-
if (power_lost) {
1153
+
if (reset_registers) {
1158
1154
if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1159
1155
!(xhci_all_ports_seen_u0(xhci))) {
1160
1156
timer_delete_sync(&xhci->comp_mode_recovery_timer);
···
1175
1177
if (retval)
1176
1178
return retval;
1177
1179
1178
-
xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1179
-
temp = readl(&xhci->op_regs->status);
1180
-
writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1181
-
xhci_disable_interrupter(xhci, xhci->interrupters[0]);
1180
+
cancel_delayed_work_sync(&xhci->cmd_timer);
1182
1181
1183
-
xhci_dbg(xhci, "cleaning up memory\n");
1184
-
xhci_mem_cleanup(xhci);
1182
+
/* Delete all remaining commands */
1183
+
xhci_cleanup_command_queue(xhci);
1184
+
1185
+
/* Clear data which is re-initilized during runtime */
1186
+
xhci_for_each_ring_seg(xhci->interrupters[0]->event_ring->first_seg, seg)
1187
+
memset(seg->trbs, 0, sizeof(union xhci_trb) * TRBS_PER_SEGMENT);
1188
+
1189
+
for (int i = xhci->max_slots; i > 0; i--)
1190
+
xhci_free_virt_devices_depth_first(xhci, i);
1191
+
1192
+
xhci_rh_bw_cleanup(xhci);
1193
+
1194
+
xhci->cmd_ring_reserved_trbs = 0;
1195
+
xhci_for_each_ring_seg(xhci->cmd_ring->first_seg, seg)
1196
+
memset(seg->trbs, 0, sizeof(union xhci_trb) * TRBS_PER_SEGMENT);
1197
+
1185
1198
xhci_debugfs_exit(xhci);
1186
-
xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1187
-
readl(&xhci->op_regs->status));
1188
1199
1189
-
/* USB core calls the PCI reinit and start functions twice:
1200
+
xhci_init(hcd);
1201
+
1202
+
/*
1203
+
* USB core calls the PCI reinit and start functions twice:
1190
1204
* first with the primary HCD, and then with the secondary HCD.
1191
1205
* If we don't do the same, the host will never be started.
1192
1206
*/
1193
-
xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1194
-
retval = xhci_init(hcd);
1195
-
if (retval)
1196
-
return retval;
1197
-
comp_timer_running = true;
1198
-
1199
1207
xhci_dbg(xhci, "Start the primary HCD\n");
1200
1208
retval = xhci_run(hcd);
1201
1209
if (!retval && xhci->shared_hcd) {
···
1245
1241
1246
1242
xhci_dbc_resume(xhci);
1247
1243
1248
-
if (retval == 0) {
1249
-
/*
1250
-
* Resume roothubs only if there are pending events.
1251
-
* USB 3 devices resend U3 LFPS wake after a 100ms delay if
1252
-
* the first wake signalling failed, give it that chance if
1253
-
* there are suspended USB 3 devices.
1254
-
*/
1255
-
if (xhci->usb3_rhub.bus_state.suspended_ports ||
1256
-
xhci->usb3_rhub.bus_state.bus_suspended)
1257
-
suspended_usb3_devs = true;
1244
+
/*
1245
+
* Resume roothubs only if there are pending events.
1246
+
* USB 3 devices resend U3 LFPS wake after a 100ms delay if
1247
+
* the first wake signalling failed, give it that chance if
1248
+
* there are suspended USB 3 devices.
1249
+
*/
1250
+
if (xhci->usb3_rhub.bus_state.suspended_ports || xhci->usb3_rhub.bus_state.bus_suspended)
1251
+
suspended_usb3_devs = true;
1258
1252
1253
+
pending_portevent = xhci_pending_portevent(xhci);
1254
+
if (suspended_usb3_devs && !pending_portevent && is_auto_resume) {
1255
+
msleep(120);
1259
1256
pending_portevent = xhci_pending_portevent(xhci);
1260
-
1261
-
if (suspended_usb3_devs && !pending_portevent && is_auto_resume) {
1262
-
msleep(120);
1263
-
pending_portevent = xhci_pending_portevent(xhci);
1264
-
}
1265
-
1266
-
if (pending_portevent) {
1267
-
if (xhci->shared_hcd)
1268
-
usb_hcd_resume_root_hub(xhci->shared_hcd);
1269
-
usb_hcd_resume_root_hub(hcd);
1270
-
}
1271
1257
}
1272
-
done:
1258
+
1259
+
if (pending_portevent) {
1260
+
if (xhci->shared_hcd)
1261
+
usb_hcd_resume_root_hub(xhci->shared_hcd);
1262
+
usb_hcd_resume_root_hub(hcd);
1263
+
}
1264
+
1273
1265
/*
1274
1266
* If system is subject to the Quirk, Compliance Mode Timer needs to
1275
1267
* be re-initialized Always after a system resume. Ports are subject
1276
1268
* to suffer the Compliance Mode issue again. It doesn't matter if
1277
1269
* ports have entered previously to U0 before system's suspension.
1278
1270
*/
1279
-
if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1271
+
if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
1280
1272
compliance_mode_recovery_timer_init(xhci);
1281
-
1273
+
done:
1282
1274
if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1283
1275
usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1284
1276
···
3201
3201
}
3202
3202
EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3203
3203
3204
-
/* Get the available bandwidth of the ports under the xhci roothub */
3204
+
/*
3205
+
* Get the available bandwidth of the ports under the xhci roothub.
3206
+
* EIO means the command failed: command not implemented or unsupported
3207
+
* speed (TRB Error), some ASMedia complete with Parameter Error when
3208
+
* querying the root hub (slot_id = 0), or other error or timeout.
3209
+
*/
3205
3210
int xhci_get_port_bandwidth(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx,
3206
3211
u8 dev_speed)
3207
3212
{
···
3235
3230
spin_unlock_irqrestore(&xhci->lock, flags);
3236
3231
3237
3232
wait_for_completion(cmd->completion);
3233
+
if (cmd->status != COMP_SUCCESS)
3234
+
ret = -EIO;
3238
3235
err_out:
3239
3236
kfree(cmd->completion);
3240
3237
kfree(cmd);
···
3292
3285
xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3293
3286
ep->ep_state);
3294
3287
done:
3295
-
host_ep->hcpriv = NULL;
3296
3288
spin_unlock_irqrestore(&xhci->lock, flags);
3297
3289
}
3298
3290
···
5527
5521
dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5528
5522
}
5529
5523
5530
-
xhci_dbg(xhci, "Calling HCD init\n");
5531
-
/* Initialize HCD and host controller data structures. */
5532
-
retval = xhci_init(hcd);
5524
+
spin_lock_init(&xhci->lock);
5525
+
INIT_LIST_HEAD(&xhci->cmd_list);
5526
+
INIT_DELAYED_WORK(&xhci->cmd_timer, xhci_handle_command_timeout);
5527
+
init_completion(&xhci->cmd_ring_stop_completion);
5528
+
xhci_hcd_page_size(xhci);
5529
+
5530
+
memset(xhci->devs, 0, MAX_HC_SLOTS * sizeof(*xhci->devs));
5531
+
5532
+
/* Allocate xHCI data structures */
5533
+
retval = xhci_mem_init(xhci, GFP_KERNEL);
5533
5534
if (retval)
5534
5535
return retval;
5535
-
xhci_dbg(xhci, "Called HCD init\n");
5536
+
5537
+
/* Initialize HCD and host controller data structures */
5538
+
xhci_init(hcd);
5536
5539
5537
5540
if (xhci_hcd_is_usb3(hcd))
5538
5541
xhci_hcd_init_usb3_data(xhci, hcd);
+64
-60
drivers/usb/host/xhci.h
+64
-60
drivers/usb/host/xhci.h
···
12
12
#ifndef __LINUX_XHCI_HCD_H
13
13
#define __LINUX_XHCI_HCD_H
14
14
15
+
#include <linux/bits.h>
15
16
#include <linux/usb.h>
16
17
#include <linux/timer.h>
17
18
#include <linux/kernel.h>
···
126
125
* PCI config regs). HC does NOT drive a USB reset on the downstream ports.
127
126
* The xHCI driver must reinitialize the xHC after setting this bit.
128
127
*/
129
-
#define CMD_RESET (1 << 1)
128
+
#define CMD_RESET BIT(1)
130
129
/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
131
130
#define CMD_EIE XHCI_CMD_EIE
132
131
/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
133
132
#define CMD_HSEIE XHCI_CMD_HSEIE
134
133
/* bits 4:6 are reserved (and should be preserved on writes). */
135
134
/* light reset (port status stays unchanged) - reset completed when this is 0 */
136
-
#define CMD_LRESET (1 << 7)
135
+
#define CMD_LRESET BIT(7)
137
136
/* host controller save/restore state. */
138
-
#define CMD_CSS (1 << 8)
139
-
#define CMD_CRS (1 << 9)
137
+
#define CMD_CSS BIT(8)
138
+
#define CMD_CRS BIT(9)
140
139
/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
141
140
#define CMD_EWE XHCI_CMD_EWE
142
141
/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
···
144
143
* '0' means the xHC can power it off if all ports are in the disconnect,
145
144
* disabled, or powered-off state.
146
145
*/
147
-
#define CMD_PM_INDEX (1 << 11)
146
+
#define CMD_PM_INDEX BIT(11)
148
147
/* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
149
-
#define CMD_ETE (1 << 14)
148
+
#define CMD_ETE BIT(14)
150
149
/* bits 15:31 are reserved (and should be preserved on writes). */
151
150
152
151
#define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
···
156
155
/* HC not running - set to 1 when run/stop bit is cleared. */
157
156
#define STS_HALT XHCI_STS_HALT
158
157
/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
159
-
#define STS_FATAL (1 << 2)
158
+
#define STS_FATAL BIT(2)
160
159
/* event interrupt - clear this prior to clearing any IP flags in IR set*/
161
-
#define STS_EINT (1 << 3)
160
+
#define STS_EINT BIT(3)
162
161
/* port change detect */
163
-
#define STS_PORT (1 << 4)
162
+
#define STS_PORT BIT(4)
164
163
/* bits 5:7 reserved and zeroed */
165
164
/* save state status - '1' means xHC is saving state */
166
-
#define STS_SAVE (1 << 8)
165
+
#define STS_SAVE BIT(8)
167
166
/* restore state status - '1' means xHC is restoring state */
168
-
#define STS_RESTORE (1 << 9)
167
+
#define STS_RESTORE BIT(9)
169
168
/* true: save or restore error */
170
-
#define STS_SRE (1 << 10)
169
+
#define STS_SRE BIT(10)
171
170
/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
172
171
#define STS_CNR XHCI_STS_CNR
173
172
/* true: internal Host Controller Error - SW needs to reset and reinitialize */
174
-
#define STS_HCE (1 << 12)
173
+
#define STS_HCE BIT(12)
175
174
/* bits 13:31 reserved and should be preserved */
176
175
177
176
/*
···
183
182
/* Most of the device notification types should only be used for debug.
184
183
* SW does need to pay attention to function wake notifications.
185
184
*/
186
-
#define DEV_NOTE_FWAKE (1 << 1)
185
+
#define DEV_NOTE_FWAKE BIT(1)
187
186
188
187
/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
189
188
/* bit 0 - Cycle bit indicates the ownership of the command ring */
190
-
#define CMD_RING_CYCLE (1 << 0)
189
+
#define CMD_RING_CYCLE BIT(0)
191
190
/* stop ring operation after completion of the currently executing command */
192
-
#define CMD_RING_PAUSE (1 << 1)
191
+
#define CMD_RING_PAUSE BIT(1)
193
192
/* stop ring immediately - abort the currently executing command */
194
-
#define CMD_RING_ABORT (1 << 2)
193
+
#define CMD_RING_ABORT BIT(2)
195
194
/* true: command ring is running */
196
-
#define CMD_RING_RUNNING (1 << 3)
195
+
#define CMD_RING_RUNNING BIT(3)
197
196
/* bits 63:6 - Command Ring pointer */
198
197
#define CMD_RING_PTR_MASK GENMASK_ULL(63, 6)
199
198
···
201
200
/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
202
201
#define MAX_DEVS(p) ((p) & 0xff)
203
202
/* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
204
-
#define CONFIG_U3E (1 << 8)
203
+
#define CONFIG_U3E BIT(8)
205
204
/* bit 9: Configuration Information Enable, xhci 1.1 */
206
-
#define CONFIG_CIE (1 << 9)
205
+
#define CONFIG_CIE BIT(9)
207
206
/* bits 10:31 - reserved and should be preserved */
208
207
209
208
/* bits 15:0 - HCD page shift bit */
···
236
235
237
236
/* iman bitmasks */
238
237
/* bit 0 - Interrupt Pending (IP), whether there is an interrupt pending. Write-1-to-clear. */
239
-
#define IMAN_IP (1 << 0)
238
+
#define IMAN_IP BIT(0)
240
239
/* bit 1 - Interrupt Enable (IE), whether the interrupter is capable of generating an interrupt */
241
-
#define IMAN_IE (1 << 1)
240
+
#define IMAN_IE BIT(1)
242
241
243
242
/* imod bitmasks */
244
243
/*
···
268
267
* bit 3 - Event Handler Busy (EHB), whether the event ring is scheduled to be serviced by
269
268
* a work queue (or delayed service routine)?
270
269
*/
271
-
#define ERST_EHB (1 << 3)
270
+
#define ERST_EHB BIT(3)
272
271
/* bits 63:4 - Event Ring Dequeue Pointer */
273
272
#define ERST_PTR_MASK GENMASK_ULL(63, 4)
274
273
···
357
356
#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
358
357
/* bit 24 reserved */
359
358
/* Is this LS/FS device connected through a HS hub? - bit 25 */
360
-
#define DEV_MTT (0x1 << 25)
359
+
#define DEV_MTT BIT(25)
361
360
/* Set if the device is a hub - bit 26 */
362
-
#define DEV_HUB (0x1 << 26)
361
+
#define DEV_HUB BIT(26)
363
362
/* Index of the last valid endpoint context in this device context - 27:31 */
364
363
#define LAST_CTX_MASK (0x1f << 27)
365
364
#define LAST_CTX(p) ((p) << 27)
366
365
#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
367
-
#define SLOT_FLAG (1 << 0)
368
-
#define EP0_FLAG (1 << 1)
366
+
#define SLOT_FLAG BIT(0)
367
+
#define EP0_FLAG BIT(1)
369
368
370
369
/* dev_info2 bitmasks */
371
370
/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
···
464
463
#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
465
464
#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
466
465
/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
467
-
#define EP_HAS_LSA (1 << 15)
466
+
#define EP_HAS_LSA BIT(15)
468
467
/* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
469
468
#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
470
469
···
499
498
#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
500
499
501
500
/* deq bitmasks */
502
-
#define EP_CTX_CYCLE_MASK (1 << 0)
501
+
#define EP_CTX_CYCLE_MASK BIT(0)
503
502
/* bits 63:4 - TR Dequeue Pointer */
504
503
#define TR_DEQ_PTR_MASK GENMASK_ULL(63, 4)
505
504
···
662
661
struct xhci_ring *new_ring;
663
662
unsigned int err_count;
664
663
unsigned int ep_state;
665
-
#define SET_DEQ_PENDING (1 << 0)
666
-
#define EP_HALTED (1 << 1) /* For stall handling */
667
-
#define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
664
+
#define SET_DEQ_PENDING BIT(0)
665
+
#define EP_HALTED BIT(1) /* For stall handling */
666
+
#define EP_STOP_CMD_PENDING BIT(2) /* For URB cancellation */
668
667
/* Transitioning the endpoint to using streams, don't enqueue URBs */
669
-
#define EP_GETTING_STREAMS (1 << 3)
670
-
#define EP_HAS_STREAMS (1 << 4)
668
+
#define EP_GETTING_STREAMS BIT(3)
669
+
#define EP_HAS_STREAMS BIT(4)
671
670
/* Transitioning the endpoint to not using streams, don't enqueue URBs */
672
-
#define EP_GETTING_NO_STREAMS (1 << 5)
673
-
#define EP_HARD_CLEAR_TOGGLE (1 << 6)
674
-
#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
671
+
#define EP_GETTING_NO_STREAMS BIT(5)
672
+
#define EP_HARD_CLEAR_TOGGLE BIT(6)
673
+
#define EP_SOFT_CLEAR_TOGGLE BIT(7)
675
674
/* usb_hub_clear_tt_buffer is in progress */
676
-
#define EP_CLEARING_TT (1 << 8)
675
+
#define EP_CLEARING_TT BIT(8)
677
676
/* ---- Related to URB cancellation ---- */
678
677
struct list_head cancelled_td_list;
679
678
struct xhci_hcd *xhci;
···
955
954
};
956
955
957
956
/* control bitfields */
958
-
#define LINK_TOGGLE (0x1<<1)
957
+
#define LINK_TOGGLE BIT(1)
959
958
960
959
/* Command completion event TRB */
961
960
struct xhci_event_cmd {
···
969
968
#define COMP_PARAM(p) ((p) & 0xffffff) /* Command Completion Parameter */
970
969
971
970
/* Address device - disable SetAddress */
972
-
#define TRB_BSR (1<<9)
971
+
#define TRB_BSR BIT(9)
973
972
974
973
/* Configure Endpoint - Deconfigure */
975
-
#define TRB_DC (1<<9)
974
+
#define TRB_DC BIT(9)
976
975
977
976
/* Stop Ring - Transfer State Preserve */
978
-
#define TRB_TSP (1<<9)
977
+
#define TRB_TSP BIT(9)
979
978
980
979
enum xhci_ep_reset_type {
981
980
EP_HARD_RESET,
···
1018
1017
#define SCT_FOR_TRB(p) (((p) & 0x7) << 1)
1019
1018
1020
1019
/* Link TRB specific fields */
1021
-
#define TRB_TC (1<<1)
1020
+
#define TRB_TC BIT(1)
1022
1021
1023
1022
/* Port Status Change Event TRB fields */
1024
1023
/* Port ID - bits 31:24 */
1025
1024
#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1026
1025
1027
-
#define EVENT_DATA (1 << 2)
1026
+
#define EVENT_DATA BIT(2)
1028
1027
1029
1028
/* Normal TRB fields */
1030
1029
/* transfer_len bitmasks - bits 0:16 */
···
1039
1038
#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1040
1039
1041
1040
/* Cycle bit - indicates TRB ownership by HC or HCD */
1042
-
#define TRB_CYCLE (1<<0)
1041
+
#define TRB_CYCLE BIT(0)
1043
1042
/*
1044
1043
* Force next event data TRB to be evaluated before task switch.
1045
1044
* Used to pass OS data back after a TD completes.
1046
1045
*/
1047
-
#define TRB_ENT (1<<1)
1046
+
#define TRB_ENT BIT(1)
1048
1047
/* Interrupt on short packet */
1049
-
#define TRB_ISP (1<<2)
1048
+
#define TRB_ISP BIT(2)
1050
1049
/* Set PCIe no snoop attribute */
1051
-
#define TRB_NO_SNOOP (1<<3)
1050
+
#define TRB_NO_SNOOP BIT(3)
1052
1051
/* Chain multiple TRBs into a TD */
1053
-
#define TRB_CHAIN (1<<4)
1052
+
#define TRB_CHAIN BIT(4)
1054
1053
/* Interrupt on completion */
1055
-
#define TRB_IOC (1<<5)
1054
+
#define TRB_IOC BIT(5)
1056
1055
/* The buffer pointer contains immediate data */
1057
-
#define TRB_IDT (1<<6)
1056
+
#define TRB_IDT BIT(6)
1058
1057
/* TDs smaller than this might use IDT */
1059
1058
#define TRB_IDT_MAX_SIZE 8
1060
1059
1061
1060
/* Block Event Interrupt */
1062
-
#define TRB_BEI (1<<9)
1061
+
#define TRB_BEI BIT(9)
1063
1062
1064
1063
/* Control transfer TRB specific fields */
1065
-
#define TRB_DIR_IN (1<<16)
1064
+
#define TRB_DIR_IN BIT(16)
1066
1065
#define TRB_TX_TYPE(p) ((p) << 16)
1067
1066
#define TRB_DATA_OUT 2
1068
1067
#define TRB_DATA_IN 3
1069
1068
1070
1069
/* Isochronous TRB specific fields */
1071
-
#define TRB_SIA (1<<31)
1070
+
#define TRB_SIA BIT(31)
1072
1071
#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1073
1072
#define GET_FRAME_ID(p) (((p) >> 20) & 0x7ff)
1074
1073
/* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
···
1536
1535
struct xhci_interrupter **interrupters;
1537
1536
struct xhci_ring *cmd_ring;
1538
1537
unsigned int cmd_ring_state;
1539
-
#define CMD_RING_STATE_RUNNING (1 << 0)
1540
-
#define CMD_RING_STATE_ABORTED (1 << 1)
1541
-
#define CMD_RING_STATE_STOPPED (1 << 2)
1538
+
#define CMD_RING_STATE_RUNNING BIT(0)
1539
+
#define CMD_RING_STATE_ABORTED BIT(1)
1540
+
#define CMD_RING_STATE_STOPPED BIT(2)
1542
1541
struct list_head cmd_list;
1543
1542
unsigned int cmd_ring_reserved_trbs;
1544
1543
struct delayed_work cmd_timer;
···
1579
1578
*
1580
1579
* There are no reports of xHCI host controllers that display this issue.
1581
1580
*/
1582
-
#define XHCI_STATE_DYING (1 << 0)
1583
-
#define XHCI_STATE_HALTED (1 << 1)
1584
-
#define XHCI_STATE_REMOVING (1 << 2)
1581
+
#define XHCI_STATE_DYING BIT(0)
1582
+
#define XHCI_STATE_HALTED BIT(1)
1583
+
#define XHCI_STATE_REMOVING BIT(2)
1585
1584
unsigned long long quirks;
1586
1585
#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1587
1586
#define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
···
1793
1792
void xhci_mem_cleanup(struct xhci_hcd *xhci);
1794
1793
int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1795
1794
void xhci_free_virt_device(struct xhci_hcd *xhci, struct xhci_virt_device *dev, int slot_id);
1795
+
void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id);
1796
1796
int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1797
1797
int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1798
1798
void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
···
1805
1803
struct xhci_virt_device *virt_dev,
1806
1804
int old_active_eps);
1807
1805
void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1806
+
void xhci_rh_bw_cleanup(struct xhci_hcd *xhci);
1808
1807
void xhci_update_bw_info(struct xhci_hcd *xhci,
1809
1808
struct xhci_container_ctx *in_ctx,
1810
1809
struct xhci_input_control_ctx *ctrl_ctx,
···
1826
1823
int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1827
1824
unsigned int num_trbs, gfp_t flags);
1828
1825
void xhci_initialize_ring_info(struct xhci_ring *ring);
1826
+
void xhci_ring_init(struct xhci_hcd *xhci, struct xhci_ring *ring);
1829
1827
void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
1830
1828
struct xhci_virt_device *virt_dev,
1831
1829
unsigned int ep_index);
+22
-57
drivers/usb/image/microtek.c
+22
-57
drivers/usb/image/microtek.c
···
55
55
* Status:
56
56
*
57
57
* Untested with multiple scanners.
58
-
* Untested on SMP.
59
58
* Untested on a bigendian machine.
60
59
*
61
60
* History:
···
169
170
#define MTS_VERSION "0.4.3"
170
171
#define MTS_NAME "microtek usb (rev " MTS_VERSION "): "
171
172
172
-
#define MTS_WARNING(x...) \
173
-
printk( KERN_WARNING MTS_NAME x )
174
-
#define MTS_ERROR(x...) \
175
-
printk( KERN_ERR MTS_NAME x )
176
-
#define MTS_INT_ERROR(x...) \
177
-
MTS_ERROR(x)
178
-
#define MTS_MESSAGE(x...) \
179
-
printk( KERN_INFO MTS_NAME x )
180
-
181
173
#if defined MTS_DO_DEBUG
182
174
183
175
#define MTS_DEBUG(x...) \
184
176
printk( KERN_DEBUG MTS_NAME x )
185
177
186
-
#define MTS_DEBUG_GOT_HERE() \
187
-
MTS_DEBUG("got to %s:%d (%s)\n", __FILE__, (int)__LINE__, __func__ )
188
178
#define MTS_DEBUG_INT() \
189
-
do { MTS_DEBUG_GOT_HERE(); \
190
-
MTS_DEBUG("transfer = 0x%x context = 0x%x\n",(int)transfer,(int)context ); \
179
+
do { MTS_DEBUG("transfer = 0x%x context = 0x%x\n",(int)transfer,(int)context ); \
191
180
MTS_DEBUG("status = 0x%x data-length = 0x%x sent = 0x%x\n",transfer->status,(int)context->data_length, (int)transfer->actual_length ); \
192
181
mts_debug_dump(context->instance);\
193
182
} while(0)
···
184
197
#define MTS_NUL_STATEMENT do { } while(0)
185
198
186
199
#define MTS_DEBUG(x...) MTS_NUL_STATEMENT
187
-
#define MTS_DEBUG_GOT_HERE() MTS_NUL_STATEMENT
188
200
#define MTS_DEBUG_INT() MTS_NUL_STATEMENT
189
201
190
202
#endif
···
302
316
#endif
303
317
304
318
static inline void mts_urb_abort(struct mts_desc* desc) {
305
-
MTS_DEBUG_GOT_HERE();
306
319
mts_debug_dump(desc);
307
320
308
321
usb_kill_urb( desc->urb );
···
317
332
{
318
333
struct mts_desc* desc = (struct mts_desc*)(srb->device->host->hostdata[0]);
319
334
320
-
MTS_DEBUG_GOT_HERE();
321
-
322
335
mts_urb_abort(desc);
323
336
324
337
return FAILED;
···
327
344
struct mts_desc* desc = (struct mts_desc*)(srb->device->host->hostdata[0]);
328
345
int result;
329
346
330
-
MTS_DEBUG_GOT_HERE();
331
347
mts_debug_dump(desc);
332
348
333
349
result = usb_lock_device_for_reset(desc->usb_dev, desc->usb_intf);
···
368
386
369
387
res = usb_submit_urb( transfer, GFP_ATOMIC );
370
388
if ( unlikely(res) ) {
371
-
MTS_INT_ERROR( "could not submit URB! Error was %d\n",(int)res );
389
+
dev_err(&context->instance->usb_dev->dev,
390
+
"could not submit URB! Error was %d\n",(int)res );
372
391
set_host_byte(context->srb, DID_ERROR);
373
392
mts_transfer_cleanup(transfer);
374
393
}
···
435
452
if ( unlikely(status) ) {
436
453
if (status == -ENOENT) {
437
454
/* We are being killed */
438
-
MTS_DEBUG_GOT_HERE();
439
455
set_host_byte(context->srb, DID_ABORT);
440
456
} else {
441
457
/* A genuine error has occurred */
442
-
MTS_DEBUG_GOT_HERE();
443
-
444
458
set_host_byte(context->srb, DID_ERROR);
445
459
}
446
460
mts_transfer_cleanup(transfer);
···
503
523
{
504
524
int pipe;
505
525
506
-
MTS_DEBUG_GOT_HERE();
507
-
508
526
desc->context.instance = desc;
509
527
desc->context.srb = srb;
510
528
···
543
565
struct mts_desc* desc = (struct mts_desc*)(srb->device->host->hostdata[0]);
544
566
int res;
545
567
546
-
MTS_DEBUG_GOT_HERE();
547
568
mts_show_command(srb);
548
569
mts_debug_dump(desc);
549
570
···
578
601
res=usb_submit_urb(desc->urb, GFP_ATOMIC);
579
602
580
603
if(unlikely(res)){
581
-
MTS_ERROR("error %d submitting URB\n",(int)res);
604
+
dev_err(&desc->usb_dev->dev, "error %d submitting URB\n",(int)res);
582
605
set_host_byte(srb, DID_ERROR);
583
606
584
607
if(likely(callback != NULL))
···
643
666
/* the current altsetting on the interface we're probing */
644
667
struct usb_host_interface *altsetting;
645
668
646
-
MTS_DEBUG_GOT_HERE();
647
669
MTS_DEBUG( "usb-device descriptor at %x\n", (int)dev );
648
670
649
671
MTS_DEBUG( "product id = 0x%x, vendor id = 0x%x\n",
650
672
le16_to_cpu(dev->descriptor.idProduct),
651
673
le16_to_cpu(dev->descriptor.idVendor) );
652
674
653
-
MTS_DEBUG_GOT_HERE();
654
-
655
675
/* the current altsetting on the interface we're probing */
656
676
altsetting = intf->cur_altsetting;
657
-
658
677
659
678
/* Check if the config is sane */
660
679
661
680
if ( altsetting->desc.bNumEndpoints != MTS_EP_TOTAL ) {
662
-
MTS_WARNING( "expecting %d got %d endpoints! Bailing out.\n",
681
+
dev_warn(&dev->dev, "expecting %d got %d endpoints! Bailing out.\n",
663
682
(int)MTS_EP_TOTAL, (int)altsetting->desc.bNumEndpoints );
664
683
return -ENODEV;
665
684
}
666
685
667
686
for( i = 0; i < altsetting->desc.bNumEndpoints; i++ ) {
668
-
if ((altsetting->endpoint[i].desc.bmAttributes &
669
-
USB_ENDPOINT_XFERTYPE_MASK) != USB_ENDPOINT_XFER_BULK) {
670
-
671
-
MTS_WARNING( "can only deal with bulk endpoints; endpoint %d is not bulk.\n",
672
-
(int)altsetting->endpoint[i].desc.bEndpointAddress );
673
-
} else {
674
-
if (altsetting->endpoint[i].desc.bEndpointAddress &
675
-
USB_DIR_IN)
676
-
*ep_in_current++
677
-
= altsetting->endpoint[i].desc.bEndpointAddress &
678
-
USB_ENDPOINT_NUMBER_MASK;
679
-
else {
680
-
if ( ep_out != -1 ) {
681
-
MTS_WARNING( "can only deal with one output endpoints. Bailing out." );
682
-
return -ENODEV;
683
-
}
684
-
685
-
ep_out = altsetting->endpoint[i].desc.bEndpointAddress &
686
-
USB_ENDPOINT_NUMBER_MASK;
687
+
if (usb_endpoint_is_bulk_in(&altsetting->endpoint[i].desc)) {
688
+
*ep_in_current++ = usb_endpoint_num(&altsetting->endpoint[i].desc);
689
+
} else if (usb_endpoint_is_bulk_out(&altsetting->endpoint[i].desc)) {
690
+
if (ep_out == -1) {
691
+
ep_out = usb_endpoint_num(&altsetting->endpoint[i].desc);
692
+
} else {
693
+
dev_warn(&dev->dev, "can only deal with bulk endpoints; endpoint %d is not bulk.\n",
694
+
usb_endpoint_num(&altsetting->endpoint[i].desc));
695
+
return -ENODEV;
687
696
}
697
+
} else {
698
+
dev_warn(&dev->dev, "can only deal with bulk endpoints; endpoint %d is not bulk.\n",
699
+
usb_endpoint_num(&altsetting->endpoint[i].desc));
688
700
}
689
-
690
701
}
691
702
692
703
if (ep_in_current != &ep_in_set[2]) {
693
-
MTS_WARNING("couldn't find two input bulk endpoints. Bailing out.\n");
704
+
dev_warn(&dev->dev, "couldn't find two input bulk endpoints. Bailing out.\n");
694
705
return -ENODEV;
695
706
}
696
707
697
708
if ( ep_out == -1 ) {
698
-
MTS_WARNING( "couldn't find an output bulk endpoint. Bailing out.\n" );
709
+
dev_warn(&dev->dev, "couldn't find an output bulk endpoint. Bailing out.\n" );
699
710
return -ENODEV;
700
711
}
701
712
···
709
744
new_desc->ep_image = ep_in_set[1];
710
745
711
746
if ( new_desc->ep_out != MTS_EP_OUT )
712
-
MTS_WARNING( "will this work? Command EP is not usually %d\n",
747
+
dev_warn(&dev->dev, "will this work? Command EP is not usually %d\n",
713
748
(int)new_desc->ep_out );
714
749
715
750
if ( new_desc->ep_response != MTS_EP_RESPONSE )
716
-
MTS_WARNING( "will this work? Response EP is not usually %d\n",
751
+
dev_warn(&dev->dev, "will this work? Response EP is not usually %d\n",
717
752
(int)new_desc->ep_response );
718
753
719
754
if ( new_desc->ep_image != MTS_EP_IMAGE )
720
-
MTS_WARNING( "will this work? Image data EP is not usually %d\n",
755
+
dev_warn(&dev->dev, "will this work? Image data EP is not usually %d\n",
721
756
(int)new_desc->ep_image );
722
757
723
758
new_desc->host = scsi_host_alloc(&mts_scsi_host_template,
+1
-2
drivers/usb/misc/apple-mfi-fastcharge.c
+1
-2
drivers/usb/misc/apple-mfi-fastcharge.c
···
210
210
goto err_free_name;
211
211
}
212
212
213
-
mfi->udev = usb_get_dev(udev);
213
+
mfi->udev = udev;
214
214
dev_set_drvdata(&udev->dev, mfi);
215
215
216
216
return 0;
···
231
231
power_supply_unregister(mfi->battery);
232
232
kfree(mfi->battery_desc.name);
233
233
dev_set_drvdata(&udev->dev, NULL);
234
-
usb_put_dev(mfi->udev);
235
234
kfree(mfi);
236
235
}
237
236
+3
-5
drivers/usb/misc/appledisplay.c
+3
-5
drivers/usb/misc/appledisplay.c
···
12
12
#include <linux/init.h>
13
13
#include <linux/module.h>
14
14
#include <linux/slab.h>
15
+
#include <linux/hid.h>
15
16
#include <linux/usb.h>
16
17
#include <linux/backlight.h>
17
18
#include <linux/timer.h>
···
20
19
#include <linux/atomic.h>
21
20
22
21
#define APPLE_VENDOR_ID 0x05AC
23
-
24
-
#define USB_REQ_GET_REPORT 0x01
25
-
#define USB_REQ_SET_REPORT 0x09
26
22
27
23
#define ACD_USB_TIMEOUT 250
28
24
···
138
140
retval = usb_control_msg(
139
141
pdata->udev,
140
142
usb_sndctrlpipe(pdata->udev, 0),
141
-
USB_REQ_SET_REPORT,
143
+
HID_REQ_SET_REPORT,
142
144
USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE,
143
145
ACD_USB_BRIGHTNESS,
144
146
0,
···
161
163
retval = usb_control_msg(
162
164
pdata->udev,
163
165
usb_rcvctrlpipe(pdata->udev, 0),
164
-
USB_REQ_GET_REPORT,
166
+
HID_REQ_GET_REPORT,
165
167
USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE,
166
168
ACD_USB_BRIGHTNESS,
167
169
0,
+1
-3
drivers/usb/misc/cypress_cy7c63.c
+1
-3
drivers/usb/misc/cypress_cy7c63.c
···
215
215
if (!dev)
216
216
goto error_mem;
217
217
218
-
dev->udev = usb_get_dev(interface_to_usbdev(interface));
218
+
dev->udev = interface_to_usbdev(interface);
219
219
220
220
/* save our data pointer in this interface device */
221
221
usb_set_intfdata(interface, dev);
···
238
238
/* the intfdata can be set to NULL only after the
239
239
* device files have been removed */
240
240
usb_set_intfdata(interface, NULL);
241
-
242
-
usb_put_dev(dev->udev);
243
241
244
242
dev_info(&interface->dev,
245
243
"Cypress CY7C63xxx device now disconnected\n");
+1
-3
drivers/usb/misc/cytherm.c
+1
-3
drivers/usb/misc/cytherm.c
···
311
311
if (!dev)
312
312
goto error_mem;
313
313
314
-
dev->udev = usb_get_dev(udev);
314
+
dev->udev = udev;
315
315
316
316
usb_set_intfdata(interface, dev);
317
317
···
333
333
334
334
/* first remove the files, then NULL the pointer */
335
335
usb_set_intfdata(interface, NULL);
336
-
337
-
usb_put_dev(dev->udev);
338
336
339
337
kfree(dev);
340
338
+14
-28
drivers/usb/misc/iowarrior.c
+14
-28
drivers/usb/misc/iowarrior.c
···
21
21
#include <linux/sched.h>
22
22
#include <linux/mutex.h>
23
23
#include <linux/poll.h>
24
+
#include <linux/hid.h>
24
25
#include <linux/usb/iowarrior.h>
25
26
26
27
#define DRIVER_AUTHOR "Christian Lucht <lucht@codemercs.com>"
···
75
74
struct mutex mutex; /* locks this structure */
76
75
struct usb_device *udev; /* save off the usb device pointer */
77
76
struct usb_interface *interface; /* the interface for this device */
78
-
unsigned char minor; /* the starting minor number for this device */
79
77
struct usb_endpoint_descriptor *int_out_endpoint; /* endpoint for reading (needed for IOW56 only) */
80
78
struct usb_endpoint_descriptor *int_in_endpoint; /* endpoint for reading */
81
79
struct urb *int_in_urb; /* the urb for reading data */
···
99
99
/* globals */
100
100
/*--------------*/
101
101
102
-
#define USB_REQ_GET_REPORT 0x01
103
102
//#if 0
104
103
static int usb_get_report(struct usb_device *dev,
105
104
struct usb_host_interface *inter, unsigned char type,
106
105
unsigned char id, void *buf, int size)
107
106
{
108
107
return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
109
-
USB_REQ_GET_REPORT,
108
+
HID_REQ_GET_REPORT,
110
109
USB_DIR_IN | USB_TYPE_CLASS |
111
110
USB_RECIP_INTERFACE, (type << 8) + id,
112
111
inter->desc.bInterfaceNumber, buf, size,
···
113
114
}
114
115
//#endif
115
116
116
-
#define USB_REQ_SET_REPORT 0x09
117
-
118
117
static int usb_set_report(struct usb_interface *intf, unsigned char type,
119
118
unsigned char id, void *buf, int size)
120
119
{
121
120
return usb_control_msg(interface_to_usbdev(intf),
122
121
usb_sndctrlpipe(interface_to_usbdev(intf), 0),
123
-
USB_REQ_SET_REPORT,
122
+
HID_REQ_SET_REPORT,
124
123
USB_TYPE_CLASS | USB_RECIP_INTERFACE,
125
124
(type << 8) + id,
126
125
intf->cur_altsetting->desc.bInterfaceNumber, buf,
···
231
234
"nonzero write bulk status received: %d\n", status);
232
235
}
233
236
/* free up our allocated buffer */
234
-
usb_free_coherent(urb->dev, urb->transfer_buffer_length,
235
-
urb->transfer_buffer, urb->transfer_dma);
237
+
kfree(urb->transfer_buffer);
236
238
/* tell a waiting writer the interrupt-out-pipe is available again */
237
239
atomic_dec(&dev->write_busy);
238
240
wake_up_interruptible(&dev->write_wait);
···
242
246
*/
243
247
static inline void iowarrior_delete(struct iowarrior *dev)
244
248
{
245
-
dev_dbg(&dev->interface->dev, "minor %d\n", dev->minor);
246
249
kfree(dev->int_in_buffer);
247
250
usb_free_urb(dev->int_in_urb);
248
251
kfree(dev->read_queue);
···
291
296
retval = -ENODEV;
292
297
goto exit;
293
298
}
294
-
295
-
dev_dbg(&dev->interface->dev, "minor %d, count = %zd\n",
296
-
dev->minor, count);
297
299
298
300
/* read count must be packet size (+ time stamp) */
299
301
if ((count != dev->report_size)
···
359
367
size_t count, loff_t *ppos)
360
368
{
361
369
struct iowarrior *dev;
362
-
int retval = 0;
370
+
int retval;
363
371
char *buf = NULL; /* for IOW24 and IOW56 we need a buffer */
364
372
struct urb *int_out_urb = NULL;
365
373
366
374
dev = file->private_data;
367
375
368
-
mutex_lock(&dev->mutex);
376
+
retval = mutex_lock_interruptible(&dev->mutex);
377
+
if (retval < 0)
378
+
return -EINTR;
379
+
369
380
/* verify that the device wasn't unplugged */
370
381
if (!dev->present) {
371
382
retval = -ENODEV;
372
383
goto exit;
373
384
}
374
-
dev_dbg(&dev->interface->dev, "minor %d, count = %zd\n",
375
-
dev->minor, count);
376
385
/* if count is 0 we're already done */
377
386
if (count == 0) {
378
387
retval = 0;
···
436
443
retval = -ENOMEM;
437
444
goto error_no_urb;
438
445
}
439
-
buf = usb_alloc_coherent(dev->udev, dev->report_size,
440
-
GFP_KERNEL, &int_out_urb->transfer_dma);
446
+
buf = kmalloc(dev->report_size, GFP_KERNEL);
441
447
if (!buf) {
442
448
retval = -ENOMEM;
443
449
dev_dbg(&dev->interface->dev,
···
449
457
buf, dev->report_size,
450
458
iowarrior_write_callback, dev,
451
459
dev->int_out_endpoint->bInterval);
452
-
int_out_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
453
460
if (copy_from_user(buf, user_buffer, count)) {
454
461
retval = -EFAULT;
455
462
goto error;
···
474
483
goto exit;
475
484
}
476
485
error:
477
-
usb_free_coherent(dev->udev, dev->report_size, buf,
478
-
int_out_urb->transfer_dma);
486
+
kfree(buf);
479
487
error_no_buffer:
480
488
usb_free_urb(int_out_urb);
481
489
error_no_urb:
···
512
522
retval = -ENODEV;
513
523
goto error_out;
514
524
}
515
-
516
-
dev_dbg(&dev->interface->dev, "minor %d, cmd 0x%.4x, arg %ld\n",
517
-
dev->minor, cmd, arg);
518
525
519
526
retval = 0;
520
527
switch (cmd) {
···
658
671
if (!dev)
659
672
return -ENODEV;
660
673
661
-
dev_dbg(&dev->interface->dev, "minor %d\n", dev->minor);
662
-
663
674
/* lock our device */
664
675
mutex_lock(&dev->mutex);
665
676
···
760
775
struct usb_host_interface *iface_desc;
761
776
int retval = -ENOMEM;
762
777
int res;
778
+
int minor;
763
779
764
780
/* allocate memory for our device state and initialize it */
765
781
dev = kzalloc_obj(struct iowarrior);
···
876
890
goto error;
877
891
}
878
892
879
-
dev->minor = interface->minor;
893
+
minor = interface->minor;
880
894
881
895
/* let the user know what node this device is now attached to */
882
896
dev_info(&interface->dev, "IOWarrior product=0x%x, serial=%s interface=%d "
883
897
"now attached to iowarrior%d\n", dev->product_id, dev->chip_serial,
884
-
iface_desc->desc.bInterfaceNumber, dev->minor - IOWARRIOR_MINOR_BASE);
898
+
iface_desc->desc.bInterfaceNumber, minor - IOWARRIOR_MINOR_BASE);
885
899
return retval;
886
900
887
901
error:
+5
drivers/usb/misc/onboard_usb_dev.c
+5
drivers/usb/misc/onboard_usb_dev.c
···
565
565
/************************** USB driver **************************/
566
566
567
567
#define VENDOR_ID_BISON 0x5986
568
+
#define VENDOR_ID_CORECHIPS 0x3431
568
569
#define VENDOR_ID_CYPRESS 0x04b4
569
570
#define VENDOR_ID_GENESYS 0x05e3
570
571
#define VENDOR_ID_MICROCHIP 0x0424
571
572
#define VENDOR_ID_PARADE 0x1da0
572
573
#define VENDOR_ID_REALTEK 0x0bda
574
+
#define VENDOR_ID_TERMINUS 0x1a40
573
575
#define VENDOR_ID_TI 0x0451
574
576
#define VENDOR_ID_VIA 0x2109
575
577
#define VENDOR_ID_XMOS 0x20B1
···
651
649
652
650
static const struct usb_device_id onboard_dev_id_table[] = {
653
651
{ USB_DEVICE(VENDOR_ID_BISON, 0x1198) }, /* Bison Electronics Inc. Integrated Camera */
652
+
{ USB_DEVICE(VENDOR_ID_CORECHIPS, 0x6241) }, /* SL6341 2.0 HUB */
653
+
{ USB_DEVICE(VENDOR_ID_CORECHIPS, 0x6341) }, /* SL6341 3.0 HUB */
654
654
{ USB_DEVICE(VENDOR_ID_CYPRESS, 0x6500) }, /* CYUSB330x 3.0 HUB */
655
655
{ USB_DEVICE(VENDOR_ID_CYPRESS, 0x6502) }, /* CYUSB330x 2.0 HUB */
656
656
{ USB_DEVICE(VENDOR_ID_CYPRESS, 0x6503) }, /* CYUSB33{0,1}x 2.0 HUB, Vendor Mode */
···
677
673
{ USB_DEVICE(VENDOR_ID_REALTEK, 0x0414) }, /* RTS5414 USB 3.2 HUB */
678
674
{ USB_DEVICE(VENDOR_ID_REALTEK, 0x5414) }, /* RTS5414 USB 2.1 HUB */
679
675
{ USB_DEVICE(VENDOR_ID_REALTEK, 0x0179) }, /* RTL8188ETV 2.4GHz WiFi */
676
+
{ USB_DEVICE(VENDOR_ID_TERMINUS, 0x0101) }, /* Terminus FE1.1s 2.0 HUB */
680
677
{ USB_DEVICE(VENDOR_ID_TI, 0x8025) }, /* TI USB8020B 3.0 HUB */
681
678
{ USB_DEVICE(VENDOR_ID_TI, 0x8027) }, /* TI USB8020B 2.0 HUB */
682
679
{ USB_DEVICE(VENDOR_ID_TI, 0x8140) }, /* TI USB8041 3.0 HUB */
+21
-19
drivers/usb/misc/onboard_usb_dev.h
+21
-19
drivers/usb/misc/onboard_usb_dev.h
···
66
66
.is_hub = true,
67
67
};
68
68
69
-
static const struct onboard_dev_pdata ti_tusb8041_data = {
70
-
.reset_us = 3000,
71
-
.num_supplies = 1,
72
-
.supply_names = { "vdd" },
73
-
.is_hub = true,
74
-
};
75
-
76
69
static const struct onboard_dev_pdata bison_intcamera_data = {
77
70
.reset_us = 1000,
78
71
.num_supplies = 1,
···
73
80
.is_hub = false,
74
81
};
75
82
83
+
static const struct onboard_dev_pdata corechips_sl6341_data = {
84
+
.reset_us = 10000,
85
+
.num_supplies = 2,
86
+
.supply_names = { "vdd1v1", "vdd3v3" },
87
+
.is_hub = true,
88
+
};
89
+
76
90
static const struct onboard_dev_pdata cypress_hx3_data = {
77
91
.reset_us = 10000,
78
92
.num_supplies = 2,
79
93
.supply_names = { "vdd", "vdd2" },
80
-
.is_hub = true,
81
-
};
82
-
83
-
static const struct onboard_dev_pdata cypress_hx2vl_data = {
84
-
.reset_us = 1,
85
-
.num_supplies = 1,
86
-
.supply_names = { "vdd" },
87
94
.is_hub = true,
88
95
};
89
96
···
99
106
.num_supplies = 1,
100
107
.supply_names = { "vdd" },
101
108
.is_hub = true,
109
+
};
110
+
111
+
static const struct onboard_dev_pdata usb_a_conn_data = {
112
+
.num_supplies = 1,
113
+
.supply_names = { "vbus" },
102
114
};
103
115
104
116
static const struct onboard_dev_pdata vialab_vl817_data = {
···
128
130
};
129
131
130
132
static const struct of_device_id onboard_dev_match[] = {
133
+
{ .compatible = "usb-a-connector", .data = &usb_a_conn_data, },
131
134
{ .compatible = "usb424,2412", .data = µchip_usb424_data, },
132
135
{ .compatible = "usb424,2514", .data = µchip_usb2514_data, },
133
136
{ .compatible = "usb424,2517", .data = µchip_usb424_data, },
···
136
137
{ .compatible = "usb424,5744", .data = µchip_usb5744_data, },
137
138
{ .compatible = "usb451,8025", .data = &ti_tusb8020b_data, },
138
139
{ .compatible = "usb451,8027", .data = &ti_tusb8020b_data, },
139
-
{ .compatible = "usb451,8140", .data = &ti_tusb8041_data, },
140
-
{ .compatible = "usb451,8142", .data = &ti_tusb8041_data, },
141
-
{ .compatible = "usb451,8440", .data = &ti_tusb8041_data, },
142
-
{ .compatible = "usb451,8442", .data = &ti_tusb8041_data, },
140
+
{ .compatible = "usb451,8140", .data = &ti_tusb8020b_data, },
141
+
{ .compatible = "usb451,8142", .data = &ti_tusb8020b_data, },
142
+
{ .compatible = "usb451,8440", .data = &ti_tusb8020b_data, },
143
+
{ .compatible = "usb451,8442", .data = &ti_tusb8020b_data, },
143
144
{ .compatible = "usb4b4,6504", .data = &cypress_hx3_data, },
144
145
{ .compatible = "usb4b4,6506", .data = &cypress_hx3_data, },
145
-
{ .compatible = "usb4b4,6570", .data = &cypress_hx2vl_data, },
146
+
{ .compatible = "usb4b4,6570", .data = µchip_usb424_data, },
146
147
{ .compatible = "usb5e3,608", .data = &genesys_gl850g_data, },
147
148
{ .compatible = "usb5e3,610", .data = &genesys_gl852g_data, },
148
149
{ .compatible = "usb5e3,620", .data = &genesys_gl852g_data, },
···
152
153
{ .compatible = "usbbda,5411", .data = &realtek_rts5411_data, },
153
154
{ .compatible = "usbbda,414", .data = &realtek_rts5411_data, },
154
155
{ .compatible = "usbbda,5414", .data = &realtek_rts5411_data, },
156
+
{ .compatible = "usb1a40,0101", .data = &vialab_vl817_data, },
155
157
{ .compatible = "usb1a86,8091", .data = &wch_ch334_data, },
156
158
{ .compatible = "usb1da0,5511", .data = ¶de_ps5511_data, },
157
159
{ .compatible = "usb1da0,55a1", .data = ¶de_ps5511_data, },
158
160
{ .compatible = "usb2109,817", .data = &vialab_vl817_data, },
159
161
{ .compatible = "usb2109,2817", .data = &vialab_vl817_data, },
160
162
{ .compatible = "usb20b1,0013", .data = &xmos_xvf3500_data, },
163
+
{ .compatible = "usb3431,6241", .data = &corechips_sl6341_data, },
164
+
{ .compatible = "usb3431,6341", .data = &corechips_sl6341_data, },
161
165
{ .compatible = "usb5986,1198", .data = &bison_intcamera_data, },
162
166
{}
163
167
};
+1
-2
drivers/usb/misc/trancevibrator.c
+1
-2
drivers/usb/misc/trancevibrator.c
···
92
92
goto error;
93
93
}
94
94
95
-
dev->udev = usb_get_dev(udev);
95
+
dev->udev = udev;
96
96
usb_set_intfdata(interface, dev);
97
97
98
98
return 0;
···
108
108
109
109
dev = usb_get_intfdata (interface);
110
110
usb_set_intfdata(interface, NULL);
111
-
usb_put_dev(dev->udev);
112
111
kfree(dev);
113
112
}
114
113
+5
-10
drivers/usb/misc/usb-ljca.c
+5
-10
drivers/usb/misc/usb-ljca.c
···
776
776
init_completion(&adap->cmd_completion);
777
777
INIT_LIST_HEAD(&adap->client_list);
778
778
779
-
adap->intf = usb_get_intf(interface);
779
+
adap->intf = interface;
780
780
adap->usb_dev = usb_dev;
781
781
adap->dev = dev;
782
782
···
787
787
ret = usb_find_common_endpoints(alt, &ep_in, &ep_out, NULL, NULL);
788
788
if (ret) {
789
789
dev_err(dev, "bulk endpoints not found\n");
790
-
goto err_put;
790
+
goto err_destroy_mutex;
791
791
}
792
792
adap->rx_pipe = usb_rcvbulkpipe(usb_dev, usb_endpoint_num(ep_in));
793
793
adap->tx_pipe = usb_sndbulkpipe(usb_dev, usb_endpoint_num(ep_out));
···
797
797
adap->rx_buf = devm_kzalloc(dev, adap->rx_len, GFP_KERNEL);
798
798
if (!adap->rx_buf) {
799
799
ret = -ENOMEM;
800
-
goto err_put;
800
+
goto err_destroy_mutex;
801
801
}
802
802
803
803
/* alloc rx urb */
804
804
adap->rx_urb = usb_alloc_urb(0, GFP_KERNEL);
805
805
if (!adap->rx_urb) {
806
806
ret = -ENOMEM;
807
-
goto err_put;
807
+
goto err_destroy_mutex;
808
808
}
809
809
usb_fill_bulk_urb(adap->rx_urb, usb_dev, adap->rx_pipe,
810
810
adap->rx_buf, adap->rx_len, ljca_recv, adap);
···
836
836
837
837
err_free:
838
838
usb_free_urb(adap->rx_urb);
839
-
840
-
err_put:
841
-
usb_put_intf(adap->intf);
842
-
839
+
err_destroy_mutex:
843
840
mutex_destroy(&adap->mutex);
844
841
845
842
return ret;
···
860
863
}
861
864
862
865
usb_free_urb(adap->rx_urb);
863
-
864
-
usb_put_intf(adap->intf);
865
866
866
867
mutex_destroy(&adap->mutex);
867
868
}
+1
-2
drivers/usb/misc/usbsevseg.c
+1
-2
drivers/usb/misc/usbsevseg.c
···
312
312
if (!mydev)
313
313
goto error_mem;
314
314
315
-
mydev->udev = usb_get_dev(udev);
315
+
mydev->udev = udev;
316
316
mydev->intf = interface;
317
317
usb_set_intfdata(interface, mydev);
318
318
···
338
338
339
339
mydev = usb_get_intfdata(interface);
340
340
usb_set_intfdata(interface, NULL);
341
-
usb_put_dev(mydev->udev);
342
341
kfree(mydev);
343
342
dev_info(&interface->dev, "USB 7 Segment now disconnected\n");
344
343
}
+14
-13
drivers/usb/misc/uss720.c
+14
-13
drivers/usb/misc/uss720.c
···
677
677
struct parport_uss720_private *priv;
678
678
struct parport *pp;
679
679
unsigned char reg;
680
-
int ret;
680
+
int ret = -ENODEV;
681
681
682
682
dev_dbg(&intf->dev, "probe: vendor id 0x%x, device id 0x%x\n",
683
683
le16_to_cpu(usbdev->descriptor.idVendor),
684
684
le16_to_cpu(usbdev->descriptor.idProduct));
685
685
686
686
/* our known interfaces have 3 alternate settings */
687
-
if (intf->num_altsetting != 3) {
688
-
usb_put_dev(usbdev);
689
-
return -ENODEV;
690
-
}
687
+
if (intf->num_altsetting != 3)
688
+
goto bail_out_early;
689
+
691
690
ret = usb_set_interface(usbdev, intf->altsetting->desc.bInterfaceNumber, 2);
692
691
dev_dbg(&intf->dev, "set interface result %d\n", ret);
693
692
694
693
interface = intf->cur_altsetting;
695
694
696
-
if (interface->desc.bNumEndpoints < 2) {
697
-
usb_put_dev(usbdev);
698
-
return -ENODEV;
699
-
}
695
+
if (interface->desc.bNumEndpoints < 2)
696
+
goto bail_out_early;
700
697
701
698
/*
702
699
* Allocate parport interface
703
700
*/
701
+
ret = -ENOMEM;
704
702
priv = kzalloc_obj(struct parport_uss720_private);
705
-
if (!priv) {
706
-
usb_put_dev(usbdev);
707
-
return -ENOMEM;
708
-
}
703
+
if (!priv)
704
+
goto bail_out_early;
705
+
709
706
priv->pp = NULL;
710
707
priv->usbdev = usbdev;
711
708
kref_init(&priv->ref_count);
···
749
752
kill_all_async_requests_priv(priv);
750
753
kref_put(&priv->ref_count, destroy_priv);
751
754
return -ENODEV;
755
+
756
+
bail_out_early:
757
+
usb_put_dev(usbdev);
758
+
return ret;
752
759
}
753
760
754
761
static void uss720_disconnect(struct usb_interface *intf)
+1
-1
drivers/usb/musb/musb_core.c
+1
-1
drivers/usb/musb/musb_core.c
···
1600
1600
/* log core options (read using indexed model) */
1601
1601
reg = musb_read_configdata(mbase);
1602
1602
1603
-
strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1603
+
strscpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1604
1604
if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1605
1605
strcat(aInfo, ", dyn FIFOs");
1606
1606
musb->dyn_fifo = true;
+3
-13
drivers/usb/renesas_usbhs/mod_gadget.c
+3
-13
drivers/usb/renesas_usbhs/mod_gadget.c
···
40
40
struct usb_gadget gadget;
41
41
struct usbhs_mod mod;
42
42
43
-
struct usbhsg_uep *uep;
44
43
int uep_size;
45
44
46
45
struct usb_gadget_driver *driver;
···
52
53
#define USBHSG_STATUS_WEDGE (1 << 2)
53
54
#define USBHSG_STATUS_SELF_POWERED (1 << 3)
54
55
#define USBHSG_STATUS_SOFT_CONNECT (1 << 4)
56
+
struct usbhsg_uep uep[] __counted_by(uep_size);
55
57
};
56
58
57
59
struct usbhsg_recip_handle {
···
1084
1084
int i;
1085
1085
int ret;
1086
1086
1087
-
gpriv = kzalloc_obj(struct usbhsg_gpriv);
1087
+
gpriv = kzalloc_flex(*gpriv, uep, pipe_size);
1088
1088
if (!gpriv)
1089
1089
return -ENOMEM;
1090
1090
1091
-
uep = kzalloc_objs(struct usbhsg_uep, pipe_size);
1092
-
if (!uep) {
1093
-
ret = -ENOMEM;
1094
-
goto usbhs_mod_gadget_probe_err_gpriv;
1095
-
}
1091
+
gpriv->uep_size = pipe_size;
1096
1092
1097
1093
gpriv->transceiver = devm_usb_get_phy(dev, USB_PHY_TYPE_UNDEFINED);
1098
1094
dev_info(dev, "%stransceiver found\n",
···
1111
1115
gpriv->mod.name = "gadget";
1112
1116
gpriv->mod.start = usbhsg_start;
1113
1117
gpriv->mod.stop = usbhsg_stop;
1114
-
gpriv->uep = uep;
1115
-
gpriv->uep_size = pipe_size;
1116
1118
usbhsg_status_init(gpriv);
1117
1119
1118
1120
/*
···
1169
1175
return 0;
1170
1176
1171
1177
err_add_udc:
1172
-
kfree(gpriv->uep);
1173
-
1174
-
usbhs_mod_gadget_probe_err_gpriv:
1175
1178
kfree(gpriv);
1176
1179
1177
1180
return ret;
···
1180
1189
1181
1190
usb_del_gadget_udc(&gpriv->gadget);
1182
1191
1183
-
kfree(gpriv->uep);
1184
1192
kfree(gpriv);
1185
1193
}
+1
-1
drivers/usb/serial/iuu_phoenix.c
+1
-1
drivers/usb/serial/iuu_phoenix.c
+2
drivers/usb/serial/option.c
+2
drivers/usb/serial/option.c
···
1383
1383
.driver_info = NCTRL(2) | RSVD(3) },
1384
1384
{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1073, 0xff), /* Telit FN990A (ECM) */
1385
1385
.driver_info = NCTRL(0) | RSVD(1) },
1386
+
{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1074, 0xff), /* Telit FN990A (MBIM) */
1387
+
.driver_info = NCTRL(5) | RSVD(6) | RSVD(7) },
1386
1388
{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1075, 0xff), /* Telit FN990A (PCIe) */
1387
1389
.driver_info = RSVD(0) },
1388
1390
{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1077, 0xff), /* Telit FN990A (rmnet + audio) */
+8
-8
drivers/usb/serial/ti_usb_3410_5052.c
+8
-8
drivers/usb/serial/ti_usb_3410_5052.c
···
1600
1600
if (le16_to_cpu(dev->descriptor.idVendor) == MTS_VENDOR_ID) {
1601
1601
switch (le16_to_cpu(dev->descriptor.idProduct)) {
1602
1602
case MTS_CDMA_PRODUCT_ID:
1603
-
strcpy(buf, "mts_cdma.fw");
1603
+
strscpy(buf, "mts_cdma.fw");
1604
1604
break;
1605
1605
case MTS_GSM_PRODUCT_ID:
1606
-
strcpy(buf, "mts_gsm.fw");
1606
+
strscpy(buf, "mts_gsm.fw");
1607
1607
break;
1608
1608
case MTS_EDGE_PRODUCT_ID:
1609
-
strcpy(buf, "mts_edge.fw");
1609
+
strscpy(buf, "mts_edge.fw");
1610
1610
break;
1611
1611
case MTS_MT9234MU_PRODUCT_ID:
1612
-
strcpy(buf, "mts_mt9234mu.fw");
1612
+
strscpy(buf, "mts_mt9234mu.fw");
1613
1613
break;
1614
1614
case MTS_MT9234ZBA_PRODUCT_ID:
1615
-
strcpy(buf, "mts_mt9234zba.fw");
1615
+
strscpy(buf, "mts_mt9234zba.fw");
1616
1616
break;
1617
1617
case MTS_MT9234ZBAOLD_PRODUCT_ID:
1618
-
strcpy(buf, "mts_mt9234zba.fw");
1618
+
strscpy(buf, "mts_mt9234zba.fw");
1619
1619
break; }
1620
1620
}
1621
1621
if (buf[0] == '\0') {
1622
1622
if (tdev->td_is_3410)
1623
-
strcpy(buf, "ti_3410.fw");
1623
+
strscpy(buf, "ti_3410.fw");
1624
1624
else
1625
-
strcpy(buf, "ti_5052.fw");
1625
+
strscpy(buf, "ti_5052.fw");
1626
1626
}
1627
1627
status = request_firmware(&fw_p, buf, &dev->dev);
1628
1628
}
+2
-2
drivers/usb/storage/uas.c
+2
-2
drivers/usb/storage/uas.c
···
772
772
return FAILED;
773
773
}
774
774
775
-
static int uas_eh_device_reset_handler(struct scsi_cmnd *cmnd)
775
+
static int uas_eh_host_reset_handler(struct scsi_cmnd *cmnd)
776
776
{
777
777
struct scsi_device *sdev = cmnd->device;
778
778
struct uas_dev_info *devinfo = sdev->hostdata;
···
918
918
.sdev_init = uas_sdev_init,
919
919
.sdev_configure = uas_sdev_configure,
920
920
.eh_abort_handler = uas_eh_abort_handler,
921
-
.eh_device_reset_handler = uas_eh_device_reset_handler,
921
+
.eh_host_reset_handler = uas_eh_host_reset_handler,
922
922
.this_id = -1,
923
923
.skip_settle_delay = 1,
924
924
/*
+4
-3
drivers/usb/storage/unusual_devs.h
+4
-3
drivers/usb/storage/unusual_devs.h
···
2350
2350
US_FL_SCM_MULT_TARG ),
2351
2351
2352
2352
/*
2353
-
* Reported by DocMAX <mail@vacharakis.de>
2354
-
* and Thomas Weißschuh <linux@weissschuh.net>
2353
+
* Reported by DocMAX <mail@vacharakis.de>,
2354
+
* Thomas Weißschuh <linux@weissschuh.net>
2355
+
* and Daniel Brát <danek.brat@gmail.com>
2355
2356
*/
2356
-
UNUSUAL_DEV( 0x2109, 0x0715, 0x9999, 0x9999,
2357
+
UNUSUAL_DEV( 0x2109, 0x0715, 0x0000, 0x9999,
2357
2358
"VIA Labs, Inc.",
2358
2359
"VL817 SATA Bridge",
2359
2360
USB_SC_DEVICE, USB_PR_DEVICE, NULL,
+23
-2
drivers/usb/typec/mux.c
+23
-2
drivers/usb/typec/mux.c
···
35
35
static void *typec_switch_match(const struct fwnode_handle *fwnode,
36
36
const char *id, void *data)
37
37
{
38
+
struct typec_switch_dev **sw_devs = data;
38
39
struct device *dev;
40
+
int i;
39
41
40
42
/*
41
43
* Device graph (OF graph) does not give any means to identify the
···
57
55
*/
58
56
dev = class_find_device(&typec_mux_class, NULL, fwnode,
59
57
switch_fwnode_match);
58
+
59
+
/* Skip duplicates */
60
+
for (i = 0; i < TYPEC_MUX_MAX_DEVS; i++)
61
+
if (to_typec_switch_dev(dev) == sw_devs[i]) {
62
+
put_device(dev);
63
+
return NULL;
64
+
}
60
65
61
66
return dev ? to_typec_switch_dev(dev) : ERR_PTR(-EPROBE_DEFER);
62
67
}
···
89
80
if (!sw)
90
81
return ERR_PTR(-ENOMEM);
91
82
92
-
count = fwnode_connection_find_matches(fwnode, "orientation-switch", NULL,
83
+
count = fwnode_connection_find_matches(fwnode, "orientation-switch",
84
+
(void **)sw_devs,
93
85
typec_switch_match,
94
86
(void **)sw_devs,
95
87
ARRAY_SIZE(sw_devs));
···
275
265
static void *typec_mux_match(const struct fwnode_handle *fwnode,
276
266
const char *id, void *data)
277
267
{
268
+
struct typec_mux_dev **mux_devs = data;
278
269
struct device *dev;
270
+
int i;
279
271
280
272
/*
281
273
* Device graph (OF graph) does not give any means to identify the
···
292
280
293
281
dev = class_find_device(&typec_mux_class, NULL, fwnode,
294
282
mux_fwnode_match);
283
+
284
+
/* Skip duplicates */
285
+
for (i = 0; i < TYPEC_MUX_MAX_DEVS; i++)
286
+
if (to_typec_mux_dev(dev) == mux_devs[i]) {
287
+
put_device(dev);
288
+
return NULL;
289
+
}
290
+
295
291
296
292
return dev ? to_typec_mux_dev(dev) : ERR_PTR(-EPROBE_DEFER);
297
293
}
···
326
306
return ERR_PTR(-ENOMEM);
327
307
328
308
count = fwnode_connection_find_matches(fwnode, "mode-switch",
329
-
NULL, typec_mux_match,
309
+
(void **)mux_devs,
310
+
typec_mux_match,
330
311
(void **)mux_devs,
331
312
ARRAY_SIZE(mux_devs));
332
313
if (count <= 0) {
+1
drivers/usb/typec/mux/ps883x.c
+1
drivers/usb/typec/mux/ps883x.c
+2
drivers/usb/typec/tcpm/Kconfig
+2
drivers/usb/typec/tcpm/Kconfig
···
58
58
tristate "Fairchild FUSB302 Type-C chip driver"
59
59
depends on I2C
60
60
depends on EXTCON || !EXTCON
61
+
depends on DRM || DRM=n
62
+
select DRM_AUX_HPD_BRIDGE if DRM_BRIDGE && OF
61
63
help
62
64
The Fairchild FUSB302 Type-C chip driver that works with
63
65
Type-C Port Controller Manager to provide USB PD and USB
+16
-2
drivers/usb/typec/tcpm/fusb302.c
+16
-2
drivers/usb/typec/tcpm/fusb302.c
···
5
5
* Fairchild FUSB302 Type-C Chip Driver
6
6
*/
7
7
8
+
#include <drm/bridge/aux-bridge.h>
8
9
#include <linux/debugfs.h>
9
10
#include <linux/delay.h>
10
11
#include <linux/errno.h>
···
1690
1689
{
1691
1690
struct fusb302_chip *chip;
1692
1691
struct i2c_adapter *adapter = client->adapter;
1692
+
struct auxiliary_device *bridge_dev;
1693
1693
struct device *dev = &client->dev;
1694
1694
const char *name;
1695
1695
int ret = 0;
···
1749
1747
goto destroy_workqueue;
1750
1748
}
1751
1749
1750
+
bridge_dev = devm_drm_dp_hpd_bridge_alloc(chip->dev, to_of_node(chip->tcpc_dev.fwnode));
1751
+
if (IS_ERR(bridge_dev)) {
1752
+
ret = PTR_ERR(bridge_dev);
1753
+
dev_err_probe(chip->dev, ret, "failed to alloc bridge\n");
1754
+
goto destroy_workqueue;
1755
+
}
1756
+
1752
1757
chip->tcpm_port = tcpm_register_port(&client->dev, &chip->tcpc_dev);
1753
1758
if (IS_ERR(chip->tcpm_port)) {
1754
1759
fwnode_handle_put(chip->tcpc_dev.fwnode);
···
1764
1755
goto destroy_workqueue;
1765
1756
}
1766
1757
1767
-
ret = request_irq(chip->gpio_int_n_irq, fusb302_irq_intn,
1768
-
IRQF_TRIGGER_LOW, "fsc_interrupt_int_n", chip);
1758
+
ret = request_threaded_irq(chip->gpio_int_n_irq, NULL, fusb302_irq_intn,
1759
+
IRQF_ONESHOT | IRQF_TRIGGER_LOW,
1760
+
"fsc_interrupt_int_n", chip);
1769
1761
if (ret < 0) {
1770
1762
dev_err(dev, "cannot request IRQ for GPIO Int_N, ret=%d", ret);
1771
1763
goto tcpm_unregister_port;
1772
1764
}
1773
1765
enable_irq_wake(chip->gpio_int_n_irq);
1774
1766
i2c_set_clientdata(client, chip);
1767
+
1768
+
ret = devm_drm_dp_hpd_bridge_add(chip->dev, bridge_dev);
1769
+
if (ret)
1770
+
return ret;
1775
1771
1776
1772
return ret;
1777
1773
+19
-1
drivers/usb/typec/tcpm/tcpci.c
+19
-1
drivers/usb/typec/tcpm/tcpci.c
···
7
7
8
8
#include <linux/bitfield.h>
9
9
#include <linux/delay.h>
10
+
#include <linux/gpio/consumer.h>
10
11
#include <linux/kernel.h>
11
12
#include <linux/module.h>
12
13
#include <linux/i2c.h>
···
43
42
44
43
struct tcpc_dev tcpc;
45
44
struct tcpci_data *data;
45
+
struct gpio_desc *orientation_gpio;
46
46
};
47
47
48
48
struct tcpci_chip {
···
317
315
{
318
316
struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
319
317
unsigned int reg;
318
+
319
+
if (tcpci->orientation_gpio)
320
+
return gpiod_set_value_cansleep(tcpci->orientation_gpio,
321
+
orientation != TYPEC_ORIENTATION_NORMAL);
320
322
321
323
switch (orientation) {
322
324
case TYPEC_ORIENTATION_NONE:
···
909
903
static int tcpci_probe(struct i2c_client *client)
910
904
{
911
905
struct tcpci_chip *chip;
906
+
struct gpio_desc *orient_gpio = NULL;
912
907
int err;
913
908
u16 val = 0;
914
909
···
938
931
if (err < 0)
939
932
return err;
940
933
934
+
if (err == 0) {
935
+
orient_gpio = devm_gpiod_get_optional(&client->dev, "orientation",
936
+
GPIOD_OUT_LOW);
937
+
if (IS_ERR(orient_gpio))
938
+
return dev_err_probe(&client->dev, PTR_ERR(orient_gpio),
939
+
"unable to acquire orientation gpio\n");
940
+
err = !!orient_gpio;
941
+
}
942
+
941
943
chip->data.set_orientation = err;
942
944
943
945
chip->tcpci = tcpci_register_port(&client->dev, &chip->data);
944
946
if (IS_ERR(chip->tcpci))
945
947
return PTR_ERR(chip->tcpci);
948
+
949
+
chip->tcpci->orientation_gpio = orient_gpio;
946
950
947
951
err = devm_request_threaded_irq(&client->dev, client->irq, NULL,
948
952
_tcpci_irq,
···
1017
999
return ret;
1018
1000
}
1019
1001
1020
-
DEFINE_SIMPLE_DEV_PM_OPS(tcpci_pm_ops, tcpci_suspend, tcpci_resume);
1002
+
static DEFINE_SIMPLE_DEV_PM_OPS(tcpci_pm_ops, tcpci_suspend, tcpci_resume);
1021
1003
1022
1004
static const struct i2c_device_id tcpci_id[] = {
1023
1005
{ "tcpci" },
+1
drivers/usb/typec/tcpm/tcpci_maxim.h
+1
drivers/usb/typec/tcpm/tcpci_maxim.h
+33
-21
drivers/usb/typec/tcpm/tcpci_maxim_core.c
+33
-21
drivers/usb/typec/tcpm/tcpci_maxim_core.c
···
10
10
#include <linux/kernel.h>
11
11
#include <linux/module.h>
12
12
#include <linux/regmap.h>
13
+
#include <linux/regulator/consumer.h>
13
14
#include <linux/usb/pd.h>
14
15
#include <linux/usb/tcpci.h>
15
16
#include <linux/usb/tcpm.h>
···
35
34
* less than or equal to 31. Since, RECEIVE_BUFFER len = 31 + 1(READABLE_BYTE_COUNT).
36
35
*/
37
36
#define TCPC_RECEIVE_BUFFER_LEN 32
38
-
39
-
#define MAX_BUCK_BOOST_SID 0x69
40
-
#define MAX_BUCK_BOOST_OP 0xb9
41
-
#define MAX_BUCK_BOOST_OFF 0
42
-
#define MAX_BUCK_BOOST_SOURCE 0xa
43
-
#define MAX_BUCK_BOOST_SINK 0x5
44
37
45
38
static const struct regmap_range max_tcpci_tcpci_range[] = {
46
39
regmap_reg_range(0x00, 0x95)
···
197
202
tcpm_pd_receive(chip->port, &msg, rx_type);
198
203
}
199
204
205
+
static int get_vbus_regulator_handle(struct max_tcpci_chip *chip)
206
+
{
207
+
if (IS_ERR_OR_NULL(chip->vbus_reg)) {
208
+
chip->vbus_reg = devm_regulator_get_exclusive(chip->dev,
209
+
"vbus");
210
+
if (IS_ERR_OR_NULL(chip->vbus_reg)) {
211
+
dev_err(chip->dev,
212
+
"Failed to get vbus regulator handle\n");
213
+
return -ENODEV;
214
+
}
215
+
}
216
+
217
+
return 0;
218
+
}
219
+
200
220
static int max_tcpci_set_vbus(struct tcpci *tcpci, struct tcpci_data *tdata, bool source, bool sink)
201
221
{
202
222
struct max_tcpci_chip *chip = tdata_to_max_tcpci(tdata);
203
-
u8 buffer_source[2] = {MAX_BUCK_BOOST_OP, MAX_BUCK_BOOST_SOURCE};
204
-
u8 buffer_sink[2] = {MAX_BUCK_BOOST_OP, MAX_BUCK_BOOST_SINK};
205
-
u8 buffer_none[2] = {MAX_BUCK_BOOST_OP, MAX_BUCK_BOOST_OFF};
206
-
struct i2c_client *i2c = chip->client;
207
223
int ret;
208
-
209
-
struct i2c_msg msgs[] = {
210
-
{
211
-
.addr = MAX_BUCK_BOOST_SID,
212
-
.flags = i2c->flags & I2C_M_TEN,
213
-
.len = 2,
214
-
.buf = source ? buffer_source : sink ? buffer_sink : buffer_none,
215
-
},
216
-
};
217
224
218
225
if (source && sink) {
219
226
dev_err(chip->dev, "Both source and sink set\n");
220
227
return -EINVAL;
221
228
}
222
229
223
-
ret = i2c_transfer(i2c->adapter, msgs, 1);
230
+
ret = get_vbus_regulator_handle(chip);
231
+
if (ret) {
232
+
/*
233
+
* Regulator is not necessary for sink only applications. Return
234
+
* success in cases where sink mode is being modified.
235
+
*/
236
+
return source ? ret : 1;
237
+
}
224
238
225
-
return ret < 0 ? ret : 1;
239
+
if (source) {
240
+
if (!regulator_is_enabled(chip->vbus_reg))
241
+
ret = regulator_enable(chip->vbus_reg);
242
+
} else {
243
+
if (regulator_is_enabled(chip->vbus_reg))
244
+
ret = regulator_disable(chip->vbus_reg);
245
+
}
246
+
247
+
return ret < 0 ? ret : 1;
226
248
}
227
249
228
250
static void process_power_status(struct max_tcpci_chip *chip)
+2
-43
drivers/usb/typec/tcpm/tcpci_rt1711h.c
+2
-43
drivers/usb/typec/tcpm/tcpci_rt1711h.c
···
18
18
#include <linux/regmap.h>
19
19
#include <linux/regulator/consumer.h>
20
20
21
-
#define RT1711H_VID 0x29CF
22
-
#define RT1711H_PID 0x1711
23
-
#define RT1711H_DID 0x2171
24
-
#define RT1715_DID 0x2173
25
-
26
21
#define RT1711H_PHYCTRL1 0x80
27
22
#define RT1711H_PHYCTRL2 0x81
28
23
···
50
55
51
56
struct rt1711h_chip_info {
52
57
u32 rxdz_sel;
53
-
u16 did;
54
58
bool enable_pd30_extended_message;
55
59
};
56
60
···
295
301
return 0;
296
302
}
297
303
298
-
static int rt1711h_check_revision(struct i2c_client *i2c, struct rt1711h_chip *chip)
299
-
{
300
-
int ret;
301
-
302
-
ret = i2c_smbus_read_word_data(i2c, TCPC_VENDOR_ID);
303
-
if (ret < 0)
304
-
return ret;
305
-
if (ret != RT1711H_VID) {
306
-
dev_err(&i2c->dev, "vid is not correct, 0x%04x\n", ret);
307
-
return -ENODEV;
308
-
}
309
-
ret = i2c_smbus_read_word_data(i2c, TCPC_PRODUCT_ID);
310
-
if (ret < 0)
311
-
return ret;
312
-
if (ret != RT1711H_PID) {
313
-
dev_err(&i2c->dev, "pid is not correct, 0x%04x\n", ret);
314
-
return -ENODEV;
315
-
}
316
-
ret = i2c_smbus_read_word_data(i2c, TCPC_BCD_DEV);
317
-
if (ret < 0)
318
-
return ret;
319
-
if (ret != chip->info->did) {
320
-
dev_err(&i2c->dev, "did is not correct, 0x%04x\n", ret);
321
-
return -ENODEV;
322
-
}
323
-
dev_dbg(&i2c->dev, "did is 0x%04x\n", ret);
324
-
return ret;
325
-
}
326
-
327
304
static int rt1711h_probe(struct i2c_client *client)
328
305
{
329
306
int ret;
···
310
345
return -ENOMEM;
311
346
312
347
chip->info = i2c_get_match_data(client);
313
-
314
-
ret = rt1711h_check_revision(client, chip);
315
-
if (ret < 0) {
316
-
dev_err(&client->dev, "check vid/pid fail\n");
317
-
return ret;
318
-
}
319
348
320
349
chip->data.regmap = devm_regmap_init_i2c(client,
321
350
&rt1711h_regmap_config);
···
365
406
}
366
407
367
408
static const struct rt1711h_chip_info rt1711h = {
368
-
.did = RT1711H_DID,
369
409
};
370
410
371
411
static const struct rt1711h_chip_info rt1715 = {
372
412
.rxdz_sel = RT1711H_BMCIO_RXDZSEL,
373
-
.did = RT1715_DID,
374
413
.enable_pd30_extended_message = true,
375
414
};
376
415
377
416
static const struct i2c_device_id rt1711h_id[] = {
417
+
{ "et7304", (kernel_ulong_t)&rt1715 },
378
418
{ "rt1711h", (kernel_ulong_t)&rt1711h },
379
419
{ "rt1715", (kernel_ulong_t)&rt1715 },
380
420
{}
···
381
423
MODULE_DEVICE_TABLE(i2c, rt1711h_id);
382
424
383
425
static const struct of_device_id rt1711h_of_match[] = {
426
+
{ .compatible = "etekmicro,et7304", .data = &rt1715 },
384
427
{ .compatible = "richtek,rt1711h", .data = &rt1711h },
385
428
{ .compatible = "richtek,rt1715", .data = &rt1715 },
386
429
{}
+767
-122
drivers/usb/typec/tcpm/tcpm.c
+767
-122
drivers/usb/typec/tcpm/tcpm.c
···
12
12
#include <linux/jiffies.h>
13
13
#include <linux/kernel.h>
14
14
#include <linux/kthread.h>
15
+
#include <linux/minmax.h>
15
16
#include <linux/module.h>
16
17
#include <linux/mutex.h>
17
18
#include <linux/power_supply.h>
···
62
61
S(SNK_WAIT_CAPABILITIES_TIMEOUT), \
63
62
S(SNK_NEGOTIATE_CAPABILITIES), \
64
63
S(SNK_NEGOTIATE_PPS_CAPABILITIES), \
64
+
S(SNK_NEGOTIATE_SPR_AVS_CAPABILITIES), \
65
65
S(SNK_TRANSITION_SINK), \
66
66
S(SNK_TRANSITION_SINK_VBUS), \
67
67
S(SNK_READY), \
···
190
188
S(STRUCTURED_VDMS), \
191
189
S(COUNTRY_INFO), \
192
190
S(COUNTRY_CODES), \
193
-
S(REVISION_INFORMATION)
191
+
S(REVISION_INFORMATION), \
192
+
S(GETTING_SINK_EXTENDED_CAPABILITIES)
194
193
195
194
#define GENERATE_ENUM(e) e
196
195
#define GENERATE_STRING(s) #s
···
232
229
PD_MSG_DATA_SINK_CAP,
233
230
PD_MSG_DATA_SOURCE_CAP,
234
231
PD_MSG_DATA_REV,
232
+
PD_MSG_EXT_SINK_CAP_EXT
235
233
};
236
234
237
235
enum adev_actions {
···
309
305
bool active;
310
306
};
311
307
308
+
enum spr_avs_status {
309
+
SPR_AVS_UNKNOWN,
310
+
SPR_AVS_NOT_SUPPORTED,
311
+
SPR_AVS_SUPPORTED
312
+
};
313
+
314
+
static const char * const spr_avs_status_strings[] = {
315
+
[SPR_AVS_UNKNOWN] = "Unknown",
316
+
[SPR_AVS_SUPPORTED] = "Supported",
317
+
[SPR_AVS_NOT_SUPPORTED] = "Not Supported",
318
+
};
319
+
320
+
/*
321
+
* Standard Power Range Adjustable Voltage Supply (SPR - AVS) data
322
+
* @max_current_ma_9v_to_15v: Max current for 9V to 15V range derived from
323
+
* source cap & sink cap
324
+
* @max_current_ma_15v_to_20v: Max current for 15V to 20V range derived from
325
+
* source cap & sink cap
326
+
* @req_op_curr_ma: Requested operating current to the port partner acting as source
327
+
* @req_out_volt_mv: Requested output voltage to the port partner acting as source
328
+
* @max_out_volt_mv: Max SPR voltage supported by the port and the port partner
329
+
* @max_current_ma; MAX SPR current supported by the port and the port partner
330
+
* @port_partner_src_status: SPR AVS status of port partner acting as source
331
+
* @port_partner_src_pdo_index: PDO index of SPR AVS cap of the port partner
332
+
* acting as source. Valid only when
333
+
* port_partner_src_status is SPR_AVS_SUPPORTED.
334
+
* @port_snk_status: SPR AVS status of the local port acting as sink.
335
+
* @port_snk_pdo_index: PDO index of SPR AVS cap of local port acting as sink
336
+
* @active: True when the local port acting as the sink has negotiated SPR AVS
337
+
* with the partner acting as source.
338
+
*/
339
+
struct pd_spr_avs_data {
340
+
u32 max_current_ma_9v_to_15v;
341
+
u32 max_current_ma_15v_to_20v;
342
+
u32 req_op_curr_ma;
343
+
u32 req_out_volt_mv;
344
+
u32 max_out_volt_mv;
345
+
u32 max_current_ma;
346
+
enum spr_avs_status port_partner_src_status;
347
+
unsigned int port_partner_src_pdo_index;
348
+
enum spr_avs_status port_snk_status;
349
+
unsigned int port_snk_pdo_index;
350
+
bool active;
351
+
};
352
+
312
353
struct pd_data {
313
354
struct usb_power_delivery *pd;
314
355
struct usb_power_delivery_capabilities *source_cap;
···
384
335
u32 ps_src_off_time;
385
336
u32 cc_debounce_time;
386
337
u32 snk_bc12_cmpletion_time;
338
+
};
339
+
340
+
/* Convert microwatt to watt */
341
+
#define UW_TO_W(pow) ((pow) / 1000000)
342
+
343
+
/*
344
+
* struct pd_identifier - Contains info about PD identifiers
345
+
* @vid: Vendor ID (assigned by USB-IF)
346
+
* @pid: Product ID (assigned by manufacturer)
347
+
* @xid: Value assigned by USB-IF for product
348
+
*/
349
+
struct pd_identifier {
350
+
u16 vid;
351
+
u16 pid;
352
+
u32 xid;
353
+
};
354
+
355
+
/*
356
+
* struct sink_caps_ext_data - Sink extended capability data
357
+
* @load_step: Indicates the load step slew rate. Value of 0 indicates 150mA/us
358
+
* & 1 indicates 500 mA/us
359
+
* @load_char: Snk overload characteristics
360
+
* @compliance: Types of sources the sink has been tested & certified on
361
+
* @modes: Charging caps & power sources supported
362
+
* @spr_min_pdp: Sink Minimum PDP for SPR mode (in Watts)
363
+
* @spr_op_pdp: Sink Operational PDP for SPR mode (in Watts)
364
+
* @spr_max_pdp: Sink Maximum PDP for SPR mode (in Watts)
365
+
*/
366
+
struct sink_caps_ext_data {
367
+
u8 load_step;
368
+
u16 load_char;
369
+
u8 compliance;
370
+
u8 modes;
371
+
u8 spr_min_pdp;
372
+
u8 spr_op_pdp;
373
+
u8 spr_max_pdp;
374
+
};
375
+
376
+
enum aug_req_type {
377
+
PD_PPS,
378
+
PD_SPR_AVS,
387
379
};
388
380
389
381
struct tcpm_port {
···
589
499
590
500
/* PPS */
591
501
struct pd_pps_data pps_data;
592
-
struct completion pps_complete;
593
-
bool pps_pending;
594
-
int pps_status;
502
+
503
+
/* SPR AVS */
504
+
struct pd_spr_avs_data spr_avs_data;
505
+
506
+
/* Augmented supply request - PPS; SPR_AVS */
507
+
struct completion aug_supply_req_complete;
508
+
bool aug_supply_req_pending;
509
+
int aug_supply_req_status;
595
510
596
511
/* Alternate mode data */
597
512
struct pd_mode_data mode_data;
···
680
585
681
586
/* Indicates maximum (revision, version) supported */
682
587
struct pd_revision_info pd_rev;
588
+
589
+
struct pd_identifier pd_ident;
590
+
struct sink_caps_ext_data sink_caps_ext;
683
591
#ifdef CONFIG_DEBUG_FS
684
592
struct dentry *dentry;
685
593
struct mutex logbuffer_lock; /* log buffer access lock */
···
703
605
struct kthread_work work;
704
606
struct tcpm_port *port;
705
607
u32 header;
706
-
u32 *data;
707
608
int cnt;
708
609
enum tcpm_transmit_type tx_sop_type;
610
+
u32 data[] __counted_by(cnt);
709
611
};
710
612
711
613
static const char * const pd_rev[] = {
···
823
725
824
726
if (tcpm_log_full(port)) {
825
727
port->logbuffer_head = max(port->logbuffer_head - 1, 0);
826
-
strcpy(tmpbuffer, "overflow");
728
+
strscpy(tmpbuffer, "overflow");
827
729
}
828
730
829
731
if (port->logbuffer_head < 0 ||
···
939
841
pdo_spr_avs_apdo_15v_to_20v_max_current_ma(pdo),
940
842
pdo_spr_avs_apdo_src_peak_current(pdo));
941
843
else
942
-
strcpy(msg, "undefined APDO");
844
+
strscpy(msg, "undefined APDO");
943
845
break;
944
846
default:
945
-
strcpy(msg, "undefined");
847
+
strscpy(msg, "undefined");
946
848
break;
947
849
}
948
850
tcpm_log(port, " PDO %d: type %d, %s",
···
1465
1367
return tcpm_pd_transmit(port, TCPC_TX_SOP, &msg);
1466
1368
}
1467
1369
1370
+
static int tcpm_pd_send_sink_cap_ext(struct tcpm_port *port)
1371
+
{
1372
+
u16 operating_snk_watt = port->operating_snk_mw / 1000;
1373
+
struct sink_caps_ext_data *data = &port->sink_caps_ext;
1374
+
struct pd_identifier *pd_ident = &port->pd_ident;
1375
+
struct sink_caps_ext_msg skedb = {0};
1376
+
struct pd_message msg;
1377
+
u8 data_obj_cnt;
1378
+
1379
+
if (!port->self_powered)
1380
+
data->spr_op_pdp = operating_snk_watt;
1381
+
1382
+
/*
1383
+
* SPR Sink Minimum PDP indicates the minimum power required to operate
1384
+
* a sink device in its lowest level of functionality without requiring
1385
+
* power from the battery. We can use the operating_snk_watt value to
1386
+
* populate it, as operating_snk_watt indicates device's min operating
1387
+
* power.
1388
+
*/
1389
+
data->spr_min_pdp = operating_snk_watt;
1390
+
1391
+
if (data->spr_op_pdp < data->spr_min_pdp ||
1392
+
data->spr_max_pdp < data->spr_op_pdp) {
1393
+
tcpm_log(port,
1394
+
"Invalid PDP values, Min PDP:%u, Op PDP:%u, Max PDP:%u",
1395
+
data->spr_min_pdp, data->spr_op_pdp, data->spr_max_pdp);
1396
+
return -EOPNOTSUPP;
1397
+
}
1398
+
1399
+
memset(&msg, 0, sizeof(msg));
1400
+
skedb.vid = cpu_to_le16(pd_ident->vid);
1401
+
skedb.pid = cpu_to_le16(pd_ident->pid);
1402
+
skedb.xid = cpu_to_le32(pd_ident->xid);
1403
+
skedb.skedb_ver = SKEDB_VER_1_0;
1404
+
skedb.load_step = data->load_step;
1405
+
skedb.load_char = cpu_to_le16(data->load_char);
1406
+
skedb.compliance = data->compliance;
1407
+
skedb.modes = data->modes;
1408
+
skedb.spr_min_pdp = data->spr_min_pdp;
1409
+
skedb.spr_op_pdp = data->spr_op_pdp;
1410
+
skedb.spr_max_pdp = data->spr_max_pdp;
1411
+
memcpy(msg.ext_msg.data, &skedb, sizeof(skedb));
1412
+
msg.ext_msg.header = PD_EXT_HDR_LE(sizeof(skedb),
1413
+
0, /* Denotes if request chunk */
1414
+
0, /* Chunk Number */
1415
+
1 /* Chunked */);
1416
+
1417
+
data_obj_cnt = count_chunked_data_objs(sizeof(skedb));
1418
+
msg.header = cpu_to_le16(PD_HEADER(PD_EXT_SINK_CAP_EXT,
1419
+
port->pwr_role,
1420
+
port->data_role,
1421
+
port->negotiated_rev,
1422
+
port->message_id,
1423
+
data_obj_cnt,
1424
+
1 /* Denotes if ext header */));
1425
+
return tcpm_pd_transmit(port, TCPC_TX_SOP, &msg);
1426
+
}
1427
+
1468
1428
static void mod_tcpm_delayed_work(struct tcpm_port *port, unsigned int delay_ms)
1469
1429
{
1470
1430
if (delay_ms) {
···
1809
1653
tcpm_queue_vdm(port, event->header, event->data, event->cnt, event->tx_sop_type);
1810
1654
1811
1655
port_unlock:
1812
-
kfree(event->data);
1813
1656
kfree(event);
1814
1657
mutex_unlock(&port->lock);
1815
1658
}
···
1817
1662
const u32 *data, int cnt, enum tcpm_transmit_type tx_sop_type)
1818
1663
{
1819
1664
struct altmode_vdm_event *event;
1820
-
u32 *data_cpy;
1821
1665
int ret = -ENOMEM;
1822
1666
1823
-
event = kzalloc_obj(*event);
1667
+
event = kzalloc_flex(*event, data, cnt);
1824
1668
if (!event)
1825
1669
goto err_event;
1826
1670
1827
-
data_cpy = kcalloc(cnt, sizeof(u32), GFP_KERNEL);
1828
-
if (!data_cpy)
1829
-
goto err_data;
1830
-
1831
1671
kthread_init_work(&event->work, tcpm_queue_vdm_work);
1672
+
event->cnt = cnt;
1832
1673
event->port = port;
1833
1674
event->header = header;
1834
-
memcpy(data_cpy, data, sizeof(u32) * cnt);
1835
-
event->data = data_cpy;
1836
-
event->cnt = cnt;
1675
+
memcpy(event->data, data, sizeof(u32) * cnt);
1837
1676
event->tx_sop_type = tx_sop_type;
1838
1677
1839
1678
ret = kthread_queue_work(port->wq, &event->work);
1840
1679
if (!ret) {
1841
1680
ret = -EBUSY;
1842
-
goto err_queue;
1681
+
goto err_data;
1843
1682
}
1844
1683
1845
1684
return 0;
1846
1685
1847
-
err_queue:
1848
-
kfree(data_cpy);
1849
1686
err_data:
1850
1687
kfree(event);
1851
1688
err_event:
···
3341
3194
3342
3195
switch (type) {
3343
3196
case PD_DATA_SOURCE_CAP:
3197
+
port->spr_avs_data.port_partner_src_status = SPR_AVS_UNKNOWN;
3344
3198
for (i = 0; i < cnt; i++)
3345
3199
port->source_caps[i] = le32_to_cpu(msg->payload[i]);
3346
3200
···
3513
3365
}
3514
3366
}
3515
3367
3516
-
static void tcpm_pps_complete(struct tcpm_port *port, int result)
3368
+
static void tcpm_aug_supply_req_complete(struct tcpm_port *port, int result)
3517
3369
{
3518
-
if (port->pps_pending) {
3519
-
port->pps_status = result;
3520
-
port->pps_pending = false;
3521
-
complete(&port->pps_complete);
3370
+
if (port->aug_supply_req_pending) {
3371
+
port->aug_supply_req_status = result;
3372
+
port->aug_supply_req_pending = false;
3373
+
complete(&port->aug_supply_req_complete);
3522
3374
}
3523
3375
}
3524
3376
···
3616
3468
/* Revert data back from any requested PPS updates */
3617
3469
port->pps_data.req_out_volt = port->supply_voltage;
3618
3470
port->pps_data.req_op_curr = port->current_limit;
3619
-
port->pps_status = (type == PD_CTRL_WAIT ?
3471
+
port->aug_supply_req_status = (type == PD_CTRL_WAIT ?
3620
3472
-EAGAIN : -EOPNOTSUPP);
3621
3473
3622
3474
/* Threshold was relaxed before sending Request. Restore it back. */
3623
3475
tcpm_set_auto_vbus_discharge_threshold(port, TYPEC_PWR_MODE_PD,
3624
3476
port->pps_data.active,
3477
+
port->supply_voltage);
3478
+
3479
+
tcpm_set_state(port, SNK_READY, 0);
3480
+
break;
3481
+
case SNK_NEGOTIATE_SPR_AVS_CAPABILITIES:
3482
+
/* Revert data back from any requested SPR AVS updates */
3483
+
port->spr_avs_data.req_out_volt_mv = port->supply_voltage;
3484
+
port->spr_avs_data.req_op_curr_ma = port->current_limit;
3485
+
port->aug_supply_req_status = (type == PD_CTRL_WAIT ?
3486
+
-EAGAIN : -EOPNOTSUPP);
3487
+
3488
+
/* Threshold was relaxed before sending Request. Restore it back. */
3489
+
tcpm_set_auto_vbus_discharge_threshold(port, TYPEC_PWR_MODE_PD,
3490
+
port->spr_avs_data.active,
3625
3491
port->supply_voltage);
3626
3492
3627
3493
tcpm_set_state(port, SNK_READY, 0);
···
3692
3530
switch (port->state) {
3693
3531
case SNK_NEGOTIATE_CAPABILITIES:
3694
3532
port->pps_data.active = false;
3533
+
port->spr_avs_data.active = false;
3695
3534
tcpm_set_state(port, SNK_TRANSITION_SINK, 0);
3696
3535
break;
3697
3536
case SNK_NEGOTIATE_PPS_CAPABILITIES:
···
3702
3539
port->pps_data.max_curr = port->pps_data.req_max_curr;
3703
3540
port->req_supply_voltage = port->pps_data.req_out_volt;
3704
3541
port->req_current_limit = port->pps_data.req_op_curr;
3542
+
power_supply_changed(port->psy);
3543
+
tcpm_set_state(port, SNK_TRANSITION_SINK, 0);
3544
+
break;
3545
+
case SNK_NEGOTIATE_SPR_AVS_CAPABILITIES:
3546
+
port->spr_avs_data.active = true;
3547
+
port->req_supply_voltage = port->spr_avs_data.req_out_volt_mv;
3548
+
port->req_current_limit = port->spr_avs_data.req_op_curr_ma;
3705
3549
power_supply_changed(port->psy);
3706
3550
tcpm_set_state(port, SNK_TRANSITION_SINK, 0);
3707
3551
break;
···
3818
3648
if (port->negotiated_rev >= PD_REV30 && port->pd_rev.rev_major)
3819
3649
tcpm_pd_handle_msg(port, PD_MSG_DATA_REV,
3820
3650
REVISION_INFORMATION);
3651
+
else
3652
+
tcpm_pd_handle_msg(port,
3653
+
port->negotiated_rev < PD_REV30 ?
3654
+
PD_MSG_CTRL_REJECT :
3655
+
PD_MSG_CTRL_NOT_SUPP,
3656
+
NONE_AMS);
3657
+
break;
3658
+
case PD_CTRL_GET_SINK_CAP_EXT:
3659
+
/* This is an unsupported message if port type is SRC */
3660
+
if (port->negotiated_rev >= PD_REV30 &&
3661
+
port->port_type != TYPEC_PORT_SRC)
3662
+
tcpm_pd_handle_msg(port, PD_MSG_EXT_SINK_CAP_EXT,
3663
+
GETTING_SINK_EXTENDED_CAPABILITIES);
3821
3664
else
3822
3665
tcpm_pd_handle_msg(port,
3823
3666
port->negotiated_rev < PD_REV30 ?
···
4090
3907
ret);
4091
3908
tcpm_ams_finish(port);
4092
3909
break;
3910
+
case PD_MSG_EXT_SINK_CAP_EXT:
3911
+
ret = tcpm_pd_send_sink_cap_ext(port);
3912
+
if (ret == -EOPNOTSUPP)
3913
+
tcpm_pd_send_control(port, PD_CTRL_NOT_SUPP, TCPC_TX_SOP);
3914
+
else if (ret < 0)
3915
+
tcpm_log(port,
3916
+
"Unable to transmit sink cap extended, ret=%d",
3917
+
ret);
3918
+
tcpm_ams_finish(port);
3919
+
break;
4093
3920
default:
4094
3921
break;
4095
3922
}
···
4209
4016
case PDO_TYPE_APDO:
4210
4017
if (pdo_apdo_type(pdo) == APDO_TYPE_PPS) {
4211
4018
port->pps_data.supported = true;
4212
-
port->usb_type =
4213
-
POWER_SUPPLY_USB_TYPE_PD_PPS;
4214
-
power_supply_changed(port->psy);
4019
+
} else if (pdo_apdo_type(pdo) == APDO_TYPE_SPR_AVS) {
4020
+
port->spr_avs_data.port_partner_src_status = SPR_AVS_SUPPORTED;
4021
+
port->spr_avs_data.port_partner_src_pdo_index = i;
4215
4022
}
4216
4023
continue;
4217
4024
default:
···
4249
4056
min_snk_mv = pdo_min_voltage(pdo);
4250
4057
break;
4251
4058
case PDO_TYPE_APDO:
4059
+
if (pdo_apdo_type(pdo) == APDO_TYPE_SPR_AVS) {
4060
+
port->spr_avs_data.port_snk_status = SPR_AVS_SUPPORTED;
4061
+
port->spr_avs_data.port_snk_pdo_index = j;
4062
+
}
4252
4063
continue;
4253
4064
default:
4254
4065
tcpm_log(port, "Invalid sink PDO type, ignoring");
···
4273
4076
}
4274
4077
}
4275
4078
}
4079
+
4080
+
if (port->spr_avs_data.port_snk_status == SPR_AVS_UNKNOWN)
4081
+
port->spr_avs_data.port_snk_status = SPR_AVS_NOT_SUPPORTED;
4082
+
4083
+
if (port->spr_avs_data.port_partner_src_status == SPR_AVS_UNKNOWN)
4084
+
port->spr_avs_data.port_partner_src_status = SPR_AVS_NOT_SUPPORTED;
4085
+
4086
+
if (port->pps_data.supported &&
4087
+
port->spr_avs_data.port_partner_src_status == SPR_AVS_SUPPORTED)
4088
+
port->usb_type = POWER_SUPPLY_USB_TYPE_PD_PPS_SPR_AVS;
4089
+
else if (port->pps_data.supported)
4090
+
port->usb_type = POWER_SUPPLY_USB_TYPE_PD_PPS;
4091
+
else if (port->spr_avs_data.port_partner_src_status == SPR_AVS_SUPPORTED)
4092
+
port->usb_type = POWER_SUPPLY_USB_TYPE_PD_SPR_AVS;
4093
+
4094
+
if (port->usb_type != POWER_SUPPLY_USB_TYPE_PD)
4095
+
power_supply_changed(port->psy);
4276
4096
4277
4097
return ret;
4278
4098
}
···
4339
4125
}
4340
4126
4341
4127
return src_pdo;
4128
+
}
4129
+
4130
+
static int tcpm_pd_select_spr_avs_apdo(struct tcpm_port *port)
4131
+
{
4132
+
u32 req_out_volt_mv, req_op_curr_ma, src_max_curr_ma = 0, source_cap;
4133
+
u32 snk_max_curr_ma = 0, src_pdo_index, snk_pdo_index, snk_pdo;
4134
+
4135
+
if (port->spr_avs_data.port_snk_status != SPR_AVS_SUPPORTED ||
4136
+
port->spr_avs_data.port_partner_src_status !=
4137
+
SPR_AVS_SUPPORTED) {
4138
+
tcpm_log(port, "SPR AVS not supported. port:%s partner:%s",
4139
+
spr_avs_status_strings[port->spr_avs_data.port_snk_status],
4140
+
spr_avs_status_strings[port->spr_avs_data.port_partner_src_status]);
4141
+
return -EOPNOTSUPP;
4142
+
}
4143
+
4144
+
/* Round up to SPR_AVS_VOLT_MV_STEP */
4145
+
req_out_volt_mv = port->spr_avs_data.req_out_volt_mv;
4146
+
if (req_out_volt_mv % SPR_AVS_VOLT_MV_STEP) {
4147
+
req_out_volt_mv += SPR_AVS_VOLT_MV_STEP -
4148
+
(req_out_volt_mv % SPR_AVS_VOLT_MV_STEP);
4149
+
port->spr_avs_data.req_out_volt_mv = req_out_volt_mv;
4150
+
}
4151
+
4152
+
/* Round up to RDO_SPR_AVS_CURR_MA_STEP */
4153
+
req_op_curr_ma = port->spr_avs_data.req_op_curr_ma;
4154
+
if (req_op_curr_ma % RDO_SPR_AVS_CURR_MA_STEP) {
4155
+
req_op_curr_ma += RDO_SPR_AVS_CURR_MA_STEP -
4156
+
(req_op_curr_ma % RDO_SPR_AVS_CURR_MA_STEP);
4157
+
port->spr_avs_data.req_op_curr_ma = req_op_curr_ma;
4158
+
}
4159
+
4160
+
src_pdo_index = port->spr_avs_data.port_partner_src_pdo_index;
4161
+
snk_pdo_index = port->spr_avs_data.port_snk_pdo_index;
4162
+
source_cap = port->source_caps[src_pdo_index];
4163
+
snk_pdo = port->snk_pdo[snk_pdo_index];
4164
+
tcpm_log(port,
4165
+
"SPR AVS src_pdo_index:%d snk_pdo_index:%d req_op_curr_ma roundup:%u req_out_volt_mv roundup:%u",
4166
+
src_pdo_index, snk_pdo_index, req_op_curr_ma, req_out_volt_mv);
4167
+
4168
+
if (req_out_volt_mv >= SPR_AVS_TIER1_MIN_VOLT_MV &&
4169
+
req_out_volt_mv <= SPR_AVS_TIER1_MAX_VOLT_MV) {
4170
+
src_max_curr_ma =
4171
+
pdo_spr_avs_apdo_9v_to_15v_max_current_ma(source_cap);
4172
+
snk_max_curr_ma =
4173
+
pdo_spr_avs_apdo_9v_to_15v_max_current_ma(snk_pdo);
4174
+
} else if (req_out_volt_mv > SPR_AVS_TIER1_MAX_VOLT_MV &&
4175
+
req_out_volt_mv <= SPR_AVS_TIER2_MAX_VOLT_MV) {
4176
+
src_max_curr_ma =
4177
+
pdo_spr_avs_apdo_15v_to_20v_max_current_ma(source_cap);
4178
+
snk_max_curr_ma =
4179
+
pdo_spr_avs_apdo_15v_to_20v_max_current_ma(snk_pdo);
4180
+
} else {
4181
+
tcpm_log(port, "Invalid SPR AVS req_volt:%umV", req_out_volt_mv);
4182
+
return -EINVAL;
4183
+
}
4184
+
4185
+
if (req_op_curr_ma > src_max_curr_ma ||
4186
+
req_op_curr_ma > snk_max_curr_ma) {
4187
+
tcpm_log(port,
4188
+
"Invalid SPR AVS request. req_volt:%umV req_curr:%umA src_max_cur:%umA snk_max_cur:%umA",
4189
+
req_out_volt_mv, req_op_curr_ma, src_max_curr_ma,
4190
+
snk_max_curr_ma);
4191
+
return -EINVAL;
4192
+
}
4193
+
4194
+
/* Max SPR voltage based on both the port and the partner caps */
4195
+
if (pdo_spr_avs_apdo_15v_to_20v_max_current_ma(snk_pdo) &&
4196
+
pdo_spr_avs_apdo_15v_to_20v_max_current_ma(source_cap))
4197
+
port->spr_avs_data.max_out_volt_mv = SPR_AVS_TIER2_MAX_VOLT_MV;
4198
+
else
4199
+
port->spr_avs_data.max_out_volt_mv = SPR_AVS_TIER1_MAX_VOLT_MV;
4200
+
4201
+
/*
4202
+
* Max SPR AVS curr based on 9V to 15V. This should be higher than or
4203
+
* equal to 15V to 20V range.
4204
+
*/
4205
+
port->spr_avs_data.max_current_ma =
4206
+
min(pdo_spr_avs_apdo_9v_to_15v_max_current_ma(source_cap),
4207
+
pdo_spr_avs_apdo_9v_to_15v_max_current_ma(snk_pdo));
4208
+
4209
+
return src_pdo_index;
4342
4210
}
4343
4211
4344
4212
static int tcpm_pd_build_request(struct tcpm_port *port, u32 *rdo)
···
4590
4294
return 0;
4591
4295
}
4592
4296
4593
-
static int tcpm_pd_send_pps_request(struct tcpm_port *port)
4297
+
static int tcpm_pd_build_spr_avs_request(struct tcpm_port *port, u32 *rdo)
4298
+
{
4299
+
u32 out_mv, op_ma, flags, snk_pdo_index, source_cap;
4300
+
unsigned int src_power_mw, snk_power_mw;
4301
+
int src_pdo_index;
4302
+
u32 snk_pdo;
4303
+
4304
+
src_pdo_index = tcpm_pd_select_spr_avs_apdo(port);
4305
+
if (src_pdo_index < 0)
4306
+
return src_pdo_index;
4307
+
snk_pdo_index = port->spr_avs_data.port_snk_pdo_index;
4308
+
source_cap = port->source_caps[src_pdo_index];
4309
+
snk_pdo = port->snk_pdo[snk_pdo_index];
4310
+
out_mv = port->spr_avs_data.req_out_volt_mv;
4311
+
op_ma = port->spr_avs_data.req_op_curr_ma;
4312
+
4313
+
flags = RDO_USB_COMM | RDO_NO_SUSPEND;
4314
+
4315
+
/*
4316
+
* Set capability mismatch when the maximum power needs in the current
4317
+
* requested AVS voltage tier range is greater than
4318
+
* port->operating_snk_mw, however, the maximum power offered by the
4319
+
* source at the current requested AVS voltage tier is less than
4320
+
* port->operating_sink_mw.
4321
+
*/
4322
+
if (out_mv > SPR_AVS_TIER1_MAX_VOLT_MV) {
4323
+
src_power_mw =
4324
+
pdo_spr_avs_apdo_15v_to_20v_max_current_ma(source_cap) *
4325
+
SPR_AVS_TIER2_MAX_VOLT_MV / 1000;
4326
+
snk_power_mw =
4327
+
pdo_spr_avs_apdo_15v_to_20v_max_current_ma(snk_pdo) *
4328
+
SPR_AVS_TIER2_MAX_VOLT_MV / 1000;
4329
+
} else {
4330
+
src_power_mw =
4331
+
pdo_spr_avs_apdo_9v_to_15v_max_current_ma(source_cap) *
4332
+
SPR_AVS_TIER1_MAX_VOLT_MV / 1000;
4333
+
snk_power_mw =
4334
+
pdo_spr_avs_apdo_9v_to_15v_max_current_ma(snk_pdo) *
4335
+
SPR_AVS_TIER1_MAX_VOLT_MV / 1000;
4336
+
}
4337
+
4338
+
if (snk_power_mw >= port->operating_snk_mw &&
4339
+
src_power_mw < port->operating_snk_mw)
4340
+
flags |= RDO_CAP_MISMATCH;
4341
+
4342
+
*rdo = RDO_AVS(src_pdo_index + 1, out_mv, op_ma, flags);
4343
+
4344
+
tcpm_log(port, "Requesting APDO SPR AVS %d: %u mV, %u mA",
4345
+
src_pdo_index, out_mv, op_ma);
4346
+
4347
+
return 0;
4348
+
}
4349
+
4350
+
static int tcpm_pd_send_aug_supply_request(struct tcpm_port *port,
4351
+
enum aug_req_type type)
4594
4352
{
4595
4353
struct pd_message msg;
4596
4354
int ret;
4597
4355
u32 rdo;
4598
4356
4599
-
ret = tcpm_pd_build_pps_request(port, &rdo);
4357
+
if (type == PD_PPS) {
4358
+
ret = tcpm_pd_build_pps_request(port, &rdo);
4359
+
} else if (type == PD_SPR_AVS) {
4360
+
ret = tcpm_pd_build_spr_avs_request(port, &rdo);
4361
+
} else {
4362
+
tcpm_log(port, "Invalid aug_req_type %d", type);
4363
+
ret = -EOPNOTSUPP;
4364
+
}
4600
4365
if (ret < 0)
4601
4366
return ret;
4602
4367
···
4880
4523
port->tcpc->set_partner_usb_comm_capable(port->tcpc, capable);
4881
4524
}
4882
4525
4526
+
static void tcpm_partner_source_caps_reset(struct tcpm_port *port)
4527
+
{
4528
+
usb_power_delivery_unregister_capabilities(port->partner_source_caps);
4529
+
port->partner_source_caps = NULL;
4530
+
port->spr_avs_data.port_partner_src_status = SPR_AVS_UNKNOWN;
4531
+
port->spr_avs_data.active = false;
4532
+
}
4533
+
4883
4534
static void tcpm_reset_port(struct tcpm_port *port)
4884
4535
{
4885
4536
tcpm_enable_auto_vbus_discharge(port, false);
···
4927
4562
4928
4563
usb_power_delivery_unregister_capabilities(port->partner_sink_caps);
4929
4564
port->partner_sink_caps = NULL;
4930
-
usb_power_delivery_unregister_capabilities(port->partner_source_caps);
4931
-
port->partner_source_caps = NULL;
4565
+
tcpm_partner_source_caps_reset(port);
4932
4566
usb_power_delivery_unregister(port->partner_pd);
4933
4567
port->partner_pd = NULL;
4934
4568
}
···
5419
5055
case SNK_UNATTACHED:
5420
5056
if (!port->non_pd_role_swap)
5421
5057
tcpm_swap_complete(port, -ENOTCONN);
5422
-
tcpm_pps_complete(port, -ENOTCONN);
5058
+
tcpm_aug_supply_req_complete(port, -ENOTCONN);
5423
5059
tcpm_snk_detach(port);
5424
5060
if (port->potential_contaminant) {
5425
5061
tcpm_set_state(port, CHECK_CONTAMINANT, 0);
···
5650
5286
}
5651
5287
break;
5652
5288
case SNK_NEGOTIATE_PPS_CAPABILITIES:
5653
-
ret = tcpm_pd_send_pps_request(port);
5289
+
case SNK_NEGOTIATE_SPR_AVS_CAPABILITIES:
5290
+
ret = tcpm_pd_send_aug_supply_request(port, port->state ==
5291
+
SNK_NEGOTIATE_PPS_CAPABILITIES ?
5292
+
PD_PPS : PD_SPR_AVS);
5654
5293
if (ret < 0) {
5655
5294
/* Restore back to the original state */
5656
5295
tcpm_set_auto_vbus_discharge_threshold(port, TYPEC_PWR_MODE_PD,
5657
5296
port->pps_data.active,
5658
5297
port->supply_voltage);
5659
-
port->pps_status = ret;
5298
+
port->aug_supply_req_status = ret;
5660
5299
/*
5661
5300
* If this was called due to updates to sink
5662
5301
* capabilities, and pps is no longer valid, we should
···
5675
5308
}
5676
5309
break;
5677
5310
case SNK_TRANSITION_SINK:
5678
-
/* From the USB PD spec:
5679
-
* "The Sink Shall transition to Sink Standby before a positive or
5680
-
* negative voltage transition of VBUS. During Sink Standby
5681
-
* the Sink Shall reduce its power draw to pSnkStdby."
5682
-
*
5683
-
* This is not applicable to PPS though as the port can continue
5684
-
* to draw negotiated power without switching to standby.
5685
-
*/
5686
-
if (port->supply_voltage != port->req_supply_voltage && !port->pps_data.active &&
5687
-
port->current_limit * port->supply_voltage / 1000 > PD_P_SNK_STDBY_MW) {
5688
-
u32 stdby_ma = PD_P_SNK_STDBY_MW * 1000 / port->supply_voltage;
5311
+
if (port->spr_avs_data.active) {
5312
+
if (abs(port->req_supply_voltage - port->supply_voltage) >
5313
+
SPR_AVS_AVS_SMALL_STEP_V * 1000) {
5314
+
/*
5315
+
* The Sink Shall reduce its current draw to
5316
+
* iSnkStdby within tSnkStdby. The reduction to
5317
+
* iSnkStdby is not required if the voltage
5318
+
* increase is less than or equal to
5319
+
* vAvsSmallStep.
5320
+
*/
5321
+
tcpm_log(port,
5322
+
"SPR AVS Setting iSnkstandby. Req vol: %u mV Curr vol: %u mV",
5323
+
port->req_supply_voltage,
5324
+
port->supply_voltage);
5325
+
tcpm_set_current_limit(port, PD_I_SNK_STBY_MA,
5326
+
port->supply_voltage);
5327
+
}
5328
+
/*
5329
+
* Although tAvsSrcTransSmall is expected to be used
5330
+
* for voltage transistions smaller than 1V, using
5331
+
* tAvsSrcTransLarge to be resilient against chargers
5332
+
* which strictly cannot honor tAvsSrcTransSmall to
5333
+
* improve interoperability.
5334
+
*/
5335
+
tcpm_set_state(port, hard_reset_state(port),
5336
+
PD_T_AVS_SRC_TRANS_LARGE);
5337
+
/*
5338
+
* From the USB PD spec:
5339
+
* "The Sink Shall transition to Sink Standby before a
5340
+
* positive ornegative voltage transition of VBUS.
5341
+
* During Sink Standby the Sink Shall reduce its power
5342
+
* draw to pSnkStdby."
5343
+
*
5344
+
* This is not applicable to PPS though as the port can
5345
+
* continue to draw negotiated power without switching
5346
+
* to standby.
5347
+
*/
5348
+
} else if (port->supply_voltage != port->req_supply_voltage &&
5349
+
!port->pps_data.active &&
5350
+
(port->current_limit * port->supply_voltage / 1000 >
5351
+
PD_P_SNK_STDBY_MW)) {
5352
+
u32 stdby_ma = PD_P_SNK_STDBY_MW * 1000 /
5353
+
port->supply_voltage;
5689
5354
5690
5355
tcpm_log(port, "Setting standby current %u mV @ %u mA",
5691
5356
port->supply_voltage, stdby_ma);
5692
-
tcpm_set_current_limit(port, stdby_ma, port->supply_voltage);
5357
+
tcpm_set_current_limit(port, stdby_ma,
5358
+
port->supply_voltage);
5359
+
tcpm_set_state(port, hard_reset_state(port),
5360
+
PD_T_PS_TRANSITION);
5693
5361
}
5694
-
fallthrough;
5362
+
break;
5695
5363
case SNK_TRANSITION_SINK_VBUS:
5696
5364
tcpm_set_state(port, hard_reset_state(port),
5697
5365
PD_T_PS_TRANSITION);
···
5746
5344
tcpm_typec_connect(port);
5747
5345
if (port->pd_capable && port->source_caps[0] & PDO_FIXED_DUAL_ROLE)
5748
5346
mod_enable_frs_delayed_work(port, 0);
5749
-
tcpm_pps_complete(port, port->pps_status);
5347
+
tcpm_aug_supply_req_complete(port, port->aug_supply_req_status);
5750
5348
5751
5349
if (port->ams != NONE_AMS)
5752
5350
tcpm_ams_finish(port);
···
5933
5531
port->message_id = 0;
5934
5532
port->rx_msgid = -1;
5935
5533
/* remove existing capabilities */
5936
-
usb_power_delivery_unregister_capabilities(port->partner_source_caps);
5937
-
port->partner_source_caps = NULL;
5534
+
tcpm_partner_source_caps_reset(port);
5938
5535
tcpm_pd_send_control(port, PD_CTRL_ACCEPT, TCPC_TX_SOP);
5939
5536
tcpm_ams_finish(port);
5940
5537
if (port->pwr_role == TYPEC_SOURCE) {
···
5966
5565
port->message_id = 0;
5967
5566
port->rx_msgid = -1;
5968
5567
/* remove existing capabilities */
5969
-
usb_power_delivery_unregister_capabilities(port->partner_source_caps);
5970
-
port->partner_source_caps = NULL;
5568
+
tcpm_partner_source_caps_reset(port);
5971
5569
if (tcpm_pd_send_control(port, PD_CTRL_SOFT_RESET, TCPC_TX_SOP))
5972
5570
tcpm_set_state_cond(port, hard_reset_state(port), 0);
5973
5571
else
···
6103
5703
break;
6104
5704
case PR_SWAP_SNK_SRC_SINK_OFF:
6105
5705
/* will be source, remove existing capabilities */
6106
-
usb_power_delivery_unregister_capabilities(port->partner_source_caps);
6107
-
port->partner_source_caps = NULL;
5706
+
tcpm_partner_source_caps_reset(port);
6108
5707
/*
6109
5708
* Prevent vbus discharge circuit from turning on during PR_SWAP
6110
5709
* as this is not a disconnect.
···
6251
5852
break;
6252
5853
case ERROR_RECOVERY:
6253
5854
tcpm_swap_complete(port, -EPROTO);
6254
-
tcpm_pps_complete(port, -EPROTO);
5855
+
tcpm_aug_supply_req_complete(port, -EPROTO);
6255
5856
tcpm_set_state(port, PORT_RESET, 0);
6256
5857
break;
6257
5858
case PORT_RESET:
···
7225
6826
return ret;
7226
6827
}
7227
6828
7228
-
static int tcpm_pps_set_op_curr(struct tcpm_port *port, u16 req_op_curr)
6829
+
static int tcpm_aug_set_op_curr(struct tcpm_port *port, u16 req_op_curr_ma)
7229
6830
{
7230
6831
unsigned int target_mw;
7231
6832
int ret;
···
7233
6834
mutex_lock(&port->swap_lock);
7234
6835
mutex_lock(&port->lock);
7235
6836
7236
-
if (!port->pps_data.active) {
6837
+
if (port->pps_data.active) {
6838
+
req_op_curr_ma = req_op_curr_ma -
6839
+
(req_op_curr_ma % RDO_PROG_CURR_MA_STEP);
6840
+
if (req_op_curr_ma > port->pps_data.max_curr) {
6841
+
ret = -EINVAL;
6842
+
goto port_unlock;
6843
+
}
6844
+
target_mw = (req_op_curr_ma * port->supply_voltage) / 1000;
6845
+
if (target_mw < port->operating_snk_mw) {
6846
+
ret = -EINVAL;
6847
+
goto port_unlock;
6848
+
}
6849
+
} else if (!port->spr_avs_data.active) {
7237
6850
ret = -EOPNOTSUPP;
7238
6851
goto port_unlock;
7239
6852
}
···
7255
6844
goto port_unlock;
7256
6845
}
7257
6846
7258
-
if (req_op_curr > port->pps_data.max_curr) {
7259
-
ret = -EINVAL;
7260
-
goto port_unlock;
7261
-
}
6847
+
if (port->pps_data.active)
6848
+
port->upcoming_state = SNK_NEGOTIATE_PPS_CAPABILITIES;
6849
+
else
6850
+
port->upcoming_state = SNK_NEGOTIATE_SPR_AVS_CAPABILITIES;
7262
6851
7263
-
target_mw = (req_op_curr * port->supply_voltage) / 1000;
7264
-
if (target_mw < port->operating_snk_mw) {
7265
-
ret = -EINVAL;
7266
-
goto port_unlock;
7267
-
}
7268
-
7269
-
port->upcoming_state = SNK_NEGOTIATE_PPS_CAPABILITIES;
7270
6852
ret = tcpm_ams_start(port, POWER_NEGOTIATION);
7271
6853
if (ret == -EAGAIN) {
7272
6854
port->upcoming_state = INVALID_STATE;
7273
6855
goto port_unlock;
7274
6856
}
7275
6857
7276
-
/* Round down operating current to align with PPS valid steps */
7277
-
req_op_curr = req_op_curr - (req_op_curr % RDO_PROG_CURR_MA_STEP);
7278
-
7279
-
reinit_completion(&port->pps_complete);
7280
-
port->pps_data.req_op_curr = req_op_curr;
7281
-
port->pps_status = 0;
7282
-
port->pps_pending = true;
6858
+
reinit_completion(&port->aug_supply_req_complete);
6859
+
if (port->pps_data.active)
6860
+
port->pps_data.req_op_curr = req_op_curr_ma;
6861
+
else
6862
+
port->spr_avs_data.req_op_curr_ma = req_op_curr_ma;
6863
+
port->aug_supply_req_status = 0;
6864
+
port->aug_supply_req_pending = true;
7283
6865
mutex_unlock(&port->lock);
7284
6866
7285
-
if (!wait_for_completion_timeout(&port->pps_complete,
7286
-
msecs_to_jiffies(PD_PPS_CTRL_TIMEOUT)))
6867
+
if (!wait_for_completion_timeout(&port->aug_supply_req_complete,
6868
+
msecs_to_jiffies(PD_AUG_PSY_CTRL_TIMEOUT)))
7287
6869
ret = -ETIMEDOUT;
7288
6870
else
7289
-
ret = port->pps_status;
6871
+
ret = port->aug_supply_req_status;
7290
6872
7291
6873
goto swap_unlock;
7292
6874
···
7291
6887
return ret;
7292
6888
}
7293
6889
7294
-
static int tcpm_pps_set_out_volt(struct tcpm_port *port, u16 req_out_volt)
6890
+
static int tcpm_aug_set_out_volt(struct tcpm_port *port, u16 req_out_volt_mv)
7295
6891
{
7296
6892
unsigned int target_mw;
7297
6893
int ret;
···
7299
6895
mutex_lock(&port->swap_lock);
7300
6896
mutex_lock(&port->lock);
7301
6897
7302
-
if (!port->pps_data.active) {
6898
+
if (port->pps_data.active) {
6899
+
req_out_volt_mv = req_out_volt_mv - (req_out_volt_mv %
6900
+
RDO_PROG_VOLT_MV_STEP);
6901
+
/* Round down output voltage to align with PPS valid steps */
6902
+
target_mw = (port->current_limit * req_out_volt_mv) / 1000;
6903
+
if (target_mw < port->operating_snk_mw) {
6904
+
ret = -EINVAL;
6905
+
goto port_unlock;
6906
+
}
6907
+
} else if (!port->spr_avs_data.active) {
7303
6908
ret = -EOPNOTSUPP;
7304
6909
goto port_unlock;
7305
6910
}
···
7318
6905
goto port_unlock;
7319
6906
}
7320
6907
7321
-
target_mw = (port->current_limit * req_out_volt) / 1000;
7322
-
if (target_mw < port->operating_snk_mw) {
7323
-
ret = -EINVAL;
7324
-
goto port_unlock;
7325
-
}
6908
+
if (port->pps_data.active)
6909
+
port->upcoming_state = SNK_NEGOTIATE_PPS_CAPABILITIES;
6910
+
else
6911
+
port->upcoming_state = SNK_NEGOTIATE_SPR_AVS_CAPABILITIES;
7326
6912
7327
-
port->upcoming_state = SNK_NEGOTIATE_PPS_CAPABILITIES;
7328
6913
ret = tcpm_ams_start(port, POWER_NEGOTIATION);
7329
6914
if (ret == -EAGAIN) {
7330
6915
port->upcoming_state = INVALID_STATE;
7331
6916
goto port_unlock;
7332
6917
}
7333
6918
7334
-
/* Round down output voltage to align with PPS valid steps */
7335
-
req_out_volt = req_out_volt - (req_out_volt % RDO_PROG_VOLT_MV_STEP);
7336
-
7337
-
reinit_completion(&port->pps_complete);
7338
-
port->pps_data.req_out_volt = req_out_volt;
7339
-
port->pps_status = 0;
7340
-
port->pps_pending = true;
6919
+
reinit_completion(&port->aug_supply_req_complete);
6920
+
if (port->pps_data.active)
6921
+
port->pps_data.req_out_volt = req_out_volt_mv;
6922
+
else
6923
+
port->spr_avs_data.req_out_volt_mv = req_out_volt_mv;
6924
+
port->aug_supply_req_status = 0;
6925
+
port->aug_supply_req_pending = true;
7341
6926
mutex_unlock(&port->lock);
7342
6927
7343
-
if (!wait_for_completion_timeout(&port->pps_complete,
7344
-
msecs_to_jiffies(PD_PPS_CTRL_TIMEOUT)))
6928
+
if (!wait_for_completion_timeout(&port->aug_supply_req_complete,
6929
+
msecs_to_jiffies(PD_AUG_PSY_CTRL_TIMEOUT)))
7345
6930
ret = -ETIMEDOUT;
7346
6931
else
7347
-
ret = port->pps_status;
6932
+
ret = port->aug_supply_req_status;
7348
6933
7349
6934
goto swap_unlock;
7350
6935
···
7385
6974
goto port_unlock;
7386
6975
}
7387
6976
7388
-
reinit_completion(&port->pps_complete);
7389
-
port->pps_status = 0;
7390
-
port->pps_pending = true;
6977
+
reinit_completion(&port->aug_supply_req_complete);
6978
+
port->aug_supply_req_status = 0;
6979
+
port->aug_supply_req_pending = true;
7391
6980
7392
6981
/* Trigger PPS request or move back to standard PDO contract */
7393
6982
if (activate) {
···
7396
6985
}
7397
6986
mutex_unlock(&port->lock);
7398
6987
7399
-
if (!wait_for_completion_timeout(&port->pps_complete,
7400
-
msecs_to_jiffies(PD_PPS_CTRL_TIMEOUT)))
6988
+
if (!wait_for_completion_timeout(&port->aug_supply_req_complete,
6989
+
msecs_to_jiffies(PD_AUG_PSY_CTRL_TIMEOUT)))
7401
6990
ret = -ETIMEDOUT;
7402
6991
else
7403
-
ret = port->pps_status;
6992
+
ret = port->aug_supply_req_status;
6993
+
6994
+
goto swap_unlock;
6995
+
6996
+
port_unlock:
6997
+
mutex_unlock(&port->lock);
6998
+
swap_unlock:
6999
+
mutex_unlock(&port->swap_lock);
7000
+
7001
+
return ret;
7002
+
}
7003
+
7004
+
static int tcpm_spr_avs_activate(struct tcpm_port *port, bool activate)
7005
+
{
7006
+
int ret = 0;
7007
+
7008
+
mutex_lock(&port->swap_lock);
7009
+
mutex_lock(&port->lock);
7010
+
7011
+
if (port->spr_avs_data.port_snk_status == SPR_AVS_NOT_SUPPORTED ||
7012
+
port->spr_avs_data.port_partner_src_status == SPR_AVS_NOT_SUPPORTED) {
7013
+
tcpm_log(port, "SPR_AVS not supported");
7014
+
ret = -EOPNOTSUPP;
7015
+
goto port_unlock;
7016
+
}
7017
+
7018
+
/* Trying to deactivate SPR AVS when already deactivated so just bail */
7019
+
if (!port->spr_avs_data.active && !activate)
7020
+
goto port_unlock;
7021
+
7022
+
if (port->state != SNK_READY) {
7023
+
tcpm_log(port,
7024
+
"SPR_AVS cannot be activated. Port not in SNK_READY");
7025
+
ret = -EAGAIN;
7026
+
goto port_unlock;
7027
+
}
7028
+
7029
+
if (activate)
7030
+
port->upcoming_state = SNK_NEGOTIATE_SPR_AVS_CAPABILITIES;
7031
+
else
7032
+
port->upcoming_state = SNK_NEGOTIATE_CAPABILITIES;
7033
+
ret = tcpm_ams_start(port, POWER_NEGOTIATION);
7034
+
if (ret == -EAGAIN) {
7035
+
tcpm_log(port, "SPR_AVS cannot be %s. AMS start failed",
7036
+
activate ? "activated" : "deactivated");
7037
+
port->upcoming_state = INVALID_STATE;
7038
+
goto port_unlock;
7039
+
}
7040
+
7041
+
reinit_completion(&port->aug_supply_req_complete);
7042
+
port->aug_supply_req_status = 0;
7043
+
port->aug_supply_req_pending = true;
7044
+
7045
+
/* Trigger AVS request or move back to standard PDO contract */
7046
+
if (activate) {
7047
+
port->spr_avs_data.req_out_volt_mv = port->supply_voltage;
7048
+
port->spr_avs_data.req_op_curr_ma = port->current_limit;
7049
+
}
7050
+
mutex_unlock(&port->lock);
7051
+
7052
+
if (!wait_for_completion_timeout(&port->aug_supply_req_complete,
7053
+
msecs_to_jiffies(PD_AUG_PSY_CTRL_TIMEOUT)))
7054
+
ret = -ETIMEDOUT;
7055
+
else
7056
+
ret = port->aug_supply_req_status;
7404
7057
7405
7058
goto swap_unlock;
7406
7059
···
7620
7145
break;
7621
7146
case SNK_NEGOTIATE_CAPABILITIES:
7622
7147
case SNK_NEGOTIATE_PPS_CAPABILITIES:
7148
+
case SNK_NEGOTIATE_SPR_AVS_CAPABILITIES:
7623
7149
case SNK_READY:
7624
7150
case SNK_TRANSITION_SINK:
7625
7151
case SNK_TRANSITION_SINK_VBUS:
7626
-
if (port->pps_data.active)
7152
+
if (port->pps_data.active) {
7627
7153
port->upcoming_state = SNK_NEGOTIATE_PPS_CAPABILITIES;
7628
-
else if (port->pd_capable)
7154
+
} else if (port->pd_capable) {
7629
7155
port->upcoming_state = SNK_NEGOTIATE_CAPABILITIES;
7630
-
else
7156
+
if (port->spr_avs_data.active) {
7157
+
/*
7158
+
* De-activate AVS and fallback to PD to
7159
+
* re-evaluate whether AVS is supported in the
7160
+
* current sink cap set.
7161
+
*/
7162
+
port->spr_avs_data.active = false;
7163
+
port->spr_avs_data.port_snk_status = SPR_AVS_UNKNOWN;
7164
+
}
7165
+
} else {
7631
7166
break;
7632
-
7167
+
}
7633
7168
port->update_sink_caps = true;
7634
7169
7635
7170
ret = tcpm_ams_start(port, POWER_NEGOTIATION);
···
7774
7289
ret = fwnode_property_read_u32(fwnode, "sink-bc12-completion-time-ms", &val);
7775
7290
if (!ret)
7776
7291
port->timings.snk_bc12_cmpletion_time = val;
7292
+
}
7293
+
7294
+
static void tcpm_fw_get_pd_ident(struct tcpm_port *port)
7295
+
{
7296
+
struct pd_identifier *pd_ident = &port->pd_ident;
7297
+
u32 *vdo;
7298
+
7299
+
/* First 3 vdo values contain info regarding USB PID, VID & XID */
7300
+
if (port->nr_snk_vdo >= 3)
7301
+
vdo = port->snk_vdo;
7302
+
else if (port->nr_snk_vdo_v1 >= 3)
7303
+
vdo = port->snk_vdo_v1;
7304
+
else
7305
+
return;
7306
+
7307
+
pd_ident->vid = PD_IDH_VID(vdo[0]);
7308
+
pd_ident->pid = PD_PRODUCT_PID(vdo[2]);
7309
+
pd_ident->xid = PD_CSTAT_XID(vdo[1]);
7310
+
tcpm_log(port, "vid:%#x pid:%#x xid:%#x",
7311
+
pd_ident->vid, pd_ident->pid, pd_ident->xid);
7312
+
}
7313
+
7314
+
static void tcpm_parse_snk_pdos(struct tcpm_port *port)
7315
+
{
7316
+
struct sink_caps_ext_data *caps = &port->sink_caps_ext;
7317
+
u32 max_mv, max_ma;
7318
+
u8 avs_tier1_pdp, avs_tier2_pdp;
7319
+
int i, pdo_itr;
7320
+
u32 *snk_pdos;
7321
+
7322
+
for (i = 0; i < port->pd_count; ++i) {
7323
+
snk_pdos = port->pd_list[i]->sink_desc.pdo;
7324
+
for (pdo_itr = 0; pdo_itr < PDO_MAX_OBJECTS && snk_pdos[pdo_itr];
7325
+
++pdo_itr) {
7326
+
u32 pdo = snk_pdos[pdo_itr];
7327
+
u8 curr_snk_pdp = 0;
7328
+
7329
+
switch (pdo_type(pdo)) {
7330
+
case PDO_TYPE_FIXED:
7331
+
max_mv = pdo_fixed_voltage(pdo);
7332
+
max_ma = pdo_fixed_current(pdo);
7333
+
curr_snk_pdp = UW_TO_W(max_mv * max_ma);
7334
+
break;
7335
+
case PDO_TYPE_BATT:
7336
+
curr_snk_pdp = UW_TO_W(pdo_max_power(pdo));
7337
+
break;
7338
+
case PDO_TYPE_VAR:
7339
+
max_mv = pdo_max_voltage(pdo);
7340
+
max_ma = pdo_max_current(pdo);
7341
+
curr_snk_pdp = UW_TO_W(max_mv * max_ma);
7342
+
break;
7343
+
case PDO_TYPE_APDO:
7344
+
if (pdo_apdo_type(pdo) == APDO_TYPE_PPS) {
7345
+
max_mv = pdo_pps_apdo_max_voltage(pdo);
7346
+
max_ma = pdo_pps_apdo_max_current(pdo);
7347
+
curr_snk_pdp = UW_TO_W(max_mv * max_ma);
7348
+
caps->modes |= SINK_MODE_PPS;
7349
+
} else if (pdo_apdo_type(pdo) ==
7350
+
APDO_TYPE_SPR_AVS) {
7351
+
avs_tier1_pdp = UW_TO_W(SPR_AVS_TIER1_MAX_VOLT_MV
7352
+
* pdo_spr_avs_apdo_9v_to_15v_max_current_ma(pdo));
7353
+
avs_tier2_pdp = UW_TO_W(SPR_AVS_TIER2_MAX_VOLT_MV
7354
+
* pdo_spr_avs_apdo_15v_to_20v_max_current_ma(pdo));
7355
+
curr_snk_pdp = max(avs_tier1_pdp, avs_tier2_pdp);
7356
+
caps->modes |= SINK_MODE_AVS;
7357
+
}
7358
+
break;
7359
+
default:
7360
+
tcpm_log(port, "Invalid source PDO type, ignoring");
7361
+
continue;
7362
+
}
7363
+
7364
+
caps->spr_max_pdp = max(caps->spr_max_pdp,
7365
+
curr_snk_pdp);
7366
+
}
7367
+
}
7368
+
}
7369
+
7370
+
static void tcpm_fw_get_sink_caps_ext(struct tcpm_port *port,
7371
+
struct fwnode_handle *fwnode)
7372
+
{
7373
+
struct sink_caps_ext_data *caps = &port->sink_caps_ext;
7374
+
int ret;
7375
+
u32 val;
7376
+
7377
+
/*
7378
+
* Load step represents the change in current per usec that a given
7379
+
* source can tolerate while maintaining Vbus within the vSrcValid
7380
+
* range. For a sink this represents the "preferred" load-step value. It
7381
+
* can only have 2 values (150 mA/usec or 500 mA/usec) with 150 mA/usec
7382
+
* being the default.
7383
+
*/
7384
+
ret = fwnode_property_read_u32(fwnode, "sink-load-step", &val);
7385
+
if (!ret)
7386
+
caps->load_step = val == 500 ? 1 : 0;
7387
+
7388
+
fwnode_property_read_u16(fwnode, "sink-load-characteristics",
7389
+
&caps->load_char);
7390
+
fwnode_property_read_u8(fwnode, "sink-compliance", &caps->compliance);
7391
+
caps->modes = SINK_MODE_VBUS;
7392
+
7393
+
/*
7394
+
* As per "6.5.13.14" SPR Sink Operational PDP definition, for battery
7395
+
* powered devices, this value will correspond to the PDP of the
7396
+
* charging adapter either shipped or recommended for use with it. For
7397
+
* batteryless sink devices SPR Operational PDP indicates the power
7398
+
* required to operate all the device's functional modes. Hence, this
7399
+
* value may be considered equal to port's operating_snk_mw. As
7400
+
* operating_sink_mw can change as per the pd set used thus, OP PDP
7401
+
* is determined when populating Sink Caps Extended Data Block.
7402
+
*/
7403
+
if (port->self_powered) {
7404
+
fwnode_property_read_u32(fwnode, "charging-adapter-pdp-milliwatt",
7405
+
&val);
7406
+
caps->spr_op_pdp = (u8)(val / 1000);
7407
+
caps->modes |= SINK_MODE_BATT;
7408
+
}
7409
+
7410
+
tcpm_parse_snk_pdos(port);
7411
+
tcpm_log(port,
7412
+
"load-step:%#x load-char:%#x compl:%#x op-pdp:%#x max-pdp:%#x",
7413
+
caps->load_step, caps->load_char, caps->compliance,
7414
+
caps->spr_op_pdp, caps->spr_max_pdp);
7777
7415
}
7778
7416
7779
7417
static int tcpm_fw_get_caps(struct tcpm_port *port, struct fwnode_handle *fwnode)
···
8072
7464
}
8073
7465
}
8074
7466
7467
+
if (port->port_type != TYPEC_PORT_SRC)
7468
+
tcpm_fw_get_sink_caps_ext(port, fwnode);
7469
+
8075
7470
put_caps:
8076
7471
if (caps != fwnode)
8077
7472
fwnode_handle_put(caps);
···
8117
7506
return ret;
8118
7507
}
8119
7508
7509
+
tcpm_fw_get_pd_ident(port);
7510
+
8120
7511
return 0;
8121
7512
}
8122
7513
···
8149
7536
enum tcpm_psy_online_states {
8150
7537
TCPM_PSY_OFFLINE = 0,
8151
7538
TCPM_PSY_FIXED_ONLINE,
8152
-
TCPM_PSY_PROG_ONLINE,
7539
+
TCPM_PSY_PPS_ONLINE,
7540
+
TCPM_PSY_SPR_AVS_ONLINE,
8153
7541
};
8154
7542
8155
7543
static enum power_supply_property tcpm_psy_props[] = {
···
8168
7554
{
8169
7555
if (port->vbus_charge) {
8170
7556
if (port->pps_data.active)
8171
-
val->intval = TCPM_PSY_PROG_ONLINE;
7557
+
val->intval = TCPM_PSY_PPS_ONLINE;
7558
+
else if (port->spr_avs_data.active)
7559
+
val->intval = TCPM_PSY_SPR_AVS_ONLINE;
8172
7560
else
8173
7561
val->intval = TCPM_PSY_FIXED_ONLINE;
8174
7562
} else {
···
8185
7569
{
8186
7570
if (port->pps_data.active)
8187
7571
val->intval = port->pps_data.min_volt * 1000;
7572
+
else if (port->spr_avs_data.active)
7573
+
val->intval = SPR_AVS_TIER1_MIN_VOLT_MV * 1000;
8188
7574
else
8189
7575
val->intval = port->supply_voltage * 1000;
8190
7576
···
8198
7580
{
8199
7581
if (port->pps_data.active)
8200
7582
val->intval = port->pps_data.max_volt * 1000;
7583
+
else if (port->spr_avs_data.active)
7584
+
val->intval = port->spr_avs_data.max_out_volt_mv * 1000;
8201
7585
else
8202
7586
val->intval = port->supply_voltage * 1000;
8203
7587
···
8219
7599
{
8220
7600
if (port->pps_data.active)
8221
7601
val->intval = port->pps_data.max_curr * 1000;
7602
+
else if (port->spr_avs_data.active)
7603
+
val->intval = port->spr_avs_data.max_current_ma * 1000;
8222
7604
else
8223
7605
val->intval = port->current_limit * 1000;
8224
7606
···
8296
7674
return ret;
8297
7675
}
8298
7676
7677
+
static int tcpm_disable_pps_avs(struct tcpm_port *port)
7678
+
{
7679
+
int ret = 0;
7680
+
7681
+
if (port->pps_data.active)
7682
+
ret = tcpm_pps_activate(port, false);
7683
+
else if (port->spr_avs_data.active)
7684
+
ret = tcpm_spr_avs_activate(port, false);
7685
+
7686
+
return ret;
7687
+
}
7688
+
8299
7689
static int tcpm_psy_set_online(struct tcpm_port *port,
8300
7690
const union power_supply_propval *val)
8301
7691
{
8302
-
int ret;
7692
+
int ret = 0;
8303
7693
8304
7694
switch (val->intval) {
8305
7695
case TCPM_PSY_FIXED_ONLINE:
8306
-
ret = tcpm_pps_activate(port, false);
7696
+
ret = tcpm_disable_pps_avs(port);
8307
7697
break;
8308
-
case TCPM_PSY_PROG_ONLINE:
8309
-
ret = tcpm_pps_activate(port, true);
7698
+
case TCPM_PSY_PPS_ONLINE:
7699
+
if (port->spr_avs_data.active)
7700
+
ret = tcpm_spr_avs_activate(port, false);
7701
+
if (!ret)
7702
+
ret = tcpm_pps_activate(port, true);
7703
+
break;
7704
+
case TCPM_PSY_SPR_AVS_ONLINE:
7705
+
tcpm_log(port, "request to set AVS online");
7706
+
if (port->spr_avs_data.active)
7707
+
return 0;
7708
+
ret = tcpm_disable_pps_avs(port);
7709
+
if (ret)
7710
+
break;
7711
+
ret = tcpm_spr_avs_activate(port, true);
8310
7712
break;
8311
7713
default:
8312
7714
ret = -EINVAL;
···
8359
7713
ret = tcpm_psy_set_online(port, val);
8360
7714
break;
8361
7715
case POWER_SUPPLY_PROP_VOLTAGE_NOW:
8362
-
ret = tcpm_pps_set_out_volt(port, val->intval / 1000);
7716
+
ret = tcpm_aug_set_out_volt(port, val->intval / 1000);
8363
7717
break;
8364
7718
case POWER_SUPPLY_PROP_CURRENT_NOW:
8365
-
if (val->intval > port->pps_data.max_curr * 1000)
8366
-
ret = -EINVAL;
8367
-
else
8368
-
ret = tcpm_pps_set_op_curr(port, val->intval / 1000);
7719
+
ret = tcpm_aug_set_op_curr(port, val->intval / 1000);
8369
7720
break;
8370
7721
default:
8371
7722
ret = -EINVAL;
···
8407
7764
port->psy_desc.type = POWER_SUPPLY_TYPE_USB;
8408
7765
port->psy_desc.usb_types = BIT(POWER_SUPPLY_USB_TYPE_C) |
8409
7766
BIT(POWER_SUPPLY_USB_TYPE_PD) |
8410
-
BIT(POWER_SUPPLY_USB_TYPE_PD_PPS);
7767
+
BIT(POWER_SUPPLY_USB_TYPE_PD_PPS) |
7768
+
BIT(POWER_SUPPLY_USB_TYPE_PD_PPS_SPR_AVS) |
7769
+
BIT(POWER_SUPPLY_USB_TYPE_PD_SPR_AVS);
8411
7770
port->psy_desc.properties = tcpm_psy_props;
8412
7771
port->psy_desc.num_properties = ARRAY_SIZE(tcpm_psy_props);
8413
7772
port->psy_desc.get_property = tcpm_psy_get_prop;
···
8504
7859
8505
7860
init_completion(&port->tx_complete);
8506
7861
init_completion(&port->swap_complete);
8507
-
init_completion(&port->pps_complete);
7862
+
init_completion(&port->aug_supply_req_complete);
8508
7863
tcpm_debugfs_init(port);
8509
7864
8510
7865
err = tcpm_fw_get_caps(port, tcpc->fwnode);
+4
-2
drivers/usb/typec/tipd/core.c
+4
-2
drivers/usb/typec/tipd/core.c
···
820
820
desc.identity = &st.partner_identity;
821
821
822
822
tps->partner = typec_register_partner(tps->port, &desc);
823
-
if (IS_ERR(tps->partner))
824
-
dev_warn(tps->dev, "%s: failed to register partnet\n", __func__);
823
+
if (IS_ERR(tps->partner)) {
824
+
dev_warn(tps->dev, "%s: failed to register partner\n", __func__);
825
+
return;
826
+
}
825
827
826
828
if (desc.identity) {
827
829
typec_partner_set_identity(tps->partner);
+24
-2
drivers/usb/typec/ucsi/cros_ec_ucsi.c
+24
-2
drivers/usb/typec/ucsi/cros_ec_ucsi.c
···
5
5
* Copyright 2024 Google LLC.
6
6
*/
7
7
8
+
#include <linux/acpi.h>
8
9
#include <linux/container_of.h>
9
10
#include <linux/dev_printk.h>
10
11
#include <linux/jiffies.h>
11
12
#include <linux/mod_devicetable.h>
12
13
#include <linux/module.h>
14
+
#include <linux/of.h>
13
15
#include <linux/platform_data/cros_ec_commands.h>
14
16
#include <linux/platform_data/cros_usbpd_notify.h>
15
17
#include <linux/platform_data/cros_ec_proto.h>
···
259
257
static int cros_ucsi_probe(struct platform_device *pdev)
260
258
{
261
259
struct device *dev = &pdev->dev;
262
-
struct cros_ec_dev *ec_data = dev_get_drvdata(dev->parent);
263
260
struct cros_ucsi_data *udata;
264
261
int ret;
265
262
···
266
265
if (!udata)
267
266
return -ENOMEM;
268
267
268
+
/* ACPI and OF FW nodes for cros_ec_ucsi are children of the ChromeOS EC. If the
269
+
* cros_ec_ucsi device has an ACPI or OF FW node, its parent is the ChromeOS EC device.
270
+
* Platforms without a FW node for cros_ec_ucsi may add it as a subdevice of cros_ec_dev.
271
+
*/
269
272
udata->dev = dev;
273
+
if (is_acpi_device_node(dev->fwnode) || is_of_node(dev->fwnode))
274
+
udata->ec = dev_get_drvdata(dev->parent);
275
+
else
276
+
udata->ec = ((struct cros_ec_dev *)dev_get_drvdata(dev->parent))->ec_dev;
270
277
271
-
udata->ec = ec_data->ec_dev;
272
278
if (!udata->ec)
273
279
return dev_err_probe(dev, -ENODEV, "couldn't find parent EC device\n");
274
280
···
356
348
};
357
349
MODULE_DEVICE_TABLE(platform, cros_ucsi_id);
358
350
351
+
static const struct acpi_device_id cros_ec_ucsi_acpi_device_ids[] = {
352
+
{ "GOOG0021", 0 },
353
+
{ }
354
+
};
355
+
MODULE_DEVICE_TABLE(acpi, cros_ec_ucsi_acpi_device_ids);
356
+
357
+
static const struct of_device_id cros_ucsi_of_match[] = {
358
+
{ .compatible = "google,cros-ec-ucsi", },
359
+
{}
360
+
};
361
+
MODULE_DEVICE_TABLE(of, cros_ucsi_of_match);
362
+
359
363
static struct platform_driver cros_ucsi_driver = {
360
364
.driver = {
361
365
.name = KBUILD_MODNAME,
362
366
.pm = &cros_ucsi_pm_ops,
367
+
.acpi_match_table = cros_ec_ucsi_acpi_device_ids,
368
+
.of_match_table = cros_ucsi_of_match,
363
369
},
364
370
.id_table = cros_ucsi_id,
365
371
.probe = cros_ucsi_probe,
+12
-2
drivers/usb/typec/ucsi/ucsi.c
+12
-2
drivers/usb/typec/ucsi/ucsi.c
···
241
241
if (cci & UCSI_CCI_ERROR)
242
242
ret = ucsi_read_error(ucsi, connector_num);
243
243
244
+
trace_ucsi_run_command(cmd, ret);
245
+
244
246
mutex_unlock(&ucsi->ppm_lock);
245
247
return ret;
246
248
}
···
1188
1186
if (UCSI_CONSTAT(con, PARTNER_FLAG_USB))
1189
1187
typec_set_mode(con->port, TYPEC_STATE_USB);
1190
1188
}
1189
+
1190
+
if (((con->ucsi->version >= UCSI_VERSION_3_0 &&
1191
+
UCSI_CONSTAT(con, PARTNER_FLAG_USB4_GEN4)) ||
1192
+
(con->ucsi->version >= UCSI_VERSION_2_0 &&
1193
+
UCSI_CONSTAT(con, PARTNER_FLAG_USB4_GEN3))) && con->partner)
1194
+
typec_partner_set_usb_mode(con->partner, USB_MODE_USB4);
1191
1195
}
1192
1196
1193
-
/* Only notify USB controller if partner supports USB data */
1194
-
if (!(UCSI_CONSTAT(con, PARTNER_FLAG_USB)))
1197
+
if ((!UCSI_CONSTAT(con, PARTNER_FLAG_USB)) &&
1198
+
((con->ucsi->quirks & UCSI_USB4_IMPLIES_USB) &&
1199
+
(!(UCSI_CONSTAT(con, PARTNER_FLAG_USB4_GEN3) ||
1200
+
UCSI_CONSTAT(con, PARTNER_FLAG_USB4_GEN4)))))
1195
1201
u_role = USB_ROLE_NONE;
1196
1202
1197
1203
ret = usb_role_switch_set_role(con->usb_role_sw, u_role);
+3
drivers/usb/typec/ucsi/ucsi.h
+3
drivers/usb/typec/ucsi/ucsi.h
···
497
497
unsigned long quirks;
498
498
#define UCSI_NO_PARTNER_PDOS BIT(0) /* Don't read partner's PDOs */
499
499
#define UCSI_DELAY_DEVICE_PDOS BIT(1) /* Reading PDOs fails until the parter is in PD mode */
500
+
501
+
/* USB4 connection can imply that USB communcation is supported */
502
+
#define UCSI_USB4_IMPLIES_USB BIT(2)
500
503
};
501
504
502
505
#define UCSI_MAX_DATA_LENGTH(u) (((u)->version < UCSI_VERSION_2_0) ? 0x10 : 0xff)
+4
drivers/usb/typec/ucsi/ucsi_glink.c
+4
drivers/usb/typec/ucsi/ucsi_glink.c
···
371
371
static unsigned long quirk_sc8180x = UCSI_NO_PARTNER_PDOS;
372
372
static unsigned long quirk_sc8280xp = UCSI_NO_PARTNER_PDOS | UCSI_DELAY_DEVICE_PDOS;
373
373
static unsigned long quirk_sm8450 = UCSI_DELAY_DEVICE_PDOS;
374
+
static unsigned long quirk_x1e80100 = UCSI_DELAY_DEVICE_PDOS | UCSI_USB4_IMPLIES_USB;
374
375
375
376
static const struct of_device_id pmic_glink_ucsi_of_quirks[] = {
377
+
{ .compatible = "qcom,glymur-pmic-glink", .data = &quirk_sm8450, },
378
+
{ .compatible = "qcom,kaanapali-pmic-glink", .data = &quirk_sm8450, },
376
379
{ .compatible = "qcom,qcm6490-pmic-glink", .data = &quirk_sc8280xp, },
377
380
{ .compatible = "qcom,sc8180x-pmic-glink", .data = &quirk_sc8180x, },
378
381
{ .compatible = "qcom,sc8280xp-pmic-glink", .data = &quirk_sc8280xp, },
379
382
{ .compatible = "qcom,sm8350-pmic-glink", .data = &quirk_sc8180x, },
380
383
{ .compatible = "qcom,sm8450-pmic-glink", .data = &quirk_sm8450, },
381
384
{ .compatible = "qcom,sm8550-pmic-glink", .data = &quirk_sm8450, },
385
+
{ .compatible = "qcom,x1e80100-pmic-glink", .data = &quirk_x1e80100, },
382
386
{}
383
387
};
384
388
+1
-1
drivers/usb/typec/ucsi/ucsi_huawei_gaokun.c
+1
-1
drivers/usb/typec/ucsi/ucsi_huawei_gaokun.c
···
193
193
gaokun_set_orientation(con, &uec->ports[idx]);
194
194
}
195
195
196
-
const struct ucsi_operations gaokun_ucsi_ops = {
196
+
static const struct ucsi_operations gaokun_ucsi_ops = {
197
197
.read_version = gaokun_ucsi_read_version,
198
198
.read_cci = gaokun_ucsi_read_cci,
199
199
.poll_cci = gaokun_ucsi_read_cci,
+1
-4
drivers/usb/usbip/stub_dev.c
+1
-4
drivers/usb/usbip/stub_dev.c
···
267
267
if (!sdev)
268
268
return NULL;
269
269
270
-
sdev->udev = usb_get_dev(udev);
270
+
sdev->udev = udev;
271
271
272
272
/*
273
273
* devid is defined with devnum when this driver is first allocated.
···
409
409
put_busid_priv(busid_priv);
410
410
411
411
sdev_free:
412
-
usb_put_dev(udev);
413
412
stub_device_free(sdev);
414
413
415
414
return rc;
···
486
487
487
488
/* shutdown the current connection */
488
489
shutdown_busid(busid_priv);
489
-
490
-
usb_put_dev(sdev->udev);
491
490
492
491
/* we already have busid_priv, just lock busid_lock */
493
492
spin_lock(&busid_priv->busid_lock);
+75
-8
drivers/usb/usbip/usbip_common.c
+75
-8
drivers/usb/usbip/usbip_common.c
···
470
470
urb->status = rpdu->status;
471
471
urb->actual_length = rpdu->actual_length;
472
472
urb->start_frame = rpdu->start_frame;
473
+
/*
474
+
* The number_of_packets field determines the length of
475
+
* iso_frame_desc[], which is a flexible array allocated
476
+
* at URB creation time. A response must never claim more
477
+
* packets than originally submitted; doing so would cause
478
+
* an out-of-bounds write in usbip_recv_iso() and
479
+
* usbip_pad_iso(). Clamp to zero on violation so both
480
+
* functions safely return early.
481
+
*/
482
+
if (rpdu->number_of_packets < 0 ||
483
+
rpdu->number_of_packets > urb->number_of_packets)
484
+
rpdu->number_of_packets = 0;
473
485
urb->number_of_packets = rpdu->number_of_packets;
474
486
urb->error_count = rpdu->error_count;
475
487
}
···
674
662
void *buff;
675
663
struct usbip_iso_packet_descriptor *iso;
676
664
int np = urb->number_of_packets;
677
-
int size = np * sizeof(*iso);
665
+
int size;
678
666
int i;
679
667
int ret;
680
-
int total_length = 0;
668
+
u32 total_length = 0;
681
669
682
670
if (!usb_pipeisoc(urb->pipe))
683
671
return 0;
684
672
685
-
/* my Bluetooth dongle gets ISO URBs which are np = 0 */
686
-
if (np == 0)
687
-
return 0;
673
+
if (np <= 0 || np > USBIP_MAX_ISO_PACKETS) {
674
+
dev_err(&urb->dev->dev,
675
+
"recv iso: invalid number_of_packets %d\n", np);
676
+
/*
677
+
* usbip_pack_ret_submit() already set urb->number_of_packets
678
+
* from the wire. Zero it so processcompl() does not iterate
679
+
* OOB descriptors on the way out.
680
+
*/
681
+
urb->number_of_packets = 0;
682
+
return -EPROTO;
683
+
}
688
684
689
-
buff = kzalloc(size, GFP_KERNEL);
685
+
size = np * sizeof(*iso);
686
+
687
+
buff = kcalloc(np, sizeof(*iso), GFP_KERNEL);
690
688
if (!buff)
691
689
return -ENOMEM;
692
690
···
718
696
for (i = 0; i < np; i++) {
719
697
usbip_iso_packet_correct_endian(&iso[i], 0);
720
698
usbip_pack_iso(&iso[i], &urb->iso_frame_desc[i], 0);
699
+
if (urb->iso_frame_desc[i].actual_length >
700
+
(unsigned int)urb->transfer_buffer_length) {
701
+
dev_err(&urb->dev->dev,
702
+
"recv iso: frame actual_length %u exceeds buffer %d\n",
703
+
urb->iso_frame_desc[i].actual_length,
704
+
urb->transfer_buffer_length);
705
+
kfree(buff);
706
+
return -EPROTO;
707
+
}
721
708
total_length += urb->iso_frame_desc[i].actual_length;
722
709
}
723
710
724
711
kfree(buff);
725
712
726
-
if (total_length != urb->actual_length) {
713
+
if (total_length != (u32)urb->actual_length) {
727
714
dev_err(&urb->dev->dev,
728
-
"total length of iso packets %d not equal to actual length of buffer %d\n",
715
+
"total length of iso packets %u not equal to actual length of buffer %d\n",
729
716
total_length, urb->actual_length);
730
717
731
718
if (ud->side == USBIP_STUB || ud->side == USBIP_VUDC)
···
782
751
*/
783
752
for (i = np-1; i > 0; i--) {
784
753
actualoffset -= urb->iso_frame_desc[i].actual_length;
754
+
755
+
/*
756
+
* Validate source range: actualoffset can go negative
757
+
* via crafted actual_length values from the wire.
758
+
*/
759
+
if (actualoffset < 0 ||
760
+
(unsigned int)actualoffset >
761
+
(unsigned int)urb->transfer_buffer_length ||
762
+
urb->iso_frame_desc[i].actual_length >
763
+
(unsigned int)urb->transfer_buffer_length -
764
+
(unsigned int)actualoffset) {
765
+
dev_err(&urb->dev->dev,
766
+
"pad_iso: bad src off=%d len=%u bufsz=%d\n",
767
+
actualoffset,
768
+
urb->iso_frame_desc[i].actual_length,
769
+
urb->transfer_buffer_length);
770
+
return;
771
+
}
772
+
773
+
/*
774
+
* Validate destination range: iso_frame_desc[i].offset
775
+
* is wire-supplied and must not exceed the buffer.
776
+
*/
777
+
if (urb->iso_frame_desc[i].offset >
778
+
(unsigned int)urb->transfer_buffer_length ||
779
+
urb->iso_frame_desc[i].actual_length >
780
+
(unsigned int)urb->transfer_buffer_length -
781
+
urb->iso_frame_desc[i].offset) {
782
+
dev_err(&urb->dev->dev,
783
+
"pad_iso: bad dst off=%u len=%u bufsz=%d\n",
784
+
urb->iso_frame_desc[i].offset,
785
+
urb->iso_frame_desc[i].actual_length,
786
+
urb->transfer_buffer_length);
787
+
return;
788
+
}
789
+
785
790
memmove(urb->transfer_buffer + urb->iso_frame_desc[i].offset,
786
791
urb->transfer_buffer + actualoffset,
787
792
urb->iso_frame_desc[i].actual_length);
+1
-1
drivers/usb/usbip/vhci_sysfs.c
+1
-1
drivers/usb/usbip/vhci_sysfs.c
+36
include/dt-bindings/usb/pd.h
+36
include/dt-bindings/usb/pd.h
···
60
60
PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma))
61
61
62
62
#define APDO_TYPE_PPS 0
63
+
#define APDO_TYPE_SPR_AVS 2
63
64
64
65
#define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */
65
66
#define PDO_APDO_TYPE_MASK 0x3
···
85
84
(PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) | \
86
85
PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) | \
87
86
PDO_PPS_APDO_MAX_CURR(max_ma))
87
+
88
+
#define PDO_SPR_AVS_APDO_9V_TO_15V_MAX_CURR_SHIFT 10 /* 10mA units */
89
+
#define PDO_SPR_AVS_APDO_15V_TO_20V_MAX_CURR_SHIFT 0 /* 10mA units */
90
+
#define PDO_SPR_AVS_APDO_MAX_CURR_MASK 0x3ff
91
+
92
+
#define PDO_SPR_AVS_APDO_9V_TO_15V_MAX_CURR(max_cur_9v_to_15v_ma) \
93
+
((((max_cur_9v_to_15v_ma) / 10) & PDO_SPR_AVS_APDO_MAX_CURR_MASK) << \
94
+
PDO_SPR_AVS_APDO_9V_TO_15V_MAX_CURR_SHIFT)
95
+
96
+
#define PDO_SPR_AVS_APDO_15V_TO_20V_MAX_CURR(max_cur_15v_to_20v_ma) \
97
+
((((max_cur_15v_to_20v_ma) / 10) & PDO_SPR_AVS_APDO_MAX_CURR_MASK) << \
98
+
PDO_SPR_AVS_APDO_15V_TO_20V_MAX_CURR_SHIFT)
99
+
100
+
#define PDO_SPR_AVS_SNK_APDO(max_cur_9v_to_15v_ma, max_cur_15v_to_20v_ma) \
101
+
(PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_SPR_AVS) | \
102
+
PDO_SPR_AVS_APDO_9V_TO_15V_MAX_CURR(max_cur_9v_to_15v_ma) | \
103
+
PDO_SPR_AVS_APDO_15V_TO_20V_MAX_CURR(max_cur_15v_to_20v_ma))
88
104
89
105
/*
90
106
* Based on "Table 6-14 Fixed Supply PDO - Sink" of "USB Power Delivery Specification Revision 3.0,
···
482
464
(((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 | ((ver) & 0x7) << 21 \
483
465
| ((vbm) & 0x3) << 15 | (curr) << 14 | ((vbi) & 0x3f) << 7 \
484
466
| ((gi) & 0x3f) << 1 | (ct))
467
+
468
+
/*
469
+
* Sink Load Characteristics
470
+
* -------------------------
471
+
* <15> :: Can tolerate vbus voltage droop
472
+
* <11:14> :: Duty cycle in 5% increments when bits 4:0 are non-zero
473
+
* <10:5> :: Overload period in 20ms when bits 4:0 are non-zero
474
+
* <4:0> :: Percent overload in 10% increments. Values higher than 25 are
475
+
* clipped to 250%
476
+
*/
477
+
#define SINK_LOAD_CHAR(vdroop, duty_cycle, period, percent_ol) \
478
+
(((vdroop) & 0x1) << 15 | ((duty_cycle) & 0xf) << 11 | \
479
+
((period) & 0x3f) << 5 | ((percent_ol) & 0x1f))
480
+
481
+
/* Compliance */
482
+
#define COMPLIANCE_LPS (1 << 0)
483
+
#define COMPLIANCE_PS1 (1 << 1)
484
+
#define COMPLIANCE_PS2 (1 << 2)
485
485
486
486
#endif /* __DT_POWER_DELIVERY_H */
+3
include/linux/linear_range.h
+3
include/linux/linear_range.h
···
57
57
int linear_range_get_selector_low_array(const struct linear_range *r,
58
58
int ranges, unsigned int val,
59
59
unsigned int *selector, bool *found);
60
+
int linear_range_get_selector_high_array(const struct linear_range *r,
61
+
int ranges, unsigned int val,
62
+
unsigned int *selector, bool *found);
60
63
61
64
#endif
+137
-29
include/linux/mfd/max77759.h
+137
-29
include/linux/mfd/max77759.h
···
59
59
#define MAX77759_MAXQ_REG_AP_DATAIN0 0xb1
60
60
#define MAX77759_MAXQ_REG_UIC_SWRST 0xe0
61
61
62
-
#define MAX77759_CHGR_REG_CHG_INT 0xb0
63
-
#define MAX77759_CHGR_REG_CHG_INT2 0xb1
64
-
#define MAX77759_CHGR_REG_CHG_INT_MASK 0xb2
65
-
#define MAX77759_CHGR_REG_CHG_INT2_MASK 0xb3
66
-
#define MAX77759_CHGR_REG_CHG_INT_OK 0xb4
67
-
#define MAX77759_CHGR_REG_CHG_DETAILS_00 0xb5
68
-
#define MAX77759_CHGR_REG_CHG_DETAILS_01 0xb6
69
-
#define MAX77759_CHGR_REG_CHG_DETAILS_02 0xb7
70
-
#define MAX77759_CHGR_REG_CHG_DETAILS_03 0xb8
71
-
#define MAX77759_CHGR_REG_CHG_CNFG_00 0xb9
72
-
#define MAX77759_CHGR_REG_CHG_CNFG_01 0xba
73
-
#define MAX77759_CHGR_REG_CHG_CNFG_02 0xbb
74
-
#define MAX77759_CHGR_REG_CHG_CNFG_03 0xbc
75
-
#define MAX77759_CHGR_REG_CHG_CNFG_04 0xbd
76
-
#define MAX77759_CHGR_REG_CHG_CNFG_05 0xbe
77
-
#define MAX77759_CHGR_REG_CHG_CNFG_06 0xbf
78
-
#define MAX77759_CHGR_REG_CHG_CNFG_07 0xc0
79
-
#define MAX77759_CHGR_REG_CHG_CNFG_08 0xc1
80
-
#define MAX77759_CHGR_REG_CHG_CNFG_09 0xc2
81
-
#define MAX77759_CHGR_REG_CHG_CNFG_10 0xc3
82
-
#define MAX77759_CHGR_REG_CHG_CNFG_11 0xc4
83
-
#define MAX77759_CHGR_REG_CHG_CNFG_12 0xc5
84
-
#define MAX77759_CHGR_REG_CHG_CNFG_13 0xc6
85
-
#define MAX77759_CHGR_REG_CHG_CNFG_14 0xc7
86
-
#define MAX77759_CHGR_REG_CHG_CNFG_15 0xc8
87
-
#define MAX77759_CHGR_REG_CHG_CNFG_16 0xc9
88
-
#define MAX77759_CHGR_REG_CHG_CNFG_17 0xca
89
-
#define MAX77759_CHGR_REG_CHG_CNFG_18 0xcb
90
-
#define MAX77759_CHGR_REG_CHG_CNFG_19 0xcc
62
+
#define MAX77759_CHGR_REG_CHG_INT 0xb0
63
+
#define MAX77759_CHGR_REG_CHG_INT_AICL BIT(7)
64
+
#define MAX77759_CHGR_REG_CHG_INT_CHGIN BIT(6)
65
+
#define MAX77759_CHGR_REG_CHG_INT_WCIN BIT(5)
66
+
#define MAX77759_CHGR_REG_CHG_INT_CHG BIT(4)
67
+
#define MAX77759_CHGR_REG_CHG_INT_BAT BIT(3)
68
+
#define MAX77759_CHGR_REG_CHG_INT_INLIM BIT(2)
69
+
#define MAX77759_CHGR_REG_CHG_INT_THM2 BIT(1)
70
+
#define MAX77759_CHGR_REG_CHG_INT_BYP BIT(0)
71
+
#define MAX77759_CHGR_REG_CHG_INT2 0xb1
72
+
#define MAX77759_CHGR_REG_CHG_INT2_INSEL BIT(7)
73
+
#define MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1 BIT(6)
74
+
#define MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2 BIT(5)
75
+
#define MAX77759_CHGR_REG_CHG_INT2_BAT_OILO BIT(4)
76
+
#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC BIT(3)
77
+
#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV BIT(2)
78
+
#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO BIT(1)
79
+
#define MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE BIT(0)
80
+
#define MAX77759_CHGR_REG_CHG_INT_MASK 0xb2
81
+
#define MAX77759_CHGR_REG_CHG_INT2_MASK 0xb3
82
+
#define MAX77759_CHGR_REG_CHG_INT_OK 0xb4
83
+
#define MAX77759_CHGR_REG_CHG_DETAILS_00 0xb5
84
+
#define MAX77759_CHGR_REG_CHG_DETAILS_00_CHGIN_DTLS GENMASK(6, 5)
85
+
#define MAX77759_CHGR_REG_CHG_DETAILS_01 0xb6
86
+
#define MAX77759_CHGR_REG_CHG_DETAILS_01_BAT_DTLS GENMASK(6, 4)
87
+
#define MAX77759_CHGR_REG_CHG_DETAILS_01_CHG_DTLS GENMASK(3, 0)
88
+
#define MAX77759_CHGR_REG_CHG_DETAILS_02 0xb7
89
+
#define MAX77759_CHGR_REG_CHG_DETAILS_02_CHGIN_STS BIT(5)
90
+
#define MAX77759_CHGR_REG_CHG_DETAILS_03 0xb8
91
+
#define MAX77759_CHGR_REG_CHG_CNFG_00 0xb9
92
+
#define MAX77759_CHGR_REG_CHG_CNFG_00_MODE GENMASK(3, 0)
93
+
#define MAX77759_CHGR_REG_CHG_CNFG_01 0xba
94
+
#define MAX77759_CHGR_REG_CHG_CNFG_02 0xbb
95
+
#define MAX77759_CHGR_REG_CHG_CNFG_02_CHGCC GENMASK(5, 0)
96
+
#define MAX77759_CHGR_REG_CHG_CNFG_03 0xbc
97
+
#define MAX77759_CHGR_REG_CHG_CNFG_04 0xbd
98
+
#define MAX77759_CHGR_REG_CHG_CNFG_04_CHG_CV_PRM GENMASK(5, 0)
99
+
#define MAX77759_CHGR_REG_CHG_CNFG_05 0xbe
100
+
#define MAX77759_CHGR_REG_CHG_CNFG_06 0xbf
101
+
#define MAX77759_CHGR_REG_CHG_CNFG_06_CHGPROT GENMASK(3, 2)
102
+
#define MAX77759_CHGR_REG_CHG_CNFG_07 0xc0
103
+
#define MAX77759_CHGR_REG_CHG_CNFG_08 0xc1
104
+
#define MAX77759_CHGR_REG_CHG_CNFG_09 0xc2
105
+
#define MAX77759_CHGR_REG_CHG_CNFG_09_CHGIN_ILIM GENMASK(6, 0)
106
+
#define MAX77759_CHGR_REG_CHG_CNFG_10 0xc3
107
+
#define MAX77759_CHGR_REG_CHG_CNFG_11 0xc4
108
+
#define MAX77759_CHGR_REG_CHG_CNFG_12 0xc5
109
+
/* Wireless Charging input channel select */
110
+
#define MAX77759_CHGR_REG_CHG_CNFG_12_WCINSEL BIT(6)
111
+
/* CHGIN/USB input channel select */
112
+
#define MAX77759_CHGR_REG_CHG_CNFG_12_CHGINSEL BIT(5)
113
+
#define MAX77759_CHGR_REG_CHG_CNFG_13 0xc6
114
+
#define MAX77759_CHGR_REG_CHG_CNFG_14 0xc7
115
+
#define MAX77759_CHGR_REG_CHG_CNFG_15 0xc8
116
+
#define MAX77759_CHGR_REG_CHG_CNFG_16 0xc9
117
+
#define MAX77759_CHGR_REG_CHG_CNFG_17 0xca
118
+
#define MAX77759_CHGR_REG_CHG_CNFG_18 0xcb
119
+
#define MAX77759_CHGR_REG_CHG_CNFG_18_WDTEN BIT(0)
120
+
#define MAX77759_CHGR_REG_CHG_CNFG_19 0xcc
91
121
92
122
/* MaxQ opcodes for max77759_maxq_command() */
93
123
#define MAX77759_MAXQ_OPCODE_MAXLENGTH (MAX77759_MAXQ_REG_AP_DATAOUT32 - \
···
130
100
#define MAX77759_MAXQ_OPCODE_GPIO_CONTROL_WRITE 0x24
131
101
#define MAX77759_MAXQ_OPCODE_USER_SPACE_READ 0x81
132
102
#define MAX77759_MAXQ_OPCODE_USER_SPACE_WRITE 0x82
103
+
104
+
/**
105
+
* enum max77759_chgr_chgin_dtls_status - Charger Input Status
106
+
* @MAX77759_CHGR_CHGIN_DTLS_VBUS_UNDERVOLTAGE:
107
+
* Charger input voltage (Vchgin) < Under Voltage Threshold (Vuvlo)
108
+
* @MAX77759_CHGR_CHGIN_DTLS_VBUS_MARGINAL_VOLTAGE:
109
+
* Vchgin > Vuvlo and Vchgin < (Battery Voltage (Vbatt) + system voltage (Vsys))
110
+
* @MAX77759_CHGR_CHGIN_DTLS_VBUS_OVERVOLTAGE:
111
+
* Vchgin > Over Voltage threshold (Vovlo)
112
+
* @MAX77759_CHGR_CHGIN_DTLS_VBUS_VALID:
113
+
* Vchgin > Vuvlo, Vchgin < Vovlo and Vchgin > (Vsys + Vbatt)
114
+
*/
115
+
enum max77759_chgr_chgin_dtls_status {
116
+
MAX77759_CHGR_CHGIN_DTLS_VBUS_UNDERVOLTAGE,
117
+
MAX77759_CHGR_CHGIN_DTLS_VBUS_MARGINAL_VOLTAGE,
118
+
MAX77759_CHGR_CHGIN_DTLS_VBUS_OVERVOLTAGE,
119
+
MAX77759_CHGR_CHGIN_DTLS_VBUS_VALID,
120
+
};
121
+
122
+
/**
123
+
* enum max77759_chgr_bat_dtls_states - Battery Details
124
+
* @MAX77759_CHGR_BAT_DTLS_NO_BATT_CHG_SUSP: No battery and the charger suspended
125
+
* @MAX77759_CHGR_BAT_DTLS_DEAD_BATTERY: Vbatt < Vtrickle
126
+
* @MAX77759_CHGR_BAT_DTLS_BAT_CHG_TIMER_FAULT: Charging suspended due to timer fault
127
+
* @MAX77759_CHGR_BAT_DTLS_BAT_OKAY: Battery okay and Vbatt > Min Sys Voltage (Vsysmin)
128
+
* @MAX77759_CHGR_BAT_DTLS_BAT_UNDERVOLTAGE: Battery is okay. Vtrickle < Vbatt < Vsysmin
129
+
* @MAX77759_CHGR_BAT_DTLS_BAT_OVERVOLTAGE: Battery voltage > Overvoltage threshold
130
+
* @MAX77759_CHGR_BAT_DTLS_BAT_OVERCURRENT: Battery current exceeds overcurrent threshold
131
+
* @MAX77759_CHGR_BAT_DTLS_BAT_ONLY_MODE: Battery only mode and battery level not available
132
+
*/
133
+
enum max77759_chgr_bat_dtls_states {
134
+
MAX77759_CHGR_BAT_DTLS_NO_BATT_CHG_SUSP,
135
+
MAX77759_CHGR_BAT_DTLS_DEAD_BATTERY,
136
+
MAX77759_CHGR_BAT_DTLS_BAT_CHG_TIMER_FAULT,
137
+
MAX77759_CHGR_BAT_DTLS_BAT_OKAY,
138
+
MAX77759_CHGR_BAT_DTLS_BAT_UNDERVOLTAGE,
139
+
MAX77759_CHGR_BAT_DTLS_BAT_OVERVOLTAGE,
140
+
MAX77759_CHGR_BAT_DTLS_BAT_OVERCURRENT,
141
+
MAX77759_CHGR_BAT_DTLS_BAT_ONLY_MODE,
142
+
};
143
+
144
+
/**
145
+
* enum max77759_chgr_chg_dtls_states - Charger Details
146
+
* @MAX77759_CHGR_CHG_DTLS_PREQUAL: Charger in prequalification mode
147
+
* @MAX77759_CHGR_CHG_DTLS_CC: Charger in fast charge const curr mode
148
+
* @MAX77759_CHGR_CHG_DTLS_CV: Charger in fast charge const voltage mode
149
+
* @MAX77759_CHGR_CHG_DTLS_TO: Charger is in top off mode
150
+
* @MAX77759_CHGR_CHG_DTLS_DONE: Charger is done
151
+
* @MAX77759_CHGR_CHG_DTLS_RSVD_1: Reserved
152
+
* @MAX77759_CHGR_CHG_DTLS_TIMER_FAULT: Charger is in timer fault mode
153
+
* @MAX77759_CHGR_CHG_DTLS_SUSP_BATT_THM: Charger is suspended as battery removal detected
154
+
* @MAX77759_CHGR_CHG_DTLS_OFF: Charger is off. Input invalid or charger disabled
155
+
* @MAX77759_CHGR_CHG_DTLS_RSVD_2: Reserved
156
+
* @MAX77759_CHGR_CHG_DTLS_RSVD_3: Reserved
157
+
* @MAX77759_CHGR_CHG_DTLS_OFF_WDOG_TIMER: Charger is off as watchdog timer expired
158
+
* @MAX77759_CHGR_CHG_DTLS_SUSP_JEITA: Charger is in JEITA control mode
159
+
*/
160
+
enum max77759_chgr_chg_dtls_states {
161
+
MAX77759_CHGR_CHG_DTLS_PREQUAL,
162
+
MAX77759_CHGR_CHG_DTLS_CC,
163
+
MAX77759_CHGR_CHG_DTLS_CV,
164
+
MAX77759_CHGR_CHG_DTLS_TO,
165
+
MAX77759_CHGR_CHG_DTLS_DONE,
166
+
MAX77759_CHGR_CHG_DTLS_RSVD_1,
167
+
MAX77759_CHGR_CHG_DTLS_TIMER_FAULT,
168
+
MAX77759_CHGR_CHG_DTLS_SUSP_BATT_THM,
169
+
MAX77759_CHGR_CHG_DTLS_OFF,
170
+
MAX77759_CHGR_CHG_DTLS_RSVD_2,
171
+
MAX77759_CHGR_CHG_DTLS_RSVD_3,
172
+
MAX77759_CHGR_CHG_DTLS_OFF_WDOG_TIMER,
173
+
MAX77759_CHGR_CHG_DTLS_SUSP_JEITA,
174
+
};
175
+
176
+
enum max77759_chgr_mode {
177
+
MAX77759_CHGR_MODE_OFF,
178
+
MAX77759_CHGR_MODE_CHG_BUCK_ON = 0x5,
179
+
MAX77759_CHGR_MODE_OTG_BOOST_ON = 0xA,
180
+
};
133
181
134
182
/**
135
183
* struct max77759 - core max77759 internal data structure
+3
include/linux/power_supply.h
+3
include/linux/power_supply.h
···
210
210
POWER_SUPPLY_USB_TYPE_PD, /* Power Delivery Port */
211
211
POWER_SUPPLY_USB_TYPE_PD_DRP, /* PD Dual Role Port */
212
212
POWER_SUPPLY_USB_TYPE_PD_PPS, /* PD Programmable Power Supply */
213
+
/* PD Standard Power Range Adjustable Voltage Supply */
214
+
POWER_SUPPLY_USB_TYPE_PD_SPR_AVS,
215
+
POWER_SUPPLY_USB_TYPE_PD_PPS_SPR_AVS, /* Supports both PD PPS + SPR AVS */
213
216
POWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID, /* Apple Charging Method */
214
217
};
215
218
+4
-1
include/linux/usb.h
+4
-1
include/linux/usb.h
···
55
55
* @eusb2_isoc_ep_comp: eUSB2 isoc companion descriptor for this endpoint
56
56
* @urb_list: urbs queued to this endpoint; maintained by usbcore
57
57
* @hcpriv: for use by HCD; typically holds hardware dma queue head (QH)
58
-
* with one or more transfer descriptors (TDs) per urb
58
+
* with one or more transfer descriptors (TDs) per urb; must be preserved
59
+
* by core while BW is allocated for the endpoint
59
60
* @ep_dev: ep_device for sysfs info
60
61
* @extra: descriptors following this endpoint in the configuration
61
62
* @extralen: how many bytes of "extra" are valid
···
2082
2081
case -ENODEV:
2083
2082
case -EOPNOTSUPP:
2084
2083
return error_code;
2084
+
case -ENOSPC:
2085
+
return -EBUSY;
2085
2086
default:
2086
2087
return -EIO;
2087
2088
}
+2
-2
include/linux/usb/cdc_ncm.h
+2
-2
include/linux/usb/cdc_ncm.h
+106
-2
include/linux/usb/pd.h
+106
-2
include/linux/usb/pd.h
···
34
34
PD_CTRL_FR_SWAP = 19,
35
35
PD_CTRL_GET_PPS_STATUS = 20,
36
36
PD_CTRL_GET_COUNTRY_CODES = 21,
37
-
/* 22-23 Reserved */
37
+
PD_CTRL_GET_SINK_CAP_EXT = 22,
38
+
/* 23 Reserved */
38
39
PD_CTRL_GET_REVISION = 24,
39
40
/* 25-31 Reserved */
40
41
};
···
73
72
PD_EXT_PPS_STATUS = 12,
74
73
PD_EXT_COUNTRY_INFO = 13,
75
74
PD_EXT_COUNTRY_CODES = 14,
76
-
/* 15-31 Reserved */
75
+
PD_EXT_SINK_CAP_EXT = 15,
76
+
/* 16-31 Reserved */
77
77
};
78
78
79
79
#define PD_REV10 0x0
···
207
205
};
208
206
} __packed;
209
207
208
+
/*
209
+
* count_chunked_data_objs - Helper to calculate number of Data Objects on a 4
210
+
* byte boundary.
211
+
* @size: Size of data block for extended message. Should *not* include extended
212
+
* header size.
213
+
*/
214
+
static inline u8 count_chunked_data_objs(u32 size)
215
+
{
216
+
size += offsetof(struct pd_chunked_ext_message_data, data);
217
+
return ((size / 4) + (size % 4 ? 1 : 0));
218
+
}
219
+
220
+
/* Sink Caps Extended Data Block Version */
221
+
#define SKEDB_VER_1_0 1
222
+
223
+
/* Sink Caps Extended Sink Modes */
224
+
#define SINK_MODE_PPS BIT(0)
225
+
#define SINK_MODE_VBUS BIT(1)
226
+
#define SINK_MODE_AC_SUPPLY BIT(2)
227
+
#define SINK_MODE_BATT BIT(3)
228
+
#define SINK_MODE_BATT_UL BIT(4) /* Unlimited battery power supply */
229
+
#define SINK_MODE_AVS BIT(5)
230
+
231
+
/**
232
+
* struct sink_caps_ext_msg - Sink extended capability PD message
233
+
* @vid: Vendor ID
234
+
* @pid: Product ID
235
+
* @xid: Value assigned by USB-IF for product
236
+
* @fw: Firmware version
237
+
* @hw: Hardware version
238
+
* @skedb_ver: Sink Caps Extended Data Block (SKEDB) Version
239
+
* @load_step: Indicates the load step slew rate.
240
+
* @load_char: Sink overload characteristics
241
+
* @compliance: Types of sources the sink has been tested & certified on
242
+
* @touch_temp: Indicates the IEC standard to which the touch temperature
243
+
* conforms to (if applicable).
244
+
* @batt_info: Indicates number batteries and hot swappable ports
245
+
* @modes: Charging caps & power sources supported
246
+
* @spr_min_pdp: Sink Minimum PDP for SPR mode
247
+
* @spr_op_pdp: Sink Operational PDP for SPR mode
248
+
* @spr_max_pdp: Sink Maximum PDP for SPR mode
249
+
* @epr_min_pdp: Sink Minimum PDP for EPR mode
250
+
* @epr_op_pdp: Sink Operational PDP for EPR mode
251
+
* @epr_max_pdp: Sink Maximum PDP for EPR mode
252
+
*/
253
+
struct sink_caps_ext_msg {
254
+
__le16 vid;
255
+
__le16 pid;
256
+
__le32 xid;
257
+
u8 fw;
258
+
u8 hw;
259
+
u8 skedb_ver;
260
+
u8 load_step;
261
+
__le16 load_char;
262
+
u8 compliance;
263
+
u8 touch_temp;
264
+
u8 batt_info;
265
+
u8 modes;
266
+
u8 spr_min_pdp;
267
+
u8 spr_op_pdp;
268
+
u8 spr_max_pdp;
269
+
u8 epr_min_pdp;
270
+
u8 epr_op_pdp;
271
+
u8 epr_max_pdp;
272
+
} __packed;
273
+
210
274
/* PDO: Power Data Object */
211
275
#define PDO_MAX_OBJECTS 7
212
276
···
397
329
#define PDO_SPR_AVS_APDO_9V_TO_15V_MAX_CURR GENMASK(19, 10) /* 10mA unit */
398
330
#define PDO_SPR_AVS_APDO_15V_TO_20V_MAX_CURR GENMASK(9, 0) /* 10mA unit */
399
331
332
+
/* SPR AVS has two different current ranges 9V - 15V, 15V - 20V */
333
+
#define SPR_AVS_TIER1_MIN_VOLT_MV 9000
334
+
#define SPR_AVS_TIER1_MAX_VOLT_MV 15000
335
+
#define SPR_AVS_TIER2_MAX_VOLT_MV 20000
336
+
337
+
#define SPR_AVS_AVS_SMALL_STEP_V 1
338
+
/* vAvsStep - 100mv */
339
+
#define SPR_AVS_VOLT_MV_STEP 100
340
+
/* SPR AVS RDO Operating Current is in 50mA step */
341
+
#define RDO_SPR_AVS_CURR_MA_STEP 50
342
+
/* SPR AVS RDO Output voltage is in 25mV step */
343
+
#define RDO_SPR_AVS_OUT_VOLT_MV_STEP 25
344
+
345
+
#define RDO_SPR_AVS_VOLT GENMASK(20, 9)
346
+
#define RDO_SPR_AVS_CURR GENMASK(6, 0)
347
+
348
+
#define RDO_SPR_AVS_OUT_VOLT(mv) \
349
+
FIELD_PREP(RDO_SPR_AVS_VOLT, ((mv) / RDO_SPR_AVS_OUT_VOLT_MV_STEP))
350
+
351
+
#define RDO_SPR_AVS_OP_CURR(ma) \
352
+
FIELD_PREP(RDO_SPR_AVS_CURR, ((ma) / RDO_SPR_AVS_CURR_MA_STEP))
353
+
354
+
#define RDO_AVS(idx, out_mv, op_ma, flags) \
355
+
(RDO_OBJ(idx) | (flags) | \
356
+
RDO_SPR_AVS_OUT_VOLT(out_mv) | RDO_SPR_AVS_OP_CURR(op_ma))
357
+
400
358
static inline enum pd_pdo_type pdo_type(u32 pdo)
401
359
{
402
360
return (pdo >> PDO_TYPE_SHIFT) & PDO_TYPE_MASK;
···
431
337
static inline unsigned int pdo_fixed_voltage(u32 pdo)
432
338
{
433
339
return ((pdo >> PDO_FIXED_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
340
+
}
341
+
342
+
static inline unsigned int pdo_fixed_current(u32 pdo)
343
+
{
344
+
return ((pdo >> PDO_FIXED_CURR_SHIFT) & PDO_CURR_MASK) * 10;
434
345
}
435
346
436
347
static inline unsigned int pdo_min_voltage(u32 pdo)
···
680
581
#define PD_N_HARD_RESET_COUNT 2
681
582
682
583
#define PD_P_SNK_STDBY_MW 2500 /* 2500 mW */
584
+
585
+
#define PD_I_SNK_STBY_MA 500 /* 500 mA */
586
+
587
+
#define PD_T_AVS_SRC_TRANS_SMALL 50 /* 50 ms */
588
+
#define PD_T_AVS_SRC_TRANS_LARGE 700 /* 700 ms */
683
589
684
590
#if IS_ENABLED(CONFIG_TYPEC)
685
591
+1
-1
include/linux/usb/tcpm.h
+1
-1
include/linux/usb/tcpm.h
···
31
31
/* Time to wait for TCPC to complete transmit */
32
32
#define PD_T_TCPC_TX_TIMEOUT 100 /* in ms */
33
33
#define PD_ROLE_SWAP_TIMEOUT (MSEC_PER_SEC * 10)
34
-
#define PD_PPS_CTRL_TIMEOUT (MSEC_PER_SEC * 10)
34
+
#define PD_AUG_PSY_CTRL_TIMEOUT (MSEC_PER_SEC * 10)
35
35
36
36
enum tcpm_transmit_status {
37
37
TCPC_TX_SUCCESS = 0,
+3
include/linux/usb/typec_altmode.h
+3
include/linux/usb/typec_altmode.h
···
26
26
* @mode: Index of the Mode
27
27
* @vdo: VDO returned by Discover Modes USB PD command
28
28
* @active: Tells has the mode been entered or not
29
+
* @priority: Priority used by the automatic alternate mode selection process
30
+
* @mode_selection: Whether entry to this alternate mode is managed by the
31
+
* automatic alternate mode selection process or by the specific driver
29
32
* @desc: Optional human readable description of the mode
30
33
* @ops: Operations vector from the driver
31
34
* @cable_ops: Cable operations vector from the driver.
+24
-9
include/uapi/linux/usb/ch9.h
+24
-9
include/uapi/linux/usb/ch9.h
···
102
102
#define USB_REQ_LOOPBACK_DATA_WRITE 0x15
103
103
#define USB_REQ_LOOPBACK_DATA_READ 0x16
104
104
#define USB_REQ_SET_INTERFACE_DS 0x17
105
+
#define USB_REQ_AUTH_IN 0x18
106
+
#define USB_REQ_AUTH_OUT 0x19
105
107
106
108
/* specific requests for USB Power Delivery */
107
109
#define USB_REQ_GET_PARTNER_PDO 20
···
123
121
* are at most sixteen features of each type.) Hubs may also support a
124
122
* new USB_REQ_TEST_AND_SET_FEATURE to put ports into L1 suspend.
125
123
*/
126
-
#define USB_DEVICE_SELF_POWERED 0 /* (read only) */
127
-
#define USB_DEVICE_REMOTE_WAKEUP 1 /* dev may initiate wakeup */
128
-
#define USB_DEVICE_TEST_MODE 2 /* (wired high speed only) */
129
-
#define USB_DEVICE_BATTERY 2 /* (wireless) */
130
-
#define USB_DEVICE_B_HNP_ENABLE 3 /* (otg) dev may initiate HNP */
131
-
#define USB_DEVICE_WUSB_DEVICE 3 /* (wireless)*/
132
-
#define USB_DEVICE_A_HNP_SUPPORT 4 /* (otg) RH port supports HNP */
133
-
#define USB_DEVICE_A_ALT_HNP_SUPPORT 5 /* (otg) other RH port does */
134
-
#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */
124
+
#define USB_DEVICE_SELF_POWERED 0 /* (read only) */
125
+
#define USB_DEVICE_REMOTE_WAKEUP 1 /* dev may initiate wakeup */
126
+
#define USB_DEVICE_TEST_MODE 2 /* (wired high speed only) */
127
+
#define USB_DEVICE_BATTERY 2 /* (wireless) */
128
+
#define USB_DEVICE_B_HNP_ENABLE 3 /* (otg) dev may initiate HNP */
129
+
#define USB_DEVICE_WUSB_DEVICE 3 /* (wireless)*/
130
+
#define USB_DEVICE_A_HNP_SUPPORT 4 /* (otg) RH port supports HNP */
131
+
#define USB_DEVICE_A_ALT_HNP_SUPPORT 5 /* (otg) other RH port does */
132
+
#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */
133
+
134
+
#define USB_DEVICE_BULK_MAX_PACKET_UPDATE 8 /* (eUSB2v2) bump maxpacket to 1024 */
135
135
136
136
/*
137
137
* Test Mode Selectors
···
1148
1144
* (SSAC) specified in bmAttributes[4:0]. SSAC is zero-based
1149
1145
*/
1150
1146
#define USB_DT_USB_SSP_CAP_SIZE(ssac) (12 + (ssac + 1) * 4)
1147
+
1148
+
/*-------------------------------------------------------------------------*/
1149
+
1150
+
struct usb_authentication_capability_descriptor {
1151
+
__u8 bLength;
1152
+
__u8 bDescriptorType; /* set to USB_DT_DEVICE_CAPABILITY */
1153
+
__u8 bmAttributes;
1154
+
1155
+
__u8 bcdProtocolVersion;
1156
+
__u8 bcdCapability;
1157
+
} __attribute__((packed));
1151
1158
1152
1159
/*-------------------------------------------------------------------------*/
1153
1160
+36
lib/linear_ranges.c
+36
lib/linear_ranges.c
···
242
242
EXPORT_SYMBOL_GPL(linear_range_get_selector_high);
243
243
244
244
/**
245
+
* linear_range_get_selector_high_array - return linear range selector for value
246
+
* @r: pointer to array of linear ranges where selector is looked from
247
+
* @ranges: amount of ranges to scan from array
248
+
* @val: value for which the selector is searched
249
+
* @selector: address where found selector value is updated
250
+
* @found: flag to indicate that given value was in the range
251
+
*
252
+
* Scan array of ranges for selector for which range value matches given
253
+
* input value. Value is matching if it is equal or higher than given value
254
+
* If given value is found to be in a range scanning is stopped and @found is
255
+
* set true. If a range with values greater than given value is found
256
+
* but the range min is being greater than given value, then the range's
257
+
* lowest selector is updated to @selector and scanning is stopped.
258
+
*
259
+
* Return: 0 on success, -EINVAL if range array is invalid or does not contain
260
+
* range with a value greater or equal to given value
261
+
*/
262
+
int linear_range_get_selector_high_array(const struct linear_range *r,
263
+
int ranges, unsigned int val,
264
+
unsigned int *selector, bool *found)
265
+
{
266
+
int i;
267
+
int ret;
268
+
269
+
for (i = 0; i < ranges; i++) {
270
+
ret = linear_range_get_selector_high(&r[i], val, selector,
271
+
found);
272
+
if (!ret)
273
+
return 0;
274
+
}
275
+
276
+
return -EINVAL;
277
+
}
278
+
EXPORT_SYMBOL_GPL(linear_range_get_selector_high_array);
279
+
280
+
/**
245
281
* linear_range_get_selector_within - return linear range selector for value
246
282
* @r: pointer to linear range where selector is looked from
247
283
* @val: value for which the selector is searched
+3
-3
tools/usb/usbip/libsrc/usbip_device_driver.c
+3
-3
tools/usb/usbip/libsrc/usbip_device_driver.c
···
137
137
INIT_LIST_HEAD(&hdriver->edev_list);
138
138
139
139
ret = usbip_generic_driver_open(hdriver);
140
-
if (ret)
141
-
err("please load " USBIP_CORE_MOD_NAME ".ko and "
142
-
USBIP_DEVICE_DRV_NAME ".ko!");
140
+
if (ret || hdriver->ndevs == 0)
141
+
info("please load " USBIP_CORE_MOD_NAME ".ko and "
142
+
USBIP_DEVICE_DRV_NAME ".ko");
143
143
144
144
return ret;
145
145
}
+3
tools/usb/usbip/libsrc/usbip_host_common.c
+3
tools/usb/usbip/libsrc/usbip_host_common.c
+4
-3
tools/usb/usbip/libsrc/usbip_host_driver.c
+4
-3
tools/usb/usbip/libsrc/usbip_host_driver.c
···
32
32
INIT_LIST_HEAD(&hdriver->edev_list);
33
33
34
34
ret = usbip_generic_driver_open(hdriver);
35
-
if (ret)
36
-
err("please load " USBIP_CORE_MOD_NAME ".ko and "
37
-
USBIP_HOST_DRV_NAME ".ko!");
35
+
if (ret || hdriver->ndevs == 0)
36
+
info("please load " USBIP_CORE_MOD_NAME ".ko and "
37
+
USBIP_HOST_DRV_NAME ".ko");
38
+
38
39
return ret;
39
40
}
40
41