Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 's390-6.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux
Pull s390 updates from Heiko Carstens:
"Note that besides two bug fixes this includes three commits for IBM
z17, which was announced this week.
- Add IBM z17 bits:
- Setup elf_platform for new machine types
- Allow to compile the kernel with z17 optimizations
- Add new performance counters
- Fix mismatch between indicator bits and queue indexes in virtio CCW code
- Fix double free in pmu setup error path"
* tag 's390-6.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux:
s390/cpumf: Fix double free on error in cpumf_pmu_event_init()
s390/cpumf: Update CPU Measurement facility extended counter set support
s390: Allow to compile with z17 optimizations
s390: Add z17 elf platform
s390/virtio_ccw: Don't allocate/assign airqs for non-existing queues
+210
-19
+19
arch/s390/Kconfig
+19
arch/s390/Kconfig
···
332
332
def_bool n
333
333
select HAVE_MARCH_Z15_FEATURES
334
334
335
+
config HAVE_MARCH_Z17_FEATURES
336
+
def_bool n
337
+
select HAVE_MARCH_Z16_FEATURES
338
+
335
339
choice
336
340
prompt "Processor type"
337
341
default MARCH_Z196
···
401
397
Select this to enable optimizations for IBM z16 (3931 and
402
398
3932 series).
403
399
400
+
config MARCH_Z17
401
+
bool "IBM z17"
402
+
select HAVE_MARCH_Z17_FEATURES
403
+
depends on $(cc-option,-march=z17)
404
+
help
405
+
Select this to enable optimizations for IBM z17 (9175 and
406
+
9176 series).
407
+
404
408
endchoice
405
409
406
410
config MARCH_Z10_TUNE
···
431
419
432
420
config MARCH_Z16_TUNE
433
421
def_bool TUNE_Z16 || MARCH_Z16 && TUNE_DEFAULT
422
+
423
+
config MARCH_Z17_TUNE
424
+
def_bool TUNE_Z17 || MARCH_Z17 && TUNE_DEFAULT
434
425
435
426
choice
436
427
prompt "Tune code generation"
···
478
463
config TUNE_Z16
479
464
bool "IBM z16"
480
465
depends on $(cc-option,-mtune=z16)
466
+
467
+
config TUNE_Z17
468
+
bool "IBM z17"
469
+
depends on $(cc-option,-mtune=z17)
481
470
482
471
endchoice
483
472
+2
arch/s390/Makefile
+2
arch/s390/Makefile
···
48
48
mflags-$(CONFIG_MARCH_Z14) := -march=z14
49
49
mflags-$(CONFIG_MARCH_Z15) := -march=z15
50
50
mflags-$(CONFIG_MARCH_Z16) := -march=z16
51
+
mflags-$(CONFIG_MARCH_Z17) := -march=z17
51
52
52
53
export CC_FLAGS_MARCH := $(mflags-y)
53
54
···
62
61
cflags-$(CONFIG_MARCH_Z14_TUNE) += -mtune=z14
63
62
cflags-$(CONFIG_MARCH_Z15_TUNE) += -mtune=z15
64
63
cflags-$(CONFIG_MARCH_Z16_TUNE) += -mtune=z16
64
+
cflags-$(CONFIG_MARCH_Z17_TUNE) += -mtune=z17
65
65
66
66
cflags-y += -Wa,-I$(srctree)/arch/$(ARCH)/include
67
67
+4
arch/s390/include/asm/march.h
+4
arch/s390/include/asm/march.h
+2
-9
arch/s390/kernel/perf_cpum_cf.c
+2
-9
arch/s390/kernel/perf_cpum_cf.c
···
442
442
ctrset_size = 48;
443
443
else if (cpumf_ctr_info.csvn >= 3 && cpumf_ctr_info.csvn <= 5)
444
444
ctrset_size = 128;
445
-
else if (cpumf_ctr_info.csvn == 6 || cpumf_ctr_info.csvn == 7)
445
+
else if (cpumf_ctr_info.csvn >= 6 && cpumf_ctr_info.csvn <= 8)
446
446
ctrset_size = 160;
447
447
break;
448
448
case CPUMF_CTR_SET_MT_DIAG:
···
858
858
static int cpumf_pmu_event_init(struct perf_event *event)
859
859
{
860
860
unsigned int type = event->attr.type;
861
-
int err;
861
+
int err = -ENOENT;
862
862
863
863
if (type == PERF_TYPE_HARDWARE || type == PERF_TYPE_RAW)
864
864
err = __hw_perf_event_init(event, type);
865
865
else if (event->pmu->type == type)
866
866
/* Registered as unknown PMU */
867
867
err = __hw_perf_event_init(event, cpumf_pmu_event_type(event));
868
-
else
869
-
return -ENOENT;
870
-
871
-
if (unlikely(err) && event->destroy)
872
-
event->destroy(event);
873
868
874
869
return err;
875
870
}
···
1814
1819
event->destroy = hw_perf_event_destroy;
1815
1820
1816
1821
err = cfdiag_event_init2(event);
1817
-
if (unlikely(err))
1818
-
event->destroy(event);
1819
1822
out:
1820
1823
return err;
1821
1824
}
+164
-3
arch/s390/kernel/perf_cpum_cf_events.c
+164
-3
arch/s390/kernel/perf_cpum_cf_events.c
···
237
237
CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
238
238
CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
239
239
CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
240
-
241
240
CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080);
242
241
CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081);
243
242
CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082);
···
364
365
CPUMF_EVENT_ATTR(cf_z16, NNPA_HOLD_LOCK, 0x010e);
365
366
CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
366
367
CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
368
+
CPUMF_EVENT_ATTR(cf_z17, L1D_RO_EXCL_WRITES, 0x0080);
369
+
CPUMF_EVENT_ATTR(cf_z17, DTLB2_WRITES, 0x0081);
370
+
CPUMF_EVENT_ATTR(cf_z17, DTLB2_MISSES, 0x0082);
371
+
CPUMF_EVENT_ATTR(cf_z17, CRSTE_1MB_WRITES, 0x0083);
372
+
CPUMF_EVENT_ATTR(cf_z17, DTLB2_GPAGE_WRITES, 0x0084);
373
+
CPUMF_EVENT_ATTR(cf_z17, ITLB2_WRITES, 0x0086);
374
+
CPUMF_EVENT_ATTR(cf_z17, ITLB2_MISSES, 0x0087);
375
+
CPUMF_EVENT_ATTR(cf_z17, TLB2_PTE_WRITES, 0x0089);
376
+
CPUMF_EVENT_ATTR(cf_z17, TLB2_CRSTE_WRITES, 0x008a);
377
+
CPUMF_EVENT_ATTR(cf_z17, TLB2_ENGINES_BUSY, 0x008b);
378
+
CPUMF_EVENT_ATTR(cf_z17, TX_C_TEND, 0x008c);
379
+
CPUMF_EVENT_ATTR(cf_z17, TX_NC_TEND, 0x008d);
380
+
CPUMF_EVENT_ATTR(cf_z17, L1C_TLB2_MISSES, 0x008f);
381
+
CPUMF_EVENT_ATTR(cf_z17, DCW_REQ, 0x0091);
382
+
CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_IV, 0x0092);
383
+
CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_CHIP_HIT, 0x0093);
384
+
CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_DRAWER_HIT, 0x0094);
385
+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP, 0x0095);
386
+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_IV, 0x0096);
387
+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_CHIP_HIT, 0x0097);
388
+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_DRAWER_HIT, 0x0098);
389
+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_MODULE, 0x0099);
390
+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_DRAWER, 0x009a);
391
+
CPUMF_EVENT_ATTR(cf_z17, DCW_OFF_DRAWER, 0x009b);
392
+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_MEMORY, 0x009c);
393
+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_MODULE_MEMORY, 0x009d);
394
+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_DRAWER_MEMORY, 0x009e);
395
+
CPUMF_EVENT_ATTR(cf_z17, DCW_OFF_DRAWER_MEMORY, 0x009f);
396
+
CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_IV, 0x00a0);
397
+
CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_CHIP_HIT, 0x00a1);
398
+
CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_DRAWER_HIT, 0x00a2);
399
+
CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_IV, 0x00a3);
400
+
CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_CHIP_HIT, 0x00a4);
401
+
CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_DRAWER_HIT, 0x00a5);
402
+
CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_IV, 0x00a6);
403
+
CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_CHIP_HIT, 0x00a7);
404
+
CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_DRAWER_HIT, 0x00a8);
405
+
CPUMF_EVENT_ATTR(cf_z17, ICW_REQ, 0x00a9);
406
+
CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_IV, 0x00aa);
407
+
CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_CHIP_HIT, 0x00ab);
408
+
CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_DRAWER_HIT, 0x00ac);
409
+
CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP, 0x00ad);
410
+
CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_IV, 0x00ae);
411
+
CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_CHIP_HIT, 0x00af);
412
+
CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_DRAWER_HIT, 0x00b0);
413
+
CPUMF_EVENT_ATTR(cf_z17, ICW_ON_MODULE, 0x00b1);
414
+
CPUMF_EVENT_ATTR(cf_z17, ICW_ON_DRAWER, 0x00b2);
415
+
CPUMF_EVENT_ATTR(cf_z17, ICW_OFF_DRAWER, 0x00b3);
416
+
CPUMF_EVENT_ATTR(cf_z17, CYCLES_SAMETHRD, 0x00ca);
417
+
CPUMF_EVENT_ATTR(cf_z17, CYCLES_DIFFTHRD, 0x00cb);
418
+
CPUMF_EVENT_ATTR(cf_z17, INST_SAMETHRD, 0x00cc);
419
+
CPUMF_EVENT_ATTR(cf_z17, INST_DIFFTHRD, 0x00cd);
420
+
CPUMF_EVENT_ATTR(cf_z17, WRONG_BRANCH_PREDICTION, 0x00ce);
421
+
CPUMF_EVENT_ATTR(cf_z17, VX_BCD_EXECUTION_SLOTS, 0x00e1);
422
+
CPUMF_EVENT_ATTR(cf_z17, DECIMAL_INSTRUCTIONS, 0x00e2);
423
+
CPUMF_EVENT_ATTR(cf_z17, LAST_HOST_TRANSLATIONS, 0x00e8);
424
+
CPUMF_EVENT_ATTR(cf_z17, TX_NC_TABORT, 0x00f4);
425
+
CPUMF_EVENT_ATTR(cf_z17, TX_C_TABORT_NO_SPECIAL, 0x00f5);
426
+
CPUMF_EVENT_ATTR(cf_z17, TX_C_TABORT_SPECIAL, 0x00f6);
427
+
CPUMF_EVENT_ATTR(cf_z17, DFLT_ACCESS, 0x00f8);
428
+
CPUMF_EVENT_ATTR(cf_z17, DFLT_CYCLES, 0x00fd);
429
+
CPUMF_EVENT_ATTR(cf_z17, SORTL, 0x0100);
430
+
CPUMF_EVENT_ATTR(cf_z17, DFLT_CC, 0x0109);
431
+
CPUMF_EVENT_ATTR(cf_z17, DFLT_CCFINISH, 0x010a);
432
+
CPUMF_EVENT_ATTR(cf_z17, NNPA_INVOCATIONS, 0x010b);
433
+
CPUMF_EVENT_ATTR(cf_z17, NNPA_COMPLETIONS, 0x010c);
434
+
CPUMF_EVENT_ATTR(cf_z17, NNPA_WAIT_LOCK, 0x010d);
435
+
CPUMF_EVENT_ATTR(cf_z17, NNPA_HOLD_LOCK, 0x010e);
436
+
CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_ONCHIP, 0x0110);
437
+
CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_OFFCHIP, 0x0111);
438
+
CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_DIFF, 0x0112);
439
+
CPUMF_EVENT_ATTR(cf_z17, NNPA_4K_PREFETCH, 0x0114);
440
+
CPUMF_EVENT_ATTR(cf_z17, NNPA_COMPL_LOCK, 0x0115);
441
+
CPUMF_EVENT_ATTR(cf_z17, NNPA_RETRY_LOCK, 0x0116);
442
+
CPUMF_EVENT_ATTR(cf_z17, NNPA_RETRY_LOCK_WITH_PLO, 0x0117);
443
+
CPUMF_EVENT_ATTR(cf_z17, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
444
+
CPUMF_EVENT_ATTR(cf_z17, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
367
445
368
446
static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
369
447
CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
···
490
414
NULL,
491
415
};
492
416
493
-
static struct attribute *cpumcf_svn_67_pmu_event_attr[] __initdata = {
417
+
static struct attribute *cpumcf_svn_678_pmu_event_attr[] __initdata = {
494
418
CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
495
419
CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
496
420
CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
···
855
779
NULL,
856
780
};
857
781
782
+
static struct attribute *cpumcf_z17_pmu_event_attr[] __initdata = {
783
+
CPUMF_EVENT_PTR(cf_z17, L1D_RO_EXCL_WRITES),
784
+
CPUMF_EVENT_PTR(cf_z17, DTLB2_WRITES),
785
+
CPUMF_EVENT_PTR(cf_z17, DTLB2_MISSES),
786
+
CPUMF_EVENT_PTR(cf_z17, CRSTE_1MB_WRITES),
787
+
CPUMF_EVENT_PTR(cf_z17, DTLB2_GPAGE_WRITES),
788
+
CPUMF_EVENT_PTR(cf_z17, ITLB2_WRITES),
789
+
CPUMF_EVENT_PTR(cf_z17, ITLB2_MISSES),
790
+
CPUMF_EVENT_PTR(cf_z17, TLB2_PTE_WRITES),
791
+
CPUMF_EVENT_PTR(cf_z17, TLB2_CRSTE_WRITES),
792
+
CPUMF_EVENT_PTR(cf_z17, TLB2_ENGINES_BUSY),
793
+
CPUMF_EVENT_PTR(cf_z17, TX_C_TEND),
794
+
CPUMF_EVENT_PTR(cf_z17, TX_NC_TEND),
795
+
CPUMF_EVENT_PTR(cf_z17, L1C_TLB2_MISSES),
796
+
CPUMF_EVENT_PTR(cf_z17, DCW_REQ),
797
+
CPUMF_EVENT_PTR(cf_z17, DCW_REQ_IV),
798
+
CPUMF_EVENT_PTR(cf_z17, DCW_REQ_CHIP_HIT),
799
+
CPUMF_EVENT_PTR(cf_z17, DCW_REQ_DRAWER_HIT),
800
+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP),
801
+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_IV),
802
+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_CHIP_HIT),
803
+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_DRAWER_HIT),
804
+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_MODULE),
805
+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_DRAWER),
806
+
CPUMF_EVENT_PTR(cf_z17, DCW_OFF_DRAWER),
807
+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_MEMORY),
808
+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_MODULE_MEMORY),
809
+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_DRAWER_MEMORY),
810
+
CPUMF_EVENT_PTR(cf_z17, DCW_OFF_DRAWER_MEMORY),
811
+
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_IV),
812
+
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_CHIP_HIT),
813
+
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_DRAWER_HIT),
814
+
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_IV),
815
+
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_CHIP_HIT),
816
+
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_DRAWER_HIT),
817
+
CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_IV),
818
+
CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_CHIP_HIT),
819
+
CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_DRAWER_HIT),
820
+
CPUMF_EVENT_PTR(cf_z17, ICW_REQ),
821
+
CPUMF_EVENT_PTR(cf_z17, ICW_REQ_IV),
822
+
CPUMF_EVENT_PTR(cf_z17, ICW_REQ_CHIP_HIT),
823
+
CPUMF_EVENT_PTR(cf_z17, ICW_REQ_DRAWER_HIT),
824
+
CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP),
825
+
CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_IV),
826
+
CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_CHIP_HIT),
827
+
CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_DRAWER_HIT),
828
+
CPUMF_EVENT_PTR(cf_z17, ICW_ON_MODULE),
829
+
CPUMF_EVENT_PTR(cf_z17, ICW_ON_DRAWER),
830
+
CPUMF_EVENT_PTR(cf_z17, ICW_OFF_DRAWER),
831
+
CPUMF_EVENT_PTR(cf_z17, CYCLES_SAMETHRD),
832
+
CPUMF_EVENT_PTR(cf_z17, CYCLES_DIFFTHRD),
833
+
CPUMF_EVENT_PTR(cf_z17, INST_SAMETHRD),
834
+
CPUMF_EVENT_PTR(cf_z17, INST_DIFFTHRD),
835
+
CPUMF_EVENT_PTR(cf_z17, WRONG_BRANCH_PREDICTION),
836
+
CPUMF_EVENT_PTR(cf_z17, VX_BCD_EXECUTION_SLOTS),
837
+
CPUMF_EVENT_PTR(cf_z17, DECIMAL_INSTRUCTIONS),
838
+
CPUMF_EVENT_PTR(cf_z17, LAST_HOST_TRANSLATIONS),
839
+
CPUMF_EVENT_PTR(cf_z17, TX_NC_TABORT),
840
+
CPUMF_EVENT_PTR(cf_z17, TX_C_TABORT_NO_SPECIAL),
841
+
CPUMF_EVENT_PTR(cf_z17, TX_C_TABORT_SPECIAL),
842
+
CPUMF_EVENT_PTR(cf_z17, DFLT_ACCESS),
843
+
CPUMF_EVENT_PTR(cf_z17, DFLT_CYCLES),
844
+
CPUMF_EVENT_PTR(cf_z17, SORTL),
845
+
CPUMF_EVENT_PTR(cf_z17, DFLT_CC),
846
+
CPUMF_EVENT_PTR(cf_z17, DFLT_CCFINISH),
847
+
CPUMF_EVENT_PTR(cf_z17, NNPA_INVOCATIONS),
848
+
CPUMF_EVENT_PTR(cf_z17, NNPA_COMPLETIONS),
849
+
CPUMF_EVENT_PTR(cf_z17, NNPA_WAIT_LOCK),
850
+
CPUMF_EVENT_PTR(cf_z17, NNPA_HOLD_LOCK),
851
+
CPUMF_EVENT_PTR(cf_z17, NNPA_INST_ONCHIP),
852
+
CPUMF_EVENT_PTR(cf_z17, NNPA_INST_OFFCHIP),
853
+
CPUMF_EVENT_PTR(cf_z17, NNPA_INST_DIFF),
854
+
CPUMF_EVENT_PTR(cf_z17, NNPA_4K_PREFETCH),
855
+
CPUMF_EVENT_PTR(cf_z17, NNPA_COMPL_LOCK),
856
+
CPUMF_EVENT_PTR(cf_z17, NNPA_RETRY_LOCK),
857
+
CPUMF_EVENT_PTR(cf_z17, NNPA_RETRY_LOCK_WITH_PLO),
858
+
CPUMF_EVENT_PTR(cf_z17, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
859
+
CPUMF_EVENT_PTR(cf_z17, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
860
+
NULL,
861
+
};
862
+
858
863
/* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
859
864
860
865
static struct attribute_group cpumcf_pmu_events_group = {
···
1016
859
if (ci.csvn >= 1 && ci.csvn <= 5)
1017
860
csvn = cpumcf_svn_12345_pmu_event_attr;
1018
861
else if (ci.csvn >= 6)
1019
-
csvn = cpumcf_svn_67_pmu_event_attr;
862
+
csvn = cpumcf_svn_678_pmu_event_attr;
1020
863
1021
864
/* Determine model-specific counter set(s) */
1022
865
get_cpu_id(&cpu_id);
···
1048
891
case 0x3931:
1049
892
case 0x3932:
1050
893
model = cpumcf_z16_pmu_event_attr;
894
+
break;
895
+
case 0x9175:
896
+
case 0x9176:
897
+
model = cpumcf_z17_pmu_event_attr;
1051
898
break;
1052
899
default:
1053
900
model = none;
-3
arch/s390/kernel/perf_cpum_sf.c
-3
arch/s390/kernel/perf_cpum_sf.c
+4
arch/s390/kernel/processor.c
+4
arch/s390/kernel/processor.c
+3
arch/s390/tools/gen_facilities.c
+3
arch/s390/tools/gen_facilities.c
+12
-4
drivers/s390/virtio/virtio_ccw.c
+12
-4
drivers/s390/virtio/virtio_ccw.c
···
302
302
static unsigned long *get_airq_indicator(struct virtqueue *vqs[], int nvqs,
303
303
u64 *first, void **airq_info)
304
304
{
305
-
int i, j;
305
+
int i, j, queue_idx, highest_queue_idx = -1;
306
306
struct airq_info *info;
307
307
unsigned long *indicator_addr = NULL;
308
308
unsigned long bit, flags;
309
+
310
+
/* Array entries without an actual queue pointer must be ignored. */
311
+
for (i = 0; i < nvqs; i++) {
312
+
if (vqs[i])
313
+
highest_queue_idx++;
314
+
}
309
315
310
316
for (i = 0; i < MAX_AIRQ_AREAS && !indicator_addr; i++) {
311
317
mutex_lock(&airq_areas_lock);
···
322
316
if (!info)
323
317
return NULL;
324
318
write_lock_irqsave(&info->lock, flags);
325
-
bit = airq_iv_alloc(info->aiv, nvqs);
319
+
bit = airq_iv_alloc(info->aiv, highest_queue_idx + 1);
326
320
if (bit == -1UL) {
327
321
/* Not enough vacancies. */
328
322
write_unlock_irqrestore(&info->lock, flags);
···
331
325
*first = bit;
332
326
*airq_info = info;
333
327
indicator_addr = info->aiv->vector;
334
-
for (j = 0; j < nvqs; j++) {
335
-
airq_iv_set_ptr(info->aiv, bit + j,
328
+
for (j = 0, queue_idx = 0; j < nvqs; j++) {
329
+
if (!vqs[j])
330
+
continue;
331
+
airq_iv_set_ptr(info->aiv, bit + queue_idx++,
336
332
(unsigned long)vqs[j]);
337
333
}
338
334
write_unlock_irqrestore(&info->lock, flags);