Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/psr: Underrun on idle PSR wa only when pkgc latency > delayed vblank
Underrun on idle PSR workaround (Wa_16025596647) is supposed to be
applied only when pkg c latency > delayed vblank. Currently we are
applying it always when other criterias are met.
Fix this by adding new boolean flag which is supposed to be set when
calculating watermark levels and pkgc latency > delayed vblank is
detected. currently this scenario is blocked but might be added
later. Due to this add also TODO comment into
skl_max_wm_level_for_vblank.
Bspec: 74151
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://lore.kernel.org/r/20250519075223.443266-1-jouni.hogander@intel.com
+17
-6
+2
drivers/gpu/drm/i915/display/intel_display_types.h
+2
drivers/gpu/drm/i915/display/intel_display_types.h
···
1121
1121
bool req_psr2_sdp_prior_scanline;
1122
1122
bool has_panel_replay;
1123
1123
bool wm_level_disabled;
1124
+
bool pkg_c_latency_used;
1124
1125
u32 dc3co_exitline;
1125
1126
u16 su_y_granularity;
1126
1127
u8 active_non_psr_pipes;
···
1684
1683
u8 entry_setup_frames;
1685
1684
1686
1685
bool link_ok;
1686
+
bool pkg_c_latency_used;
1687
1687
1688
1688
u8 active_non_psr_pipes;
1689
1689
};
+10
-6
drivers/gpu/drm/i915/display/intel_psr.c
+10
-6
drivers/gpu/drm/i915/display/intel_psr.c
···
915
915
/* Wa_16025596647 */
916
916
if ((DISPLAY_VER(display) == 20 ||
917
917
IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
918
-
is_dc5_dc6_blocked(intel_dp))
918
+
is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
919
919
intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,
920
920
intel_dp->psr.pipe,
921
921
true);
···
1005
1005
/* Wa_16025596647 */
1006
1006
if ((DISPLAY_VER(display) == 20 ||
1007
1007
IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
1008
-
is_dc5_dc6_blocked(intel_dp))
1008
+
is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
1009
1009
idle_frames = 0;
1010
1010
else
1011
1011
idle_frames = psr_compute_idle_frames(intel_dp);
···
2006
2006
intel_dp->psr.req_psr2_sdp_prior_scanline =
2007
2007
crtc_state->req_psr2_sdp_prior_scanline;
2008
2008
intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes;
2009
+
intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;
2009
2010
2010
2011
if (!psr_interrupt_error_check(intel_dp))
2011
2012
return;
···
2187
2186
intel_dp->psr.su_region_et_enabled = false;
2188
2187
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
2189
2188
intel_dp->psr.active_non_psr_pipes = 0;
2189
+
intel_dp->psr.pkg_c_latency_used = 0;
2190
2190
}
2191
2191
2192
2192
/**
···
3704
3702
struct intel_display *display = to_intel_display(intel_dp);
3705
3703
bool dc5_dc6_blocked;
3706
3704
3707
-
if (!intel_dp->psr.active)
3705
+
if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used)
3708
3706
return;
3709
3707
3710
3708
dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp);
···
3729
3727
3730
3728
mutex_lock(&intel_dp->psr.lock);
3731
3729
3732
-
if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled)
3730
+
if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled &&
3731
+
!intel_dp->psr.pkg_c_latency_used)
3733
3732
intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);
3734
3733
3735
3734
mutex_unlock(&intel_dp->psr.lock);
···
3808
3805
goto unlock;
3809
3806
3810
3807
if ((enable && intel_dp->psr.active_non_psr_pipes) ||
3811
-
(!enable && !intel_dp->psr.active_non_psr_pipes)) {
3808
+
(!enable && !intel_dp->psr.active_non_psr_pipes) ||
3809
+
!intel_dp->psr.pkg_c_latency_used) {
3812
3810
intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;
3813
3811
goto unlock;
3814
3812
}
···
3844
3840
break;
3845
3841
}
3846
3842
3847
-
if (intel_dp->psr.enabled)
3843
+
if (intel_dp->psr.enabled && intel_dp->psr.pkg_c_latency_used)
3848
3844
intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);
3849
3845
3850
3846
mutex_unlock(&intel_dp->psr.lock);
+5
drivers/gpu/drm/i915/display/skl_watermark.c
+5
drivers/gpu/drm/i915/display/skl_watermark.c
···
2272
2272
return wm0_lines;
2273
2273
}
2274
2274
2275
+
/*
2276
+
* TODO: In case we use PKG_C_LATENCY to allow C-states when the delayed vblank
2277
+
* size is too small for the package C exit latency we need to notify PSR about
2278
+
* the scenario to apply Wa_16025596647.
2279
+
*/
2275
2280
static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
2276
2281
int wm0_lines)
2277
2282
{