Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Enable support for PSP 15_0_0
Add support for PSP v 15.0.0.
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Pratik Vishwakarma
and committed by
Alex Deucher
9b24f63d
19eeae76
+254
-1
+1
drivers/gpu/drm/amd/amdgpu/Makefile
+1
drivers/gpu/drm/amd/amdgpu/Makefile
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
···
2168
2168
case IP_VERSION(14, 0, 5):
2169
2169
amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block);
2170
2170
break;
2171
+
case IP_VERSION(15, 0, 0):
2172
+
amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block);
2173
+
break;
2171
2174
case IP_VERSION(15, 0, 8):
2172
2175
amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block);
2173
2176
break;
+17
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+17
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
···
39
39
#include "psp_v13_0.h"
40
40
#include "psp_v13_0_4.h"
41
41
#include "psp_v14_0.h"
42
+
#include "psp_v15_0.h"
42
43
#include "psp_v15_0_8.h"
43
44
44
45
#include "amdgpu_ras.h"
···
259
258
break;
260
259
case IP_VERSION(14, 0, 5):
261
260
psp_v14_0_set_psp_funcs(psp);
261
+
psp->boot_time_tmr = false;
262
+
break;
263
+
case IP_VERSION(15, 0, 0):
264
+
psp_v15_0_0_set_psp_funcs(psp);
262
265
psp->boot_time_tmr = false;
263
266
break;
264
267
case IP_VERSION(15, 0, 8):
···
910
905
case IP_VERSION(13, 0, 10):
911
906
case IP_VERSION(13, 0, 12):
912
907
case IP_VERSION(13, 0, 14):
908
+
case IP_VERSION(15, 0, 0):
913
909
case IP_VERSION(15, 0, 8):
914
910
return true;
915
911
default:
···
2933
2927
2934
2928
ret = psp_get_fw_type(psp, ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2935
2929
if (ret)
2936
-
dev_err(psp->adev->dev, "Unknown firmware type\n");
2930
+
dev_err(psp->adev->dev, "Unknown firmware type %d\n", ucode->ucode_id);
2937
2931
return ret;
2938
2932
}
2939
2933
···
3097
3091
IP_VERSION(11, 0, 11) ||
3098
3092
amdgpu_ip_version(adev, MP0_HWIP, 0) ==
3099
3093
IP_VERSION(11, 0, 12) ||
3094
+
amdgpu_ip_version(adev, MP0_HWIP, 0) ==
3095
+
IP_VERSION(15, 0, 0) ||
3100
3096
amdgpu_ip_version(adev, MP0_HWIP, 0) ==
3101
3097
IP_VERSION(15, 0, 8)) &&
3102
3098
(ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
···
4550
4542
const struct amdgpu_ip_block_version psp_v14_0_ip_block = {
4551
4543
.type = AMD_IP_BLOCK_TYPE_PSP,
4552
4544
.major = 14,
4545
+
.minor = 0,
4546
+
.rev = 0,
4547
+
.funcs = &psp_ip_funcs,
4548
+
};
4549
+
4550
+
const struct amdgpu_ip_block_version psp_v15_0_ip_block = {
4551
+
.type = AMD_IP_BLOCK_TYPE_PSP,
4552
+
.major = 15,
4553
4553
.minor = 0,
4554
4554
.rev = 0,
4555
4555
.funcs = &psp_ip_funcs,
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
···
540
540
extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
541
541
extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
542
542
extern const struct amdgpu_ip_block_version psp_v14_0_ip_block;
543
+
extern const struct amdgpu_ip_block_version psp_v15_0_ip_block;
543
544
extern const struct amdgpu_ip_block_version psp_v15_0_8_ip_block;
544
545
545
546
int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
+202
drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
+202
drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
···
1
+
/*
2
+
* Copyright 2025 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
#include <drm/drm_drv.h>
24
+
#include <linux/vmalloc.h>
25
+
#include "amdgpu.h"
26
+
#include "amdgpu_psp.h"
27
+
#include "amdgpu_ucode.h"
28
+
#include "soc15_common.h"
29
+
#include "psp_v15_0.h"
30
+
31
+
#include "mp/mp_15_0_0_offset.h"
32
+
#include "mp/mp_15_0_0_sh_mask.h"
33
+
34
+
MODULE_FIRMWARE("amdgpu/psp_15_0_0_toc.bin");
35
+
36
+
static int psp_v15_0_0_init_microcode(struct psp_context *psp)
37
+
{
38
+
struct amdgpu_device *adev = psp->adev;
39
+
char ucode_prefix[30];
40
+
int err = 0;
41
+
42
+
amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
43
+
44
+
err = psp_init_toc_microcode(psp, ucode_prefix);
45
+
if (err)
46
+
return err;
47
+
48
+
return 0;
49
+
}
50
+
51
+
static int psp_v15_0_0_ring_stop(struct psp_context *psp,
52
+
enum psp_ring_type ring_type)
53
+
{
54
+
int ret = 0;
55
+
struct amdgpu_device *adev = psp->adev;
56
+
57
+
if (amdgpu_sriov_vf(adev)) {
58
+
/* Write the ring destroy command*/
59
+
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
60
+
GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
61
+
/* there might be handshake issue with hardware which needs delay */
62
+
mdelay(20);
63
+
/* Wait for response flag (bit 31) */
64
+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
65
+
0x80000000, 0x80000000, false);
66
+
} else {
67
+
/* Write the ring destroy command*/
68
+
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
69
+
GFX_CTRL_CMD_ID_DESTROY_RINGS);
70
+
/* there might be handshake issue with hardware which needs delay */
71
+
mdelay(20);
72
+
/* Wait for response flag (bit 31) */
73
+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
74
+
0x80000000, 0x80000000, false);
75
+
}
76
+
77
+
return ret;
78
+
}
79
+
80
+
static int psp_v15_0_0_ring_create(struct psp_context *psp,
81
+
enum psp_ring_type ring_type)
82
+
{
83
+
int ret = 0;
84
+
unsigned int psp_ring_reg = 0;
85
+
struct psp_ring *ring = &psp->km_ring;
86
+
struct amdgpu_device *adev = psp->adev;
87
+
88
+
if (amdgpu_sriov_vf(adev)) {
89
+
ret = psp_v15_0_0_ring_stop(psp, ring_type);
90
+
if (ret) {
91
+
DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n");
92
+
return ret;
93
+
}
94
+
95
+
/* Write low address of the ring to C2PMSG_102 */
96
+
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
97
+
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg);
98
+
/* Write high address of the ring to C2PMSG_103 */
99
+
psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
100
+
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg);
101
+
102
+
/* Write the ring initialization command to C2PMSG_101 */
103
+
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
104
+
GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
105
+
106
+
/* there might be handshake issue with hardware which needs delay */
107
+
mdelay(20);
108
+
109
+
/* Wait for response flag (bit 31) in C2PMSG_101 */
110
+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
111
+
0x80000000, 0x8000FFFF, false);
112
+
113
+
} else {
114
+
/* Wait for sOS ready for ring creation */
115
+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
116
+
0x80000000, 0x80000000, false);
117
+
if (ret) {
118
+
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
119
+
return ret;
120
+
}
121
+
122
+
/* Write low address of the ring to C2PMSG_69 */
123
+
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
124
+
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg);
125
+
/* Write high address of the ring to C2PMSG_70 */
126
+
psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
127
+
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg);
128
+
/* Write size of ring to C2PMSG_71 */
129
+
psp_ring_reg = ring->ring_size;
130
+
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg);
131
+
/* Write the ring initialization command to C2PMSG_64 */
132
+
psp_ring_reg = ring_type;
133
+
psp_ring_reg = psp_ring_reg << 16;
134
+
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg);
135
+
136
+
/* there might be handshake issue with hardware which needs delay */
137
+
mdelay(20);
138
+
139
+
/* Wait for response flag (bit 31) in C2PMSG_64 */
140
+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
141
+
0x80000000, 0x8000FFFF, false);
142
+
}
143
+
144
+
return ret;
145
+
}
146
+
147
+
static int psp_v15_0_0_ring_destroy(struct psp_context *psp,
148
+
enum psp_ring_type ring_type)
149
+
{
150
+
int ret = 0;
151
+
struct psp_ring *ring = &psp->km_ring;
152
+
struct amdgpu_device *adev = psp->adev;
153
+
154
+
ret = psp_v15_0_0_ring_stop(psp, ring_type);
155
+
if (ret)
156
+
DRM_ERROR("Fail to stop psp ring\n");
157
+
158
+
amdgpu_bo_free_kernel(&adev->firmware.rbuf,
159
+
&ring->ring_mem_mc_addr,
160
+
(void **)&ring->ring_mem);
161
+
162
+
return ret;
163
+
}
164
+
165
+
static uint32_t psp_v15_0_0_ring_get_wptr(struct psp_context *psp)
166
+
{
167
+
uint32_t data;
168
+
struct amdgpu_device *adev = psp->adev;
169
+
170
+
if (amdgpu_sriov_vf(adev))
171
+
data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);
172
+
else
173
+
data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67);
174
+
175
+
return data;
176
+
}
177
+
178
+
static void psp_v15_0_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
179
+
{
180
+
struct amdgpu_device *adev = psp->adev;
181
+
182
+
if (amdgpu_sriov_vf(adev)) {
183
+
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value);
184
+
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
185
+
GFX_CTRL_CMD_ID_CONSUME_CMD);
186
+
} else
187
+
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value);
188
+
}
189
+
190
+
static const struct psp_funcs psp_v15_0_0_funcs = {
191
+
.init_microcode = psp_v15_0_0_init_microcode,
192
+
.ring_create = psp_v15_0_0_ring_create,
193
+
.ring_stop = psp_v15_0_0_ring_stop,
194
+
.ring_destroy = psp_v15_0_0_ring_destroy,
195
+
.ring_get_wptr = psp_v15_0_0_ring_get_wptr,
196
+
.ring_set_wptr = psp_v15_0_0_ring_set_wptr,
197
+
};
198
+
199
+
void psp_v15_0_0_set_psp_funcs(struct psp_context *psp)
200
+
{
201
+
psp->funcs = &psp_v15_0_0_funcs;
202
+
}
+30
drivers/gpu/drm/amd/amdgpu/psp_v15_0.h
+30
drivers/gpu/drm/amd/amdgpu/psp_v15_0.h
···
1
+
/*
2
+
* Copyright 2025 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
#ifndef __PSP_V15_0_0_H__
24
+
#define __PSP_V15_0_0_H__
25
+
26
+
#include "amdgpu_psp.h"
27
+
28
+
void psp_v15_0_0_set_psp_funcs(struct psp_context *psp);
29
+
30
+
#endif