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crypto: qat - differentiate between pf2vf and vf2pf offset

Add the function get_vf2pf_offset() to adf_pfvf_ops to differentiate the
CSRs used for pf2vf and vf2pf.

Offsets may or may not be direction specific depending on QAT
generation. Since in QAT GEN2 the CSR is not direction specific, i.e.
there is a single mailbox register shared for pf2vf and vf2pf, both
get_vf2pf_offset() and get_vf2pf_offset() will return the same offset.

This change is to make the direction explicit, so it is easier to
understand and debug and also in preparation for the introduction of
PFVF support in the qat_4xxx driver since QAT GEN4 devices have a
separate CSR for pf2vf and vf2pf communications.

Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Marco Chiappero and committed by
Herbert Xu 9baf2de7 bc63dabe

+10 -7
+1
drivers/crypto/qat/qat_common/adf_accel_devices.h
··· 150 150 struct adf_pfvf_ops { 151 151 int (*enable_comms)(struct adf_accel_dev *accel_dev); 152 152 u32 (*get_pf2vf_offset)(u32 i); 153 + u32 (*get_vf2pf_offset)(u32 i); 153 154 u32 (*get_vf2pf_sources)(void __iomem *pmisc_addr); 154 155 void (*enable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask); 155 156 void (*disable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask);
+6 -4
drivers/crypto/qat/qat_common/adf_gen2_pfvf.c
··· 12 12 #define ADF_GEN2_PF_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i) * 0x04)) 13 13 #define ADF_GEN2_VF_PF2VF_OFFSET 0x200 14 14 15 - static u32 adf_gen2_pf_get_pf2vf_offset(u32 i) 15 + static u32 adf_gen2_pf_get_pfvf_offset(u32 i) 16 16 { 17 17 return ADF_GEN2_PF_PF2VF_OFFSET(i); 18 18 } 19 19 20 - static u32 adf_gen2_vf_get_pf2vf_offset(u32 i) 20 + static u32 adf_gen2_vf_get_pfvf_offset(u32 i) 21 21 { 22 22 return ADF_GEN2_VF_PF2VF_OFFSET; 23 23 } ··· 64 64 void adf_gen2_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops) 65 65 { 66 66 pfvf_ops->enable_comms = adf_enable_pf2vf_comms; 67 - pfvf_ops->get_pf2vf_offset = adf_gen2_pf_get_pf2vf_offset; 67 + pfvf_ops->get_pf2vf_offset = adf_gen2_pf_get_pfvf_offset; 68 + pfvf_ops->get_vf2pf_offset = adf_gen2_pf_get_pfvf_offset; 68 69 pfvf_ops->get_vf2pf_sources = adf_gen2_get_vf2pf_sources; 69 70 pfvf_ops->enable_vf2pf_interrupts = adf_gen2_enable_vf2pf_interrupts; 70 71 pfvf_ops->disable_vf2pf_interrupts = adf_gen2_disable_vf2pf_interrupts; ··· 75 74 void adf_gen2_init_vf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops) 76 75 { 77 76 pfvf_ops->enable_comms = adf_enable_vf2pf_comms; 78 - pfvf_ops->get_pf2vf_offset = adf_gen2_vf_get_pf2vf_offset; 77 + pfvf_ops->get_pf2vf_offset = adf_gen2_vf_get_pfvf_offset; 78 + pfvf_ops->get_vf2pf_offset = adf_gen2_vf_get_pfvf_offset; 79 79 } 80 80 EXPORT_SYMBOL_GPL(adf_gen2_init_vf_pfvf_ops);
+3 -3
drivers/crypto/qat/qat_common/adf_pf2vf_msg.c
··· 29 29 int ret; 30 30 31 31 if (accel_dev->is_vf) { 32 - pf2vf_offset = hw_data->pfvf_ops.get_pf2vf_offset(0); 32 + pf2vf_offset = hw_data->pfvf_ops.get_vf2pf_offset(0); 33 33 lock = &accel_dev->vf.vf2pf_lock; 34 34 local_in_use_mask = ADF_VF2PF_IN_USE_BY_VF_MASK; 35 35 local_in_use_pattern = ADF_VF2PF_IN_USE_BY_VF; ··· 258 258 u32 msg, resp = 0; 259 259 260 260 /* Read message from the VF */ 261 - msg = ADF_CSR_RD(pmisc_addr, hw_data->pfvf_ops.get_pf2vf_offset(vf_nr)); 261 + msg = ADF_CSR_RD(pmisc_addr, hw_data->pfvf_ops.get_vf2pf_offset(vf_nr)); 262 262 if (!(msg & ADF_VF2PF_INT)) { 263 263 dev_info(&GET_DEV(accel_dev), 264 264 "Spurious VF2PF interrupt, msg %X. Ignored\n", msg); ··· 275 275 276 276 /* To ACK, clear the VF2PFINT bit */ 277 277 msg &= ~ADF_VF2PF_INT; 278 - ADF_CSR_WR(pmisc_addr, hw_data->pfvf_ops.get_pf2vf_offset(vf_nr), msg); 278 + ADF_CSR_WR(pmisc_addr, hw_data->pfvf_ops.get_vf2pf_offset(vf_nr), msg); 279 279 280 280 if (adf_handle_vf2pf_msg(accel_dev, vf_nr, msg, &resp)) 281 281 return false;