Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: support plane splitting in quad-pipe case
The content of every half of screen is sent out via one interface in
dual-DSI case. The content for every interface is blended by a LM
pair in quad-pipe case, thus a LM pair should not blend any content
that cross the half of screen in this case. Clip plane into pipes per
left and right half screen ROI if topology is quad pipe case.
The clipped rectangle on every half of screen is futher handled by two
pipes if its width exceeds a limit for a single pipe.
For non-virtual-plane case, there is always one stage config to serve
a LM or LM pair. So the clipping does not occur when interating stages
in this case. The plane is mapped to 2 pipes only when width or clock
rate exceeds hardware constrain within stage check.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/711324/
Link: https://lore.kernel.org/r/20260312-msm-next-quad-pipe-split-v19-3-4ffa2b06c996@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
authored by
Jun Nie
and committed by
Dmitry Baryshkov
9c171c36
25ee1092
+118
-43
+11
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+11
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
···
1667
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return 0;
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}
1669
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+
/**
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* dpu_crtc_get_num_lm - Get mixer number in this CRTC pipeline
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+
* @state: Pointer to drm crtc state object
1673
+
*/
1674
+
unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state)
1675
+
{
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struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
1677
+
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return cstate->num_mixers;
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+
}
1680
+
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#ifdef CONFIG_DEBUG_FS
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static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
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{
+2
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+2
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+105
-43
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+105
-43
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
···
878
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struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
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struct dpu_sw_pipe_cfg *pipe_cfg;
880
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struct dpu_sw_pipe_cfg *r_pipe_cfg;
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+
const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
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uint32_t max_linewidth;
882
-
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-
/* move the assignment here, to ease handling to another pairs later */
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-
pipe_cfg = &pstate->pipe_cfg[0];
885
-
r_pipe_cfg = &pstate->pipe_cfg[1];
886
-
/* state->src is 16.16, src_rect is not */
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drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src);
888
-
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-
pipe_cfg->dst_rect = new_plane_state->dst;
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+
u32 num_lm;
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+
int stage_id, num_stages;
890
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max_linewidth = pdpu->catalog->caps->max_linewidth;
892
887
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-
drm_rect_rotate(&pipe_cfg->src_rect,
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-
new_plane_state->fb->width, new_plane_state->fb->height,
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-
new_plane_state->rotation);
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+
/* In non-virtual plane case, one mixer pair is always needed. */
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+
num_lm = dpu_crtc_get_num_lm(crtc_state);
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+
if (dpu_use_virtual_planes)
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num_stages = (num_lm + 1) / 2;
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+
else
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+
num_stages = 1;
896
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-
if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) ||
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-
_dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) {
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if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) {
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-
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
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-
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
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-
return -E2BIG;
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+
/*
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* For wide plane that exceeds SSPP rectangle constrain, it needed to
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+
* be split and mapped to 2 rectangles with 1 config for 2:2:1.
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+
* For 2 interfaces cases, such as dual DSI, 2:2:2 topology is needed.
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+
* If the width or clock exceeds hardware limitation in every half of
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+
* screen, 4:4:2 topology is needed and virtual plane feature should
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+
* be enabled to map plane to more than 1 SSPP. 2 stage configs are
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+
* needed to serve 2 mixer pairs in this 4:4:2 case. So both left/right
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+
* half of plane splitting, and splitting within the half of screen is
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* needed in quad-pipe case. Check dest rectangle left/right clipping
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+
* and iterate mixer configs for this plane first, then check wide
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+
* rectangle splitting in every half next.
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+
*/
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+
for (stage_id = 0; stage_id < num_stages; stage_id++) {
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+
struct drm_rect mixer_rect = {
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+
.x1 = stage_id * mode->hdisplay / num_stages,
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+
.y1 = 0,
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+
.x2 = (stage_id + 1) * mode->hdisplay / num_stages,
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+
.y2 = mode->vdisplay
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+
};
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+
int cfg_idx = stage_id * PIPES_PER_STAGE;
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+
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+
pipe_cfg = &pstate->pipe_cfg[cfg_idx];
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+
r_pipe_cfg = &pstate->pipe_cfg[cfg_idx + 1];
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+
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+
drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src);
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+
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+
drm_rect_rotate(&pipe_cfg->src_rect,
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new_plane_state->fb->width, new_plane_state->fb->height,
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+
new_plane_state->rotation);
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+
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pipe_cfg->dst_rect = new_plane_state->dst;
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+
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DPU_DEBUG_PLANE(pdpu, "checking src " DRM_RECT_FMT
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+
" vs clip window " DRM_RECT_FMT "\n",
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DRM_RECT_ARG(&pipe_cfg->src_rect),
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DRM_RECT_ARG(&mixer_rect));
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+
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+
/*
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* If this plane does not fall into mixer rect, check next
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* mixer rect.
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+
*/
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+
if (!drm_rect_clip_scaled(&pipe_cfg->src_rect,
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&pipe_cfg->dst_rect,
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&mixer_rect)) {
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+
memset(pipe_cfg, 0, 2 * sizeof(struct dpu_sw_pipe_cfg));
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+
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+
continue;
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}
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-
*r_pipe_cfg = *pipe_cfg;
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-
pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1;
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-
pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1;
908
-
r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2;
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-
r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2;
910
-
} else {
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-
memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg));
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-
}
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+
pipe_cfg->dst_rect.x1 -= mixer_rect.x1;
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+
pipe_cfg->dst_rect.x2 -= mixer_rect.x1;
913
947
914
-
drm_rect_rotate_inv(&pipe_cfg->src_rect,
915
-
new_plane_state->fb->width, new_plane_state->fb->height,
916
-
new_plane_state->rotation);
917
-
if (drm_rect_width(&r_pipe_cfg->src_rect) != 0)
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-
drm_rect_rotate_inv(&r_pipe_cfg->src_rect,
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-
new_plane_state->fb->width, new_plane_state->fb->height,
948
+
DPU_DEBUG_PLANE(pdpu, "Got clip src:" DRM_RECT_FMT " dst: " DRM_RECT_FMT "\n",
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+
DRM_RECT_ARG(&pipe_cfg->src_rect), DRM_RECT_ARG(&pipe_cfg->dst_rect));
950
+
951
+
/* Split wide rect into 2 rect */
952
+
if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) ||
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+
_dpu_plane_calc_clk(mode, pipe_cfg) > max_mdp_clk_rate) {
954
+
955
+
if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) {
956
+
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
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+
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
958
+
return -E2BIG;
959
+
}
960
+
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+
memcpy(r_pipe_cfg, pipe_cfg, sizeof(struct dpu_sw_pipe_cfg));
962
+
pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1;
963
+
pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1;
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+
r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2;
965
+
r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2;
966
+
DPU_DEBUG_PLANE(pdpu, "Split wide plane into:"
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+
DRM_RECT_FMT " and " DRM_RECT_FMT "\n",
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+
DRM_RECT_ARG(&pipe_cfg->src_rect),
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+
DRM_RECT_ARG(&r_pipe_cfg->src_rect));
970
+
} else {
971
+
memset(r_pipe_cfg, 0, sizeof(struct dpu_sw_pipe_cfg));
972
+
}
973
+
974
+
drm_rect_rotate_inv(&pipe_cfg->src_rect,
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+
new_plane_state->fb->width,
976
+
new_plane_state->fb->height,
920
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new_plane_state->rotation);
978
+
979
+
if (drm_rect_width(&r_pipe_cfg->src_rect) != 0)
980
+
drm_rect_rotate_inv(&r_pipe_cfg->src_rect,
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+
new_plane_state->fb->width,
982
+
new_plane_state->fb->height,
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+
new_plane_state->rotation);
984
+
}
921
985
922
986
return 0;
923
987
}
···
1056
992
drm_atomic_get_new_plane_state(state, plane);
1057
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struct dpu_plane *pdpu = to_dpu_plane(plane);
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struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
1059
-
struct dpu_sw_pipe *pipe = &pstate->pipe[0];
1060
-
struct dpu_sw_pipe *r_pipe = &pstate->pipe[1];
1061
-
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0];
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-
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1];
1063
-
int ret = 0;
1064
995
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-
ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg,
1066
-
&crtc_state->adjusted_mode,
1067
-
new_plane_state);
1068
-
if (ret)
1069
-
return ret;
996
+
struct dpu_sw_pipe *pipe;
997
+
struct dpu_sw_pipe_cfg *pipe_cfg;
998
+
int ret = 0, i;
1070
999
1071
-
if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) {
1072
-
ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg,
1000
+
for (i = 0; i < PIPES_PER_PLANE; i++) {
1001
+
pipe = &pstate->pipe[i];
1002
+
pipe_cfg = &pstate->pipe_cfg[i];
1003
+
if (!drm_rect_width(&pipe_cfg->src_rect))
1004
+
continue;
1005
+
DPU_DEBUG_PLANE(pdpu, "pipe %d is in use, validate it\n", i);
1006
+
ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg,
1073
1007
&crtc_state->adjusted_mode,
1074
1008
new_plane_state);
1075
1009
if (ret)