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kernel
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linux
dt-bindings: clk: gxbb-clkc: expose all clock ids
Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.
This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.
It was decided to move every gxbb-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.
[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-7-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
authored by
Neil Armstrong
and committed by
Jerome Brunet
9ce85552
05d3b7c6
+65
-76
-76
drivers/clk/meson/gxbb.h
-76
drivers/clk/meson/gxbb.h
···
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#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */
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#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */
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-
/*
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* CLKID index values
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*
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* These indices are entirely contrived and do not map onto the hardware.
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* It has now been decided to expose everything by default in the DT header:
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* include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
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* to expose, such as the internal muxes and dividers of composite clocks,
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* will remain defined here.
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*/
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/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
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#define CLKID_MPEG_SEL 10
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#define CLKID_MPEG_DIV 11
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#define CLKID_SAR_ADC_DIV 99
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#define CLKID_MALI_0_DIV 101
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#define CLKID_MALI_1_DIV 104
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#define CLKID_CTS_AMCLK_SEL 108
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#define CLKID_CTS_AMCLK_DIV 109
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#define CLKID_CTS_MCLK_I958_SEL 111
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#define CLKID_CTS_MCLK_I958_DIV 112
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#define CLKID_32K_CLK_SEL 115
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#define CLKID_32K_CLK_DIV 116
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#define CLKID_SD_EMMC_A_CLK0_SEL 117
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#define CLKID_SD_EMMC_A_CLK0_DIV 118
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#define CLKID_SD_EMMC_B_CLK0_SEL 120
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#define CLKID_SD_EMMC_B_CLK0_DIV 121
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#define CLKID_SD_EMMC_C_CLK0_SEL 123
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#define CLKID_SD_EMMC_C_CLK0_DIV 124
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#define CLKID_VPU_0_DIV 127
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#define CLKID_VPU_1_DIV 130
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#define CLKID_VAPB_0_DIV 134
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#define CLKID_VAPB_1_DIV 137
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#define CLKID_HDMI_PLL_PRE_MULT 141
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#define CLKID_MPLL0_DIV 142
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#define CLKID_MPLL1_DIV 143
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#define CLKID_MPLL2_DIV 144
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#define CLKID_MPLL_PREDIV 145
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#define CLKID_FCLK_DIV2_DIV 146
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#define CLKID_FCLK_DIV3_DIV 147
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#define CLKID_FCLK_DIV4_DIV 148
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#define CLKID_FCLK_DIV5_DIV 149
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#define CLKID_FCLK_DIV7_DIV 150
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#define CLKID_VDEC_1_SEL 151
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#define CLKID_VDEC_1_DIV 152
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#define CLKID_VDEC_HEVC_SEL 154
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#define CLKID_VDEC_HEVC_DIV 155
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#define CLKID_GEN_CLK_SEL 157
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#define CLKID_GEN_CLK_DIV 158
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#define CLKID_FIXED_PLL_DCO 160
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#define CLKID_HDMI_PLL_DCO 161
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#define CLKID_HDMI_PLL_OD 162
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#define CLKID_HDMI_PLL_OD2 163
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#define CLKID_SYS_PLL_DCO 164
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#define CLKID_GP0_PLL_DCO 165
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#define CLKID_VID_PLL_SEL 167
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#define CLKID_VID_PLL_DIV 168
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#define CLKID_VCLK_SEL 169
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#define CLKID_VCLK2_SEL 170
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#define CLKID_VCLK_INPUT 171
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#define CLKID_VCLK2_INPUT 172
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#define CLKID_VCLK_DIV 173
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#define CLKID_VCLK2_DIV 174
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#define CLKID_VCLK_DIV2_EN 177
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#define CLKID_VCLK_DIV4_EN 178
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#define CLKID_VCLK_DIV6_EN 179
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#define CLKID_VCLK_DIV12_EN 180
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#define CLKID_VCLK2_DIV2_EN 181
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#define CLKID_VCLK2_DIV4_EN 182
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#define CLKID_VCLK2_DIV6_EN 183
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#define CLKID_VCLK2_DIV12_EN 184
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#define CLKID_CTS_ENCI_SEL 195
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#define CLKID_CTS_ENCP_SEL 196
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#define CLKID_CTS_VDAC_SEL 197
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#define CLKID_HDMI_TX_SEL 198
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#define CLKID_HDMI_SEL 203
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#define CLKID_HDMI_DIV 204
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/* include the CLKIDs that have been made part of the DT binding */
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#include <dt-bindings/clock/gxbb-clkc.h>
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+65
include/dt-bindings/clock/gxbb-clkc.h
+65
include/dt-bindings/clock/gxbb-clkc.h
···
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#define CLKID_FCLK_DIV5 7
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#define CLKID_FCLK_DIV7 8
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#define CLKID_GP0_PLL 9
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+
#define CLKID_MPEG_SEL 10
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#define CLKID_MPEG_DIV 11
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#define CLKID_CLK81 12
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#define CLKID_MPLL0 13
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#define CLKID_MPLL1 14
···
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#define CLKID_SD_EMMC_C 96
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#define CLKID_SAR_ADC_CLK 97
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#define CLKID_SAR_ADC_SEL 98
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#define CLKID_SAR_ADC_DIV 99
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#define CLKID_MALI_0_SEL 100
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#define CLKID_MALI_0_DIV 101
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#define CLKID_MALI_0 102
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#define CLKID_MALI_1_SEL 103
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#define CLKID_MALI_1_DIV 104
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#define CLKID_MALI_1 105
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#define CLKID_MALI 106
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#define CLKID_CTS_AMCLK 107
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#define CLKID_CTS_AMCLK_SEL 108
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#define CLKID_CTS_AMCLK_DIV 109
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#define CLKID_CTS_MCLK_I958 110
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#define CLKID_CTS_MCLK_I958_SEL 111
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#define CLKID_CTS_MCLK_I958_DIV 112
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#define CLKID_CTS_I958 113
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#define CLKID_32K_CLK 114
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#define CLKID_32K_CLK_SEL 115
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#define CLKID_32K_CLK_DIV 116
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#define CLKID_SD_EMMC_A_CLK0_SEL 117
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#define CLKID_SD_EMMC_A_CLK0_DIV 118
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#define CLKID_SD_EMMC_A_CLK0 119
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#define CLKID_SD_EMMC_B_CLK0_SEL 120
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#define CLKID_SD_EMMC_B_CLK0_DIV 121
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#define CLKID_SD_EMMC_B_CLK0 122
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#define CLKID_SD_EMMC_C_CLK0_SEL 123
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#define CLKID_SD_EMMC_C_CLK0_DIV 124
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#define CLKID_SD_EMMC_C_CLK0 125
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#define CLKID_VPU_0_SEL 126
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#define CLKID_VPU_0_DIV 127
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#define CLKID_VPU_0 128
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#define CLKID_VPU_1_SEL 129
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#define CLKID_VPU_1_DIV 130
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#define CLKID_VPU_1 131
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#define CLKID_VPU 132
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#define CLKID_VAPB_0_SEL 133
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#define CLKID_VAPB_0_DIV 134
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#define CLKID_VAPB_0 135
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#define CLKID_VAPB_1_SEL 136
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#define CLKID_VAPB_1_DIV 137
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#define CLKID_VAPB_1 138
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#define CLKID_VAPB_SEL 139
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#define CLKID_VAPB 140
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#define CLKID_HDMI_PLL_PRE_MULT 141
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#define CLKID_MPLL0_DIV 142
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#define CLKID_MPLL1_DIV 143
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#define CLKID_MPLL2_DIV 144
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#define CLKID_MPLL_PREDIV 145
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#define CLKID_FCLK_DIV2_DIV 146
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#define CLKID_FCLK_DIV3_DIV 147
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#define CLKID_FCLK_DIV4_DIV 148
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#define CLKID_FCLK_DIV5_DIV 149
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#define CLKID_FCLK_DIV7_DIV 150
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#define CLKID_VDEC_1_SEL 151
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#define CLKID_VDEC_1_DIV 152
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#define CLKID_VDEC_1 153
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#define CLKID_VDEC_HEVC_SEL 154
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+
#define CLKID_VDEC_HEVC_DIV 155
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#define CLKID_VDEC_HEVC 156
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#define CLKID_GEN_CLK_SEL 157
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#define CLKID_GEN_CLK_DIV 158
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#define CLKID_GEN_CLK 159
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#define CLKID_FIXED_PLL_DCO 160
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#define CLKID_HDMI_PLL_DCO 161
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#define CLKID_HDMI_PLL_OD 162
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#define CLKID_HDMI_PLL_OD2 163
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#define CLKID_SYS_PLL_DCO 164
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#define CLKID_GP0_PLL_DCO 165
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#define CLKID_VID_PLL 166
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#define CLKID_VID_PLL_SEL 167
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#define CLKID_VID_PLL_DIV 168
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#define CLKID_VCLK_SEL 169
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#define CLKID_VCLK2_SEL 170
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#define CLKID_VCLK_INPUT 171
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#define CLKID_VCLK2_INPUT 172
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#define CLKID_VCLK_DIV 173
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#define CLKID_VCLK2_DIV 174
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#define CLKID_VCLK 175
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#define CLKID_VCLK2 176
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#define CLKID_VCLK_DIV2_EN 177
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#define CLKID_VCLK_DIV4_EN 178
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#define CLKID_VCLK_DIV6_EN 179
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#define CLKID_VCLK_DIV12_EN 180
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#define CLKID_VCLK2_DIV2_EN 181
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#define CLKID_VCLK2_DIV4_EN 182
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#define CLKID_VCLK2_DIV6_EN 183
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#define CLKID_VCLK2_DIV12_EN 184
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#define CLKID_VCLK_DIV1 185
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#define CLKID_VCLK_DIV2 186
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#define CLKID_VCLK_DIV4 187
···
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#define CLKID_VCLK2_DIV4 192
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#define CLKID_VCLK2_DIV6 193
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#define CLKID_VCLK2_DIV12 194
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+
#define CLKID_CTS_ENCI_SEL 195
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+
#define CLKID_CTS_ENCP_SEL 196
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#define CLKID_CTS_VDAC_SEL 197
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+
#define CLKID_HDMI_TX_SEL 198
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#define CLKID_CTS_ENCI 199
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#define CLKID_CTS_ENCP 200
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#define CLKID_CTS_VDAC 201
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#define CLKID_HDMI_TX 202
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+
#define CLKID_HDMI_SEL 203
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+
#define CLKID_HDMI_DIV 204
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#define CLKID_HDMI 205
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#define CLKID_ACODEC 206
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