Merge branch 'i2c/for-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

+6 -2

Documentation/devicetree/bindings/i2c/i2c-ocores.txt

··· 5 5 "aeroflexgaisler,i2cmst" 6 6 "sifive,fu540-c000-i2c", "sifive,i2c0" 7 7 For Opencore based I2C IP block reimplemented in 8 - FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt 9 - for additional details. 8 + FU540-C000 SoC. 9 + "sifive,fu740-c000-i2c", "sifive,i2c0" 10 + For Opencore based I2C IP block reimplemented in 11 + FU740-C000 SoC. 12 + Please refer to sifive-blocks-ip-versioning.txt for 13 + additional details. 10 14 - reg : bus address start and address range size of device 11 15 - clocks : handle to the controller clock; see the note below. 12 16 Mutually exclusive with opencores,ip-clock-frequency

+1

Documentation/devicetree/bindings/i2c/i2c-omap.txt

··· 8 8 "ti,omap4-i2c" for OMAP4+ SoCs 9 9 "ti,am654-i2c", "ti,omap4-i2c" for AM654 SoCs 10 10 "ti,j721e-i2c", "ti,omap4-i2c" for J721E SoCs 11 + "ti,am64-i2c", "ti,omap4-i2c" for AM64 SoCs 11 12 - ti,hwmods : Must be "i2c<n>", n being the instance number (1-based) 12 13 - #address-cells = <1>; 13 14 - #size-cells = <0>;

-29

Documentation/devicetree/bindings/i2c/i2c-owl.txt

··· 1 - Actions Semiconductor Owl I2C controller 2 - 3 - Required properties: 4 - 5 - - compatible : Should be one of the following: 6 - - "actions,s700-i2c" for S700 SoC 7 - - "actions,s900-i2c" for S900 SoC 8 - - reg : Offset and length of the register set for the device. 9 - - #address-cells : Should be 1. 10 - - #size-cells : Should be 0. 11 - - interrupts : A single interrupt specifier. 12 - - clocks : Phandle of the clock feeding the I2C controller. 13 - 14 - Optional properties: 15 - 16 - - clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and 17 - Fast modes are supported, possible values are 100000 and 18 - 400000. 19 - Examples: 20 - 21 - i2c0: i2c@e0170000 { 22 - compatible = "actions,s900-i2c"; 23 - reg = <0 0xe0170000 0 0x1000>; 24 - #address-cells = <1>; 25 - #size-cells = <0>; 26 - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 27 - clocks = <&clock CLK_I2C0>; 28 - clock-frequency = <100000>; 29 - };

+62

Documentation/devicetree/bindings/i2c/i2c-owl.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/i2c/i2c-owl.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Actions Semi Owl I2C Controller 8 + 9 + maintainers: 10 + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 11 + 12 + description: | 13 + This I2C controller is found in the Actions Semi Owl SoCs: 14 + S500, S700 and S900. 15 + 16 + allOf: 17 + - $ref: /schemas/i2c/i2c-controller.yaml# 18 + 19 + properties: 20 + compatible: 21 + enum: 22 + - actions,s500-i2c # Actions Semi S500 compatible SoCs 23 + - actions,s700-i2c # Actions Semi S700 compatible SoCs 24 + - actions,s900-i2c # Actions Semi S900 compatible SoCs 25 + 26 + reg: 27 + maxItems: 1 28 + 29 + interrupts: 30 + maxItems: 1 31 + 32 + clocks: 33 + description: Phandle of the clock feeding the I2C controller. 34 + minItems: 1 35 + 36 + clock-frequency: 37 + description: | 38 + Desired I2C bus clock frequency in Hz. As only Standard and Fast 39 + modes are supported, possible values are 100000 and 400000. 40 + enum: [100000, 400000] 41 + 42 + required: 43 + - compatible 44 + - reg 45 + - interrupts 46 + - clocks 47 + 48 + unevaluatedProperties: false 49 + 50 + examples: 51 + - | 52 + #include <dt-bindings/clock/actions,s900-cmu.h> 53 + #include <dt-bindings/interrupt-controller/arm-gic.h> 54 + i2c@e0170000 { 55 + compatible = "actions,s900-i2c"; 56 + reg = <0xe0170000 0x1000>; 57 + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 58 + clocks = <&cmu CLK_I2C0>; 59 + clock-frequency = <100000>; 60 + }; 61 + 62 + ...

-42

Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.txt

··· 1 - Device tree configuration for the Mellanox I2C SMBus on BlueField SoCs 2 - 3 - Required Properties: 4 - 5 - - compatible : should be "mellanox,i2c-mlxbf1" or "mellanox,i2c-mlxbf2". 6 - 7 - - reg : address offset and length of the device registers. The 8 - registers consist of the following set of resources: 9 - 1) Smbus block registers. 10 - 2) Cause master registers. 11 - 3) Cause slave registers. 12 - 4) Cause coalesce registers (if compatible isn't set 13 - to "mellanox,i2c-mlxbf1"). 14 - 15 - - interrupts : interrupt number. 16 - 17 - Optional Properties: 18 - 19 - - clock-frequency : bus frequency used to configure timing registers; 20 - allowed values are 100000, 400000 and 1000000; 21 - those are expressed in Hz. Default is 100000. 22 - 23 - Example: 24 - 25 - i2c@2804000 { 26 - compatible = "mellanox,i2c-mlxbf1"; 27 - reg = <0x02804000 0x800>, 28 - <0x02801200 0x020>, 29 - <0x02801260 0x020>; 30 - interrupts = <57>; 31 - clock-frequency = <100000>; 32 - }; 33 - 34 - i2c@2808800 { 35 - compatible = "mellanox,i2c-mlxbf2"; 36 - reg = <0x02808800 0x600>, 37 - <0x02808e00 0x020>, 38 - <0x02808e20 0x020>, 39 - <0x02808e40 0x010>; 40 - interrupts = <57>; 41 - clock-frequency = <400000>; 42 - };

+78

Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/i2c/mellanox,i2c-mlxbf.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Mellanox I2C SMBus on BlueField SoCs 8 + 9 + maintainers: 10 + - Khalil Blaiech <kblaiech@nvidia.com> 11 + 12 + allOf: 13 + - $ref: /schemas/i2c/i2c-controller.yaml# 14 + 15 + properties: 16 + compatible: 17 + enum: 18 + - mellanox,i2c-mlxbf1 19 + - mellanox,i2c-mlxbf2 20 + 21 + reg: 22 + minItems: 3 23 + maxItems: 4 24 + items: 25 + - description: Smbus block registers 26 + - description: Cause master registers 27 + - description: Cause slave registers 28 + - description: Cause coalesce registers 29 + 30 + interrupts: 31 + maxItems: 1 32 + 33 + clock-frequency: 34 + enum: [ 100000, 400000, 1000000 ] 35 + description: 36 + bus frequency used to configure timing registers; 37 + The frequency is expressed in Hz. Default is 100000. 38 + 39 + required: 40 + - compatible 41 + - reg 42 + - interrupts 43 + 44 + unevaluatedProperties: false 45 + 46 + if: 47 + properties: 48 + compatible: 49 + contains: 50 + enum: 51 + - mellanox,i2c-mlxbf1 52 + 53 + then: 54 + properties: 55 + reg: 56 + maxItems: 3 57 + 58 + examples: 59 + - | 60 + i2c@2804000 { 61 + compatible = "mellanox,i2c-mlxbf1"; 62 + reg = <0x02804000 0x800>, 63 + <0x02801200 0x020>, 64 + <0x02801260 0x020>; 65 + interrupts = <57>; 66 + clock-frequency = <100000>; 67 + }; 68 + 69 + - | 70 + i2c@2808800 { 71 + compatible = "mellanox,i2c-mlxbf2"; 72 + reg = <0x02808800 0x600>, 73 + <0x02808e00 0x020>, 74 + <0x02808e20 0x020>, 75 + <0x02808e40 0x010>; 76 + interrupts = <57>; 77 + clock-frequency = <400000>; 78 + };

+2 -1

MAINTAINERS

··· 1502 1502 F: Documentation/devicetree/bindings/arm/actions.yaml 1503 1503 F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt 1504 1504 F: Documentation/devicetree/bindings/dma/owl-dma.yaml 1505 - F: Documentation/devicetree/bindings/i2c/i2c-owl.txt 1505 + F: Documentation/devicetree/bindings/i2c/i2c-owl.yaml 1506 1506 F: Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml 1507 1507 F: Documentation/devicetree/bindings/mmc/owl-mmc.yaml 1508 1508 F: Documentation/devicetree/bindings/pinctrl/actions,* ··· 11254 11254 M: Khalil Blaiech <kblaiech@nvidia.com> 11255 11255 L: linux-i2c@vger.kernel.org 11256 11256 S: Supported 11257 + F: Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml 11257 11258 F: drivers/i2c/busses/i2c-mlxbf.c 11258 11259 11259 11260 MELLANOX ETHERNET DRIVER (mlx4_en)

+1

drivers/i2c/busses/Kconfig

··· 675 675 config I2C_IMX 676 676 tristate "IMX I2C interface" 677 677 depends on ARCH_MXC || ARCH_LAYERSCAPE || COLDFIRE 678 + select I2C_SLAVE 678 679 help 679 680 Say Y here if you want to use the IIC bus controller on 680 681 the Freescale i.MX/MXC, Layerscape or ColdFire processors.

-1

drivers/i2c/busses/i2c-at91-master.c

··· 26 26 #include <linux/of_device.h> 27 27 #include <linux/pinctrl/consumer.h> 28 28 #include <linux/platform_device.h> 29 - #include <linux/platform_data/dma-atmel.h> 30 29 #include <linux/pm_runtime.h> 31 30 32 31 #include "i2c-at91.h"

-2

drivers/i2c/busses/i2c-at91.h

··· 18 18 #include <linux/dma-mapping.h> 19 19 #include <linux/dmaengine.h> 20 20 #include <linux/i2c.h> 21 - #include <linux/platform_data/dma-atmel.h> 22 21 #include <linux/platform_device.h> 23 22 24 23 #define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */ ··· 122 123 bool has_adv_dig_filtr; 123 124 bool has_ana_filtr; 124 125 bool has_clear_cmd; 125 - struct at_dma_slave dma_slave; 126 126 }; 127 127 128 128 struct at91_twi_dma {

+49 -49

drivers/i2c/busses/i2c-designware-core.h

··· 25 25 I2C_FUNC_SMBUS_BLOCK_DATA | \ 26 26 I2C_FUNC_SMBUS_I2C_BLOCK) 27 27 28 - #define DW_IC_CON_MASTER 0x1 29 - #define DW_IC_CON_SPEED_STD 0x2 30 - #define DW_IC_CON_SPEED_FAST 0x4 31 - #define DW_IC_CON_SPEED_HIGH 0x6 32 - #define DW_IC_CON_SPEED_MASK 0x6 33 - #define DW_IC_CON_10BITADDR_SLAVE 0x8 34 - #define DW_IC_CON_10BITADDR_MASTER 0x10 35 - #define DW_IC_CON_RESTART_EN 0x20 36 - #define DW_IC_CON_SLAVE_DISABLE 0x40 37 - #define DW_IC_CON_STOP_DET_IFADDRESSED 0x80 38 - #define DW_IC_CON_TX_EMPTY_CTRL 0x100 39 - #define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL 0x200 28 + #define DW_IC_CON_MASTER BIT(0) 29 + #define DW_IC_CON_SPEED_STD (1 << 1) 30 + #define DW_IC_CON_SPEED_FAST (2 << 1) 31 + #define DW_IC_CON_SPEED_HIGH (3 << 1) 32 + #define DW_IC_CON_SPEED_MASK GENMASK(2, 1) 33 + #define DW_IC_CON_10BITADDR_SLAVE BIT(3) 34 + #define DW_IC_CON_10BITADDR_MASTER BIT(4) 35 + #define DW_IC_CON_RESTART_EN BIT(5) 36 + #define DW_IC_CON_SLAVE_DISABLE BIT(6) 37 + #define DW_IC_CON_STOP_DET_IFADDRESSED BIT(7) 38 + #define DW_IC_CON_TX_EMPTY_CTRL BIT(8) 39 + #define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9) 40 40 41 41 /* 42 42 * Registers offset 43 43 */ 44 - #define DW_IC_CON 0x0 45 - #define DW_IC_TAR 0x4 46 - #define DW_IC_SAR 0x8 44 + #define DW_IC_CON 0x00 45 + #define DW_IC_TAR 0x04 46 + #define DW_IC_SAR 0x08 47 47 #define DW_IC_DATA_CMD 0x10 48 48 #define DW_IC_SS_SCL_HCNT 0x14 49 49 #define DW_IC_SS_SCL_LCNT 0x18 ··· 81 81 #define DW_IC_COMP_TYPE 0xfc 82 82 #define DW_IC_COMP_TYPE_VALUE 0x44570140 83 83 84 - #define DW_IC_INTR_RX_UNDER 0x001 85 - #define DW_IC_INTR_RX_OVER 0x002 86 - #define DW_IC_INTR_RX_FULL 0x004 87 - #define DW_IC_INTR_TX_OVER 0x008 88 - #define DW_IC_INTR_TX_EMPTY 0x010 89 - #define DW_IC_INTR_RD_REQ 0x020 90 - #define DW_IC_INTR_TX_ABRT 0x040 91 - #define DW_IC_INTR_RX_DONE 0x080 92 - #define DW_IC_INTR_ACTIVITY 0x100 93 - #define DW_IC_INTR_STOP_DET 0x200 94 - #define DW_IC_INTR_START_DET 0x400 95 - #define DW_IC_INTR_GEN_CALL 0x800 96 - #define DW_IC_INTR_RESTART_DET 0x1000 84 + #define DW_IC_INTR_RX_UNDER BIT(0) 85 + #define DW_IC_INTR_RX_OVER BIT(1) 86 + #define DW_IC_INTR_RX_FULL BIT(2) 87 + #define DW_IC_INTR_TX_OVER BIT(3) 88 + #define DW_IC_INTR_TX_EMPTY BIT(4) 89 + #define DW_IC_INTR_RD_REQ BIT(5) 90 + #define DW_IC_INTR_TX_ABRT BIT(6) 91 + #define DW_IC_INTR_RX_DONE BIT(7) 92 + #define DW_IC_INTR_ACTIVITY BIT(8) 93 + #define DW_IC_INTR_STOP_DET BIT(9) 94 + #define DW_IC_INTR_START_DET BIT(10) 95 + #define DW_IC_INTR_GEN_CALL BIT(11) 96 + #define DW_IC_INTR_RESTART_DET BIT(12) 97 97 98 98 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ 99 99 DW_IC_INTR_TX_ABRT | \ ··· 105 105 DW_IC_INTR_RX_UNDER | \ 106 106 DW_IC_INTR_RD_REQ) 107 107 108 - #define DW_IC_STATUS_ACTIVITY 0x1 108 + #define DW_IC_STATUS_ACTIVITY BIT(0) 109 109 #define DW_IC_STATUS_TFE BIT(2) 110 110 #define DW_IC_STATUS_MASTER_ACTIVITY BIT(5) 111 111 #define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6) 112 112 113 113 #define DW_IC_SDA_HOLD_RX_SHIFT 16 114 - #define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT) 114 + #define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, 16) 115 115 116 116 #define DW_IC_ERR_TX_ABRT 0x1 117 117 ··· 154 154 #define ABRT_SLAVE_ARBLOST 14 155 155 #define ABRT_SLAVE_RD_INTX 15 156 156 157 - #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) 158 - #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) 159 - #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) 160 - #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) 161 - #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) 162 - #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) 163 - #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) 164 - #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) 165 - #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) 166 - #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) 167 - #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) 168 - #define DW_IC_RX_ABRT_SLAVE_RD_INTX (1UL << ABRT_SLAVE_RD_INTX) 169 - #define DW_IC_RX_ABRT_SLAVE_ARBLOST (1UL << ABRT_SLAVE_ARBLOST) 170 - #define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO (1UL << ABRT_SLAVE_FLUSH_TXFIFO) 157 + #define DW_IC_TX_ABRT_7B_ADDR_NOACK BIT(ABRT_7B_ADDR_NOACK) 158 + #define DW_IC_TX_ABRT_10ADDR1_NOACK BIT(ABRT_10ADDR1_NOACK) 159 + #define DW_IC_TX_ABRT_10ADDR2_NOACK BIT(ABRT_10ADDR2_NOACK) 160 + #define DW_IC_TX_ABRT_TXDATA_NOACK BIT(ABRT_TXDATA_NOACK) 161 + #define DW_IC_TX_ABRT_GCALL_NOACK BIT(ABRT_GCALL_NOACK) 162 + #define DW_IC_TX_ABRT_GCALL_READ BIT(ABRT_GCALL_READ) 163 + #define DW_IC_TX_ABRT_SBYTE_ACKDET BIT(ABRT_SBYTE_ACKDET) 164 + #define DW_IC_TX_ABRT_SBYTE_NORSTRT BIT(ABRT_SBYTE_NORSTRT) 165 + #define DW_IC_TX_ABRT_10B_RD_NORSTRT BIT(ABRT_10B_RD_NORSTRT) 166 + #define DW_IC_TX_ABRT_MASTER_DIS BIT(ABRT_MASTER_DIS) 167 + #define DW_IC_TX_ARB_LOST BIT(ARB_LOST) 168 + #define DW_IC_RX_ABRT_SLAVE_RD_INTX BIT(ABRT_SLAVE_RD_INTX) 169 + #define DW_IC_RX_ABRT_SLAVE_ARBLOST BIT(ABRT_SLAVE_ARBLOST) 170 + #define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO BIT(ABRT_SLAVE_FLUSH_TXFIFO) 171 171 172 172 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ 173 173 DW_IC_TX_ABRT_10ADDR1_NOACK | \ ··· 288 288 bool suspended; 289 289 }; 290 290 291 - #define ACCESS_INTR_MASK 0x00000001 292 - #define ACCESS_NO_IRQ_SUSPEND 0x00000002 291 + #define ACCESS_INTR_MASK BIT(0) 292 + #define ACCESS_NO_IRQ_SUSPEND BIT(1) 293 293 294 - #define MODEL_MSCC_OCELOT 0x00000100 295 - #define MODEL_BAIKAL_BT1 0x00000200 296 - #define MODEL_MASK 0x00000f00 294 + #define MODEL_MSCC_OCELOT BIT(8) 295 + #define MODEL_BAIKAL_BT1 BIT(9) 296 + #define MODEL_MASK GENMASK(11, 8) 297 297 298 298 int i2c_dw_init_regmap(struct dw_i2c_dev *dev); 299 299 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset);

+1 -4

drivers/i2c/busses/i2c-exynos5.c

··· 778 778 init_completion(&i2c->msg_complete); 779 779 780 780 i2c->irq = ret = platform_get_irq(pdev, 0); 781 - if (ret <= 0) { 782 - dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n"); 783 - ret = -EINVAL; 781 + if (ret < 0) 784 782 goto err_clk; 785 - } 786 783 787 784 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq, 788 785 IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c);

+196 -43

drivers/i2c/busses/i2c-imx.c

··· 17 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 18 * 19 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 + * Copyright 2020 NXP 20 21 * 21 22 */ 22 23 ··· 74 73 #define IMX_I2C_I2SR 0x03 /* i2c status */ 75 74 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 76 75 76 + /* 77 + * All of the layerscape series SoCs support IBIC register. 78 + */ 79 + #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */ 80 + 77 81 #define IMX_I2C_REGSHIFT 2 78 82 #define VF610_I2C_REGSHIFT 0 79 83 ··· 97 91 #define I2CR_MSTA 0x20 98 92 #define I2CR_IIEN 0x40 99 93 #define I2CR_IEN 0x80 94 + #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */ 100 95 101 96 /* register bits different operating codes definition: 102 97 * 1) I2SR: Interrupt flags clear operation differ between SoCs: ··· 208 201 struct pinctrl_state *pinctrl_pins_gpio; 209 202 210 203 struct imx_i2c_dma *dma; 204 + struct i2c_client *slave; 211 205 }; 212 206 213 207 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { ··· 241 233 242 234 }; 243 235 244 - static const struct platform_device_id imx_i2c_devtype[] = { 245 - { 246 - .name = "imx1-i2c", 247 - .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 248 - }, { 249 - .name = "imx21-i2c", 250 - .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 251 - }, { 252 - /* sentinel */ 253 - } 254 - }; 255 - MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 256 - 257 236 static const struct of_device_id i2c_imx_dt_ids[] = { 258 237 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 259 238 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, ··· 260 265 return i2c_imx->hwdata->devtype == IMX1_I2C; 261 266 } 262 267 268 + static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx) 269 + { 270 + return i2c_imx->hwdata->devtype == VF610_I2C; 271 + } 272 + 263 273 static inline void imx_i2c_write_reg(unsigned int val, 264 274 struct imx_i2c_struct *i2c_imx, unsigned int reg) 265 275 { ··· 275 275 unsigned int reg) 276 276 { 277 277 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 278 + } 279 + 280 + static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) 281 + { 282 + unsigned int temp; 283 + 284 + /* 285 + * i2sr_clr_opcode is the value to clear all interrupts. Here we want to 286 + * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits> 287 + * toggled. This is required because i.MX needs W0C and Vybrid uses W1C. 288 + */ 289 + temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; 290 + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 291 + } 292 + 293 + /* Set up i2c controller register and i2c status register to default value. */ 294 + static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx) 295 + { 296 + imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 297 + i2c_imx, IMX_I2C_I2CR); 298 + i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 278 299 } 279 300 280 301 /* Functions for DMA support */ ··· 431 410 dma->chan_rx = NULL; 432 411 433 412 dma->chan_using = NULL; 434 - } 435 - 436 - static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) 437 - { 438 - unsigned int temp; 439 - 440 - /* 441 - * i2sr_clr_opcode is the value to clear all interrupts. Here we want to 442 - * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits> 443 - * toggled. This is required because i.MX needs W0C and Vybrid uses W1C. 444 - */ 445 - temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; 446 - imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 447 413 } 448 414 449 415 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic) ··· 646 638 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 647 639 } 648 640 641 + /* 642 + * Enable bus idle interrupts 643 + * Note: IBIC register will be cleared after disabled i2c module. 644 + * All of layerscape series SoCs support IBIC register. 645 + */ 646 + static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) 647 + { 648 + if (is_vf610_i2c(i2c_imx)) { 649 + unsigned int temp; 650 + 651 + temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC); 652 + temp |= IBIC_BIIE; 653 + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC); 654 + } 655 + } 656 + 657 + static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx, 658 + unsigned int status, unsigned int ctl) 659 + { 660 + u8 value; 661 + 662 + if (status & I2SR_IAL) { /* Arbitration lost */ 663 + i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 664 + if (!(status & I2SR_IAAS)) 665 + return IRQ_HANDLED; 666 + } 667 + 668 + if (status & I2SR_IAAS) { /* Addressed as a slave */ 669 + if (status & I2SR_SRW) { /* Master wants to read from us*/ 670 + dev_dbg(&i2c_imx->adapter.dev, "read requested"); 671 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_REQUESTED, &value); 672 + 673 + /* Slave transmit */ 674 + ctl |= I2CR_MTX; 675 + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 676 + 677 + /* Send data */ 678 + imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 679 + } else { /* Master wants to write to us */ 680 + dev_dbg(&i2c_imx->adapter.dev, "write requested"); 681 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 682 + 683 + /* Slave receive */ 684 + ctl &= ~I2CR_MTX; 685 + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 686 + /* Dummy read */ 687 + imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 688 + } 689 + } else if (!(ctl & I2CR_MTX)) { /* Receive mode */ 690 + if (status & I2SR_IBB) { /* No STOP signal detected */ 691 + value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 692 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 693 + } else { /* STOP signal is detected */ 694 + dev_dbg(&i2c_imx->adapter.dev, 695 + "STOP signal detected"); 696 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_STOP, &value); 697 + } 698 + } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */ 699 + ctl |= I2CR_MTX; 700 + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 701 + 702 + i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_PROCESSED, &value); 703 + 704 + imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 705 + } else { /* Transmit mode received NAK */ 706 + ctl &= ~I2CR_MTX; 707 + imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 708 + imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 709 + } 710 + 711 + return IRQ_HANDLED; 712 + } 713 + 714 + static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) 715 + { 716 + int temp; 717 + 718 + /* Set slave addr. */ 719 + imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR); 720 + 721 + i2c_imx_reset_regs(i2c_imx); 722 + 723 + /* Enable module */ 724 + temp = i2c_imx->hwdata->i2cr_ien_opcode; 725 + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 726 + 727 + /* Enable interrupt from i2c module */ 728 + temp |= I2CR_IIEN; 729 + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 730 + 731 + i2c_imx_enable_bus_idle(i2c_imx); 732 + } 733 + 734 + static int i2c_imx_reg_slave(struct i2c_client *client) 735 + { 736 + struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 737 + int ret; 738 + 739 + if (i2c_imx->slave) 740 + return -EBUSY; 741 + 742 + i2c_imx->slave = client; 743 + 744 + /* Resume */ 745 + ret = pm_runtime_get_sync(i2c_imx->adapter.dev.parent); 746 + if (ret < 0) { 747 + dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller"); 748 + return ret; 749 + } 750 + 751 + i2c_imx_slave_init(i2c_imx); 752 + 753 + return 0; 754 + } 755 + 756 + static int i2c_imx_unreg_slave(struct i2c_client *client) 757 + { 758 + struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 759 + int ret; 760 + 761 + if (!i2c_imx->slave) 762 + return -EINVAL; 763 + 764 + /* Reset slave address. */ 765 + imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 766 + 767 + i2c_imx_reset_regs(i2c_imx); 768 + 769 + i2c_imx->slave = NULL; 770 + 771 + /* Suspend */ 772 + ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent); 773 + if (ret < 0) 774 + dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller"); 775 + 776 + return ret; 777 + } 778 + 779 + static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status) 780 + { 781 + /* save status register */ 782 + i2c_imx->i2csr = status; 783 + wake_up(&i2c_imx->queue); 784 + 785 + return IRQ_HANDLED; 786 + } 787 + 649 788 static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 650 789 { 651 790 struct imx_i2c_struct *i2c_imx = dev_id; 652 - unsigned int temp; 791 + unsigned int ctl, status; 653 792 654 - temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 655 - if (temp & I2SR_IIF) { 656 - /* save status register */ 657 - i2c_imx->i2csr = temp; 793 + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 794 + ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 795 + if (status & I2SR_IIF) { 658 796 i2c_imx_clear_irq(i2c_imx, I2SR_IIF); 659 - wake_up(&i2c_imx->queue); 660 - return IRQ_HANDLED; 797 + if (i2c_imx->slave && !(ctl & I2CR_MSTA)) 798 + return i2c_imx_slave_isr(i2c_imx, status, ctl); 799 + return i2c_imx_master_isr(i2c_imx, status); 661 800 } 662 801 663 802 return IRQ_NONE; ··· 1182 1027 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 1183 1028 (result < 0) ? "error" : "success msg", 1184 1029 (result < 0) ? result : num); 1030 + /* After data is transferred, switch to slave mode(as a receiver) */ 1031 + if (i2c_imx->slave) 1032 + i2c_imx_slave_init(i2c_imx); 1033 + 1185 1034 return (result < 0) ? result : num; 1186 1035 } 1187 1036 ··· 1299 1140 .master_xfer = i2c_imx_xfer, 1300 1141 .master_xfer_atomic = i2c_imx_xfer_atomic, 1301 1142 .functionality = i2c_imx_func, 1143 + .reg_slave = i2c_imx_reg_slave, 1144 + .unreg_slave = i2c_imx_unreg_slave, 1302 1145 }; 1303 1146 1304 1147 static int i2c_imx_probe(struct platform_device *pdev) ··· 1330 1169 return -ENOMEM; 1331 1170 1332 1171 match = device_get_match_data(&pdev->dev); 1333 - if (match) 1334 - i2c_imx->hwdata = match; 1335 - else 1336 - i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1337 - platform_get_device_id(pdev)->driver_data; 1172 + i2c_imx->hwdata = match; 1338 1173 1339 1174 /* Setup i2c_imx driver structure */ 1340 1175 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); ··· 1390 1233 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1391 1234 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1392 1235 1393 - /* Set up chip registers to defaults */ 1394 - imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 1395 - i2c_imx, IMX_I2C_I2CR); 1396 - imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 1236 + i2c_imx_reset_regs(i2c_imx); 1397 1237 1398 1238 /* Init optional bus recovery function */ 1399 1239 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); ··· 1498 1344 .of_match_table = i2c_imx_dt_ids, 1499 1345 .acpi_match_table = i2c_imx_acpi_ids, 1500 1346 }, 1501 - .id_table = imx_i2c_devtype, 1502 1347 }; 1503 1348 1504 1349 static int __init i2c_adap_imx_init(void)

+17 -2

drivers/i2c/busses/i2c-ismt.c

··· 53 53 * Features supported by this driver: 54 54 * Hardware PEC yes 55 55 * Block buffer yes 56 - * Block process call transaction no 56 + * Block process call transaction yes 57 57 * Slave mode no 58 58 */ 59 59 ··· 332 332 333 333 if (desc->status & ISMT_DESC_SCS) { 334 334 if (read_write == I2C_SMBUS_WRITE && 335 - size != I2C_SMBUS_PROC_CALL) 335 + size != I2C_SMBUS_PROC_CALL && 336 + size != I2C_SMBUS_BLOCK_PROC_CALL) 336 337 return 0; 337 338 338 339 switch (size) { ··· 346 345 data->word = dma_buffer[0] | (dma_buffer[1] << 8); 347 346 break; 348 347 case I2C_SMBUS_BLOCK_DATA: 348 + case I2C_SMBUS_BLOCK_PROC_CALL: 349 349 if (desc->rxbytes != dma_buffer[0] + 1) 350 350 return -EMSGSIZE; 351 351 ··· 520 518 } 521 519 break; 522 520 521 + case I2C_SMBUS_BLOCK_PROC_CALL: 522 + dev_dbg(dev, "I2C_SMBUS_BLOCK_PROC_CALL\n"); 523 + dma_size = I2C_SMBUS_BLOCK_MAX; 524 + desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 1); 525 + desc->wr_len_cmd = data->block[0] + 1; 526 + desc->rd_len = dma_size; 527 + desc->control |= ISMT_DESC_BLK; 528 + dma_direction = DMA_BIDIRECTIONAL; 529 + dma_buffer[0] = command; 530 + memcpy(&dma_buffer[1], &data->block[1], data->block[0]); 531 + break; 532 + 523 533 case I2C_SMBUS_I2C_BLOCK_DATA: 524 534 /* Make sure the length is valid */ 525 535 if (data->block[0] < 1) ··· 638 624 I2C_FUNC_SMBUS_BYTE_DATA | 639 625 I2C_FUNC_SMBUS_WORD_DATA | 640 626 I2C_FUNC_SMBUS_PROC_CALL | 627 + I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 641 628 I2C_FUNC_SMBUS_BLOCK_DATA | 642 629 I2C_FUNC_SMBUS_I2C_BLOCK | 643 630 I2C_FUNC_SMBUS_PEC;

+28 -1

drivers/i2c/busses/i2c-mv64xxx.c

··· 17 17 #include <linux/interrupt.h> 18 18 #include <linux/mv643xx_i2c.h> 19 19 #include <linux/platform_device.h> 20 + #include <linux/pinctrl/consumer.h> 20 21 #include <linux/reset.h> 21 22 #include <linux/io.h> 22 23 #include <linux/of.h> ··· 148 147 bool irq_clear_inverted; 149 148 /* Clk div is 2 to the power n, not 2 to the power n + 1 */ 150 149 bool clk_n_base_0; 150 + struct i2c_bus_recovery_info rinfo; 151 151 }; 152 152 153 153 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = { ··· 327 325 drv_data->msg->flags); 328 326 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 329 327 mv64xxx_i2c_hw_init(drv_data); 330 - drv_data->rc = -EIO; 328 + i2c_recover_bus(&drv_data->adapter); 329 + drv_data->rc = -EAGAIN; 331 330 } 332 331 } 333 332 ··· 564 561 "time_left: %d\n", drv_data->block, 565 562 (int)time_left); 566 563 mv64xxx_i2c_hw_init(drv_data); 564 + i2c_recover_bus(&drv_data->adapter); 567 565 } 568 566 } else 569 567 spin_unlock_irqrestore(&drv_data->lock, flags); ··· 874 870 } 875 871 #endif /* CONFIG_OF */ 876 872 873 + static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data, 874 + struct device *dev) 875 + { 876 + struct i2c_bus_recovery_info *rinfo = &drv_data->rinfo; 877 + 878 + rinfo->pinctrl = devm_pinctrl_get(dev); 879 + if (IS_ERR(rinfo->pinctrl)) { 880 + if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER) 881 + return -EPROBE_DEFER; 882 + dev_info(dev, "can't get pinctrl, bus recovery not supported\n"); 883 + return PTR_ERR(rinfo->pinctrl); 884 + } else if (!rinfo->pinctrl) { 885 + return -ENODEV; 886 + } 887 + 888 + drv_data->adapter.bus_recovery_info = rinfo; 889 + return 0; 890 + } 891 + 877 892 static int 878 893 mv64xxx_i2c_probe(struct platform_device *pd) 879 894 { ··· 948 925 rc = drv_data->irq; 949 926 goto exit_reset; 950 927 } 928 + 929 + rc = mv64xxx_i2c_init_recovery_info(drv_data, &pd->dev); 930 + if (rc == -EPROBE_DEFER) 931 + goto exit_reset; 951 932 952 933 drv_data->adapter.dev.parent = &pd->dev; 953 934 drv_data->adapter.algo = &mv64xxx_i2c_algo;

+3 -19

drivers/i2c/busses/i2c-mxs.c

··· 781 781 return 0; 782 782 } 783 783 784 - static const struct platform_device_id mxs_i2c_devtype[] = { 785 - { 786 - .name = "imx23-i2c", 787 - .driver_data = MXS_I2C_V1, 788 - }, { 789 - .name = "imx28-i2c", 790 - .driver_data = MXS_I2C_V2, 791 - }, { /* sentinel */ } 792 - }; 793 - MODULE_DEVICE_TABLE(platform, mxs_i2c_devtype); 794 - 795 784 static const struct of_device_id mxs_i2c_dt_ids[] = { 796 - { .compatible = "fsl,imx23-i2c", .data = &mxs_i2c_devtype[0], }, 797 - { .compatible = "fsl,imx28-i2c", .data = &mxs_i2c_devtype[1], }, 785 + { .compatible = "fsl,imx23-i2c", .data = (void *)MXS_I2C_V1, }, 786 + { .compatible = "fsl,imx28-i2c", .data = (void *)MXS_I2C_V2, }, 798 787 { /* sentinel */ } 799 788 }; 800 789 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids); 801 790 802 791 static int mxs_i2c_probe(struct platform_device *pdev) 803 792 { 804 - const struct of_device_id *of_id = 805 - of_match_device(mxs_i2c_dt_ids, &pdev->dev); 806 793 struct device *dev = &pdev->dev; 807 794 struct mxs_i2c_dev *i2c; 808 795 struct i2c_adapter *adap; ··· 799 812 if (!i2c) 800 813 return -ENOMEM; 801 814 802 - if (of_id) { 803 - const struct platform_device_id *device_id = of_id->data; 804 - i2c->dev_type = device_id->driver_data; 805 - } 815 + i2c->dev_type = (enum mxs_i2c_devtype)of_device_get_match_data(&pdev->dev); 806 816 807 817 i2c->regs = devm_platform_ioremap_resource(pdev, 0); 808 818 if (IS_ERR(i2c->regs))

+1 -9

drivers/i2c/busses/i2c-nvidia-gpu.c

··· 353 353 pci_free_irq_vectors(pdev); 354 354 } 355 355 356 - /* 357 - * We need gpu_i2c_suspend() even if it is stub, for runtime pm to work 358 - * correctly. Without it, lspci shows runtime pm status as "D0" for the card. 359 - * Documentation/power/pci.rst also insists for driver to provide this. 360 - */ 361 - static __maybe_unused int gpu_i2c_suspend(struct device *dev) 362 - { 363 - return 0; 364 - } 356 + #define gpu_i2c_suspend NULL 365 357 366 358 static __maybe_unused int gpu_i2c_resume(struct device *dev) 367 359 {

+12 -13

drivers/i2c/busses/i2c-ocores.c

··· 83 83 84 84 #define TYPE_OCORES 0 85 85 #define TYPE_GRLIB 1 86 - #define TYPE_SIFIVE_REV0 2 87 86 88 87 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */ 89 88 ··· 475 476 }, 476 477 { 477 478 .compatible = "sifive,fu540-c000-i2c", 478 - .data = (void *)TYPE_SIFIVE_REV0, 479 479 }, 480 480 { 481 481 .compatible = "sifive,i2c0", 482 - .data = (void *)TYPE_SIFIVE_REV0, 483 482 }, 484 483 {}, 485 484 }; ··· 603 606 { 604 607 struct ocores_i2c *i2c; 605 608 struct ocores_i2c_platform_data *pdata; 606 - const struct of_device_id *match; 607 609 struct resource *res; 608 610 int irq; 609 611 int ret; ··· 682 686 683 687 init_waitqueue_head(&i2c->wait); 684 688 685 - irq = platform_get_irq(pdev, 0); 689 + irq = platform_get_irq_optional(pdev, 0); 690 + /* 691 + * Since the SoC does have an interrupt, its DT has an interrupt 692 + * property - But this should be bypassed as the IRQ logic in this 693 + * SoC is broken. 694 + */ 695 + if (of_device_is_compatible(pdev->dev.of_node, 696 + "sifive,fu540-c000-i2c")) { 697 + i2c->flags |= OCORES_FLAG_BROKEN_IRQ; 698 + irq = -ENXIO; 699 + } 700 + 686 701 if (irq == -ENXIO) { 687 702 ocores_algorithm.master_xfer = ocores_xfer_polling; 688 - 689 - /* 690 - * Set in OCORES_FLAG_BROKEN_IRQ to enable workaround for 691 - * FU540-C000 SoC in polling mode. 692 - */ 693 - match = of_match_node(ocores_i2c_match, pdev->dev.of_node); 694 - if (match && (long)match->data == TYPE_SIFIVE_REV0) 695 - i2c->flags |= OCORES_FLAG_BROKEN_IRQ; 696 703 } else { 697 704 if (irq < 0) 698 705 return irq;

+56 -19

drivers/i2c/busses/i2c-owl.c

··· 14 14 #include <linux/i2c.h> 15 15 #include <linux/interrupt.h> 16 16 #include <linux/io.h> 17 + #include <linux/iopoll.h> 17 18 #include <linux/module.h> 18 19 #include <linux/of_device.h> 19 20 ··· 77 76 #define OWL_I2C_FIFOCTL_TFR BIT(2) 78 77 79 78 /* I2Cc_FIFOSTAT Bit Mask */ 79 + #define OWL_I2C_FIFOSTAT_CECB BIT(0) 80 80 #define OWL_I2C_FIFOSTAT_RNB BIT(1) 81 81 #define OWL_I2C_FIFOSTAT_RFE BIT(2) 82 82 #define OWL_I2C_FIFOSTAT_TFF BIT(5) ··· 85 83 #define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8) 86 84 87 85 /* I2C bus timeout */ 88 - #define OWL_I2C_TIMEOUT msecs_to_jiffies(4 * 1000) 86 + #define OWL_I2C_TIMEOUT_MS (4 * 1000) 87 + #define OWL_I2C_TIMEOUT msecs_to_jiffies(OWL_I2C_TIMEOUT_MS) 89 88 90 89 #define OWL_I2C_MAX_RETRIES 50 91 90 ··· 164 161 writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV); 165 162 } 166 163 167 - static irqreturn_t owl_i2c_interrupt(int irq, void *_dev) 164 + static void owl_i2c_xfer_data(struct owl_i2c_dev *i2c_dev) 168 165 { 169 - struct owl_i2c_dev *i2c_dev = _dev; 170 166 struct i2c_msg *msg = i2c_dev->msg; 171 167 unsigned int stat, fifostat; 172 - 173 - spin_lock(&i2c_dev->lock); 174 168 175 169 i2c_dev->err = 0; 176 170 ··· 178 178 /* Clear NACK error bit by writing "1" */ 179 179 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOSTAT, 180 180 OWL_I2C_FIFOSTAT_RNB, true); 181 - goto stop; 181 + return; 182 182 } 183 183 184 184 /* Handle bus error */ ··· 188 188 /* Clear BUS error bit by writing "1" */ 189 189 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, 190 190 OWL_I2C_STAT_BEB, true); 191 - goto stop; 191 + return; 192 192 } 193 193 194 194 /* Handle FIFO read */ ··· 206 206 i2c_dev->base + OWL_I2C_REG_TXDAT); 207 207 } 208 208 } 209 + } 209 210 210 - stop: 211 + static irqreturn_t owl_i2c_interrupt(int irq, void *_dev) 212 + { 213 + struct owl_i2c_dev *i2c_dev = _dev; 214 + 215 + spin_lock(&i2c_dev->lock); 216 + 217 + owl_i2c_xfer_data(i2c_dev); 218 + 211 219 /* Clear pending interrupts */ 212 220 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, 213 221 OWL_I2C_STAT_IRQP, true); ··· 248 240 return 0; 249 241 } 250 242 251 - static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 252 - int num) 243 + static int owl_i2c_xfer_common(struct i2c_adapter *adap, struct i2c_msg *msgs, 244 + int num, bool atomic) 253 245 { 254 246 struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 255 247 struct i2c_msg *msg; ··· 293 285 goto err_exit; 294 286 } 295 287 296 - reinit_completion(&i2c_dev->msg_complete); 288 + if (!atomic) 289 + reinit_completion(&i2c_dev->msg_complete); 297 290 298 - /* Enable I2C controller interrupt */ 291 + /* Enable/disable I2C controller interrupt */ 299 292 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 300 - OWL_I2C_CTL_IRQE, true); 293 + OWL_I2C_CTL_IRQE, !atomic); 301 294 302 295 /* 303 296 * Select: FIFO enable, Master mode, Stop enable, Data count enable, ··· 366 357 367 358 spin_unlock_irqrestore(&i2c_dev->lock, flags); 368 359 369 - time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, 370 - adap->timeout); 360 + if (atomic) { 361 + /* Wait for Command Execute Completed or NACK Error bits */ 362 + ret = readl_poll_timeout_atomic(i2c_dev->base + OWL_I2C_REG_FIFOSTAT, 363 + val, val & (OWL_I2C_FIFOSTAT_CECB | 364 + OWL_I2C_FIFOSTAT_RNB), 365 + 10, OWL_I2C_TIMEOUT_MS * 1000); 366 + } else { 367 + time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, 368 + adap->timeout); 369 + if (!time_left) 370 + ret = -ETIMEDOUT; 371 + } 371 372 372 373 spin_lock_irqsave(&i2c_dev->lock, flags); 373 - if (time_left == 0) { 374 + 375 + if (ret) { 374 376 dev_err(&adap->dev, "Transaction timed out\n"); 375 377 /* Send stop condition and release the bus */ 376 378 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 377 379 OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, 378 380 true); 379 - ret = -ETIMEDOUT; 380 381 goto err_exit; 381 382 } 383 + 384 + if (atomic) 385 + owl_i2c_xfer_data(i2c_dev); 382 386 383 387 ret = i2c_dev->err < 0 ? i2c_dev->err : num; 384 388 ··· 406 384 return ret; 407 385 } 408 386 387 + static int owl_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 388 + int num) 389 + { 390 + return owl_i2c_xfer_common(adap, msgs, num, false); 391 + } 392 + 393 + static int owl_i2c_xfer_atomic(struct i2c_adapter *adap, 394 + struct i2c_msg *msgs, int num) 395 + { 396 + return owl_i2c_xfer_common(adap, msgs, num, true); 397 + } 398 + 409 399 static const struct i2c_algorithm owl_i2c_algorithm = { 410 - .master_xfer = owl_i2c_master_xfer, 411 - .functionality = owl_i2c_func, 400 + .master_xfer = owl_i2c_xfer, 401 + .master_xfer_atomic = owl_i2c_xfer_atomic, 402 + .functionality = owl_i2c_func, 412 403 }; 413 404 414 405 static const struct i2c_adapter_quirks owl_i2c_quirks = { ··· 508 473 } 509 474 510 475 static const struct of_device_id owl_i2c_of_match[] = { 476 + { .compatible = "actions,s500-i2c" }, 511 477 { .compatible = "actions,s700-i2c" }, 512 478 { .compatible = "actions,s900-i2c" }, 513 479 { /* sentinel */ } ··· 520 484 .driver = { 521 485 .name = "owl-i2c", 522 486 .of_match_table = of_match_ptr(owl_i2c_of_match), 487 + .probe_type = PROBE_PREFER_ASYNCHRONOUS, 523 488 }, 524 489 }; 525 490 module_platform_driver(owl_i2c_driver);

-4

drivers/i2c/busses/i2c-pca-platform.c

··· 33 33 wait_queue_head_t wait; 34 34 struct i2c_adapter adap; 35 35 struct i2c_algo_pca_data algo_data; 36 - unsigned long io_base; 37 - unsigned long io_size; 38 36 }; 39 37 40 38 /* Read/Write functions for different register alignments */ ··· 154 156 155 157 init_waitqueue_head(&i2c->wait); 156 158 157 - i2c->io_base = res->start; 158 - i2c->io_size = resource_size(res); 159 159 i2c->irq = irq; 160 160 161 161 i2c->adap.nr = pdev->id;

+8 -68

drivers/i2c/busses/i2c-pxa.c

··· 264 264 u32 hs_mask; 265 265 266 266 struct i2c_bus_recovery_info recovery; 267 - struct pinctrl *pinctrl; 268 - struct pinctrl_state *pinctrl_default; 269 - struct pinctrl_state *pinctrl_recovery; 270 267 }; 271 268 272 269 #define _IBMR(i2c) ((i2c)->reg_ibmr) ··· 1302 1305 */ 1303 1306 gpiod_set_value(i2c->recovery.scl_gpiod, ibmr & IBMR_SCLS); 1304 1307 gpiod_set_value(i2c->recovery.sda_gpiod, ibmr & IBMR_SDAS); 1305 - 1306 - WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery)); 1307 1308 } 1308 1309 1309 1310 static void i2c_pxa_unprepare_recovery(struct i2c_adapter *adap) 1310 1311 { 1311 1312 struct pxa_i2c *i2c = adap->algo_data; 1313 + struct i2c_bus_recovery_info *bri = adap->bus_recovery_info; 1312 1314 u32 isr; 1313 1315 1314 1316 /* ··· 1321 1325 i2c_pxa_do_reset(i2c); 1322 1326 } 1323 1327 1324 - WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default)); 1328 + WARN_ON(pinctrl_select_state(bri->pinctrl, bri->pins_default)); 1325 1329 1326 1330 dev_dbg(&i2c->adap.dev, "recovery: IBMR 0x%08x ISR 0x%08x\n", 1327 1331 readl(_IBMR(i2c)), readl(_ISR(i2c))); ··· 1343 1347 if (IS_ENABLED(CONFIG_I2C_PXA_SLAVE)) 1344 1348 return 0; 1345 1349 1346 - i2c->pinctrl = devm_pinctrl_get(dev); 1347 - if (PTR_ERR(i2c->pinctrl) == -ENODEV) 1348 - i2c->pinctrl = NULL; 1349 - if (IS_ERR(i2c->pinctrl)) 1350 - return PTR_ERR(i2c->pinctrl); 1351 - 1352 - if (!i2c->pinctrl) 1353 - return 0; 1354 - 1355 - i2c->pinctrl_default = pinctrl_lookup_state(i2c->pinctrl, 1356 - PINCTRL_STATE_DEFAULT); 1357 - i2c->pinctrl_recovery = pinctrl_lookup_state(i2c->pinctrl, "recovery"); 1358 - 1359 - if (IS_ERR(i2c->pinctrl_default) || IS_ERR(i2c->pinctrl_recovery)) { 1360 - dev_info(dev, "missing pinmux recovery information: %ld %ld\n", 1361 - PTR_ERR(i2c->pinctrl_default), 1362 - PTR_ERR(i2c->pinctrl_recovery)); 1350 + bri->pinctrl = devm_pinctrl_get(dev); 1351 + if (PTR_ERR(bri->pinctrl) == -ENODEV) { 1352 + bri->pinctrl = NULL; 1363 1353 return 0; 1364 1354 } 1365 - 1366 - /* 1367 - * Claiming GPIOs can influence the pinmux state, and may glitch the 1368 - * I2C bus. Do this carefully. 1369 - */ 1370 - bri->scl_gpiod = devm_gpiod_get(dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN); 1371 - if (bri->scl_gpiod == ERR_PTR(-EPROBE_DEFER)) 1372 - return -EPROBE_DEFER; 1373 - if (IS_ERR(bri->scl_gpiod)) { 1374 - dev_info(dev, "missing scl gpio recovery information: %pe\n", 1375 - bri->scl_gpiod); 1376 - return 0; 1377 - } 1378 - 1379 - /* 1380 - * We have SCL. Pull SCL low and wait a bit so that SDA glitches 1381 - * have no effect. 1382 - */ 1383 - gpiod_direction_output(bri->scl_gpiod, 0); 1384 - udelay(10); 1385 - bri->sda_gpiod = devm_gpiod_get(dev, "sda", GPIOD_OUT_HIGH_OPEN_DRAIN); 1386 - 1387 - /* Wait a bit in case of a SDA glitch, and then release SCL. */ 1388 - udelay(10); 1389 - gpiod_direction_output(bri->scl_gpiod, 1); 1390 - 1391 - if (bri->sda_gpiod == ERR_PTR(-EPROBE_DEFER)) 1392 - return -EPROBE_DEFER; 1393 - 1394 - if (IS_ERR(bri->sda_gpiod)) { 1395 - dev_info(dev, "missing sda gpio recovery information: %pe\n", 1396 - bri->sda_gpiod); 1397 - return 0; 1398 - } 1355 + if (IS_ERR(bri->pinctrl)) 1356 + return PTR_ERR(bri->pinctrl); 1399 1357 1400 1358 bri->prepare_recovery = i2c_pxa_prepare_recovery; 1401 1359 bri->unprepare_recovery = i2c_pxa_unprepare_recovery; 1402 - bri->recover_bus = i2c_generic_scl_recovery; 1403 1360 1404 1361 i2c->adap.bus_recovery_info = bri; 1405 1362 1406 - /* 1407 - * Claiming GPIOs can change the pinmux state, which confuses the 1408 - * pinctrl since pinctrl's idea of the current setting is unaffected 1409 - * by the pinmux change caused by claiming the GPIO. Work around that 1410 - * by switching pinctrl to the GPIO state here. We do it this way to 1411 - * avoid glitching the I2C bus. 1412 - */ 1413 - pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery); 1414 - 1415 - return pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default); 1363 + return 0; 1416 1364 } 1417 1365 1418 1366 static int i2c_pxa_probe(struct platform_device *dev)

+6 -12

drivers/i2c/busses/i2c-qcom-geni.c

··· 353 353 { 354 354 dma_addr_t rx_dma; 355 355 unsigned long time_left; 356 - void *dma_buf = NULL; 356 + void *dma_buf; 357 357 struct geni_se *se = &gi2c->se; 358 358 size_t len = msg->len; 359 359 360 - if (!of_machine_is_compatible("lenovo,yoga-c630")) 361 - dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 362 - 360 + dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 363 361 if (dma_buf) 364 362 geni_se_select_mode(se, GENI_SE_DMA); 365 363 else 366 364 geni_se_select_mode(se, GENI_SE_FIFO); 367 365 368 366 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN); 367 + geni_se_setup_m_cmd(se, I2C_READ, m_param); 369 368 370 369 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) { 371 370 geni_se_select_mode(se, GENI_SE_FIFO); 372 371 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 373 372 dma_buf = NULL; 374 373 } 375 - 376 - geni_se_setup_m_cmd(se, I2C_READ, m_param); 377 374 378 375 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 379 376 if (!time_left) ··· 392 395 { 393 396 dma_addr_t tx_dma; 394 397 unsigned long time_left; 395 - void *dma_buf = NULL; 398 + void *dma_buf; 396 399 struct geni_se *se = &gi2c->se; 397 400 size_t len = msg->len; 398 401 399 - if (!of_machine_is_compatible("lenovo,yoga-c630")) 400 - dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 401 - 402 + dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 402 403 if (dma_buf) 403 404 geni_se_select_mode(se, GENI_SE_DMA); 404 405 else 405 406 geni_se_select_mode(se, GENI_SE_FIFO); 406 407 407 408 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN); 409 + geni_se_setup_m_cmd(se, I2C_WRITE, m_param); 408 410 409 411 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) { 410 412 geni_se_select_mode(se, GENI_SE_FIFO); 411 413 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 412 414 dma_buf = NULL; 413 415 } 414 - 415 - geni_se_setup_m_cmd(se, I2C_WRITE, m_param); 416 416 417 417 if (!dma_buf) /* Get FIFO IRQ */ 418 418 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);

+28

drivers/i2c/busses/i2c-sh_mobile.c

··· 956 956 return 0; 957 957 } 958 958 959 + #ifdef CONFIG_PM_SLEEP 960 + static int sh_mobile_i2c_suspend(struct device *dev) 961 + { 962 + struct sh_mobile_i2c_data *pd = dev_get_drvdata(dev); 963 + 964 + i2c_mark_adapter_suspended(&pd->adap); 965 + return 0; 966 + } 967 + 968 + static int sh_mobile_i2c_resume(struct device *dev) 969 + { 970 + struct sh_mobile_i2c_data *pd = dev_get_drvdata(dev); 971 + 972 + i2c_mark_adapter_resumed(&pd->adap); 973 + return 0; 974 + } 975 + 976 + static const struct dev_pm_ops sh_mobile_i2c_pm_ops = { 977 + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_mobile_i2c_suspend, 978 + sh_mobile_i2c_resume) 979 + }; 980 + 981 + #define DEV_PM_OPS (&sh_mobile_i2c_pm_ops) 982 + #else 983 + #define DEV_PM_OPS NULL 984 + #endif /* CONFIG_PM_SLEEP */ 985 + 959 986 static struct platform_driver sh_mobile_i2c_driver = { 960 987 .driver = { 961 988 .name = "i2c-sh_mobile", 962 989 .of_match_table = sh_mobile_i2c_dt_ids, 990 + .pm = DEV_PM_OPS, 963 991 }, 964 992 .probe = sh_mobile_i2c_probe, 965 993 .remove = sh_mobile_i2c_remove,

+8 -6

drivers/i2c/i2c-core-base.c

··· 549 549 550 550 static int i2c_device_remove(struct device *dev) 551 551 { 552 - struct i2c_client *client = i2c_verify_client(dev); 552 + struct i2c_client *client = to_i2c_client(dev); 553 553 struct i2c_driver *driver; 554 - int status = 0; 555 - 556 - if (!client || !dev->driver) 557 - return 0; 558 554 559 555 driver = to_i2c_driver(dev->driver); 560 556 if (driver->remove) { 557 + int status; 558 + 561 559 dev_dbg(dev, "remove\n"); 560 + 562 561 status = driver->remove(client); 562 + if (status) 563 + dev_warn(dev, "remove failed (%pe), will be ignored\n", ERR_PTR(status)); 563 564 } 564 565 565 566 dev_pm_domain_detach(&client->dev, true); ··· 572 571 if (client->flags & I2C_CLIENT_HOST_NOTIFY) 573 572 pm_runtime_put(&client->adapter->dev); 574 573 575 - return status; 574 + /* return always 0 because there is WIP to make remove-functions void */ 575 + return 0; 576 576 } 577 577 578 578 static void i2c_device_shutdown(struct device *dev)

+41 -14

drivers/soc/qcom/qcom-geni-se.c

··· 266 266 static void geni_se_select_fifo_mode(struct geni_se *se) 267 267 { 268 268 u32 proto = geni_se_read_proto(se); 269 - u32 val; 269 + u32 val, val_old; 270 270 271 271 geni_se_irq_clear(se); 272 272 273 - val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 273 + /* 274 + * The RX path for the UART is asynchronous and so needs more 275 + * complex logic for enabling / disabling its interrupts. 276 + * 277 + * Specific notes: 278 + * - The done and TX-related interrupts are managed manually. 279 + * - We don't RX from the main sequencer (we use the secondary) so 280 + * we don't need the RX-related interrupts enabled in the main 281 + * sequencer for UART. 282 + */ 274 283 if (proto != GENI_SE_UART) { 284 + val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 275 285 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; 276 286 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; 277 - } 278 - writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 287 + if (val != val_old) 288 + writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 279 289 280 - val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 281 - if (proto != GENI_SE_UART) 290 + val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 282 291 val |= S_CMD_DONE_EN; 283 - writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 292 + if (val != val_old) 293 + writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 294 + } 284 295 285 - val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 296 + val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 286 297 val &= ~GENI_DMA_MODE_EN; 287 - writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 298 + if (val != val_old) 299 + writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 288 300 } 289 301 290 302 static void geni_se_select_dma_mode(struct geni_se *se) 291 303 { 292 - u32 val; 304 + u32 proto = geni_se_read_proto(se); 305 + u32 val, val_old; 293 306 294 307 geni_se_irq_clear(se); 295 308 296 - val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 309 + if (proto != GENI_SE_UART) { 310 + val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); 311 + val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); 312 + val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); 313 + if (val != val_old) 314 + writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); 315 + 316 + val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); 317 + val &= ~S_CMD_DONE_EN; 318 + if (val != val_old) 319 + writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); 320 + } 321 + 322 + val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); 297 323 val |= GENI_DMA_MODE_EN; 298 - writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 324 + if (val != val_old) 325 + writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); 299 326 } 300 327 301 328 /** ··· 678 651 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); 679 652 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); 680 653 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); 681 - writel_relaxed(len, se->base + SE_DMA_TX_LEN); 654 + writel(len, se->base + SE_DMA_TX_LEN); 682 655 return 0; 683 656 } 684 657 EXPORT_SYMBOL(geni_se_tx_dma_prep); ··· 715 688 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); 716 689 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ 717 690 writel_relaxed(0, se->base + SE_DMA_RX_ATTR); 718 - writel_relaxed(len, se->base + SE_DMA_RX_LEN); 691 + writel(len, se->base + SE_DMA_RX_LEN); 719 692 return 0; 720 693 } 721 694 EXPORT_SYMBOL(geni_se_rx_dma_prep);

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