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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: Add TCSR clock driver for Nord SoC
Add a clock driver for the TCSR clock controller found on Nord SoC,
which provides refclks for PCIE, USB, SGMII, UFS subsystems.
[Shawn:
- Use compatible qcom,nord-tcsrcc
- Drop include of <linux/of.h> as the driver doesn't use any OF APIs]
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260403-nord-clks-v1-4-018af14979fd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Taniya Das
and committed by
Bjorn Andersson
9d13c7bb
06498d59
+345
+7
drivers/clk/qcom/Kconfig
+7
drivers/clk/qcom/Kconfig
···
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Say Y if you want to use multimedia devices or peripheral
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devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
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+
config CLK_NORD_TCSRCC
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tristate "Nord TCSR Clock Controller"
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depends on ARM64 || COMPILE_TEST
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help
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Support for the TCSR clock controller on Nord devices.
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Say Y if you want to use peripheral devices such as PCIe, USB, UFS etc.
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config SA_CAMCC_8775P
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tristate "SA8775P Camera Clock Controller"
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depends on ARM64 || COMPILE_TEST
+1
drivers/clk/qcom/Makefile
+1
drivers/clk/qcom/Makefile
···
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obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o
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obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o
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obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o
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obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o
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obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o
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obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
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obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
+337
drivers/clk/qcom/tcsrcc-nord.c
+337
drivers/clk/qcom/tcsrcc-nord.c
···
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+
// SPDX-License-Identifier: GPL-2.0-only
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+
/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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+
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#include <linux/clk-provider.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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+
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#include <dt-bindings/clock/qcom,nord-tcsrcc.h>
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+
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "common.h"
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#include "reset.h"
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+
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enum {
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DT_BI_TCXO_PAD,
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};
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+
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static struct clk_branch tcsr_dp_rx_0_clkref_en = {
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.halt_reg = 0xa008,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0xa008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_dp_rx_0_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch tcsr_dp_rx_1_clkref_en = {
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.halt_reg = 0xb008,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0xb008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_dp_rx_1_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch tcsr_dp_tx_0_clkref_en = {
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.halt_reg = 0xc008,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0xc008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_dp_tx_0_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch tcsr_dp_tx_1_clkref_en = {
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.halt_reg = 0xd008,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0xd008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_dp_tx_1_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch tcsr_dp_tx_2_clkref_en = {
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.halt_reg = 0xe008,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0xe008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_dp_tx_2_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch tcsr_dp_tx_3_clkref_en = {
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.halt_reg = 0xf008,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0xf008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_dp_tx_3_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch tcsr_pcie_clkref_en = {
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.halt_reg = 0x8,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x8,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_pcie_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch tcsr_ufs_clkref_en = {
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.halt_reg = 0x3008,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x3008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_ufs_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch tcsr_usb2_0_clkref_en = {
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.halt_reg = 0x4008,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x4008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_usb2_0_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch tcsr_usb2_1_clkref_en = {
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.halt_reg = 0x5008,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x5008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_usb2_1_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch tcsr_usb2_2_clkref_en = {
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.halt_reg = 0x6008,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x6008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_usb2_2_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch tcsr_usb3_0_clkref_en = {
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.halt_reg = 0x8008,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x8008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_usb3_0_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch tcsr_usb3_1_clkref_en = {
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.halt_reg = 0x7008,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x7008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_usb3_1_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch tcsr_ux_sgmii_0_clkref_en = {
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.halt_reg = 0x1008,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_ux_sgmii_0_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_branch tcsr_ux_sgmii_1_clkref_en = {
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.halt_reg = 0x2008,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x2008,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "tcsr_ux_sgmii_1_clkref_en",
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.parent_data = &(const struct clk_parent_data){
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.index = DT_BI_TCXO_PAD,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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+
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static struct clk_regmap *tcsr_cc_nord_clocks[] = {
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[TCSR_DP_RX_0_CLKREF_EN] = &tcsr_dp_rx_0_clkref_en.clkr,
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[TCSR_DP_RX_1_CLKREF_EN] = &tcsr_dp_rx_1_clkref_en.clkr,
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[TCSR_DP_TX_0_CLKREF_EN] = &tcsr_dp_tx_0_clkref_en.clkr,
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[TCSR_DP_TX_1_CLKREF_EN] = &tcsr_dp_tx_1_clkref_en.clkr,
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[TCSR_DP_TX_2_CLKREF_EN] = &tcsr_dp_tx_2_clkref_en.clkr,
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[TCSR_DP_TX_3_CLKREF_EN] = &tcsr_dp_tx_3_clkref_en.clkr,
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[TCSR_PCIE_CLKREF_EN] = &tcsr_pcie_clkref_en.clkr,
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[TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
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[TCSR_USB2_0_CLKREF_EN] = &tcsr_usb2_0_clkref_en.clkr,
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[TCSR_USB2_1_CLKREF_EN] = &tcsr_usb2_1_clkref_en.clkr,
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[TCSR_USB2_2_CLKREF_EN] = &tcsr_usb2_2_clkref_en.clkr,
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[TCSR_USB3_0_CLKREF_EN] = &tcsr_usb3_0_clkref_en.clkr,
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[TCSR_USB3_1_CLKREF_EN] = &tcsr_usb3_1_clkref_en.clkr,
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[TCSR_UX_SGMII_0_CLKREF_EN] = &tcsr_ux_sgmii_0_clkref_en.clkr,
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[TCSR_UX_SGMII_1_CLKREF_EN] = &tcsr_ux_sgmii_1_clkref_en.clkr,
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};
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+
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static const struct regmap_config tcsr_cc_nord_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0xf008,
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.fast_io = true,
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};
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+
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static const struct qcom_cc_desc tcsr_cc_nord_desc = {
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.config = &tcsr_cc_nord_regmap_config,
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.clks = tcsr_cc_nord_clocks,
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.num_clks = ARRAY_SIZE(tcsr_cc_nord_clocks),
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};
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+
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static const struct of_device_id tcsr_cc_nord_match_table[] = {
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{ .compatible = "qcom,nord-tcsrcc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, tcsr_cc_nord_match_table);
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+
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static int tcsr_cc_nord_probe(struct platform_device *pdev)
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{
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return qcom_cc_probe(pdev, &tcsr_cc_nord_desc);
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}
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+
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static struct platform_driver tcsr_cc_nord_driver = {
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.probe = tcsr_cc_nord_probe,
328
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.driver = {
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.name = "tcsrcc-nord",
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.of_match_table = tcsr_cc_nord_match_table,
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},
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+
};
333
+
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module_platform_driver(tcsr_cc_nord_driver);
335
+
336
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MODULE_DESCRIPTION("QTI TCSRCC NORD Driver");
337
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MODULE_LICENSE("GPL");