tjh.dev / kernel
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clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe()

There are no more non-common calls in clk_mt7986_topckgen_probe():
migrate this driver to mtk_clk_simple_probe().

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230120092053.182923-24-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

AngeloGioacchino Del Regno and committed by
Stephen Boyd 9d8d1fe5 a0c3ef25

+13 -42
+13 -42
drivers/clk/mediatek/clk-mt7986-topckgen.c
··· 290 290 0x1C4, 5), 291 291 }; 292 292 293 - static int clk_mt7986_topckgen_probe(struct platform_device *pdev) 294 - { 295 - struct clk_hw_onecell_data *clk_data; 296 - struct device_node *node = pdev->dev.of_node; 297 - int r; 298 - void __iomem *base; 299 - int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + 300 - ARRAY_SIZE(top_muxes); 301 - 302 - base = of_iomap(node, 0); 303 - if (!base) { 304 - pr_err("%s(): ioremap failed\n", __func__); 305 - return -ENOMEM; 306 - } 307 - 308 - clk_data = mtk_alloc_clk_data(nr); 309 - if (!clk_data) 310 - return -ENOMEM; 311 - 312 - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), 313 - clk_data); 314 - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); 315 - mtk_clk_register_muxes(&pdev->dev, top_muxes, 316 - ARRAY_SIZE(top_muxes), node, 317 - &mt7986_clk_lock, clk_data); 318 - 319 - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 320 - 321 - if (r) { 322 - pr_err("%s(): could not register clock provider: %d\n", 323 - __func__, r); 324 - goto free_topckgen_data; 325 - } 326 - return r; 327 - 328 - free_topckgen_data: 329 - mtk_free_clk_data(clk_data); 330 - return r; 331 - } 293 + static const struct mtk_clk_desc topck_desc = { 294 + .fixed_clks = top_fixed_clks, 295 + .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 296 + .factor_clks = top_divs, 297 + .num_factor_clks = ARRAY_SIZE(top_divs), 298 + .mux_clks = top_muxes, 299 + .num_mux_clks = ARRAY_SIZE(top_muxes), 300 + .clk_lock = &mt7986_clk_lock, 301 + }; 332 302 333 303 static const struct of_device_id of_match_clk_mt7986_topckgen[] = { 334 - { .compatible = "mediatek,mt7986-topckgen", }, 335 - {} 304 + { .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc }, 305 + { /* sentinel */ } 336 306 }; 337 307 338 308 static struct platform_driver clk_mt7986_topckgen_drv = { 339 - .probe = clk_mt7986_topckgen_probe, 309 + .probe = mtk_clk_simple_probe, 310 + .remove = mtk_clk_simple_remove, 340 311 .driver = { 341 312 .name = "clk-mt7986-topckgen", 342 313 .of_match_table = of_match_clk_mt7986_topckgen,