tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: mediatek: clk-mt7986-topckgen: Properly keep some clocks enabled

Instead of calling clk_prepare_enable() on a bunch of clocks at probe
time, set the CLK_IS_CRITICAL flag to the same as these are required
to be always on, and this is the right way of achieving that.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-23-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

AngeloGioacchino Del Regno and committed by
Stephen Boyd a0c3ef25 72feb6f1

+24 -22
+24 -22
drivers/clk/mediatek/clk-mt7986-topckgen.c
··· 202 202 MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", 203 203 f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, 204 204 0x1C0, 10), 205 - MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 206 - 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), 205 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", 206 + f_26m_adc_parents, 0x020, 0x024, 0x028, 207 + 24, 1, 31, 0x1C0, 11, 208 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 207 209 /* CLK_CFG_3 */ 208 - MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", 209 - dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7, 210 - 0x1C0, 12), 211 - MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 212 - 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), 213 - MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 214 - 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14), 210 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", 211 + dramc_md32_parents, 0x030, 0x034, 0x038, 212 + 0, 1, 7, 0x1C0, 12, 213 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 214 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", 215 + sysaxi_parents, 0x030, 0x034, 0x038, 216 + 8, 2, 15, 0x1C0, 13, 217 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 218 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", 219 + sysapb_parents, 0x030, 0x034, 0x038, 220 + 16, 2, 23, 0x1C0, 14, 221 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 215 222 MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", 216 223 arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 217 224 31, 0x1C0, 15), ··· 241 234 MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", 242 235 sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, 243 236 0x1C0, 21), 244 - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", 245 - sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, 246 - 0x1C0, 22), 237 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", 238 + sgm_reg_parents, 0x050, 0x054, 0x058, 239 + 16, 1, 23, 0x1C0, 22, 240 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 247 241 MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 248 242 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), 249 243 /* CLK_CFG_6 */ ··· 260 252 f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, 261 253 0x1C0, 27), 262 254 /* CLK_CFG_7 */ 263 - MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel", 264 - f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7, 265 - 0x1C0, 28), 255 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", 256 + f_26m_adc_parents, 0x070, 0x074, 0x078, 257 + 0, 1, 7, 0x1C0, 28, 258 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 266 259 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 267 260 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), 268 261 MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", ··· 315 306 mtk_clk_register_muxes(&pdev->dev, top_muxes, 316 307 ARRAY_SIZE(top_muxes), node, 317 308 &mt7986_clk_lock, clk_data); 318 - 319 - clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk); 320 - clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk); 321 - clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk); 322 - clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk); 323 - clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk); 324 - clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk); 325 309 326 310 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 327 311