Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm-soc/for-6.4/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree changes
for 6.4, please pull the following:
- Rob fixes the GICv3 ITS node name for the Stingray platforms
- William adds the new-style High Speed SPI controller nodes to the BCA
SocS
- Rafal fixes the NAND controller interrupt name for BCM4908, LED
node(s) and procmon for BCM4908. He also adds support for the USB
ports, and declares USB triggered LEDs for the Netgear R8000P and
TP-Link C2300.
* tag 'arm-soc/for-6.4/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: bcmbca: bcm4908: add TP-Link C2300 USB LED triggers
arm64: dts: broadcom: bcmbca: bcm4908: add Netgear R8000P USB LED triggers
arm64: dts: broadcom: bcmbca: bcm4908: add on-SoC USB ports
arm64: dts: broadcom: bcmbca: bcm4908: fix procmon nodename
arm64: dts: broadcom: bcmbca: bcm4908: fix LED nodenames
arm64: dts: broadcom: bcmbca: bcm4908: fix NAND interrupt name
arm64: dts: broadcom: bcmbca: Add spi controller node
arm64: dts: broadcom: stringray: Fix GICv3 ITS node name
Link: https://lore.kernel.org/r/20230410232606.1917803-2-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+216
-9
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
···
58
58
function = "usb2";
59
59
color = <LED_COLOR_ID_WHITE>;
60
60
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
61
+
trigger-sources = <&ohci_port1>, <&ehci_port1>;
62
+
linux,default-trigger = "usbport";
61
63
};
62
64
63
65
led-usb3 {
64
66
function = "usb3";
65
67
color = <LED_COLOR_ID_WHITE>;
66
68
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
69
+
trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>;
70
+
linux,default-trigger = "usbport";
67
71
};
68
72
69
73
led-wifi {
+5
-1
arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
+5
-1
arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
···
64
64
function = "usb2";
65
65
color = <LED_COLOR_ID_BLUE>;
66
66
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
67
+
trigger-sources = <&ohci_port1>, <&ehci_port1>;
68
+
linux,default-trigger = "usbport";
67
69
};
68
70
69
71
led-usb3 {
70
-
function = "usbd3";
72
+
function = "usb3";
71
73
color = <LED_COLOR_ID_BLUE>;
72
74
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
75
+
trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>;
76
+
linux,default-trigger = "usbport";
73
77
};
74
78
75
79
led-brightness {
+5
-5
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
+5
-5
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
···
120
120
};
121
121
122
122
&leds {
123
-
led-power@11 {
123
+
led@11 {
124
124
reg = <0x11>;
125
125
function = LED_FUNCTION_POWER;
126
126
color = <LED_COLOR_ID_WHITE>;
···
130
130
pinctrl-0 = <&pins_led_17_a>;
131
131
};
132
132
133
-
led-wan-red@12 {
133
+
led@12 {
134
134
reg = <0x12>;
135
135
function = LED_FUNCTION_WAN;
136
136
color = <LED_COLOR_ID_RED>;
···
139
139
pinctrl-0 = <&pins_led_18_a>;
140
140
};
141
141
142
-
led-wps@14 {
142
+
led@14 {
143
143
reg = <0x14>;
144
144
function = LED_FUNCTION_WPS;
145
145
color = <LED_COLOR_ID_WHITE>;
···
148
148
pinctrl-0 = <&pins_led_20_a>;
149
149
};
150
150
151
-
led-wan-white@15 {
151
+
led@15 {
152
152
reg = <0x15>;
153
153
function = LED_FUNCTION_WAN;
154
154
color = <LED_COLOR_ID_WHITE>;
···
157
157
pinctrl-0 = <&pins_led_21_a>;
158
158
};
159
159
160
-
led-lan@19 {
160
+
led@19 {
161
161
reg = <0x19>;
162
162
function = LED_FUNCTION_LAN;
163
163
color = <LED_COLOR_ID_WHITE>;
+59
-2
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+59
-2
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
···
107
107
clock-frequency = <50000000>;
108
108
clock-output-names = "periph";
109
109
};
110
+
111
+
hsspi_pll: hsspi-pll {
112
+
compatible = "fixed-clock";
113
+
#clock-cells = <0>;
114
+
clock-frequency = <400000000>;
115
+
};
110
116
};
111
117
112
118
soc {
···
148
142
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
149
143
phys = <&usb_phy PHY_TYPE_USB2>;
150
144
status = "disabled";
145
+
146
+
#address-cells = <1>;
147
+
#size-cells = <0>;
148
+
149
+
ehci_port1: port@1 {
150
+
reg = <1>;
151
+
#trigger-source-cells = <0>;
152
+
};
153
+
154
+
ehci_port2: port@2 {
155
+
reg = <2>;
156
+
#trigger-source-cells = <0>;
157
+
};
151
158
};
152
159
153
160
ohci: usb@c400 {
···
169
150
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
170
151
phys = <&usb_phy PHY_TYPE_USB2>;
171
152
status = "disabled";
153
+
154
+
#address-cells = <1>;
155
+
#size-cells = <0>;
156
+
157
+
ohci_port1: port@1 {
158
+
reg = <1>;
159
+
#trigger-source-cells = <0>;
160
+
};
161
+
162
+
ohci_port2: port@2 {
163
+
reg = <2>;
164
+
#trigger-source-cells = <0>;
165
+
};
172
166
};
173
167
174
168
xhci: usb@d000 {
···
190
158
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
191
159
phys = <&usb_phy PHY_TYPE_USB3>;
192
160
status = "disabled";
161
+
162
+
#address-cells = <1>;
163
+
#size-cells = <0>;
164
+
165
+
xhci_port1: port@1 {
166
+
reg = <1>;
167
+
#trigger-source-cells = <0>;
168
+
};
169
+
170
+
xhci_port2: port@2 {
171
+
reg = <2>;
172
+
#trigger-source-cells = <0>;
173
+
};
193
174
};
194
175
195
176
bus@80000 {
···
299
254
};
300
255
};
301
256
302
-
procmon: syscon@280000 {
257
+
procmon: bus@280000 {
303
258
compatible = "simple-bus";
304
259
reg = <0x280000 0x1000>;
305
260
ranges;
···
576
531
#size-cells = <0>;
577
532
};
578
533
534
+
hsspi: spi@1000{
535
+
#address-cells = <1>;
536
+
#size-cells = <0>;
537
+
compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0";
538
+
reg = <0x1000 0x600>;
539
+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
540
+
clocks = <&hsspi_pll &hsspi_pll>;
541
+
clock-names = "hsspi", "pll";
542
+
num-cs = <8>;
543
+
status = "disabled";
544
+
};
545
+
579
546
nand-controller@1800 {
580
547
#address-cells = <1>;
581
548
#size-cells = <0>;
···
595
538
reg = <0x1800 0x600>, <0x2000 0x10>;
596
539
reg-names = "nand", "nand-int-base";
597
540
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
598
-
interrupt-names = "nand";
541
+
interrupt-names = "nand_ctlrdy";
599
542
status = "okay";
600
543
601
544
nandcs: nand@0 {
+20
arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
+20
arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
···
79
79
#clock-cells = <0>;
80
80
clock-frequency = <200000000>;
81
81
};
82
+
82
83
uart_clk: uart-clk {
83
84
compatible = "fixed-factor-clock";
84
85
#clock-cells = <0>;
85
86
clocks = <&periph_clk>;
86
87
clock-div = <4>;
87
88
clock-mult = <1>;
89
+
};
90
+
91
+
hsspi_pll: hsspi-pll {
92
+
compatible = "fixed-clock";
93
+
#clock-cells = <0>;
94
+
clock-frequency = <200000000>;
88
95
};
89
96
};
90
97
···
123
116
#address-cells = <1>;
124
117
#size-cells = <1>;
125
118
ranges = <0x0 0x0 0xff800000 0x800000>;
119
+
120
+
hsspi: spi@1000 {
121
+
#address-cells = <1>;
122
+
#size-cells = <0>;
123
+
compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1";
124
+
reg = <0x1000 0x600>, <0x2610 0x4>;
125
+
reg-names = "hsspi", "spim-ctrl";
126
+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
127
+
clocks = <&hsspi_pll &hsspi_pll>;
128
+
clock-names = "hsspi", "pll";
129
+
num-cs = <8>;
130
+
status = "disabled";
131
+
};
126
132
127
133
uart0: serial@12000 {
128
134
compatible = "arm,pl011", "arm,primecell";
+19
arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
+19
arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
···
60
60
#clock-cells = <0>;
61
61
clock-frequency = <200000000>;
62
62
};
63
+
63
64
uart_clk: uart-clk {
64
65
compatible = "fixed-factor-clock";
65
66
#clock-cells = <0>;
66
67
clocks = <&periph_clk>;
67
68
clock-div = <4>;
68
69
clock-mult = <1>;
70
+
};
71
+
72
+
hsspi_pll: hsspi-pll {
73
+
compatible = "fixed-clock";
74
+
#clock-cells = <0>;
75
+
clock-frequency = <200000000>;
69
76
};
70
77
};
71
78
···
105
98
#address-cells = <1>;
106
99
#size-cells = <1>;
107
100
ranges = <0x0 0x0 0xff800000 0x800000>;
101
+
102
+
hsspi: spi@1000 {
103
+
#address-cells = <1>;
104
+
#size-cells = <0>;
105
+
compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0";
106
+
reg = <0x1000 0x600>;
107
+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
108
+
clocks = <&hsspi_pll &hsspi_pll>;
109
+
clock-names = "hsspi", "pll";
110
+
num-cs = <8>;
111
+
status = "disabled";
112
+
};
108
113
109
114
uart0: serial@12000 {
110
115
compatible = "arm,pl011", "arm,primecell";
+19
arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
+19
arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
···
79
79
#clock-cells = <0>;
80
80
clock-frequency = <200000000>;
81
81
};
82
+
82
83
uart_clk: uart-clk {
83
84
compatible = "fixed-factor-clock";
84
85
#clock-cells = <0>;
85
86
clocks = <&periph_clk>;
86
87
clock-div = <4>;
87
88
clock-mult = <1>;
89
+
};
90
+
91
+
hsspi_pll: hsspi-pll {
92
+
compatible = "fixed-clock";
93
+
#clock-cells = <0>;
94
+
clock-frequency = <400000000>;
88
95
};
89
96
};
90
97
···
123
116
#address-cells = <1>;
124
117
#size-cells = <1>;
125
118
ranges = <0x0 0x0 0xff800000 0x800000>;
119
+
120
+
hsspi: spi@1000 {
121
+
#address-cells = <1>;
122
+
#size-cells = <0>;
123
+
compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0";
124
+
reg = <0x1000 0x600>;
125
+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
126
+
clocks = <&hsspi_pll &hsspi_pll>;
127
+
clock-names = "hsspi", "pll";
128
+
num-cs = <8>;
129
+
status = "disabled";
130
+
};
126
131
127
132
uart0: serial@12000 {
128
133
compatible = "arm,pl011", "arm,primecell";
+20
arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
+20
arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
···
79
79
#clock-cells = <0>;
80
80
clock-frequency = <200000000>;
81
81
};
82
+
82
83
uart_clk: uart-clk {
83
84
compatible = "fixed-factor-clock";
84
85
#clock-cells = <0>;
85
86
clocks = <&periph_clk>;
86
87
clock-div = <4>;
87
88
clock-mult = <1>;
89
+
};
90
+
91
+
hsspi_pll: hsspi-pll {
92
+
compatible = "fixed-clock";
93
+
#clock-cells = <0>;
94
+
clock-frequency = <200000000>;
88
95
};
89
96
};
90
97
···
123
116
#address-cells = <1>;
124
117
#size-cells = <1>;
125
118
ranges = <0x0 0x0 0xff800000 0x800000>;
119
+
120
+
hsspi: spi@1000 {
121
+
#address-cells = <1>;
122
+
#size-cells = <0>;
123
+
compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1";
124
+
reg = <0x1000 0x600>, <0x2610 0x4>;
125
+
reg-names = "hsspi", "spim-ctrl";
126
+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
127
+
clocks = <&hsspi_pll &hsspi_pll>;
128
+
clock-names = "hsspi", "pll";
129
+
num-cs = <8>;
130
+
status = "disabled";
131
+
};
126
132
127
133
uart0: serial@12000 {
128
134
compatible = "arm,pl011", "arm,primecell";
+18
arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
+18
arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
···
60
60
#clock-cells = <0>;
61
61
clock-frequency = <200000000>;
62
62
};
63
+
64
+
hsspi_pll: hsspi-pll {
65
+
compatible = "fixed-clock";
66
+
#clock-cells = <0>;
67
+
clock-frequency = <400000000>;
68
+
};
63
69
};
64
70
65
71
psci {
···
104
98
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
105
99
clocks = <&periph_clk>;
106
100
clock-names = "refclk";
101
+
status = "disabled";
102
+
};
103
+
104
+
hsspi: spi@1000 {
105
+
#address-cells = <1>;
106
+
#size-cells = <0>;
107
+
compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0";
108
+
reg = <0x1000 0x600>;
109
+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
110
+
clocks = <&hsspi_pll &hsspi_pll>;
111
+
clock-names = "hsspi", "pll";
112
+
num-cs = <8>;
107
113
status = "disabled";
108
114
};
109
115
};
+18
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+18
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
···
78
78
#clock-cells = <0>;
79
79
clock-frequency = <200000000>;
80
80
};
81
+
82
+
hsspi_pll: hsspi-pll {
83
+
compatible = "fixed-clock";
84
+
#clock-cells = <0>;
85
+
clock-frequency = <400000000>;
86
+
};
81
87
};
82
88
83
89
psci {
···
141
135
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
142
136
clocks = <&periph_clk>;
143
137
clock-names = "refclk";
138
+
status = "disabled";
139
+
};
140
+
141
+
hsspi: spi@1000 {
142
+
#address-cells = <1>;
143
+
#size-cells = <0>;
144
+
compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0";
145
+
reg = <0x1000 0x600>;
146
+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
147
+
clocks = <&hsspi_pll &hsspi_pll>;
148
+
clock-names = "hsspi", "pll";
149
+
num-cs = <8>;
144
150
status = "disabled";
145
151
};
146
152
};
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
+4
arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
+1
-1
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+1
-1
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi