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phy: qcom-qmp-pcie: add support for pipediv2 clock

Some QMP PHYs have a second fixed-divider pipe clock that needs to be
enabled along with the pipe clock.

Add support for an optional "pipediv2" clock.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221105145939.20318-15-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Johan Hovold and committed by
Vinod Koul 9e420f1e fffdeaf8

+15 -10
+15 -10
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
··· 1378 1378 void __iomem *tx2; 1379 1379 void __iomem *rx2; 1380 1380 1381 - struct clk *pipe_clk; 1382 1381 struct clk_bulk_data *clks; 1382 + struct clk_bulk_data pipe_clks[2]; 1383 + int num_pipe_clks; 1384 + 1383 1385 struct reset_control_bulk_data *resets; 1384 1386 struct regulator_bulk_data *vregs; 1385 1387 ··· 1925 1923 qmp_pcie_init_registers(qmp, &cfg->tbls); 1926 1924 qmp_pcie_init_registers(qmp, mode_tbls); 1927 1925 1928 - ret = clk_prepare_enable(qmp->pipe_clk); 1929 - if (ret) { 1930 - dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1926 + ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); 1927 + if (ret) 1931 1928 return ret; 1932 - } 1933 1929 1934 1930 /* Pull PHY out of reset state */ 1935 1931 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ··· 1950 1950 return 0; 1951 1951 1952 1952 err_disable_pipe_clk: 1953 - clk_disable_unprepare(qmp->pipe_clk); 1953 + clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 1954 1954 1955 1955 return ret; 1956 1956 } ··· 1960 1960 struct qmp_pcie *qmp = phy_get_drvdata(phy); 1961 1961 const struct qmp_phy_cfg *cfg = qmp->cfg; 1962 1962 1963 - clk_disable_unprepare(qmp->pipe_clk); 1963 + clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 1964 1964 1965 1965 /* PHY reset */ 1966 1966 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); ··· 2154 2154 struct platform_device *pdev = to_platform_device(qmp->dev); 2155 2155 const struct qmp_phy_cfg *cfg = qmp->cfg; 2156 2156 struct device *dev = qmp->dev; 2157 + struct clk *clk; 2157 2158 2158 2159 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2159 2160 if (IS_ERR(qmp->serdes)) ··· 2207 2206 } 2208 2207 } 2209 2208 2210 - qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2211 - if (IS_ERR(qmp->pipe_clk)) { 2212 - return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2209 + clk = devm_get_clk_from_child(dev, np, NULL); 2210 + if (IS_ERR(clk)) { 2211 + return dev_err_probe(dev, PTR_ERR(clk), 2213 2212 "failed to get pipe clock\n"); 2214 2213 } 2214 + 2215 + qmp->num_pipe_clks = 1; 2216 + qmp->pipe_clks[0].id = "pipe"; 2217 + qmp->pipe_clks[0].clk = clk; 2215 2218 2216 2219 return 0; 2217 2220 }