tjh.dev / kernel
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clk: qcom: Merge alt alpha plls for qcm2260, sm6115

The qcom2260 and sm6115 GCC drivers use a common modified DEFAULT and
BRAMMO alpha pll offsets. Move these common offsets to the shared place
to avoid duplication. The new layouts have a suffix EVO similar to LUCID
and RIVIAN.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220830075620.974009-4-iskren.chernev@gmail.com

authored by

Iskren Chernev and committed by
Bjorn Andersson 9e48f051 65f1fa35

+57 -82
+21
drivers/clk/qcom/clk-alpha-pll.c
··· 166 166 [PLL_OFF_TEST_CTL] = 0x28, 167 167 [PLL_OFF_TEST_CTL_U] = 0x2c, 168 168 }, 169 + [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = { 170 + [PLL_OFF_L_VAL] = 0x04, 171 + [PLL_OFF_ALPHA_VAL] = 0x08, 172 + [PLL_OFF_ALPHA_VAL_U] = 0x0c, 173 + [PLL_OFF_TEST_CTL] = 0x10, 174 + [PLL_OFF_TEST_CTL_U] = 0x14, 175 + [PLL_OFF_USER_CTL] = 0x18, 176 + [PLL_OFF_USER_CTL_U] = 0x1c, 177 + [PLL_OFF_CONFIG_CTL] = 0x20, 178 + [PLL_OFF_STATUS] = 0x24, 179 + }, 180 + [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = { 181 + [PLL_OFF_L_VAL] = 0x04, 182 + [PLL_OFF_ALPHA_VAL] = 0x08, 183 + [PLL_OFF_ALPHA_VAL_U] = 0x0c, 184 + [PLL_OFF_TEST_CTL] = 0x10, 185 + [PLL_OFF_TEST_CTL_U] = 0x14, 186 + [PLL_OFF_USER_CTL] = 0x18, 187 + [PLL_OFF_CONFIG_CTL] = 0x1C, 188 + [PLL_OFF_STATUS] = 0x20, 189 + }, 169 190 }; 170 191 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 171 192
+2
drivers/clk/qcom/clk-alpha-pll.h
··· 19 19 CLK_ALPHA_PLL_TYPE_ZONDA, 20 20 CLK_ALPHA_PLL_TYPE_LUCID_EVO, 21 21 CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, 22 + CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, 23 + CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, 22 24 CLK_ALPHA_PLL_TYPE_MAX, 23 25 }; 24 26
+16 -40
drivers/clk/qcom/gcc-qcm2290.c
··· 54 54 { 750000000, 1500000000, 1 }, 55 55 }; 56 56 57 - static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = { 58 - [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 59 - [PLL_OFF_L_VAL] = 0x04, 60 - [PLL_OFF_ALPHA_VAL] = 0x08, 61 - [PLL_OFF_ALPHA_VAL_U] = 0x0c, 62 - [PLL_OFF_TEST_CTL] = 0x10, 63 - [PLL_OFF_TEST_CTL_U] = 0x14, 64 - [PLL_OFF_USER_CTL] = 0x18, 65 - [PLL_OFF_USER_CTL_U] = 0x1C, 66 - [PLL_OFF_CONFIG_CTL] = 0x20, 67 - [PLL_OFF_STATUS] = 0x24, 68 - }, 69 - [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 70 - [PLL_OFF_L_VAL] = 0x04, 71 - [PLL_OFF_ALPHA_VAL] = 0x08, 72 - [PLL_OFF_ALPHA_VAL_U] = 0x0c, 73 - [PLL_OFF_TEST_CTL] = 0x10, 74 - [PLL_OFF_TEST_CTL_U] = 0x14, 75 - [PLL_OFF_USER_CTL] = 0x18, 76 - [PLL_OFF_CONFIG_CTL] = 0x1C, 77 - [PLL_OFF_STATUS] = 0x20, 78 - }, 79 - }; 80 - 81 57 static struct clk_alpha_pll gpll0 = { 82 58 .offset = 0x0, 83 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 59 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 84 60 .clkr = { 85 61 .enable_reg = 0x79000, 86 62 .enable_mask = BIT(0), ··· 82 106 .post_div_table = post_div_table_gpll0_out_aux2, 83 107 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2), 84 108 .width = 4, 85 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 109 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 86 110 .clkr.hw.init = &(struct clk_init_data){ 87 111 .name = "gpll0_out_aux2", 88 112 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, ··· 93 117 94 118 static struct clk_alpha_pll gpll1 = { 95 119 .offset = 0x1000, 96 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 120 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 97 121 .clkr = { 98 122 .enable_reg = 0x79000, 99 123 .enable_mask = BIT(1), ··· 123 147 .offset = 0xa000, 124 148 .vco_table = spark_vco, 125 149 .num_vco = ARRAY_SIZE(spark_vco), 126 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 150 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 127 151 .clkr = { 128 152 .enable_reg = 0x79000, 129 153 .enable_mask = BIT(10), ··· 155 179 .offset = 0xb000, 156 180 .vco_table = default_vco, 157 181 .num_vco = ARRAY_SIZE(default_vco), 158 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 182 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 159 183 .flags = SUPPORTS_DYNAMIC_UPDATE, 160 184 .clkr = { 161 185 .enable_reg = 0x79000, ··· 173 197 174 198 static struct clk_alpha_pll gpll3 = { 175 199 .offset = 0x3000, 176 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 200 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 177 201 .clkr = { 178 202 .enable_reg = 0x79000, 179 203 .enable_mask = BIT(3), ··· 199 223 .post_div_table = post_div_table_gpll3_out_main, 200 224 .num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_main), 201 225 .width = 4, 202 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 226 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 203 227 .clkr.hw.init = &(struct clk_init_data){ 204 228 .name = "gpll3_out_main", 205 229 .parent_hws = (const struct clk_hw *[]){ &gpll3.clkr.hw }, ··· 210 234 211 235 static struct clk_alpha_pll gpll4 = { 212 236 .offset = 0x4000, 213 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 237 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 214 238 .clkr = { 215 239 .enable_reg = 0x79000, 216 240 .enable_mask = BIT(4), ··· 227 251 228 252 static struct clk_alpha_pll gpll5 = { 229 253 .offset = 0x5000, 230 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 254 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 231 255 .clkr = { 232 256 .enable_reg = 0x79000, 233 257 .enable_mask = BIT(5), ··· 244 268 245 269 static struct clk_alpha_pll gpll6 = { 246 270 .offset = 0x6000, 247 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 271 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 248 272 .clkr = { 249 273 .enable_reg = 0x79000, 250 274 .enable_mask = BIT(6), ··· 270 294 .post_div_table = post_div_table_gpll6_out_main, 271 295 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main), 272 296 .width = 4, 273 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 297 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 274 298 .clkr.hw.init = &(struct clk_init_data){ 275 299 .name = "gpll6_out_main", 276 300 .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw }, ··· 281 305 282 306 static struct clk_alpha_pll gpll7 = { 283 307 .offset = 0x7000, 284 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 308 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 285 309 .clkr = { 286 310 .enable_reg = 0x79000, 287 311 .enable_mask = BIT(7), ··· 316 340 .offset = 0x8000, 317 341 .vco_table = default_vco, 318 342 .num_vco = ARRAY_SIZE(default_vco), 319 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 343 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 320 344 .flags = SUPPORTS_DYNAMIC_UPDATE, 321 345 .clkr = { 322 346 .enable_reg = 0x79000, ··· 343 367 .post_div_table = post_div_table_gpll8_out_main, 344 368 .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main), 345 369 .width = 4, 346 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 370 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 347 371 .clkr.hw.init = &(struct clk_init_data){ 348 372 .name = "gpll8_out_main", 349 373 .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw }, ··· 369 393 .offset = 0x9000, 370 394 .vco_table = brammo_vco, 371 395 .num_vco = ARRAY_SIZE(brammo_vco), 372 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO], 396 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], 373 397 .clkr = { 374 398 .enable_reg = 0x79000, 375 399 .enable_mask = BIT(9), ··· 395 419 .post_div_table = post_div_table_gpll9_out_main, 396 420 .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 397 421 .width = 2, 398 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO], 422 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], 399 423 .clkr.hw.init = &(struct clk_init_data){ 400 424 .name = "gpll9_out_main", 401 425 .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },
+18 -42
drivers/clk/qcom/gcc-sm6115.c
··· 53 53 { 750000000, 1500000000, 1 }, 54 54 }; 55 55 56 - static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = { 57 - [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 58 - [PLL_OFF_L_VAL] = 0x04, 59 - [PLL_OFF_ALPHA_VAL] = 0x08, 60 - [PLL_OFF_ALPHA_VAL_U] = 0x0c, 61 - [PLL_OFF_TEST_CTL] = 0x10, 62 - [PLL_OFF_TEST_CTL_U] = 0x14, 63 - [PLL_OFF_USER_CTL] = 0x18, 64 - [PLL_OFF_USER_CTL_U] = 0x1c, 65 - [PLL_OFF_CONFIG_CTL] = 0x20, 66 - [PLL_OFF_STATUS] = 0x24, 67 - }, 68 - [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 69 - [PLL_OFF_L_VAL] = 0x04, 70 - [PLL_OFF_ALPHA_VAL] = 0x08, 71 - [PLL_OFF_ALPHA_VAL_U] = 0x0c, 72 - [PLL_OFF_TEST_CTL] = 0x10, 73 - [PLL_OFF_TEST_CTL_U] = 0x14, 74 - [PLL_OFF_USER_CTL] = 0x18, 75 - [PLL_OFF_CONFIG_CTL] = 0x1C, 76 - [PLL_OFF_STATUS] = 0x20, 77 - }, 78 - }; 79 - 80 56 static struct clk_alpha_pll gpll0 = { 81 57 .offset = 0x0, 82 58 .vco_table = default_vco, 83 59 .num_vco = ARRAY_SIZE(default_vco), 84 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 60 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 85 61 .clkr = { 86 62 .enable_reg = 0x79000, 87 63 .enable_mask = BIT(0), ··· 83 107 .post_div_table = post_div_table_gpll0_out_aux2, 84 108 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2), 85 109 .width = 4, 86 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 110 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 87 111 .clkr.hw.init = &(struct clk_init_data){ 88 112 .name = "gpll0_out_aux2", 89 113 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, ··· 103 127 .post_div_table = post_div_table_gpll0_out_main, 104 128 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main), 105 129 .width = 4, 106 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 130 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 107 131 .clkr.hw.init = &(struct clk_init_data){ 108 132 .name = "gpll0_out_main", 109 133 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, ··· 125 149 .offset = 0xa000, 126 150 .vco_table = gpll10_vco, 127 151 .num_vco = ARRAY_SIZE(gpll10_vco), 128 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 152 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 129 153 .clkr = { 130 154 .enable_reg = 0x79000, 131 155 .enable_mask = BIT(10), ··· 151 175 .post_div_table = post_div_table_gpll10_out_main, 152 176 .num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main), 153 177 .width = 4, 154 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 178 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 155 179 .clkr.hw.init = &(struct clk_init_data){ 156 180 .name = "gpll10_out_main", 157 181 .parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw }, ··· 177 201 .vco_table = default_vco, 178 202 .num_vco = ARRAY_SIZE(default_vco), 179 203 .flags = SUPPORTS_DYNAMIC_UPDATE, 180 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 204 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 181 205 .clkr = { 182 206 .enable_reg = 0x79000, 183 207 .enable_mask = BIT(11), ··· 203 227 .post_div_table = post_div_table_gpll11_out_main, 204 228 .num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main), 205 229 .width = 4, 206 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 230 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 207 231 .clkr.hw.init = &(struct clk_init_data){ 208 232 .name = "gpll11_out_main", 209 233 .parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw }, ··· 217 241 .offset = 0x3000, 218 242 .vco_table = default_vco, 219 243 .num_vco = ARRAY_SIZE(default_vco), 220 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 244 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 221 245 .clkr = { 222 246 .enable_reg = 0x79000, 223 247 .enable_mask = BIT(3), ··· 236 260 .offset = 0x4000, 237 261 .vco_table = default_vco, 238 262 .num_vco = ARRAY_SIZE(default_vco), 239 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 263 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 240 264 .clkr = { 241 265 .enable_reg = 0x79000, 242 266 .enable_mask = BIT(4), ··· 262 286 .post_div_table = post_div_table_gpll4_out_main, 263 287 .num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main), 264 288 .width = 4, 265 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 289 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 266 290 .clkr.hw.init = &(struct clk_init_data){ 267 291 .name = "gpll4_out_main", 268 292 .parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw }, ··· 275 299 .offset = 0x6000, 276 300 .vco_table = default_vco, 277 301 .num_vco = ARRAY_SIZE(default_vco), 278 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 302 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 279 303 .clkr = { 280 304 .enable_reg = 0x79000, 281 305 .enable_mask = BIT(6), ··· 301 325 .post_div_table = post_div_table_gpll6_out_main, 302 326 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main), 303 327 .width = 4, 304 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 328 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 305 329 .clkr.hw.init = &(struct clk_init_data){ 306 330 .name = "gpll6_out_main", 307 331 .parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw }, ··· 314 338 .offset = 0x7000, 315 339 .vco_table = default_vco, 316 340 .num_vco = ARRAY_SIZE(default_vco), 317 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 341 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 318 342 .clkr = { 319 343 .enable_reg = 0x79000, 320 344 .enable_mask = BIT(7), ··· 340 364 .post_div_table = post_div_table_gpll7_out_main, 341 365 .num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main), 342 366 .width = 4, 343 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 367 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 344 368 .clkr.hw.init = &(struct clk_init_data){ 345 369 .name = "gpll7_out_main", 346 370 .parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw }, ··· 368 392 .offset = 0x8000, 369 393 .vco_table = default_vco, 370 394 .num_vco = ARRAY_SIZE(default_vco), 371 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 395 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 372 396 .flags = SUPPORTS_DYNAMIC_UPDATE, 373 397 .clkr = { 374 398 .enable_reg = 0x79000, ··· 395 419 .post_div_table = post_div_table_gpll8_out_main, 396 420 .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main), 397 421 .width = 4, 398 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], 422 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO], 399 423 .clkr.hw.init = &(struct clk_init_data){ 400 424 .name = "gpll8_out_main", 401 425 .parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw }, ··· 419 443 .offset = 0x9000, 420 444 .vco_table = gpll9_vco, 421 445 .num_vco = ARRAY_SIZE(gpll9_vco), 422 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO], 446 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], 423 447 .clkr = { 424 448 .enable_reg = 0x79000, 425 449 .enable_mask = BIT(9), ··· 445 469 .post_div_table = post_div_table_gpll9_out_main, 446 470 .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), 447 471 .width = 2, 448 - .regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_BRAMMO], 472 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO], 449 473 .clkr.hw.init = &(struct clk_init_data){ 450 474 .name = "gpll9_out_main", 451 475 .parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },