Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
interconnect: qcom: sm8350: Retire DEFINE_QNODE
The struct definition macros are hard to read and compare, expand them.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-9-c03aaeffc769@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
authored by
Konrad Dybcio
and committed by
Georgi Djakov
9e62ccde
aaf7d02f
+1338
-150
+1338
-150
drivers/interconnect/qcom/sm8350.c
+1338
-150
drivers/interconnect/qcom/sm8350.c
···
15
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#include "icc-rpmh.h"
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#include "sm8350.h"
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DEFINE_QNODE(qhm_qspi, SM8350_MASTER_QSPI_0, 1, 4, SM8350_SLAVE_A1NOC_SNOC);
19
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DEFINE_QNODE(qhm_qup0, SM8350_MASTER_QUP_0, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
20
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DEFINE_QNODE(qhm_qup1, SM8350_MASTER_QUP_1, 1, 4, SM8350_SLAVE_A1NOC_SNOC);
21
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DEFINE_QNODE(qhm_qup2, SM8350_MASTER_QUP_2, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
22
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DEFINE_QNODE(qnm_a1noc_cfg, SM8350_MASTER_A1NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A1NOC);
23
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DEFINE_QNODE(xm_sdc4, SM8350_MASTER_SDCC_4, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
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DEFINE_QNODE(xm_ufs_mem, SM8350_MASTER_UFS_MEM, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
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DEFINE_QNODE(xm_usb3_0, SM8350_MASTER_USB3_0, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
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DEFINE_QNODE(xm_usb3_1, SM8350_MASTER_USB3_1, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
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DEFINE_QNODE(qhm_qdss_bam, SM8350_MASTER_QDSS_BAM, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
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DEFINE_QNODE(qnm_a2noc_cfg, SM8350_MASTER_A2NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A2NOC);
29
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DEFINE_QNODE(qxm_crypto, SM8350_MASTER_CRYPTO, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
30
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DEFINE_QNODE(qxm_ipa, SM8350_MASTER_IPA, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
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DEFINE_QNODE(xm_pcie3_0, SM8350_MASTER_PCIE_0, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC);
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DEFINE_QNODE(xm_pcie3_1, SM8350_MASTER_PCIE_1, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC);
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DEFINE_QNODE(xm_qdss_etr, SM8350_MASTER_QDSS_ETR, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
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DEFINE_QNODE(xm_sdc2, SM8350_MASTER_SDCC_2, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
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DEFINE_QNODE(xm_ufs_card, SM8350_MASTER_UFS_CARD, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
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DEFINE_QNODE(qnm_gemnoc_cnoc, SM8350_MASTER_GEM_NOC_CNOC, 1, 16, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU);
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DEFINE_QNODE(qnm_gemnoc_pcie, SM8350_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8350_SLAVE_PCIE_0, SM8350_SLAVE_PCIE_1);
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DEFINE_QNODE(xm_qdss_dap, SM8350_MASTER_QDSS_DAP, 1, 8, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU);
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DEFINE_QNODE(qnm_cnoc_dc_noc, SM8350_MASTER_CNOC_DC_NOC, 1, 4, SM8350_SLAVE_LLCC_CFG, SM8350_SLAVE_GEM_NOC_CFG);
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DEFINE_QNODE(alm_gpu_tcu, SM8350_MASTER_GPU_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
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DEFINE_QNODE(alm_sys_tcu, SM8350_MASTER_SYS_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
42
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DEFINE_QNODE(chm_apps, SM8350_MASTER_APPSS_PROC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC);
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DEFINE_QNODE(qnm_cmpnoc, SM8350_MASTER_COMPUTE_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
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DEFINE_QNODE(qnm_gemnoc_cfg, SM8350_MASTER_GEM_NOC_CFG, 1, 4, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, SM8350_SLAVE_MCDMA_MS_MPU_CFG, SM8350_SLAVE_SERVICE_GEM_NOC_1, SM8350_SLAVE_SERVICE_GEM_NOC_2, SM8350_SLAVE_SERVICE_GEM_NOC);
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DEFINE_QNODE(qnm_gpu, SM8350_MASTER_GFX3D, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
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DEFINE_QNODE(qnm_mnoc_hf, SM8350_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8350_SLAVE_LLCC);
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DEFINE_QNODE(qnm_mnoc_sf, SM8350_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
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DEFINE_QNODE(qnm_pcie, SM8350_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
49
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DEFINE_QNODE(qnm_snoc_gc, SM8350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8350_SLAVE_LLCC);
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DEFINE_QNODE(qnm_snoc_sf, SM8350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC);
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DEFINE_QNODE(qhm_config_noc, SM8350_MASTER_CNOC_LPASS_AG_NOC, 1, 4, SM8350_SLAVE_LPASS_CORE_CFG, SM8350_SLAVE_LPASS_LPI_CFG, SM8350_SLAVE_LPASS_MPU_CFG, SM8350_SLAVE_LPASS_TOP_CFG, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, SM8350_SLAVE_SERVICE_LPASS_AG_NOC);
52
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DEFINE_QNODE(llcc_mc, SM8350_MASTER_LLCC, 4, 4, SM8350_SLAVE_EBI1);
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DEFINE_QNODE(qnm_camnoc_hf, SM8350_MASTER_CAMNOC_HF, 2, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
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DEFINE_QNODE(qnm_camnoc_icp, SM8350_MASTER_CAMNOC_ICP, 1, 8, SM8350_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qnm_camnoc_sf, SM8350_MASTER_CAMNOC_SF, 2, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qnm_mnoc_cfg, SM8350_MASTER_CNOC_MNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_MNOC);
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DEFINE_QNODE(qnm_video0, SM8350_MASTER_VIDEO_P0, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qnm_video1, SM8350_MASTER_VIDEO_P1, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qnm_video_cvp, SM8350_MASTER_VIDEO_PROC, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qxm_mdp0, SM8350_MASTER_MDP0, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
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DEFINE_QNODE(qxm_mdp1, SM8350_MASTER_MDP1, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
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DEFINE_QNODE(qxm_rot, SM8350_MASTER_ROTATOR, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qhm_nsp_noc_config, SM8350_MASTER_CDSP_NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_NSP_NOC);
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DEFINE_QNODE(qxm_nsp, SM8350_MASTER_CDSP_PROC, 2, 32, SM8350_SLAVE_CDSP_MEM_NOC);
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DEFINE_QNODE(qnm_aggre1_noc, SM8350_MASTER_A1NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF);
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DEFINE_QNODE(qnm_aggre2_noc, SM8350_MASTER_A2NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF);
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DEFINE_QNODE(qnm_snoc_cfg, SM8350_MASTER_SNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_SNOC);
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DEFINE_QNODE(qxm_pimem, SM8350_MASTER_PIMEM, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC);
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DEFINE_QNODE(xm_gic, SM8350_MASTER_GIC, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC);
70
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DEFINE_QNODE(qnm_mnoc_hf_disp, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP);
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DEFINE_QNODE(qnm_mnoc_sf_disp, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP);
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DEFINE_QNODE(llcc_mc_disp, SM8350_MASTER_LLCC_DISP, 4, 4, SM8350_SLAVE_EBI1_DISP);
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DEFINE_QNODE(qxm_mdp0_disp, SM8350_MASTER_MDP0_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP);
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DEFINE_QNODE(qxm_mdp1_disp, SM8350_MASTER_MDP1_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP);
75
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DEFINE_QNODE(qxm_rot_disp, SM8350_MASTER_ROTATOR_DISP, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP);
76
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DEFINE_QNODE(qns_a1noc_snoc, SM8350_SLAVE_A1NOC_SNOC, 1, 16, SM8350_MASTER_A1NOC_SNOC);
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DEFINE_QNODE(srvc_aggre1_noc, SM8350_SLAVE_SERVICE_A1NOC, 1, 4);
78
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DEFINE_QNODE(qns_a2noc_snoc, SM8350_SLAVE_A2NOC_SNOC, 1, 16, SM8350_MASTER_A2NOC_SNOC);
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DEFINE_QNODE(qns_pcie_mem_noc, SM8350_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_MASTER_ANOC_PCIE_GEM_NOC);
80
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DEFINE_QNODE(srvc_aggre2_noc, SM8350_SLAVE_SERVICE_A2NOC, 1, 4);
81
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DEFINE_QNODE(qhs_ahb2phy0, SM8350_SLAVE_AHB2PHY_SOUTH, 1, 4);
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DEFINE_QNODE(qhs_ahb2phy1, SM8350_SLAVE_AHB2PHY_NORTH, 1, 4);
83
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DEFINE_QNODE(qhs_aoss, SM8350_SLAVE_AOSS, 1, 4);
84
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DEFINE_QNODE(qhs_apss, SM8350_SLAVE_APPSS, 1, 8);
85
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DEFINE_QNODE(qhs_camera_cfg, SM8350_SLAVE_CAMERA_CFG, 1, 4);
86
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DEFINE_QNODE(qhs_clk_ctl, SM8350_SLAVE_CLK_CTL, 1, 4);
87
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DEFINE_QNODE(qhs_compute_cfg, SM8350_SLAVE_CDSP_CFG, 1, 4);
88
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DEFINE_QNODE(qhs_cpr_cx, SM8350_SLAVE_RBCPR_CX_CFG, 1, 4);
89
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DEFINE_QNODE(qhs_cpr_mmcx, SM8350_SLAVE_RBCPR_MMCX_CFG, 1, 4);
90
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DEFINE_QNODE(qhs_cpr_mx, SM8350_SLAVE_RBCPR_MX_CFG, 1, 4);
91
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DEFINE_QNODE(qhs_crypto0_cfg, SM8350_SLAVE_CRYPTO_0_CFG, 1, 4);
92
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DEFINE_QNODE(qhs_cx_rdpm, SM8350_SLAVE_CX_RDPM, 1, 4);
93
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DEFINE_QNODE(qhs_dcc_cfg, SM8350_SLAVE_DCC_CFG, 1, 4);
94
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DEFINE_QNODE(qhs_display_cfg, SM8350_SLAVE_DISPLAY_CFG, 1, 4);
95
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DEFINE_QNODE(qhs_gpuss_cfg, SM8350_SLAVE_GFX3D_CFG, 1, 8);
96
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DEFINE_QNODE(qhs_hwkm, SM8350_SLAVE_HWKM, 1, 4);
97
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DEFINE_QNODE(qhs_imem_cfg, SM8350_SLAVE_IMEM_CFG, 1, 4);
98
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DEFINE_QNODE(qhs_ipa, SM8350_SLAVE_IPA_CFG, 1, 4);
99
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DEFINE_QNODE(qhs_ipc_router, SM8350_SLAVE_IPC_ROUTER_CFG, 1, 4);
100
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DEFINE_QNODE(qhs_lpass_cfg, SM8350_SLAVE_LPASS, 1, 4, SM8350_MASTER_CNOC_LPASS_AG_NOC);
101
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DEFINE_QNODE(qhs_mss_cfg, SM8350_SLAVE_CNOC_MSS, 1, 4);
102
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DEFINE_QNODE(qhs_mx_rdpm, SM8350_SLAVE_MX_RDPM, 1, 4);
103
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DEFINE_QNODE(qhs_pcie0_cfg, SM8350_SLAVE_PCIE_0_CFG, 1, 4);
104
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DEFINE_QNODE(qhs_pcie1_cfg, SM8350_SLAVE_PCIE_1_CFG, 1, 4);
105
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DEFINE_QNODE(qhs_pdm, SM8350_SLAVE_PDM, 1, 4);
106
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DEFINE_QNODE(qhs_pimem_cfg, SM8350_SLAVE_PIMEM_CFG, 1, 4);
107
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DEFINE_QNODE(qhs_pka_wrapper_cfg, SM8350_SLAVE_PKA_WRAPPER_CFG, 1, 4);
108
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DEFINE_QNODE(qhs_pmu_wrapper_cfg, SM8350_SLAVE_PMU_WRAPPER_CFG, 1, 4);
109
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DEFINE_QNODE(qhs_qdss_cfg, SM8350_SLAVE_QDSS_CFG, 1, 4);
110
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DEFINE_QNODE(qhs_qspi, SM8350_SLAVE_QSPI_0, 1, 4);
111
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DEFINE_QNODE(qhs_qup0, SM8350_SLAVE_QUP_0, 1, 4);
112
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DEFINE_QNODE(qhs_qup1, SM8350_SLAVE_QUP_1, 1, 4);
113
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DEFINE_QNODE(qhs_qup2, SM8350_SLAVE_QUP_2, 1, 4);
114
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DEFINE_QNODE(qhs_sdc2, SM8350_SLAVE_SDCC_2, 1, 4);
115
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DEFINE_QNODE(qhs_sdc4, SM8350_SLAVE_SDCC_4, 1, 4);
116
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DEFINE_QNODE(qhs_security, SM8350_SLAVE_SECURITY, 1, 4);
117
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DEFINE_QNODE(qhs_spss_cfg, SM8350_SLAVE_SPSS_CFG, 1, 4);
118
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DEFINE_QNODE(qhs_tcsr, SM8350_SLAVE_TCSR, 1, 4);
119
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DEFINE_QNODE(qhs_tlmm, SM8350_SLAVE_TLMM, 1, 4);
120
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DEFINE_QNODE(qhs_ufs_card_cfg, SM8350_SLAVE_UFS_CARD_CFG, 1, 4);
121
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DEFINE_QNODE(qhs_ufs_mem_cfg, SM8350_SLAVE_UFS_MEM_CFG, 1, 4);
122
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DEFINE_QNODE(qhs_usb3_0, SM8350_SLAVE_USB3_0, 1, 4);
123
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DEFINE_QNODE(qhs_usb3_1, SM8350_SLAVE_USB3_1, 1, 4);
124
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DEFINE_QNODE(qhs_venus_cfg, SM8350_SLAVE_VENUS_CFG, 1, 4);
125
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DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8350_SLAVE_VSENSE_CTRL_CFG, 1, 4);
126
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DEFINE_QNODE(qns_a1_noc_cfg, SM8350_SLAVE_A1NOC_CFG, 1, 4);
127
-
DEFINE_QNODE(qns_a2_noc_cfg, SM8350_SLAVE_A2NOC_CFG, 1, 4);
128
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DEFINE_QNODE(qns_ddrss_cfg, SM8350_SLAVE_DDRSS_CFG, 1, 4);
129
-
DEFINE_QNODE(qns_mnoc_cfg, SM8350_SLAVE_CNOC_MNOC_CFG, 1, 4);
130
-
DEFINE_QNODE(qns_snoc_cfg, SM8350_SLAVE_SNOC_CFG, 1, 4);
131
-
DEFINE_QNODE(qxs_boot_imem, SM8350_SLAVE_BOOT_IMEM, 1, 8);
132
-
DEFINE_QNODE(qxs_imem, SM8350_SLAVE_IMEM, 1, 8);
133
-
DEFINE_QNODE(qxs_pimem, SM8350_SLAVE_PIMEM, 1, 8);
134
-
DEFINE_QNODE(srvc_cnoc, SM8350_SLAVE_SERVICE_CNOC, 1, 4);
135
-
DEFINE_QNODE(xs_pcie_0, SM8350_SLAVE_PCIE_0, 1, 8);
136
-
DEFINE_QNODE(xs_pcie_1, SM8350_SLAVE_PCIE_1, 1, 8);
137
-
DEFINE_QNODE(xs_qdss_stm, SM8350_SLAVE_QDSS_STM, 1, 4);
138
-
DEFINE_QNODE(xs_sys_tcu_cfg, SM8350_SLAVE_TCU, 1, 8);
139
-
DEFINE_QNODE(qhs_llcc, SM8350_SLAVE_LLCC_CFG, 1, 4);
140
-
DEFINE_QNODE(qns_gemnoc, SM8350_SLAVE_GEM_NOC_CFG, 1, 4);
141
-
DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
142
-
DEFINE_QNODE(qhs_modem_ms_mpu_cfg, SM8350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4);
143
-
DEFINE_QNODE(qns_gem_noc_cnoc, SM8350_SLAVE_GEM_NOC_CNOC, 1, 16, SM8350_MASTER_GEM_NOC_CNOC);
144
-
DEFINE_QNODE(qns_llcc, SM8350_SLAVE_LLCC, 4, 16, SM8350_MASTER_LLCC);
145
-
DEFINE_QNODE(qns_pcie, SM8350_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8);
146
-
DEFINE_QNODE(srvc_even_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
147
-
DEFINE_QNODE(srvc_odd_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
148
-
DEFINE_QNODE(srvc_sys_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC, 1, 4);
149
-
DEFINE_QNODE(qhs_lpass_core, SM8350_SLAVE_LPASS_CORE_CFG, 1, 4);
150
-
DEFINE_QNODE(qhs_lpass_lpi, SM8350_SLAVE_LPASS_LPI_CFG, 1, 4);
151
-
DEFINE_QNODE(qhs_lpass_mpu, SM8350_SLAVE_LPASS_MPU_CFG, 1, 4);
152
-
DEFINE_QNODE(qhs_lpass_top, SM8350_SLAVE_LPASS_TOP_CFG, 1, 4);
153
-
DEFINE_QNODE(srvc_niu_aml_noc, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, 1, 4);
154
-
DEFINE_QNODE(srvc_niu_lpass_agnoc, SM8350_SLAVE_SERVICE_LPASS_AG_NOC, 1, 4);
155
-
DEFINE_QNODE(ebi, SM8350_SLAVE_EBI1, 4, 4);
156
-
DEFINE_QNODE(qns_mem_noc_hf, SM8350_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC);
157
-
DEFINE_QNODE(qns_mem_noc_sf, SM8350_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC);
158
-
DEFINE_QNODE(srvc_mnoc, SM8350_SLAVE_SERVICE_MNOC, 1, 4);
159
-
DEFINE_QNODE(qns_nsp_gemnoc, SM8350_SLAVE_CDSP_MEM_NOC, 2, 32, SM8350_MASTER_COMPUTE_NOC);
160
-
DEFINE_QNODE(service_nsp_noc, SM8350_SLAVE_SERVICE_NSP_NOC, 1, 4);
161
-
DEFINE_QNODE(qns_gemnoc_gc, SM8350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8350_MASTER_SNOC_GC_MEM_NOC);
162
-
DEFINE_QNODE(qns_gemnoc_sf, SM8350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8350_MASTER_SNOC_SF_MEM_NOC);
163
-
DEFINE_QNODE(srvc_snoc, SM8350_SLAVE_SERVICE_SNOC, 1, 4);
164
-
DEFINE_QNODE(qns_llcc_disp, SM8350_SLAVE_LLCC_DISP, 4, 16, SM8350_MASTER_LLCC_DISP);
165
-
DEFINE_QNODE(ebi_disp, SM8350_SLAVE_EBI1_DISP, 4, 4);
166
-
DEFINE_QNODE(qns_mem_noc_hf_disp, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP);
167
-
DEFINE_QNODE(qns_mem_noc_sf_disp, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP);
18
+
static struct qcom_icc_node qhm_qspi = {
19
+
.name = "qhm_qspi",
20
+
.id = SM8350_MASTER_QSPI_0,
21
+
.channels = 1,
22
+
.buswidth = 4,
23
+
.num_links = 1,
24
+
.links = { SM8350_SLAVE_A1NOC_SNOC },
25
+
};
26
+
27
+
static struct qcom_icc_node qhm_qup0 = {
28
+
.name = "qhm_qup0",
29
+
.id = SM8350_MASTER_QUP_0,
30
+
.channels = 1,
31
+
.buswidth = 4,
32
+
.num_links = 1,
33
+
.links = { SM8350_SLAVE_A2NOC_SNOC },
34
+
};
35
+
36
+
static struct qcom_icc_node qhm_qup1 = {
37
+
.name = "qhm_qup1",
38
+
.id = SM8350_MASTER_QUP_1,
39
+
.channels = 1,
40
+
.buswidth = 4,
41
+
.num_links = 1,
42
+
.links = { SM8350_SLAVE_A1NOC_SNOC },
43
+
};
44
+
45
+
static struct qcom_icc_node qhm_qup2 = {
46
+
.name = "qhm_qup2",
47
+
.id = SM8350_MASTER_QUP_2,
48
+
.channels = 1,
49
+
.buswidth = 4,
50
+
.num_links = 1,
51
+
.links = { SM8350_SLAVE_A2NOC_SNOC },
52
+
};
53
+
54
+
static struct qcom_icc_node qnm_a1noc_cfg = {
55
+
.name = "qnm_a1noc_cfg",
56
+
.id = SM8350_MASTER_A1NOC_CFG,
57
+
.channels = 1,
58
+
.buswidth = 4,
59
+
.num_links = 1,
60
+
.links = { SM8350_SLAVE_SERVICE_A1NOC },
61
+
};
62
+
63
+
static struct qcom_icc_node xm_sdc4 = {
64
+
.name = "xm_sdc4",
65
+
.id = SM8350_MASTER_SDCC_4,
66
+
.channels = 1,
67
+
.buswidth = 8,
68
+
.num_links = 1,
69
+
.links = { SM8350_SLAVE_A1NOC_SNOC },
70
+
};
71
+
72
+
static struct qcom_icc_node xm_ufs_mem = {
73
+
.name = "xm_ufs_mem",
74
+
.id = SM8350_MASTER_UFS_MEM,
75
+
.channels = 1,
76
+
.buswidth = 8,
77
+
.num_links = 1,
78
+
.links = { SM8350_SLAVE_A1NOC_SNOC },
79
+
};
80
+
81
+
static struct qcom_icc_node xm_usb3_0 = {
82
+
.name = "xm_usb3_0",
83
+
.id = SM8350_MASTER_USB3_0,
84
+
.channels = 1,
85
+
.buswidth = 8,
86
+
.num_links = 1,
87
+
.links = { SM8350_SLAVE_A1NOC_SNOC },
88
+
};
89
+
90
+
static struct qcom_icc_node xm_usb3_1 = {
91
+
.name = "xm_usb3_1",
92
+
.id = SM8350_MASTER_USB3_1,
93
+
.channels = 1,
94
+
.buswidth = 8,
95
+
.num_links = 1,
96
+
.links = { SM8350_SLAVE_A1NOC_SNOC },
97
+
};
98
+
99
+
static struct qcom_icc_node qhm_qdss_bam = {
100
+
.name = "qhm_qdss_bam",
101
+
.id = SM8350_MASTER_QDSS_BAM,
102
+
.channels = 1,
103
+
.buswidth = 4,
104
+
.num_links = 1,
105
+
.links = { SM8350_SLAVE_A2NOC_SNOC },
106
+
};
107
+
108
+
static struct qcom_icc_node qnm_a2noc_cfg = {
109
+
.name = "qnm_a2noc_cfg",
110
+
.id = SM8350_MASTER_A2NOC_CFG,
111
+
.channels = 1,
112
+
.buswidth = 4,
113
+
.num_links = 1,
114
+
.links = { SM8350_SLAVE_SERVICE_A2NOC },
115
+
};
116
+
117
+
static struct qcom_icc_node qxm_crypto = {
118
+
.name = "qxm_crypto",
119
+
.id = SM8350_MASTER_CRYPTO,
120
+
.channels = 1,
121
+
.buswidth = 8,
122
+
.num_links = 1,
123
+
.links = { SM8350_SLAVE_A2NOC_SNOC },
124
+
};
125
+
126
+
static struct qcom_icc_node qxm_ipa = {
127
+
.name = "qxm_ipa",
128
+
.id = SM8350_MASTER_IPA,
129
+
.channels = 1,
130
+
.buswidth = 8,
131
+
.num_links = 1,
132
+
.links = { SM8350_SLAVE_A2NOC_SNOC },
133
+
};
134
+
135
+
static struct qcom_icc_node xm_pcie3_0 = {
136
+
.name = "xm_pcie3_0",
137
+
.id = SM8350_MASTER_PCIE_0,
138
+
.channels = 1,
139
+
.buswidth = 8,
140
+
.num_links = 1,
141
+
.links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC },
142
+
};
143
+
144
+
static struct qcom_icc_node xm_pcie3_1 = {
145
+
.name = "xm_pcie3_1",
146
+
.id = SM8350_MASTER_PCIE_1,
147
+
.channels = 1,
148
+
.buswidth = 8,
149
+
.num_links = 1,
150
+
.links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC },
151
+
};
152
+
153
+
static struct qcom_icc_node xm_qdss_etr = {
154
+
.name = "xm_qdss_etr",
155
+
.id = SM8350_MASTER_QDSS_ETR,
156
+
.channels = 1,
157
+
.buswidth = 8,
158
+
.num_links = 1,
159
+
.links = { SM8350_SLAVE_A2NOC_SNOC },
160
+
};
161
+
162
+
static struct qcom_icc_node xm_sdc2 = {
163
+
.name = "xm_sdc2",
164
+
.id = SM8350_MASTER_SDCC_2,
165
+
.channels = 1,
166
+
.buswidth = 8,
167
+
.num_links = 1,
168
+
.links = { SM8350_SLAVE_A2NOC_SNOC },
169
+
};
170
+
171
+
static struct qcom_icc_node xm_ufs_card = {
172
+
.name = "xm_ufs_card",
173
+
.id = SM8350_MASTER_UFS_CARD,
174
+
.channels = 1,
175
+
.buswidth = 8,
176
+
.num_links = 1,
177
+
.links = { SM8350_SLAVE_A2NOC_SNOC },
178
+
};
179
+
180
+
static struct qcom_icc_node qnm_gemnoc_cnoc = {
181
+
.name = "qnm_gemnoc_cnoc",
182
+
.id = SM8350_MASTER_GEM_NOC_CNOC,
183
+
.channels = 1,
184
+
.buswidth = 16,
185
+
.num_links = 56,
186
+
.links = { SM8350_SLAVE_AHB2PHY_SOUTH,
187
+
SM8350_SLAVE_AHB2PHY_NORTH,
188
+
SM8350_SLAVE_AOSS,
189
+
SM8350_SLAVE_APPSS,
190
+
SM8350_SLAVE_CAMERA_CFG,
191
+
SM8350_SLAVE_CLK_CTL,
192
+
SM8350_SLAVE_CDSP_CFG,
193
+
SM8350_SLAVE_RBCPR_CX_CFG,
194
+
SM8350_SLAVE_RBCPR_MMCX_CFG,
195
+
SM8350_SLAVE_RBCPR_MX_CFG,
196
+
SM8350_SLAVE_CRYPTO_0_CFG,
197
+
SM8350_SLAVE_CX_RDPM,
198
+
SM8350_SLAVE_DCC_CFG,
199
+
SM8350_SLAVE_DISPLAY_CFG,
200
+
SM8350_SLAVE_GFX3D_CFG,
201
+
SM8350_SLAVE_HWKM,
202
+
SM8350_SLAVE_IMEM_CFG,
203
+
SM8350_SLAVE_IPA_CFG,
204
+
SM8350_SLAVE_IPC_ROUTER_CFG,
205
+
SM8350_SLAVE_LPASS,
206
+
SM8350_SLAVE_CNOC_MSS,
207
+
SM8350_SLAVE_MX_RDPM,
208
+
SM8350_SLAVE_PCIE_0_CFG,
209
+
SM8350_SLAVE_PCIE_1_CFG,
210
+
SM8350_SLAVE_PDM,
211
+
SM8350_SLAVE_PIMEM_CFG,
212
+
SM8350_SLAVE_PKA_WRAPPER_CFG,
213
+
SM8350_SLAVE_PMU_WRAPPER_CFG,
214
+
SM8350_SLAVE_QDSS_CFG,
215
+
SM8350_SLAVE_QSPI_0,
216
+
SM8350_SLAVE_QUP_0,
217
+
SM8350_SLAVE_QUP_1,
218
+
SM8350_SLAVE_QUP_2,
219
+
SM8350_SLAVE_SDCC_2,
220
+
SM8350_SLAVE_SDCC_4,
221
+
SM8350_SLAVE_SECURITY,
222
+
SM8350_SLAVE_SPSS_CFG,
223
+
SM8350_SLAVE_TCSR,
224
+
SM8350_SLAVE_TLMM,
225
+
SM8350_SLAVE_UFS_CARD_CFG,
226
+
SM8350_SLAVE_UFS_MEM_CFG,
227
+
SM8350_SLAVE_USB3_0,
228
+
SM8350_SLAVE_USB3_1,
229
+
SM8350_SLAVE_VENUS_CFG,
230
+
SM8350_SLAVE_VSENSE_CTRL_CFG,
231
+
SM8350_SLAVE_A1NOC_CFG,
232
+
SM8350_SLAVE_A2NOC_CFG,
233
+
SM8350_SLAVE_DDRSS_CFG,
234
+
SM8350_SLAVE_CNOC_MNOC_CFG,
235
+
SM8350_SLAVE_SNOC_CFG,
236
+
SM8350_SLAVE_BOOT_IMEM,
237
+
SM8350_SLAVE_IMEM,
238
+
SM8350_SLAVE_PIMEM,
239
+
SM8350_SLAVE_SERVICE_CNOC,
240
+
SM8350_SLAVE_QDSS_STM,
241
+
SM8350_SLAVE_TCU
242
+
},
243
+
};
244
+
245
+
static struct qcom_icc_node qnm_gemnoc_pcie = {
246
+
.name = "qnm_gemnoc_pcie",
247
+
.id = SM8350_MASTER_GEM_NOC_PCIE_SNOC,
248
+
.channels = 1,
249
+
.buswidth = 8,
250
+
.num_links = 2,
251
+
.links = { SM8350_SLAVE_PCIE_0,
252
+
SM8350_SLAVE_PCIE_1
253
+
},
254
+
};
255
+
256
+
static struct qcom_icc_node xm_qdss_dap = {
257
+
.name = "xm_qdss_dap",
258
+
.id = SM8350_MASTER_QDSS_DAP,
259
+
.channels = 1,
260
+
.buswidth = 8,
261
+
.num_links = 56,
262
+
.links = { SM8350_SLAVE_AHB2PHY_SOUTH,
263
+
SM8350_SLAVE_AHB2PHY_NORTH,
264
+
SM8350_SLAVE_AOSS,
265
+
SM8350_SLAVE_APPSS,
266
+
SM8350_SLAVE_CAMERA_CFG,
267
+
SM8350_SLAVE_CLK_CTL,
268
+
SM8350_SLAVE_CDSP_CFG,
269
+
SM8350_SLAVE_RBCPR_CX_CFG,
270
+
SM8350_SLAVE_RBCPR_MMCX_CFG,
271
+
SM8350_SLAVE_RBCPR_MX_CFG,
272
+
SM8350_SLAVE_CRYPTO_0_CFG,
273
+
SM8350_SLAVE_CX_RDPM,
274
+
SM8350_SLAVE_DCC_CFG,
275
+
SM8350_SLAVE_DISPLAY_CFG,
276
+
SM8350_SLAVE_GFX3D_CFG,
277
+
SM8350_SLAVE_HWKM,
278
+
SM8350_SLAVE_IMEM_CFG,
279
+
SM8350_SLAVE_IPA_CFG,
280
+
SM8350_SLAVE_IPC_ROUTER_CFG,
281
+
SM8350_SLAVE_LPASS,
282
+
SM8350_SLAVE_CNOC_MSS,
283
+
SM8350_SLAVE_MX_RDPM,
284
+
SM8350_SLAVE_PCIE_0_CFG,
285
+
SM8350_SLAVE_PCIE_1_CFG,
286
+
SM8350_SLAVE_PDM,
287
+
SM8350_SLAVE_PIMEM_CFG,
288
+
SM8350_SLAVE_PKA_WRAPPER_CFG,
289
+
SM8350_SLAVE_PMU_WRAPPER_CFG,
290
+
SM8350_SLAVE_QDSS_CFG,
291
+
SM8350_SLAVE_QSPI_0,
292
+
SM8350_SLAVE_QUP_0,
293
+
SM8350_SLAVE_QUP_1,
294
+
SM8350_SLAVE_QUP_2,
295
+
SM8350_SLAVE_SDCC_2,
296
+
SM8350_SLAVE_SDCC_4,
297
+
SM8350_SLAVE_SECURITY,
298
+
SM8350_SLAVE_SPSS_CFG,
299
+
SM8350_SLAVE_TCSR,
300
+
SM8350_SLAVE_TLMM,
301
+
SM8350_SLAVE_UFS_CARD_CFG,
302
+
SM8350_SLAVE_UFS_MEM_CFG,
303
+
SM8350_SLAVE_USB3_0,
304
+
SM8350_SLAVE_USB3_1,
305
+
SM8350_SLAVE_VENUS_CFG,
306
+
SM8350_SLAVE_VSENSE_CTRL_CFG,
307
+
SM8350_SLAVE_A1NOC_CFG,
308
+
SM8350_SLAVE_A2NOC_CFG,
309
+
SM8350_SLAVE_DDRSS_CFG,
310
+
SM8350_SLAVE_CNOC_MNOC_CFG,
311
+
SM8350_SLAVE_SNOC_CFG,
312
+
SM8350_SLAVE_BOOT_IMEM,
313
+
SM8350_SLAVE_IMEM,
314
+
SM8350_SLAVE_PIMEM,
315
+
SM8350_SLAVE_SERVICE_CNOC,
316
+
SM8350_SLAVE_QDSS_STM,
317
+
SM8350_SLAVE_TCU
318
+
},
319
+
};
320
+
321
+
static struct qcom_icc_node qnm_cnoc_dc_noc = {
322
+
.name = "qnm_cnoc_dc_noc",
323
+
.id = SM8350_MASTER_CNOC_DC_NOC,
324
+
.channels = 1,
325
+
.buswidth = 4,
326
+
.num_links = 2,
327
+
.links = { SM8350_SLAVE_LLCC_CFG,
328
+
SM8350_SLAVE_GEM_NOC_CFG
329
+
},
330
+
};
331
+
332
+
static struct qcom_icc_node alm_gpu_tcu = {
333
+
.name = "alm_gpu_tcu",
334
+
.id = SM8350_MASTER_GPU_TCU,
335
+
.channels = 1,
336
+
.buswidth = 8,
337
+
.num_links = 2,
338
+
.links = { SM8350_SLAVE_GEM_NOC_CNOC,
339
+
SM8350_SLAVE_LLCC
340
+
},
341
+
};
342
+
343
+
static struct qcom_icc_node alm_sys_tcu = {
344
+
.name = "alm_sys_tcu",
345
+
.id = SM8350_MASTER_SYS_TCU,
346
+
.channels = 1,
347
+
.buswidth = 8,
348
+
.num_links = 2,
349
+
.links = { SM8350_SLAVE_GEM_NOC_CNOC,
350
+
SM8350_SLAVE_LLCC
351
+
},
352
+
};
353
+
354
+
static struct qcom_icc_node chm_apps = {
355
+
.name = "chm_apps",
356
+
.id = SM8350_MASTER_APPSS_PROC,
357
+
.channels = 2,
358
+
.buswidth = 32,
359
+
.num_links = 3,
360
+
.links = { SM8350_SLAVE_GEM_NOC_CNOC,
361
+
SM8350_SLAVE_LLCC,
362
+
SM8350_SLAVE_MEM_NOC_PCIE_SNOC
363
+
},
364
+
};
365
+
366
+
static struct qcom_icc_node qnm_cmpnoc = {
367
+
.name = "qnm_cmpnoc",
368
+
.id = SM8350_MASTER_COMPUTE_NOC,
369
+
.channels = 2,
370
+
.buswidth = 32,
371
+
.num_links = 2,
372
+
.links = { SM8350_SLAVE_GEM_NOC_CNOC,
373
+
SM8350_SLAVE_LLCC
374
+
},
375
+
};
376
+
377
+
static struct qcom_icc_node qnm_gemnoc_cfg = {
378
+
.name = "qnm_gemnoc_cfg",
379
+
.id = SM8350_MASTER_GEM_NOC_CFG,
380
+
.channels = 1,
381
+
.buswidth = 4,
382
+
.num_links = 5,
383
+
.links = { SM8350_SLAVE_MSS_PROC_MS_MPU_CFG,
384
+
SM8350_SLAVE_MCDMA_MS_MPU_CFG,
385
+
SM8350_SLAVE_SERVICE_GEM_NOC_1,
386
+
SM8350_SLAVE_SERVICE_GEM_NOC_2,
387
+
SM8350_SLAVE_SERVICE_GEM_NOC
388
+
},
389
+
};
390
+
391
+
static struct qcom_icc_node qnm_gpu = {
392
+
.name = "qnm_gpu",
393
+
.id = SM8350_MASTER_GFX3D,
394
+
.channels = 2,
395
+
.buswidth = 32,
396
+
.num_links = 2,
397
+
.links = { SM8350_SLAVE_GEM_NOC_CNOC,
398
+
SM8350_SLAVE_LLCC
399
+
},
400
+
};
401
+
402
+
static struct qcom_icc_node qnm_mnoc_hf = {
403
+
.name = "qnm_mnoc_hf",
404
+
.id = SM8350_MASTER_MNOC_HF_MEM_NOC,
405
+
.channels = 2,
406
+
.buswidth = 32,
407
+
.num_links = 1,
408
+
.links = { SM8350_SLAVE_LLCC },
409
+
};
410
+
411
+
static struct qcom_icc_node qnm_mnoc_sf = {
412
+
.name = "qnm_mnoc_sf",
413
+
.id = SM8350_MASTER_MNOC_SF_MEM_NOC,
414
+
.channels = 2,
415
+
.buswidth = 32,
416
+
.num_links = 2,
417
+
.links = { SM8350_SLAVE_GEM_NOC_CNOC,
418
+
SM8350_SLAVE_LLCC
419
+
},
420
+
};
421
+
422
+
static struct qcom_icc_node qnm_pcie = {
423
+
.name = "qnm_pcie",
424
+
.id = SM8350_MASTER_ANOC_PCIE_GEM_NOC,
425
+
.channels = 1,
426
+
.buswidth = 16,
427
+
.num_links = 2,
428
+
.links = { SM8350_SLAVE_GEM_NOC_CNOC,
429
+
SM8350_SLAVE_LLCC
430
+
},
431
+
};
432
+
433
+
static struct qcom_icc_node qnm_snoc_gc = {
434
+
.name = "qnm_snoc_gc",
435
+
.id = SM8350_MASTER_SNOC_GC_MEM_NOC,
436
+
.channels = 1,
437
+
.buswidth = 8,
438
+
.num_links = 1,
439
+
.links = { SM8350_SLAVE_LLCC },
440
+
};
441
+
442
+
static struct qcom_icc_node qnm_snoc_sf = {
443
+
.name = "qnm_snoc_sf",
444
+
.id = SM8350_MASTER_SNOC_SF_MEM_NOC,
445
+
.channels = 1,
446
+
.buswidth = 16,
447
+
.num_links = 3,
448
+
.links = { SM8350_SLAVE_GEM_NOC_CNOC,
449
+
SM8350_SLAVE_LLCC,
450
+
SM8350_SLAVE_MEM_NOC_PCIE_SNOC
451
+
},
452
+
};
453
+
454
+
static struct qcom_icc_node qhm_config_noc = {
455
+
.name = "qhm_config_noc",
456
+
.id = SM8350_MASTER_CNOC_LPASS_AG_NOC,
457
+
.channels = 1,
458
+
.buswidth = 4,
459
+
.num_links = 6,
460
+
.links = { SM8350_SLAVE_LPASS_CORE_CFG,
461
+
SM8350_SLAVE_LPASS_LPI_CFG,
462
+
SM8350_SLAVE_LPASS_MPU_CFG,
463
+
SM8350_SLAVE_LPASS_TOP_CFG,
464
+
SM8350_SLAVE_SERVICES_LPASS_AML_NOC,
465
+
SM8350_SLAVE_SERVICE_LPASS_AG_NOC
466
+
},
467
+
};
468
+
469
+
static struct qcom_icc_node llcc_mc = {
470
+
.name = "llcc_mc",
471
+
.id = SM8350_MASTER_LLCC,
472
+
.channels = 4,
473
+
.buswidth = 4,
474
+
.num_links = 1,
475
+
.links = { SM8350_SLAVE_EBI1 },
476
+
};
477
+
478
+
static struct qcom_icc_node qnm_camnoc_hf = {
479
+
.name = "qnm_camnoc_hf",
480
+
.id = SM8350_MASTER_CAMNOC_HF,
481
+
.channels = 2,
482
+
.buswidth = 32,
483
+
.num_links = 1,
484
+
.links = { SM8350_SLAVE_MNOC_HF_MEM_NOC },
485
+
};
486
+
487
+
static struct qcom_icc_node qnm_camnoc_icp = {
488
+
.name = "qnm_camnoc_icp",
489
+
.id = SM8350_MASTER_CAMNOC_ICP,
490
+
.channels = 1,
491
+
.buswidth = 8,
492
+
.num_links = 1,
493
+
.links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
494
+
};
495
+
496
+
static struct qcom_icc_node qnm_camnoc_sf = {
497
+
.name = "qnm_camnoc_sf",
498
+
.id = SM8350_MASTER_CAMNOC_SF,
499
+
.channels = 2,
500
+
.buswidth = 32,
501
+
.num_links = 1,
502
+
.links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
503
+
};
504
+
505
+
static struct qcom_icc_node qnm_mnoc_cfg = {
506
+
.name = "qnm_mnoc_cfg",
507
+
.id = SM8350_MASTER_CNOC_MNOC_CFG,
508
+
.channels = 1,
509
+
.buswidth = 4,
510
+
.num_links = 1,
511
+
.links = { SM8350_SLAVE_SERVICE_MNOC },
512
+
};
513
+
514
+
static struct qcom_icc_node qnm_video0 = {
515
+
.name = "qnm_video0",
516
+
.id = SM8350_MASTER_VIDEO_P0,
517
+
.channels = 1,
518
+
.buswidth = 32,
519
+
.num_links = 1,
520
+
.links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
521
+
};
522
+
523
+
static struct qcom_icc_node qnm_video1 = {
524
+
.name = "qnm_video1",
525
+
.id = SM8350_MASTER_VIDEO_P1,
526
+
.channels = 1,
527
+
.buswidth = 32,
528
+
.num_links = 1,
529
+
.links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
530
+
};
531
+
532
+
static struct qcom_icc_node qnm_video_cvp = {
533
+
.name = "qnm_video_cvp",
534
+
.id = SM8350_MASTER_VIDEO_PROC,
535
+
.channels = 1,
536
+
.buswidth = 32,
537
+
.num_links = 1,
538
+
.links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
539
+
};
540
+
541
+
static struct qcom_icc_node qxm_mdp0 = {
542
+
.name = "qxm_mdp0",
543
+
.id = SM8350_MASTER_MDP0,
544
+
.channels = 1,
545
+
.buswidth = 32,
546
+
.num_links = 1,
547
+
.links = { SM8350_SLAVE_MNOC_HF_MEM_NOC },
548
+
};
549
+
550
+
static struct qcom_icc_node qxm_mdp1 = {
551
+
.name = "qxm_mdp1",
552
+
.id = SM8350_MASTER_MDP1,
553
+
.channels = 1,
554
+
.buswidth = 32,
555
+
.num_links = 1,
556
+
.links = { SM8350_SLAVE_MNOC_HF_MEM_NOC },
557
+
};
558
+
559
+
static struct qcom_icc_node qxm_rot = {
560
+
.name = "qxm_rot",
561
+
.id = SM8350_MASTER_ROTATOR,
562
+
.channels = 1,
563
+
.buswidth = 32,
564
+
.num_links = 1,
565
+
.links = { SM8350_SLAVE_MNOC_SF_MEM_NOC },
566
+
};
567
+
568
+
static struct qcom_icc_node qhm_nsp_noc_config = {
569
+
.name = "qhm_nsp_noc_config",
570
+
.id = SM8350_MASTER_CDSP_NOC_CFG,
571
+
.channels = 1,
572
+
.buswidth = 4,
573
+
.num_links = 1,
574
+
.links = { SM8350_SLAVE_SERVICE_NSP_NOC },
575
+
};
576
+
577
+
static struct qcom_icc_node qxm_nsp = {
578
+
.name = "qxm_nsp",
579
+
.id = SM8350_MASTER_CDSP_PROC,
580
+
.channels = 2,
581
+
.buswidth = 32,
582
+
.num_links = 1,
583
+
.links = { SM8350_SLAVE_CDSP_MEM_NOC },
584
+
};
585
+
586
+
static struct qcom_icc_node qnm_aggre1_noc = {
587
+
.name = "qnm_aggre1_noc",
588
+
.id = SM8350_MASTER_A1NOC_SNOC,
589
+
.channels = 1,
590
+
.buswidth = 16,
591
+
.num_links = 1,
592
+
.links = { SM8350_SLAVE_SNOC_GEM_NOC_SF },
593
+
};
594
+
595
+
static struct qcom_icc_node qnm_aggre2_noc = {
596
+
.name = "qnm_aggre2_noc",
597
+
.id = SM8350_MASTER_A2NOC_SNOC,
598
+
.channels = 1,
599
+
.buswidth = 16,
600
+
.num_links = 1,
601
+
.links = { SM8350_SLAVE_SNOC_GEM_NOC_SF },
602
+
};
603
+
604
+
static struct qcom_icc_node qnm_snoc_cfg = {
605
+
.name = "qnm_snoc_cfg",
606
+
.id = SM8350_MASTER_SNOC_CFG,
607
+
.channels = 1,
608
+
.buswidth = 4,
609
+
.num_links = 1,
610
+
.links = { SM8350_SLAVE_SERVICE_SNOC },
611
+
};
612
+
613
+
static struct qcom_icc_node qxm_pimem = {
614
+
.name = "qxm_pimem",
615
+
.id = SM8350_MASTER_PIMEM,
616
+
.channels = 1,
617
+
.buswidth = 8,
618
+
.num_links = 1,
619
+
.links = { SM8350_SLAVE_SNOC_GEM_NOC_GC },
620
+
};
621
+
622
+
static struct qcom_icc_node xm_gic = {
623
+
.name = "xm_gic",
624
+
.id = SM8350_MASTER_GIC,
625
+
.channels = 1,
626
+
.buswidth = 8,
627
+
.num_links = 1,
628
+
.links = { SM8350_SLAVE_SNOC_GEM_NOC_GC },
629
+
};
630
+
631
+
static struct qcom_icc_node qnm_mnoc_hf_disp = {
632
+
.name = "qnm_mnoc_hf_disp",
633
+
.id = SM8350_MASTER_MNOC_HF_MEM_NOC_DISP,
634
+
.channels = 2,
635
+
.buswidth = 32,
636
+
.num_links = 1,
637
+
.links = { SM8350_SLAVE_LLCC_DISP },
638
+
};
639
+
640
+
static struct qcom_icc_node qnm_mnoc_sf_disp = {
641
+
.name = "qnm_mnoc_sf_disp",
642
+
.id = SM8350_MASTER_MNOC_SF_MEM_NOC_DISP,
643
+
.channels = 2,
644
+
.buswidth = 32,
645
+
.num_links = 1,
646
+
.links = { SM8350_SLAVE_LLCC_DISP },
647
+
};
648
+
649
+
static struct qcom_icc_node llcc_mc_disp = {
650
+
.name = "llcc_mc_disp",
651
+
.id = SM8350_MASTER_LLCC_DISP,
652
+
.channels = 4,
653
+
.buswidth = 4,
654
+
.num_links = 1,
655
+
.links = { SM8350_SLAVE_EBI1_DISP },
656
+
};
657
+
658
+
static struct qcom_icc_node qxm_mdp0_disp = {
659
+
.name = "qxm_mdp0_disp",
660
+
.id = SM8350_MASTER_MDP0_DISP,
661
+
.channels = 1,
662
+
.buswidth = 32,
663
+
.num_links = 1,
664
+
.links = { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP },
665
+
};
666
+
667
+
static struct qcom_icc_node qxm_mdp1_disp = {
668
+
.name = "qxm_mdp1_disp",
669
+
.id = SM8350_MASTER_MDP1_DISP,
670
+
.channels = 1,
671
+
.buswidth = 32,
672
+
.num_links = 1,
673
+
.links = { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP },
674
+
};
675
+
676
+
static struct qcom_icc_node qxm_rot_disp = {
677
+
.name = "qxm_rot_disp",
678
+
.id = SM8350_MASTER_ROTATOR_DISP,
679
+
.channels = 1,
680
+
.buswidth = 32,
681
+
.num_links = 1,
682
+
.links = { SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP },
683
+
};
684
+
685
+
static struct qcom_icc_node qns_a1noc_snoc = {
686
+
.name = "qns_a1noc_snoc",
687
+
.id = SM8350_SLAVE_A1NOC_SNOC,
688
+
.channels = 1,
689
+
.buswidth = 16,
690
+
.num_links = 1,
691
+
.links = { SM8350_MASTER_A1NOC_SNOC },
692
+
};
693
+
694
+
static struct qcom_icc_node srvc_aggre1_noc = {
695
+
.name = "srvc_aggre1_noc",
696
+
.id = SM8350_SLAVE_SERVICE_A1NOC,
697
+
.channels = 1,
698
+
.buswidth = 4,
699
+
};
700
+
701
+
static struct qcom_icc_node qns_a2noc_snoc = {
702
+
.name = "qns_a2noc_snoc",
703
+
.id = SM8350_SLAVE_A2NOC_SNOC,
704
+
.channels = 1,
705
+
.buswidth = 16,
706
+
.num_links = 1,
707
+
.links = { SM8350_MASTER_A2NOC_SNOC },
708
+
};
709
+
710
+
static struct qcom_icc_node qns_pcie_mem_noc = {
711
+
.name = "qns_pcie_mem_noc",
712
+
.id = SM8350_SLAVE_ANOC_PCIE_GEM_NOC,
713
+
.channels = 1,
714
+
.buswidth = 16,
715
+
.num_links = 1,
716
+
.links = { SM8350_MASTER_ANOC_PCIE_GEM_NOC },
717
+
};
718
+
719
+
static struct qcom_icc_node srvc_aggre2_noc = {
720
+
.name = "srvc_aggre2_noc",
721
+
.id = SM8350_SLAVE_SERVICE_A2NOC,
722
+
.channels = 1,
723
+
.buswidth = 4,
724
+
};
725
+
726
+
static struct qcom_icc_node qhs_ahb2phy0 = {
727
+
.name = "qhs_ahb2phy0",
728
+
.id = SM8350_SLAVE_AHB2PHY_SOUTH,
729
+
.channels = 1,
730
+
.buswidth = 4,
731
+
};
732
+
733
+
static struct qcom_icc_node qhs_ahb2phy1 = {
734
+
.name = "qhs_ahb2phy1",
735
+
.id = SM8350_SLAVE_AHB2PHY_NORTH,
736
+
.channels = 1,
737
+
.buswidth = 4,
738
+
};
739
+
740
+
static struct qcom_icc_node qhs_aoss = {
741
+
.name = "qhs_aoss",
742
+
.id = SM8350_SLAVE_AOSS,
743
+
.channels = 1,
744
+
.buswidth = 4,
745
+
};
746
+
747
+
static struct qcom_icc_node qhs_apss = {
748
+
.name = "qhs_apss",
749
+
.id = SM8350_SLAVE_APPSS,
750
+
.channels = 1,
751
+
.buswidth = 8,
752
+
};
753
+
754
+
static struct qcom_icc_node qhs_camera_cfg = {
755
+
.name = "qhs_camera_cfg",
756
+
.id = SM8350_SLAVE_CAMERA_CFG,
757
+
.channels = 1,
758
+
.buswidth = 4,
759
+
};
760
+
761
+
static struct qcom_icc_node qhs_clk_ctl = {
762
+
.name = "qhs_clk_ctl",
763
+
.id = SM8350_SLAVE_CLK_CTL,
764
+
.channels = 1,
765
+
.buswidth = 4,
766
+
};
767
+
768
+
static struct qcom_icc_node qhs_compute_cfg = {
769
+
.name = "qhs_compute_cfg",
770
+
.id = SM8350_SLAVE_CDSP_CFG,
771
+
.channels = 1,
772
+
.buswidth = 4,
773
+
};
774
+
775
+
static struct qcom_icc_node qhs_cpr_cx = {
776
+
.name = "qhs_cpr_cx",
777
+
.id = SM8350_SLAVE_RBCPR_CX_CFG,
778
+
.channels = 1,
779
+
.buswidth = 4,
780
+
};
781
+
782
+
static struct qcom_icc_node qhs_cpr_mmcx = {
783
+
.name = "qhs_cpr_mmcx",
784
+
.id = SM8350_SLAVE_RBCPR_MMCX_CFG,
785
+
.channels = 1,
786
+
.buswidth = 4,
787
+
};
788
+
789
+
static struct qcom_icc_node qhs_cpr_mx = {
790
+
.name = "qhs_cpr_mx",
791
+
.id = SM8350_SLAVE_RBCPR_MX_CFG,
792
+
.channels = 1,
793
+
.buswidth = 4,
794
+
};
795
+
796
+
static struct qcom_icc_node qhs_crypto0_cfg = {
797
+
.name = "qhs_crypto0_cfg",
798
+
.id = SM8350_SLAVE_CRYPTO_0_CFG,
799
+
.channels = 1,
800
+
.buswidth = 4,
801
+
};
802
+
803
+
static struct qcom_icc_node qhs_cx_rdpm = {
804
+
.name = "qhs_cx_rdpm",
805
+
.id = SM8350_SLAVE_CX_RDPM,
806
+
.channels = 1,
807
+
.buswidth = 4,
808
+
};
809
+
810
+
static struct qcom_icc_node qhs_dcc_cfg = {
811
+
.name = "qhs_dcc_cfg",
812
+
.id = SM8350_SLAVE_DCC_CFG,
813
+
.channels = 1,
814
+
.buswidth = 4,
815
+
};
816
+
817
+
static struct qcom_icc_node qhs_display_cfg = {
818
+
.name = "qhs_display_cfg",
819
+
.id = SM8350_SLAVE_DISPLAY_CFG,
820
+
.channels = 1,
821
+
.buswidth = 4,
822
+
};
823
+
824
+
static struct qcom_icc_node qhs_gpuss_cfg = {
825
+
.name = "qhs_gpuss_cfg",
826
+
.id = SM8350_SLAVE_GFX3D_CFG,
827
+
.channels = 1,
828
+
.buswidth = 8,
829
+
};
830
+
831
+
static struct qcom_icc_node qhs_hwkm = {
832
+
.name = "qhs_hwkm",
833
+
.id = SM8350_SLAVE_HWKM,
834
+
.channels = 1,
835
+
.buswidth = 4,
836
+
};
837
+
838
+
static struct qcom_icc_node qhs_imem_cfg = {
839
+
.name = "qhs_imem_cfg",
840
+
.id = SM8350_SLAVE_IMEM_CFG,
841
+
.channels = 1,
842
+
.buswidth = 4,
843
+
};
844
+
845
+
static struct qcom_icc_node qhs_ipa = {
846
+
.name = "qhs_ipa",
847
+
.id = SM8350_SLAVE_IPA_CFG,
848
+
.channels = 1,
849
+
.buswidth = 4,
850
+
};
851
+
852
+
static struct qcom_icc_node qhs_ipc_router = {
853
+
.name = "qhs_ipc_router",
854
+
.id = SM8350_SLAVE_IPC_ROUTER_CFG,
855
+
.channels = 1,
856
+
.buswidth = 4,
857
+
};
858
+
859
+
static struct qcom_icc_node qhs_lpass_cfg = {
860
+
.name = "qhs_lpass_cfg",
861
+
.id = SM8350_SLAVE_LPASS,
862
+
.channels = 1,
863
+
.buswidth = 4,
864
+
.num_links = 1,
865
+
.links = { SM8350_MASTER_CNOC_LPASS_AG_NOC },
866
+
};
867
+
868
+
static struct qcom_icc_node qhs_mss_cfg = {
869
+
.name = "qhs_mss_cfg",
870
+
.id = SM8350_SLAVE_CNOC_MSS,
871
+
.channels = 1,
872
+
.buswidth = 4,
873
+
};
874
+
875
+
static struct qcom_icc_node qhs_mx_rdpm = {
876
+
.name = "qhs_mx_rdpm",
877
+
.id = SM8350_SLAVE_MX_RDPM,
878
+
.channels = 1,
879
+
.buswidth = 4,
880
+
};
881
+
882
+
static struct qcom_icc_node qhs_pcie0_cfg = {
883
+
.name = "qhs_pcie0_cfg",
884
+
.id = SM8350_SLAVE_PCIE_0_CFG,
885
+
.channels = 1,
886
+
.buswidth = 4,
887
+
};
888
+
889
+
static struct qcom_icc_node qhs_pcie1_cfg = {
890
+
.name = "qhs_pcie1_cfg",
891
+
.id = SM8350_SLAVE_PCIE_1_CFG,
892
+
.channels = 1,
893
+
.buswidth = 4,
894
+
};
895
+
896
+
static struct qcom_icc_node qhs_pdm = {
897
+
.name = "qhs_pdm",
898
+
.id = SM8350_SLAVE_PDM,
899
+
.channels = 1,
900
+
.buswidth = 4,
901
+
};
902
+
903
+
static struct qcom_icc_node qhs_pimem_cfg = {
904
+
.name = "qhs_pimem_cfg",
905
+
.id = SM8350_SLAVE_PIMEM_CFG,
906
+
.channels = 1,
907
+
.buswidth = 4,
908
+
};
909
+
910
+
static struct qcom_icc_node qhs_pka_wrapper_cfg = {
911
+
.name = "qhs_pka_wrapper_cfg",
912
+
.id = SM8350_SLAVE_PKA_WRAPPER_CFG,
913
+
.channels = 1,
914
+
.buswidth = 4,
915
+
};
916
+
917
+
static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
918
+
.name = "qhs_pmu_wrapper_cfg",
919
+
.id = SM8350_SLAVE_PMU_WRAPPER_CFG,
920
+
.channels = 1,
921
+
.buswidth = 4,
922
+
};
923
+
924
+
static struct qcom_icc_node qhs_qdss_cfg = {
925
+
.name = "qhs_qdss_cfg",
926
+
.id = SM8350_SLAVE_QDSS_CFG,
927
+
.channels = 1,
928
+
.buswidth = 4,
929
+
};
930
+
931
+
static struct qcom_icc_node qhs_qspi = {
932
+
.name = "qhs_qspi",
933
+
.id = SM8350_SLAVE_QSPI_0,
934
+
.channels = 1,
935
+
.buswidth = 4,
936
+
};
937
+
938
+
static struct qcom_icc_node qhs_qup0 = {
939
+
.name = "qhs_qup0",
940
+
.id = SM8350_SLAVE_QUP_0,
941
+
.channels = 1,
942
+
.buswidth = 4,
943
+
};
944
+
945
+
static struct qcom_icc_node qhs_qup1 = {
946
+
.name = "qhs_qup1",
947
+
.id = SM8350_SLAVE_QUP_1,
948
+
.channels = 1,
949
+
.buswidth = 4,
950
+
};
951
+
952
+
static struct qcom_icc_node qhs_qup2 = {
953
+
.name = "qhs_qup2",
954
+
.id = SM8350_SLAVE_QUP_2,
955
+
.channels = 1,
956
+
.buswidth = 4,
957
+
};
958
+
959
+
static struct qcom_icc_node qhs_sdc2 = {
960
+
.name = "qhs_sdc2",
961
+
.id = SM8350_SLAVE_SDCC_2,
962
+
.channels = 1,
963
+
.buswidth = 4,
964
+
};
965
+
966
+
static struct qcom_icc_node qhs_sdc4 = {
967
+
.name = "qhs_sdc4",
968
+
.id = SM8350_SLAVE_SDCC_4,
969
+
.channels = 1,
970
+
.buswidth = 4,
971
+
};
972
+
973
+
static struct qcom_icc_node qhs_security = {
974
+
.name = "qhs_security",
975
+
.id = SM8350_SLAVE_SECURITY,
976
+
.channels = 1,
977
+
.buswidth = 4,
978
+
};
979
+
980
+
static struct qcom_icc_node qhs_spss_cfg = {
981
+
.name = "qhs_spss_cfg",
982
+
.id = SM8350_SLAVE_SPSS_CFG,
983
+
.channels = 1,
984
+
.buswidth = 4,
985
+
};
986
+
987
+
static struct qcom_icc_node qhs_tcsr = {
988
+
.name = "qhs_tcsr",
989
+
.id = SM8350_SLAVE_TCSR,
990
+
.channels = 1,
991
+
.buswidth = 4,
992
+
};
993
+
994
+
static struct qcom_icc_node qhs_tlmm = {
995
+
.name = "qhs_tlmm",
996
+
.id = SM8350_SLAVE_TLMM,
997
+
.channels = 1,
998
+
.buswidth = 4,
999
+
};
1000
+
1001
+
static struct qcom_icc_node qhs_ufs_card_cfg = {
1002
+
.name = "qhs_ufs_card_cfg",
1003
+
.id = SM8350_SLAVE_UFS_CARD_CFG,
1004
+
.channels = 1,
1005
+
.buswidth = 4,
1006
+
};
1007
+
1008
+
static struct qcom_icc_node qhs_ufs_mem_cfg = {
1009
+
.name = "qhs_ufs_mem_cfg",
1010
+
.id = SM8350_SLAVE_UFS_MEM_CFG,
1011
+
.channels = 1,
1012
+
.buswidth = 4,
1013
+
};
1014
+
1015
+
static struct qcom_icc_node qhs_usb3_0 = {
1016
+
.name = "qhs_usb3_0",
1017
+
.id = SM8350_SLAVE_USB3_0,
1018
+
.channels = 1,
1019
+
.buswidth = 4,
1020
+
};
1021
+
1022
+
static struct qcom_icc_node qhs_usb3_1 = {
1023
+
.name = "qhs_usb3_1",
1024
+
.id = SM8350_SLAVE_USB3_1,
1025
+
.channels = 1,
1026
+
.buswidth = 4,
1027
+
};
1028
+
1029
+
static struct qcom_icc_node qhs_venus_cfg = {
1030
+
.name = "qhs_venus_cfg",
1031
+
.id = SM8350_SLAVE_VENUS_CFG,
1032
+
.channels = 1,
1033
+
.buswidth = 4,
1034
+
};
1035
+
1036
+
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1037
+
.name = "qhs_vsense_ctrl_cfg",
1038
+
.id = SM8350_SLAVE_VSENSE_CTRL_CFG,
1039
+
.channels = 1,
1040
+
.buswidth = 4,
1041
+
};
1042
+
1043
+
static struct qcom_icc_node qns_a1_noc_cfg = {
1044
+
.name = "qns_a1_noc_cfg",
1045
+
.id = SM8350_SLAVE_A1NOC_CFG,
1046
+
.channels = 1,
1047
+
.buswidth = 4,
1048
+
};
1049
+
1050
+
static struct qcom_icc_node qns_a2_noc_cfg = {
1051
+
.name = "qns_a2_noc_cfg",
1052
+
.id = SM8350_SLAVE_A2NOC_CFG,
1053
+
.channels = 1,
1054
+
.buswidth = 4,
1055
+
};
1056
+
1057
+
static struct qcom_icc_node qns_ddrss_cfg = {
1058
+
.name = "qns_ddrss_cfg",
1059
+
.id = SM8350_SLAVE_DDRSS_CFG,
1060
+
.channels = 1,
1061
+
.buswidth = 4,
1062
+
};
1063
+
1064
+
static struct qcom_icc_node qns_mnoc_cfg = {
1065
+
.name = "qns_mnoc_cfg",
1066
+
.id = SM8350_SLAVE_CNOC_MNOC_CFG,
1067
+
.channels = 1,
1068
+
.buswidth = 4,
1069
+
};
1070
+
1071
+
static struct qcom_icc_node qns_snoc_cfg = {
1072
+
.name = "qns_snoc_cfg",
1073
+
.id = SM8350_SLAVE_SNOC_CFG,
1074
+
.channels = 1,
1075
+
.buswidth = 4,
1076
+
};
1077
+
1078
+
static struct qcom_icc_node qxs_boot_imem = {
1079
+
.name = "qxs_boot_imem",
1080
+
.id = SM8350_SLAVE_BOOT_IMEM,
1081
+
.channels = 1,
1082
+
.buswidth = 8,
1083
+
};
1084
+
1085
+
static struct qcom_icc_node qxs_imem = {
1086
+
.name = "qxs_imem",
1087
+
.id = SM8350_SLAVE_IMEM,
1088
+
.channels = 1,
1089
+
.buswidth = 8,
1090
+
};
1091
+
1092
+
static struct qcom_icc_node qxs_pimem = {
1093
+
.name = "qxs_pimem",
1094
+
.id = SM8350_SLAVE_PIMEM,
1095
+
.channels = 1,
1096
+
.buswidth = 8,
1097
+
};
1098
+
1099
+
static struct qcom_icc_node srvc_cnoc = {
1100
+
.name = "srvc_cnoc",
1101
+
.id = SM8350_SLAVE_SERVICE_CNOC,
1102
+
.channels = 1,
1103
+
.buswidth = 4,
1104
+
};
1105
+
1106
+
static struct qcom_icc_node xs_pcie_0 = {
1107
+
.name = "xs_pcie_0",
1108
+
.id = SM8350_SLAVE_PCIE_0,
1109
+
.channels = 1,
1110
+
.buswidth = 8,
1111
+
};
1112
+
1113
+
static struct qcom_icc_node xs_pcie_1 = {
1114
+
.name = "xs_pcie_1",
1115
+
.id = SM8350_SLAVE_PCIE_1,
1116
+
.channels = 1,
1117
+
.buswidth = 8,
1118
+
};
1119
+
1120
+
static struct qcom_icc_node xs_qdss_stm = {
1121
+
.name = "xs_qdss_stm",
1122
+
.id = SM8350_SLAVE_QDSS_STM,
1123
+
.channels = 1,
1124
+
.buswidth = 4,
1125
+
};
1126
+
1127
+
static struct qcom_icc_node xs_sys_tcu_cfg = {
1128
+
.name = "xs_sys_tcu_cfg",
1129
+
.id = SM8350_SLAVE_TCU,
1130
+
.channels = 1,
1131
+
.buswidth = 8,
1132
+
};
1133
+
1134
+
static struct qcom_icc_node qhs_llcc = {
1135
+
.name = "qhs_llcc",
1136
+
.id = SM8350_SLAVE_LLCC_CFG,
1137
+
.channels = 1,
1138
+
.buswidth = 4,
1139
+
};
1140
+
1141
+
static struct qcom_icc_node qns_gemnoc = {
1142
+
.name = "qns_gemnoc",
1143
+
.id = SM8350_SLAVE_GEM_NOC_CFG,
1144
+
.channels = 1,
1145
+
.buswidth = 4,
1146
+
};
1147
+
1148
+
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1149
+
.name = "qhs_mdsp_ms_mpu_cfg",
1150
+
.id = SM8350_SLAVE_MSS_PROC_MS_MPU_CFG,
1151
+
.channels = 1,
1152
+
.buswidth = 4,
1153
+
};
1154
+
1155
+
static struct qcom_icc_node qhs_modem_ms_mpu_cfg = {
1156
+
.name = "qhs_modem_ms_mpu_cfg",
1157
+
.id = SM8350_SLAVE_MCDMA_MS_MPU_CFG,
1158
+
.channels = 1,
1159
+
.buswidth = 4,
1160
+
};
1161
+
1162
+
static struct qcom_icc_node qns_gem_noc_cnoc = {
1163
+
.name = "qns_gem_noc_cnoc",
1164
+
.id = SM8350_SLAVE_GEM_NOC_CNOC,
1165
+
.channels = 1,
1166
+
.buswidth = 16,
1167
+
.num_links = 1,
1168
+
.links = { SM8350_MASTER_GEM_NOC_CNOC },
1169
+
};
1170
+
1171
+
static struct qcom_icc_node qns_llcc = {
1172
+
.name = "qns_llcc",
1173
+
.id = SM8350_SLAVE_LLCC,
1174
+
.channels = 4,
1175
+
.buswidth = 16,
1176
+
.num_links = 1,
1177
+
.links = { SM8350_MASTER_LLCC },
1178
+
};
1179
+
1180
+
static struct qcom_icc_node qns_pcie = {
1181
+
.name = "qns_pcie",
1182
+
.id = SM8350_SLAVE_MEM_NOC_PCIE_SNOC,
1183
+
.channels = 1,
1184
+
.buswidth = 8,
1185
+
};
1186
+
1187
+
static struct qcom_icc_node srvc_even_gemnoc = {
1188
+
.name = "srvc_even_gemnoc",
1189
+
.id = SM8350_SLAVE_SERVICE_GEM_NOC_1,
1190
+
.channels = 1,
1191
+
.buswidth = 4,
1192
+
};
1193
+
1194
+
static struct qcom_icc_node srvc_odd_gemnoc = {
1195
+
.name = "srvc_odd_gemnoc",
1196
+
.id = SM8350_SLAVE_SERVICE_GEM_NOC_2,
1197
+
.channels = 1,
1198
+
.buswidth = 4,
1199
+
};
1200
+
1201
+
static struct qcom_icc_node srvc_sys_gemnoc = {
1202
+
.name = "srvc_sys_gemnoc",
1203
+
.id = SM8350_SLAVE_SERVICE_GEM_NOC,
1204
+
.channels = 1,
1205
+
.buswidth = 4,
1206
+
};
1207
+
1208
+
static struct qcom_icc_node qhs_lpass_core = {
1209
+
.name = "qhs_lpass_core",
1210
+
.id = SM8350_SLAVE_LPASS_CORE_CFG,
1211
+
.channels = 1,
1212
+
.buswidth = 4,
1213
+
};
1214
+
1215
+
static struct qcom_icc_node qhs_lpass_lpi = {
1216
+
.name = "qhs_lpass_lpi",
1217
+
.id = SM8350_SLAVE_LPASS_LPI_CFG,
1218
+
.channels = 1,
1219
+
.buswidth = 4,
1220
+
};
1221
+
1222
+
static struct qcom_icc_node qhs_lpass_mpu = {
1223
+
.name = "qhs_lpass_mpu",
1224
+
.id = SM8350_SLAVE_LPASS_MPU_CFG,
1225
+
.channels = 1,
1226
+
.buswidth = 4,
1227
+
};
1228
+
1229
+
static struct qcom_icc_node qhs_lpass_top = {
1230
+
.name = "qhs_lpass_top",
1231
+
.id = SM8350_SLAVE_LPASS_TOP_CFG,
1232
+
.channels = 1,
1233
+
.buswidth = 4,
1234
+
};
1235
+
1236
+
static struct qcom_icc_node srvc_niu_aml_noc = {
1237
+
.name = "srvc_niu_aml_noc",
1238
+
.id = SM8350_SLAVE_SERVICES_LPASS_AML_NOC,
1239
+
.channels = 1,
1240
+
.buswidth = 4,
1241
+
};
1242
+
1243
+
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1244
+
.name = "srvc_niu_lpass_agnoc",
1245
+
.id = SM8350_SLAVE_SERVICE_LPASS_AG_NOC,
1246
+
.channels = 1,
1247
+
.buswidth = 4,
1248
+
};
1249
+
1250
+
static struct qcom_icc_node ebi = {
1251
+
.name = "ebi",
1252
+
.id = SM8350_SLAVE_EBI1,
1253
+
.channels = 4,
1254
+
.buswidth = 4,
1255
+
};
1256
+
1257
+
static struct qcom_icc_node qns_mem_noc_hf = {
1258
+
.name = "qns_mem_noc_hf",
1259
+
.id = SM8350_SLAVE_MNOC_HF_MEM_NOC,
1260
+
.channels = 2,
1261
+
.buswidth = 32,
1262
+
.num_links = 1,
1263
+
.links = { SM8350_MASTER_MNOC_HF_MEM_NOC },
1264
+
};
1265
+
1266
+
static struct qcom_icc_node qns_mem_noc_sf = {
1267
+
.name = "qns_mem_noc_sf",
1268
+
.id = SM8350_SLAVE_MNOC_SF_MEM_NOC,
1269
+
.channels = 2,
1270
+
.buswidth = 32,
1271
+
.num_links = 1,
1272
+
.links = { SM8350_MASTER_MNOC_SF_MEM_NOC },
1273
+
};
1274
+
1275
+
static struct qcom_icc_node srvc_mnoc = {
1276
+
.name = "srvc_mnoc",
1277
+
.id = SM8350_SLAVE_SERVICE_MNOC,
1278
+
.channels = 1,
1279
+
.buswidth = 4,
1280
+
};
1281
+
1282
+
static struct qcom_icc_node qns_nsp_gemnoc = {
1283
+
.name = "qns_nsp_gemnoc",
1284
+
.id = SM8350_SLAVE_CDSP_MEM_NOC,
1285
+
.channels = 2,
1286
+
.buswidth = 32,
1287
+
.num_links = 1,
1288
+
.links = { SM8350_MASTER_COMPUTE_NOC },
1289
+
};
1290
+
1291
+
static struct qcom_icc_node service_nsp_noc = {
1292
+
.name = "service_nsp_noc",
1293
+
.id = SM8350_SLAVE_SERVICE_NSP_NOC,
1294
+
.channels = 1,
1295
+
.buswidth = 4,
1296
+
};
1297
+
1298
+
static struct qcom_icc_node qns_gemnoc_gc = {
1299
+
.name = "qns_gemnoc_gc",
1300
+
.id = SM8350_SLAVE_SNOC_GEM_NOC_GC,
1301
+
.channels = 1,
1302
+
.buswidth = 8,
1303
+
.num_links = 1,
1304
+
.links = { SM8350_MASTER_SNOC_GC_MEM_NOC },
1305
+
};
1306
+
1307
+
static struct qcom_icc_node qns_gemnoc_sf = {
1308
+
.name = "qns_gemnoc_sf",
1309
+
.id = SM8350_SLAVE_SNOC_GEM_NOC_SF,
1310
+
.channels = 1,
1311
+
.buswidth = 16,
1312
+
.num_links = 1,
1313
+
.links = { SM8350_MASTER_SNOC_SF_MEM_NOC },
1314
+
};
1315
+
1316
+
static struct qcom_icc_node srvc_snoc = {
1317
+
.name = "srvc_snoc",
1318
+
.id = SM8350_SLAVE_SERVICE_SNOC,
1319
+
.channels = 1,
1320
+
.buswidth = 4,
1321
+
};
1322
+
1323
+
static struct qcom_icc_node qns_llcc_disp = {
1324
+
.name = "qns_llcc_disp",
1325
+
.id = SM8350_SLAVE_LLCC_DISP,
1326
+
.channels = 4,
1327
+
.buswidth = 16,
1328
+
.num_links = 1,
1329
+
.links = { SM8350_MASTER_LLCC_DISP },
1330
+
};
1331
+
1332
+
static struct qcom_icc_node ebi_disp = {
1333
+
.name = "ebi_disp",
1334
+
.id = SM8350_SLAVE_EBI1_DISP,
1335
+
.channels = 4,
1336
+
.buswidth = 4,
1337
+
};
1338
+
1339
+
static struct qcom_icc_node qns_mem_noc_hf_disp = {
1340
+
.name = "qns_mem_noc_hf_disp",
1341
+
.id = SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP,
1342
+
.channels = 2,
1343
+
.buswidth = 32,
1344
+
.num_links = 1,
1345
+
.links = { SM8350_MASTER_MNOC_HF_MEM_NOC_DISP },
1346
+
};
1347
+
1348
+
static struct qcom_icc_node qns_mem_noc_sf_disp = {
1349
+
.name = "qns_mem_noc_sf_disp",
1350
+
.id = SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP,
1351
+
.channels = 2,
1352
+
.buswidth = 32,
1353
+
.num_links = 1,
1354
+
.links = { SM8350_MASTER_MNOC_SF_MEM_NOC_DISP },
1355
+
};
168
1356
169
1357
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
170
1358
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);