Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
interconnect: qcom: sm8250: Retire DEFINE_QNODE
The struct definition macros are hard to read and compare, expand them.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-8-c03aaeffc769@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
authored by
Konrad Dybcio
and committed by
Georgi Djakov
aaf7d02f
9533964b
+1330
-148
+1330
-148
drivers/interconnect/qcom/sm8250.c
+1330
-148
drivers/interconnect/qcom/sm8250.c
···
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#include "icc-rpmh.h"
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#include "sm8250.h"
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DEFINE_QNODE(qhm_a1noc_cfg, SM8250_MASTER_A1NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A1NOC);
20
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DEFINE_QNODE(qhm_qspi, SM8250_MASTER_QSPI_0, 1, 4, SM8250_A1NOC_SNOC_SLV);
21
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DEFINE_QNODE(qhm_qup1, SM8250_MASTER_QUP_1, 1, 4, SM8250_A1NOC_SNOC_SLV);
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DEFINE_QNODE(qhm_qup2, SM8250_MASTER_QUP_2, 1, 4, SM8250_A1NOC_SNOC_SLV);
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DEFINE_QNODE(qhm_tsif, SM8250_MASTER_TSIF, 1, 4, SM8250_A1NOC_SNOC_SLV);
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DEFINE_QNODE(xm_pcie3_modem, SM8250_MASTER_PCIE_2, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1);
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DEFINE_QNODE(xm_sdc4, SM8250_MASTER_SDCC_4, 1, 8, SM8250_A1NOC_SNOC_SLV);
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DEFINE_QNODE(xm_ufs_mem, SM8250_MASTER_UFS_MEM, 1, 8, SM8250_A1NOC_SNOC_SLV);
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DEFINE_QNODE(xm_usb3_0, SM8250_MASTER_USB3, 1, 8, SM8250_A1NOC_SNOC_SLV);
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DEFINE_QNODE(xm_usb3_1, SM8250_MASTER_USB3_1, 1, 8, SM8250_A1NOC_SNOC_SLV);
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DEFINE_QNODE(qhm_a2noc_cfg, SM8250_MASTER_A2NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A2NOC);
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DEFINE_QNODE(qhm_qdss_bam, SM8250_MASTER_QDSS_BAM, 1, 4, SM8250_A2NOC_SNOC_SLV);
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DEFINE_QNODE(qhm_qup0, SM8250_MASTER_QUP_0, 1, 4, SM8250_A2NOC_SNOC_SLV);
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DEFINE_QNODE(qnm_cnoc, SM8250_MASTER_CNOC_A2NOC, 1, 8, SM8250_A2NOC_SNOC_SLV);
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DEFINE_QNODE(qxm_crypto, SM8250_MASTER_CRYPTO_CORE_0, 1, 8, SM8250_A2NOC_SNOC_SLV);
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DEFINE_QNODE(qxm_ipa, SM8250_MASTER_IPA, 1, 8, SM8250_A2NOC_SNOC_SLV);
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DEFINE_QNODE(xm_pcie3_0, SM8250_MASTER_PCIE, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
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DEFINE_QNODE(xm_pcie3_1, SM8250_MASTER_PCIE_1, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
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DEFINE_QNODE(xm_qdss_etr, SM8250_MASTER_QDSS_ETR, 1, 8, SM8250_A2NOC_SNOC_SLV);
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DEFINE_QNODE(xm_sdc2, SM8250_MASTER_SDCC_2, 1, 8, SM8250_A2NOC_SNOC_SLV);
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DEFINE_QNODE(xm_ufs_card, SM8250_MASTER_UFS_CARD, 1, 8, SM8250_A2NOC_SNOC_SLV);
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DEFINE_QNODE(qnm_npu, SM8250_MASTER_NPU, 2, 32, SM8250_SLAVE_CDSP_MEM_NOC);
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DEFINE_QNODE(qnm_snoc, SM8250_SNOC_CNOC_MAS, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
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DEFINE_QNODE(xm_qdss_dap, SM8250_MASTER_QDSS_DAP, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_CNOC_A2NOC, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
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DEFINE_QNODE(qhm_cnoc_dc_noc, SM8250_MASTER_CNOC_DC_NOC, 1, 4, SM8250_SLAVE_GEM_NOC_CFG, SM8250_SLAVE_LLCC_CFG);
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DEFINE_QNODE(alm_gpu_tcu, SM8250_MASTER_GPU_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
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DEFINE_QNODE(alm_sys_tcu, SM8250_MASTER_SYS_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
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DEFINE_QNODE(chm_apps, SM8250_MASTER_AMPSS_M0, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
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DEFINE_QNODE(qhm_gemnoc_cfg, SM8250_MASTER_GEM_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_GEM_NOC_2, SM8250_SLAVE_SERVICE_GEM_NOC_1, SM8250_SLAVE_SERVICE_GEM_NOC);
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DEFINE_QNODE(qnm_cmpnoc, SM8250_MASTER_COMPUTE_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
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DEFINE_QNODE(qnm_gpu, SM8250_MASTER_GRAPHICS_3D, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
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DEFINE_QNODE(qnm_mnoc_hf, SM8250_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC);
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DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
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DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
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DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAVE_LLCC);
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DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
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DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0);
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DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_MNOC);
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DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
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DEFINE_QNODE(qnm_camnoc_icp, SM8250_MASTER_CAMNOC_ICP, 1, 8, SM8250_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qnm_camnoc_sf, SM8250_MASTER_CAMNOC_SF, 2, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qnm_video0, SM8250_MASTER_VIDEO_P0, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qnm_video1, SM8250_MASTER_VIDEO_P1, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qnm_video_cvp, SM8250_MASTER_VIDEO_PROC, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(qxm_mdp0, SM8250_MASTER_MDP_PORT0, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
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DEFINE_QNODE(qxm_mdp1, SM8250_MASTER_MDP_PORT1, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
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DEFINE_QNODE(qxm_rot, SM8250_MASTER_ROTATOR, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
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DEFINE_QNODE(amm_npu_sys, SM8250_MASTER_NPU_SYS, 4, 32, SM8250_SLAVE_NPU_COMPUTE_NOC);
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DEFINE_QNODE(amm_npu_sys_cdp_w, SM8250_MASTER_NPU_CDP, 2, 16, SM8250_SLAVE_NPU_COMPUTE_NOC);
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DEFINE_QNODE(qhm_cfg, SM8250_MASTER_NPU_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_NPU_NOC, SM8250_SLAVE_ISENSE_CFG, SM8250_SLAVE_NPU_LLM_CFG, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, SM8250_SLAVE_NPU_CP, SM8250_SLAVE_NPU_TCM, SM8250_SLAVE_NPU_CAL_DP0, SM8250_SLAVE_NPU_CAL_DP1, SM8250_SLAVE_NPU_DPM);
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DEFINE_QNODE(qhm_snoc_cfg, SM8250_MASTER_SNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_SNOC);
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DEFINE_QNODE(qnm_aggre1_noc, SM8250_A1NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
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DEFINE_QNODE(qnm_aggre2_noc, SM8250_A2NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
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DEFINE_QNODE(qnm_gemnoc, SM8250_MASTER_GEM_NOC_SNOC, 1, 16, SM8250_SLAVE_PIMEM, SM8250_SLAVE_OCIMEM, SM8250_SLAVE_APPSS, SM8250_SNOC_CNOC_SLV, SM8250_SLAVE_TCU, SM8250_SLAVE_QDSS_STM);
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DEFINE_QNODE(qnm_gemnoc_pcie, SM8250_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8250_SLAVE_PCIE_2, SM8250_SLAVE_PCIE_0, SM8250_SLAVE_PCIE_1);
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DEFINE_QNODE(qxm_pimem, SM8250_MASTER_PIMEM, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
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DEFINE_QNODE(xm_gic, SM8250_MASTER_GIC, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
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DEFINE_QNODE(qns_a1noc_snoc, SM8250_A1NOC_SNOC_SLV, 1, 16, SM8250_A1NOC_SNOC_MAS);
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DEFINE_QNODE(qns_pcie_modem_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
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DEFINE_QNODE(srvc_aggre1_noc, SM8250_SLAVE_SERVICE_A1NOC, 1, 4);
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DEFINE_QNODE(qns_a2noc_snoc, SM8250_A2NOC_SNOC_SLV, 1, 16, SM8250_A2NOC_SNOC_MAS);
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DEFINE_QNODE(qns_pcie_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
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DEFINE_QNODE(srvc_aggre2_noc, SM8250_SLAVE_SERVICE_A2NOC, 1, 4);
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DEFINE_QNODE(qns_cdsp_mem_noc, SM8250_SLAVE_CDSP_MEM_NOC, 2, 32, SM8250_MASTER_COMPUTE_NOC);
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DEFINE_QNODE(qhs_a1_noc_cfg, SM8250_SLAVE_A1NOC_CFG, 1, 4, SM8250_MASTER_A1NOC_CFG);
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DEFINE_QNODE(qhs_a2_noc_cfg, SM8250_SLAVE_A2NOC_CFG, 1, 4, SM8250_MASTER_A2NOC_CFG);
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DEFINE_QNODE(qhs_ahb2phy0, SM8250_SLAVE_AHB2PHY_SOUTH, 1, 4);
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DEFINE_QNODE(qhs_ahb2phy1, SM8250_SLAVE_AHB2PHY_NORTH, 1, 4);
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DEFINE_QNODE(qhs_aoss, SM8250_SLAVE_AOSS, 1, 4);
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DEFINE_QNODE(qhs_camera_cfg, SM8250_SLAVE_CAMERA_CFG, 1, 4);
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DEFINE_QNODE(qhs_clk_ctl, SM8250_SLAVE_CLK_CTL, 1, 4);
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DEFINE_QNODE(qhs_compute_dsp, SM8250_SLAVE_CDSP_CFG, 1, 4);
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DEFINE_QNODE(qhs_cpr_cx, SM8250_SLAVE_RBCPR_CX_CFG, 1, 4);
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DEFINE_QNODE(qhs_cpr_mmcx, SM8250_SLAVE_RBCPR_MMCX_CFG, 1, 4);
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DEFINE_QNODE(qhs_cpr_mx, SM8250_SLAVE_RBCPR_MX_CFG, 1, 4);
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DEFINE_QNODE(qhs_crypto0_cfg, SM8250_SLAVE_CRYPTO_0_CFG, 1, 4);
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DEFINE_QNODE(qhs_cx_rdpm, SM8250_SLAVE_CX_RDPM, 1, 4);
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DEFINE_QNODE(qhs_dcc_cfg, SM8250_SLAVE_DCC_CFG, 1, 4);
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DEFINE_QNODE(qhs_ddrss_cfg, SM8250_SLAVE_CNOC_DDRSS, 1, 4, SM8250_MASTER_CNOC_DC_NOC);
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DEFINE_QNODE(qhs_display_cfg, SM8250_SLAVE_DISPLAY_CFG, 1, 4);
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DEFINE_QNODE(qhs_gpuss_cfg, SM8250_SLAVE_GRAPHICS_3D_CFG, 1, 8);
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DEFINE_QNODE(qhs_imem_cfg, SM8250_SLAVE_IMEM_CFG, 1, 4);
101
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DEFINE_QNODE(qhs_ipa, SM8250_SLAVE_IPA_CFG, 1, 4);
102
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DEFINE_QNODE(qhs_ipc_router, SM8250_SLAVE_IPC_ROUTER_CFG, 1, 4);
103
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DEFINE_QNODE(qhs_lpass_cfg, SM8250_SLAVE_LPASS, 1, 4);
104
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DEFINE_QNODE(qhs_mnoc_cfg, SM8250_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8250_MASTER_CNOC_MNOC_CFG);
105
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DEFINE_QNODE(qhs_npu_cfg, SM8250_SLAVE_NPU_CFG, 1, 4, SM8250_MASTER_NPU_NOC_CFG);
106
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DEFINE_QNODE(qhs_pcie0_cfg, SM8250_SLAVE_PCIE_0_CFG, 1, 4);
107
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DEFINE_QNODE(qhs_pcie1_cfg, SM8250_SLAVE_PCIE_1_CFG, 1, 4);
108
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DEFINE_QNODE(qhs_pcie_modem_cfg, SM8250_SLAVE_PCIE_2_CFG, 1, 4);
109
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DEFINE_QNODE(qhs_pdm, SM8250_SLAVE_PDM, 1, 4);
110
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DEFINE_QNODE(qhs_pimem_cfg, SM8250_SLAVE_PIMEM_CFG, 1, 4);
111
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DEFINE_QNODE(qhs_prng, SM8250_SLAVE_PRNG, 1, 4);
112
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DEFINE_QNODE(qhs_qdss_cfg, SM8250_SLAVE_QDSS_CFG, 1, 4);
113
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DEFINE_QNODE(qhs_qspi, SM8250_SLAVE_QSPI_0, 1, 4);
114
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DEFINE_QNODE(qhs_qup0, SM8250_SLAVE_QUP_0, 1, 4);
115
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DEFINE_QNODE(qhs_qup1, SM8250_SLAVE_QUP_1, 1, 4);
116
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DEFINE_QNODE(qhs_qup2, SM8250_SLAVE_QUP_2, 1, 4);
117
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DEFINE_QNODE(qhs_sdc2, SM8250_SLAVE_SDCC_2, 1, 4);
118
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DEFINE_QNODE(qhs_sdc4, SM8250_SLAVE_SDCC_4, 1, 4);
119
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DEFINE_QNODE(qhs_snoc_cfg, SM8250_SLAVE_SNOC_CFG, 1, 4, SM8250_MASTER_SNOC_CFG);
120
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DEFINE_QNODE(qhs_tcsr, SM8250_SLAVE_TCSR, 1, 4);
121
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DEFINE_QNODE(qhs_tlmm0, SM8250_SLAVE_TLMM_NORTH, 1, 4);
122
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DEFINE_QNODE(qhs_tlmm1, SM8250_SLAVE_TLMM_SOUTH, 1, 4);
123
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DEFINE_QNODE(qhs_tlmm2, SM8250_SLAVE_TLMM_WEST, 1, 4);
124
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DEFINE_QNODE(qhs_tsif, SM8250_SLAVE_TSIF, 1, 4);
125
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DEFINE_QNODE(qhs_ufs_card_cfg, SM8250_SLAVE_UFS_CARD_CFG, 1, 4);
126
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DEFINE_QNODE(qhs_ufs_mem_cfg, SM8250_SLAVE_UFS_MEM_CFG, 1, 4);
127
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DEFINE_QNODE(qhs_usb3_0, SM8250_SLAVE_USB3, 1, 4);
128
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DEFINE_QNODE(qhs_usb3_1, SM8250_SLAVE_USB3_1, 1, 4);
129
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DEFINE_QNODE(qhs_venus_cfg, SM8250_SLAVE_VENUS_CFG, 1, 4);
130
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DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8250_SLAVE_VSENSE_CTRL_CFG, 1, 4);
131
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DEFINE_QNODE(qns_cnoc_a2noc, SM8250_SLAVE_CNOC_A2NOC, 1, 8, SM8250_MASTER_CNOC_A2NOC);
132
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DEFINE_QNODE(srvc_cnoc, SM8250_SLAVE_SERVICE_CNOC, 1, 4);
133
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DEFINE_QNODE(qhs_llcc, SM8250_SLAVE_LLCC_CFG, 1, 4);
134
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DEFINE_QNODE(qhs_memnoc, SM8250_SLAVE_GEM_NOC_CFG, 1, 4, SM8250_MASTER_GEM_NOC_CFG);
135
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DEFINE_QNODE(qns_gem_noc_snoc, SM8250_SLAVE_GEM_NOC_SNOC, 1, 16, SM8250_MASTER_GEM_NOC_SNOC);
136
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DEFINE_QNODE(qns_llcc, SM8250_SLAVE_LLCC, 4, 16, SM8250_MASTER_LLCC);
137
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DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MASTER_GEM_NOC_PCIE_SNOC);
138
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DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
139
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DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
140
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DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4);
141
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DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4);
142
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DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC);
143
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DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC);
144
-
DEFINE_QNODE(srvc_mnoc, SM8250_SLAVE_SERVICE_MNOC, 1, 4);
145
-
DEFINE_QNODE(qhs_cal_dp0, SM8250_SLAVE_NPU_CAL_DP0, 1, 4);
146
-
DEFINE_QNODE(qhs_cal_dp1, SM8250_SLAVE_NPU_CAL_DP1, 1, 4);
147
-
DEFINE_QNODE(qhs_cp, SM8250_SLAVE_NPU_CP, 1, 4);
148
-
DEFINE_QNODE(qhs_dma_bwmon, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
149
-
DEFINE_QNODE(qhs_dpm, SM8250_SLAVE_NPU_DPM, 1, 4);
150
-
DEFINE_QNODE(qhs_isense, SM8250_SLAVE_ISENSE_CFG, 1, 4);
151
-
DEFINE_QNODE(qhs_llm, SM8250_SLAVE_NPU_LLM_CFG, 1, 4);
152
-
DEFINE_QNODE(qhs_tcm, SM8250_SLAVE_NPU_TCM, 1, 4);
153
-
DEFINE_QNODE(qns_npu_sys, SM8250_SLAVE_NPU_COMPUTE_NOC, 2, 32);
154
-
DEFINE_QNODE(srvc_noc, SM8250_SLAVE_SERVICE_NPU_NOC, 1, 4);
155
-
DEFINE_QNODE(qhs_apss, SM8250_SLAVE_APPSS, 1, 8);
156
-
DEFINE_QNODE(qns_cnoc, SM8250_SNOC_CNOC_SLV, 1, 8, SM8250_SNOC_CNOC_MAS);
157
-
DEFINE_QNODE(qns_gemnoc_gc, SM8250_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8250_MASTER_SNOC_GC_MEM_NOC);
158
-
DEFINE_QNODE(qns_gemnoc_sf, SM8250_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8250_MASTER_SNOC_SF_MEM_NOC);
159
-
DEFINE_QNODE(qxs_imem, SM8250_SLAVE_OCIMEM, 1, 8);
160
-
DEFINE_QNODE(qxs_pimem, SM8250_SLAVE_PIMEM, 1, 8);
161
-
DEFINE_QNODE(srvc_snoc, SM8250_SLAVE_SERVICE_SNOC, 1, 4);
162
-
DEFINE_QNODE(xs_pcie_0, SM8250_SLAVE_PCIE_0, 1, 8);
163
-
DEFINE_QNODE(xs_pcie_1, SM8250_SLAVE_PCIE_1, 1, 8);
164
-
DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8);
165
-
DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4);
166
-
DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8);
19
+
static struct qcom_icc_node qhm_a1noc_cfg = {
20
+
.name = "qhm_a1noc_cfg",
21
+
.id = SM8250_MASTER_A1NOC_CFG,
22
+
.channels = 1,
23
+
.buswidth = 4,
24
+
.num_links = 1,
25
+
.links = { SM8250_SLAVE_SERVICE_A1NOC },
26
+
};
27
+
28
+
static struct qcom_icc_node qhm_qspi = {
29
+
.name = "qhm_qspi",
30
+
.id = SM8250_MASTER_QSPI_0,
31
+
.channels = 1,
32
+
.buswidth = 4,
33
+
.num_links = 1,
34
+
.links = { SM8250_A1NOC_SNOC_SLV },
35
+
};
36
+
37
+
static struct qcom_icc_node qhm_qup1 = {
38
+
.name = "qhm_qup1",
39
+
.id = SM8250_MASTER_QUP_1,
40
+
.channels = 1,
41
+
.buswidth = 4,
42
+
.num_links = 1,
43
+
.links = { SM8250_A1NOC_SNOC_SLV },
44
+
};
45
+
46
+
static struct qcom_icc_node qhm_qup2 = {
47
+
.name = "qhm_qup2",
48
+
.id = SM8250_MASTER_QUP_2,
49
+
.channels = 1,
50
+
.buswidth = 4,
51
+
.num_links = 1,
52
+
.links = { SM8250_A1NOC_SNOC_SLV },
53
+
};
54
+
55
+
static struct qcom_icc_node qhm_tsif = {
56
+
.name = "qhm_tsif",
57
+
.id = SM8250_MASTER_TSIF,
58
+
.channels = 1,
59
+
.buswidth = 4,
60
+
.num_links = 1,
61
+
.links = { SM8250_A1NOC_SNOC_SLV },
62
+
};
63
+
64
+
static struct qcom_icc_node xm_pcie3_modem = {
65
+
.name = "xm_pcie3_modem",
66
+
.id = SM8250_MASTER_PCIE_2,
67
+
.channels = 1,
68
+
.buswidth = 8,
69
+
.num_links = 1,
70
+
.links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 },
71
+
};
72
+
73
+
static struct qcom_icc_node xm_sdc4 = {
74
+
.name = "xm_sdc4",
75
+
.id = SM8250_MASTER_SDCC_4,
76
+
.channels = 1,
77
+
.buswidth = 8,
78
+
.num_links = 1,
79
+
.links = { SM8250_A1NOC_SNOC_SLV },
80
+
};
81
+
82
+
static struct qcom_icc_node xm_ufs_mem = {
83
+
.name = "xm_ufs_mem",
84
+
.id = SM8250_MASTER_UFS_MEM,
85
+
.channels = 1,
86
+
.buswidth = 8,
87
+
.num_links = 1,
88
+
.links = { SM8250_A1NOC_SNOC_SLV },
89
+
};
90
+
91
+
static struct qcom_icc_node xm_usb3_0 = {
92
+
.name = "xm_usb3_0",
93
+
.id = SM8250_MASTER_USB3,
94
+
.channels = 1,
95
+
.buswidth = 8,
96
+
.num_links = 1,
97
+
.links = { SM8250_A1NOC_SNOC_SLV },
98
+
};
99
+
100
+
static struct qcom_icc_node xm_usb3_1 = {
101
+
.name = "xm_usb3_1",
102
+
.id = SM8250_MASTER_USB3_1,
103
+
.channels = 1,
104
+
.buswidth = 8,
105
+
.num_links = 1,
106
+
.links = { SM8250_A1NOC_SNOC_SLV },
107
+
};
108
+
109
+
static struct qcom_icc_node qhm_a2noc_cfg = {
110
+
.name = "qhm_a2noc_cfg",
111
+
.id = SM8250_MASTER_A2NOC_CFG,
112
+
.channels = 1,
113
+
.buswidth = 4,
114
+
.num_links = 1,
115
+
.links = { SM8250_SLAVE_SERVICE_A2NOC },
116
+
};
117
+
118
+
static struct qcom_icc_node qhm_qdss_bam = {
119
+
.name = "qhm_qdss_bam",
120
+
.id = SM8250_MASTER_QDSS_BAM,
121
+
.channels = 1,
122
+
.buswidth = 4,
123
+
.num_links = 1,
124
+
.links = { SM8250_A2NOC_SNOC_SLV },
125
+
};
126
+
127
+
static struct qcom_icc_node qhm_qup0 = {
128
+
.name = "qhm_qup0",
129
+
.id = SM8250_MASTER_QUP_0,
130
+
.channels = 1,
131
+
.buswidth = 4,
132
+
.num_links = 1,
133
+
.links = { SM8250_A2NOC_SNOC_SLV },
134
+
};
135
+
136
+
static struct qcom_icc_node qnm_cnoc = {
137
+
.name = "qnm_cnoc",
138
+
.id = SM8250_MASTER_CNOC_A2NOC,
139
+
.channels = 1,
140
+
.buswidth = 8,
141
+
.num_links = 1,
142
+
.links = { SM8250_A2NOC_SNOC_SLV },
143
+
};
144
+
145
+
static struct qcom_icc_node qxm_crypto = {
146
+
.name = "qxm_crypto",
147
+
.id = SM8250_MASTER_CRYPTO_CORE_0,
148
+
.channels = 1,
149
+
.buswidth = 8,
150
+
.num_links = 1,
151
+
.links = { SM8250_A2NOC_SNOC_SLV },
152
+
};
153
+
154
+
static struct qcom_icc_node qxm_ipa = {
155
+
.name = "qxm_ipa",
156
+
.id = SM8250_MASTER_IPA,
157
+
.channels = 1,
158
+
.buswidth = 8,
159
+
.num_links = 1,
160
+
.links = { SM8250_A2NOC_SNOC_SLV },
161
+
};
162
+
163
+
static struct qcom_icc_node xm_pcie3_0 = {
164
+
.name = "xm_pcie3_0",
165
+
.id = SM8250_MASTER_PCIE,
166
+
.channels = 1,
167
+
.buswidth = 8,
168
+
.num_links = 1,
169
+
.links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC },
170
+
};
171
+
172
+
static struct qcom_icc_node xm_pcie3_1 = {
173
+
.name = "xm_pcie3_1",
174
+
.id = SM8250_MASTER_PCIE_1,
175
+
.channels = 1,
176
+
.buswidth = 8,
177
+
.num_links = 1,
178
+
.links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC },
179
+
};
180
+
181
+
static struct qcom_icc_node xm_qdss_etr = {
182
+
.name = "xm_qdss_etr",
183
+
.id = SM8250_MASTER_QDSS_ETR,
184
+
.channels = 1,
185
+
.buswidth = 8,
186
+
.num_links = 1,
187
+
.links = { SM8250_A2NOC_SNOC_SLV },
188
+
};
189
+
190
+
static struct qcom_icc_node xm_sdc2 = {
191
+
.name = "xm_sdc2",
192
+
.id = SM8250_MASTER_SDCC_2,
193
+
.channels = 1,
194
+
.buswidth = 8,
195
+
.num_links = 1,
196
+
.links = { SM8250_A2NOC_SNOC_SLV },
197
+
};
198
+
199
+
static struct qcom_icc_node xm_ufs_card = {
200
+
.name = "xm_ufs_card",
201
+
.id = SM8250_MASTER_UFS_CARD,
202
+
.channels = 1,
203
+
.buswidth = 8,
204
+
.num_links = 1,
205
+
.links = { SM8250_A2NOC_SNOC_SLV },
206
+
};
207
+
208
+
static struct qcom_icc_node qnm_npu = {
209
+
.name = "qnm_npu",
210
+
.id = SM8250_MASTER_NPU,
211
+
.channels = 2,
212
+
.buswidth = 32,
213
+
.num_links = 1,
214
+
.links = { SM8250_SLAVE_CDSP_MEM_NOC },
215
+
};
216
+
217
+
static struct qcom_icc_node qnm_snoc = {
218
+
.name = "qnm_snoc",
219
+
.id = SM8250_SNOC_CNOC_MAS,
220
+
.channels = 1,
221
+
.buswidth = 8,
222
+
.num_links = 49,
223
+
.links = { SM8250_SLAVE_CDSP_CFG,
224
+
SM8250_SLAVE_CAMERA_CFG,
225
+
SM8250_SLAVE_TLMM_SOUTH,
226
+
SM8250_SLAVE_TLMM_NORTH,
227
+
SM8250_SLAVE_SDCC_4,
228
+
SM8250_SLAVE_TLMM_WEST,
229
+
SM8250_SLAVE_SDCC_2,
230
+
SM8250_SLAVE_CNOC_MNOC_CFG,
231
+
SM8250_SLAVE_UFS_MEM_CFG,
232
+
SM8250_SLAVE_SNOC_CFG,
233
+
SM8250_SLAVE_PDM,
234
+
SM8250_SLAVE_CX_RDPM,
235
+
SM8250_SLAVE_PCIE_1_CFG,
236
+
SM8250_SLAVE_A2NOC_CFG,
237
+
SM8250_SLAVE_QDSS_CFG,
238
+
SM8250_SLAVE_DISPLAY_CFG,
239
+
SM8250_SLAVE_PCIE_2_CFG,
240
+
SM8250_SLAVE_TCSR,
241
+
SM8250_SLAVE_DCC_CFG,
242
+
SM8250_SLAVE_CNOC_DDRSS,
243
+
SM8250_SLAVE_IPC_ROUTER_CFG,
244
+
SM8250_SLAVE_PCIE_0_CFG,
245
+
SM8250_SLAVE_RBCPR_MMCX_CFG,
246
+
SM8250_SLAVE_NPU_CFG,
247
+
SM8250_SLAVE_AHB2PHY_SOUTH,
248
+
SM8250_SLAVE_AHB2PHY_NORTH,
249
+
SM8250_SLAVE_GRAPHICS_3D_CFG,
250
+
SM8250_SLAVE_VENUS_CFG,
251
+
SM8250_SLAVE_TSIF,
252
+
SM8250_SLAVE_IPA_CFG,
253
+
SM8250_SLAVE_IMEM_CFG,
254
+
SM8250_SLAVE_USB3,
255
+
SM8250_SLAVE_SERVICE_CNOC,
256
+
SM8250_SLAVE_UFS_CARD_CFG,
257
+
SM8250_SLAVE_USB3_1,
258
+
SM8250_SLAVE_LPASS,
259
+
SM8250_SLAVE_RBCPR_CX_CFG,
260
+
SM8250_SLAVE_A1NOC_CFG,
261
+
SM8250_SLAVE_AOSS,
262
+
SM8250_SLAVE_PRNG,
263
+
SM8250_SLAVE_VSENSE_CTRL_CFG,
264
+
SM8250_SLAVE_QSPI_0,
265
+
SM8250_SLAVE_CRYPTO_0_CFG,
266
+
SM8250_SLAVE_PIMEM_CFG,
267
+
SM8250_SLAVE_RBCPR_MX_CFG,
268
+
SM8250_SLAVE_QUP_0,
269
+
SM8250_SLAVE_QUP_1,
270
+
SM8250_SLAVE_QUP_2,
271
+
SM8250_SLAVE_CLK_CTL
272
+
},
273
+
};
274
+
275
+
static struct qcom_icc_node xm_qdss_dap = {
276
+
.name = "xm_qdss_dap",
277
+
.id = SM8250_MASTER_QDSS_DAP,
278
+
.channels = 1,
279
+
.buswidth = 8,
280
+
.num_links = 50,
281
+
.links = { SM8250_SLAVE_CDSP_CFG,
282
+
SM8250_SLAVE_CAMERA_CFG,
283
+
SM8250_SLAVE_TLMM_SOUTH,
284
+
SM8250_SLAVE_TLMM_NORTH,
285
+
SM8250_SLAVE_SDCC_4,
286
+
SM8250_SLAVE_TLMM_WEST,
287
+
SM8250_SLAVE_SDCC_2,
288
+
SM8250_SLAVE_CNOC_MNOC_CFG,
289
+
SM8250_SLAVE_UFS_MEM_CFG,
290
+
SM8250_SLAVE_SNOC_CFG,
291
+
SM8250_SLAVE_PDM,
292
+
SM8250_SLAVE_CX_RDPM,
293
+
SM8250_SLAVE_PCIE_1_CFG,
294
+
SM8250_SLAVE_A2NOC_CFG,
295
+
SM8250_SLAVE_QDSS_CFG,
296
+
SM8250_SLAVE_DISPLAY_CFG,
297
+
SM8250_SLAVE_PCIE_2_CFG,
298
+
SM8250_SLAVE_TCSR,
299
+
SM8250_SLAVE_DCC_CFG,
300
+
SM8250_SLAVE_CNOC_DDRSS,
301
+
SM8250_SLAVE_IPC_ROUTER_CFG,
302
+
SM8250_SLAVE_CNOC_A2NOC,
303
+
SM8250_SLAVE_PCIE_0_CFG,
304
+
SM8250_SLAVE_RBCPR_MMCX_CFG,
305
+
SM8250_SLAVE_NPU_CFG,
306
+
SM8250_SLAVE_AHB2PHY_SOUTH,
307
+
SM8250_SLAVE_AHB2PHY_NORTH,
308
+
SM8250_SLAVE_GRAPHICS_3D_CFG,
309
+
SM8250_SLAVE_VENUS_CFG,
310
+
SM8250_SLAVE_TSIF,
311
+
SM8250_SLAVE_IPA_CFG,
312
+
SM8250_SLAVE_IMEM_CFG,
313
+
SM8250_SLAVE_USB3,
314
+
SM8250_SLAVE_SERVICE_CNOC,
315
+
SM8250_SLAVE_UFS_CARD_CFG,
316
+
SM8250_SLAVE_USB3_1,
317
+
SM8250_SLAVE_LPASS,
318
+
SM8250_SLAVE_RBCPR_CX_CFG,
319
+
SM8250_SLAVE_A1NOC_CFG,
320
+
SM8250_SLAVE_AOSS,
321
+
SM8250_SLAVE_PRNG,
322
+
SM8250_SLAVE_VSENSE_CTRL_CFG,
323
+
SM8250_SLAVE_QSPI_0,
324
+
SM8250_SLAVE_CRYPTO_0_CFG,
325
+
SM8250_SLAVE_PIMEM_CFG,
326
+
SM8250_SLAVE_RBCPR_MX_CFG,
327
+
SM8250_SLAVE_QUP_0,
328
+
SM8250_SLAVE_QUP_1,
329
+
SM8250_SLAVE_QUP_2,
330
+
SM8250_SLAVE_CLK_CTL
331
+
},
332
+
};
333
+
334
+
static struct qcom_icc_node qhm_cnoc_dc_noc = {
335
+
.name = "qhm_cnoc_dc_noc",
336
+
.id = SM8250_MASTER_CNOC_DC_NOC,
337
+
.channels = 1,
338
+
.buswidth = 4,
339
+
.num_links = 2,
340
+
.links = { SM8250_SLAVE_GEM_NOC_CFG,
341
+
SM8250_SLAVE_LLCC_CFG
342
+
},
343
+
};
344
+
345
+
static struct qcom_icc_node alm_gpu_tcu = {
346
+
.name = "alm_gpu_tcu",
347
+
.id = SM8250_MASTER_GPU_TCU,
348
+
.channels = 1,
349
+
.buswidth = 8,
350
+
.num_links = 2,
351
+
.links = { SM8250_SLAVE_LLCC,
352
+
SM8250_SLAVE_GEM_NOC_SNOC
353
+
},
354
+
};
355
+
356
+
static struct qcom_icc_node alm_sys_tcu = {
357
+
.name = "alm_sys_tcu",
358
+
.id = SM8250_MASTER_SYS_TCU,
359
+
.channels = 1,
360
+
.buswidth = 8,
361
+
.num_links = 2,
362
+
.links = { SM8250_SLAVE_LLCC,
363
+
SM8250_SLAVE_GEM_NOC_SNOC
364
+
},
365
+
};
366
+
367
+
static struct qcom_icc_node chm_apps = {
368
+
.name = "chm_apps",
369
+
.id = SM8250_MASTER_AMPSS_M0,
370
+
.channels = 2,
371
+
.buswidth = 32,
372
+
.num_links = 3,
373
+
.links = { SM8250_SLAVE_LLCC,
374
+
SM8250_SLAVE_GEM_NOC_SNOC,
375
+
SM8250_SLAVE_MEM_NOC_PCIE_SNOC
376
+
},
377
+
};
378
+
379
+
static struct qcom_icc_node qhm_gemnoc_cfg = {
380
+
.name = "qhm_gemnoc_cfg",
381
+
.id = SM8250_MASTER_GEM_NOC_CFG,
382
+
.channels = 1,
383
+
.buswidth = 4,
384
+
.num_links = 3,
385
+
.links = { SM8250_SLAVE_SERVICE_GEM_NOC_2,
386
+
SM8250_SLAVE_SERVICE_GEM_NOC_1,
387
+
SM8250_SLAVE_SERVICE_GEM_NOC
388
+
},
389
+
};
390
+
391
+
static struct qcom_icc_node qnm_cmpnoc = {
392
+
.name = "qnm_cmpnoc",
393
+
.id = SM8250_MASTER_COMPUTE_NOC,
394
+
.channels = 2,
395
+
.buswidth = 32,
396
+
.num_links = 2,
397
+
.links = { SM8250_SLAVE_LLCC,
398
+
SM8250_SLAVE_GEM_NOC_SNOC
399
+
},
400
+
};
401
+
402
+
static struct qcom_icc_node qnm_gpu = {
403
+
.name = "qnm_gpu",
404
+
.id = SM8250_MASTER_GRAPHICS_3D,
405
+
.channels = 2,
406
+
.buswidth = 32,
407
+
.num_links = 2,
408
+
.links = { SM8250_SLAVE_LLCC,
409
+
SM8250_SLAVE_GEM_NOC_SNOC },
410
+
};
411
+
412
+
static struct qcom_icc_node qnm_mnoc_hf = {
413
+
.name = "qnm_mnoc_hf",
414
+
.id = SM8250_MASTER_MNOC_HF_MEM_NOC,
415
+
.channels = 2,
416
+
.buswidth = 32,
417
+
.num_links = 1,
418
+
.links = { SM8250_SLAVE_LLCC },
419
+
};
420
+
421
+
static struct qcom_icc_node qnm_mnoc_sf = {
422
+
.name = "qnm_mnoc_sf",
423
+
.id = SM8250_MASTER_MNOC_SF_MEM_NOC,
424
+
.channels = 2,
425
+
.buswidth = 32,
426
+
.num_links = 2,
427
+
.links = { SM8250_SLAVE_LLCC,
428
+
SM8250_SLAVE_GEM_NOC_SNOC
429
+
},
430
+
};
431
+
432
+
static struct qcom_icc_node qnm_pcie = {
433
+
.name = "qnm_pcie",
434
+
.id = SM8250_MASTER_ANOC_PCIE_GEM_NOC,
435
+
.channels = 1,
436
+
.buswidth = 16,
437
+
.num_links = 2,
438
+
.links = { SM8250_SLAVE_LLCC,
439
+
SM8250_SLAVE_GEM_NOC_SNOC
440
+
},
441
+
};
442
+
443
+
static struct qcom_icc_node qnm_snoc_gc = {
444
+
.name = "qnm_snoc_gc",
445
+
.id = SM8250_MASTER_SNOC_GC_MEM_NOC,
446
+
.channels = 1,
447
+
.buswidth = 8,
448
+
.num_links = 1,
449
+
.links = { SM8250_SLAVE_LLCC },
450
+
};
451
+
452
+
static struct qcom_icc_node qnm_snoc_sf = {
453
+
.name = "qnm_snoc_sf",
454
+
.id = SM8250_MASTER_SNOC_SF_MEM_NOC,
455
+
.channels = 1,
456
+
.buswidth = 16,
457
+
.num_links = 3,
458
+
.links = { SM8250_SLAVE_LLCC,
459
+
SM8250_SLAVE_GEM_NOC_SNOC,
460
+
SM8250_SLAVE_MEM_NOC_PCIE_SNOC
461
+
},
462
+
};
463
+
464
+
static struct qcom_icc_node llcc_mc = {
465
+
.name = "llcc_mc",
466
+
.id = SM8250_MASTER_LLCC,
467
+
.channels = 4,
468
+
.buswidth = 4,
469
+
.num_links = 1,
470
+
.links = { SM8250_SLAVE_EBI_CH0 },
471
+
};
472
+
473
+
static struct qcom_icc_node qhm_mnoc_cfg = {
474
+
.name = "qhm_mnoc_cfg",
475
+
.id = SM8250_MASTER_CNOC_MNOC_CFG,
476
+
.channels = 1,
477
+
.buswidth = 4,
478
+
.num_links = 1,
479
+
.links = { SM8250_SLAVE_SERVICE_MNOC },
480
+
};
481
+
482
+
static struct qcom_icc_node qnm_camnoc_hf = {
483
+
.name = "qnm_camnoc_hf",
484
+
.id = SM8250_MASTER_CAMNOC_HF,
485
+
.channels = 2,
486
+
.buswidth = 32,
487
+
.num_links = 1,
488
+
.links = { SM8250_SLAVE_MNOC_HF_MEM_NOC },
489
+
};
490
+
491
+
static struct qcom_icc_node qnm_camnoc_icp = {
492
+
.name = "qnm_camnoc_icp",
493
+
.id = SM8250_MASTER_CAMNOC_ICP,
494
+
.channels = 1,
495
+
.buswidth = 8,
496
+
.num_links = 1,
497
+
.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
498
+
};
499
+
500
+
static struct qcom_icc_node qnm_camnoc_sf = {
501
+
.name = "qnm_camnoc_sf",
502
+
.id = SM8250_MASTER_CAMNOC_SF,
503
+
.channels = 2,
504
+
.buswidth = 32,
505
+
.num_links = 1,
506
+
.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
507
+
};
508
+
509
+
static struct qcom_icc_node qnm_video0 = {
510
+
.name = "qnm_video0",
511
+
.id = SM8250_MASTER_VIDEO_P0,
512
+
.channels = 1,
513
+
.buswidth = 32,
514
+
.num_links = 1,
515
+
.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
516
+
};
517
+
518
+
static struct qcom_icc_node qnm_video1 = {
519
+
.name = "qnm_video1",
520
+
.id = SM8250_MASTER_VIDEO_P1,
521
+
.channels = 1,
522
+
.buswidth = 32,
523
+
.num_links = 1,
524
+
.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
525
+
};
526
+
527
+
static struct qcom_icc_node qnm_video_cvp = {
528
+
.name = "qnm_video_cvp",
529
+
.id = SM8250_MASTER_VIDEO_PROC,
530
+
.channels = 1,
531
+
.buswidth = 32,
532
+
.num_links = 1,
533
+
.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
534
+
};
535
+
536
+
static struct qcom_icc_node qxm_mdp0 = {
537
+
.name = "qxm_mdp0",
538
+
.id = SM8250_MASTER_MDP_PORT0,
539
+
.channels = 1,
540
+
.buswidth = 32,
541
+
.num_links = 1,
542
+
.links = { SM8250_SLAVE_MNOC_HF_MEM_NOC },
543
+
};
544
+
545
+
static struct qcom_icc_node qxm_mdp1 = {
546
+
.name = "qxm_mdp1",
547
+
.id = SM8250_MASTER_MDP_PORT1,
548
+
.channels = 1,
549
+
.buswidth = 32,
550
+
.num_links = 1,
551
+
.links = { SM8250_SLAVE_MNOC_HF_MEM_NOC },
552
+
};
553
+
554
+
static struct qcom_icc_node qxm_rot = {
555
+
.name = "qxm_rot",
556
+
.id = SM8250_MASTER_ROTATOR,
557
+
.channels = 1,
558
+
.buswidth = 32,
559
+
.num_links = 1,
560
+
.links = { SM8250_SLAVE_MNOC_SF_MEM_NOC },
561
+
};
562
+
563
+
static struct qcom_icc_node amm_npu_sys = {
564
+
.name = "amm_npu_sys",
565
+
.id = SM8250_MASTER_NPU_SYS,
566
+
.channels = 4,
567
+
.buswidth = 32,
568
+
.num_links = 1,
569
+
.links = { SM8250_SLAVE_NPU_COMPUTE_NOC },
570
+
};
571
+
572
+
static struct qcom_icc_node amm_npu_sys_cdp_w = {
573
+
.name = "amm_npu_sys_cdp_w",
574
+
.id = SM8250_MASTER_NPU_CDP,
575
+
.channels = 2,
576
+
.buswidth = 16,
577
+
.num_links = 1,
578
+
.links = { SM8250_SLAVE_NPU_COMPUTE_NOC },
579
+
};
580
+
581
+
static struct qcom_icc_node qhm_cfg = {
582
+
.name = "qhm_cfg",
583
+
.id = SM8250_MASTER_NPU_NOC_CFG,
584
+
.channels = 1,
585
+
.buswidth = 4,
586
+
.num_links = 9,
587
+
.links = { SM8250_SLAVE_SERVICE_NPU_NOC,
588
+
SM8250_SLAVE_ISENSE_CFG,
589
+
SM8250_SLAVE_NPU_LLM_CFG,
590
+
SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG,
591
+
SM8250_SLAVE_NPU_CP,
592
+
SM8250_SLAVE_NPU_TCM,
593
+
SM8250_SLAVE_NPU_CAL_DP0,
594
+
SM8250_SLAVE_NPU_CAL_DP1,
595
+
SM8250_SLAVE_NPU_DPM
596
+
},
597
+
};
598
+
599
+
static struct qcom_icc_node qhm_snoc_cfg = {
600
+
.name = "qhm_snoc_cfg",
601
+
.id = SM8250_MASTER_SNOC_CFG,
602
+
.channels = 1,
603
+
.buswidth = 4,
604
+
.num_links = 1,
605
+
.links = { SM8250_SLAVE_SERVICE_SNOC },
606
+
};
607
+
608
+
static struct qcom_icc_node qnm_aggre1_noc = {
609
+
.name = "qnm_aggre1_noc",
610
+
.id = SM8250_A1NOC_SNOC_MAS,
611
+
.channels = 1,
612
+
.buswidth = 16,
613
+
.num_links = 1,
614
+
.links = { SM8250_SLAVE_SNOC_GEM_NOC_SF },
615
+
};
616
+
617
+
static struct qcom_icc_node qnm_aggre2_noc = {
618
+
.name = "qnm_aggre2_noc",
619
+
.id = SM8250_A2NOC_SNOC_MAS,
620
+
.channels = 1,
621
+
.buswidth = 16,
622
+
.num_links = 1,
623
+
.links = { SM8250_SLAVE_SNOC_GEM_NOC_SF },
624
+
};
625
+
626
+
static struct qcom_icc_node qnm_gemnoc = {
627
+
.name = "qnm_gemnoc",
628
+
.id = SM8250_MASTER_GEM_NOC_SNOC,
629
+
.channels = 1,
630
+
.buswidth = 16,
631
+
.num_links = 6,
632
+
.links = { SM8250_SLAVE_PIMEM,
633
+
SM8250_SLAVE_OCIMEM,
634
+
SM8250_SLAVE_APPSS,
635
+
SM8250_SNOC_CNOC_SLV,
636
+
SM8250_SLAVE_TCU,
637
+
SM8250_SLAVE_QDSS_STM
638
+
},
639
+
};
640
+
641
+
static struct qcom_icc_node qnm_gemnoc_pcie = {
642
+
.name = "qnm_gemnoc_pcie",
643
+
.id = SM8250_MASTER_GEM_NOC_PCIE_SNOC,
644
+
.channels = 1,
645
+
.buswidth = 8,
646
+
.num_links = 3,
647
+
.links = { SM8250_SLAVE_PCIE_2,
648
+
SM8250_SLAVE_PCIE_0,
649
+
SM8250_SLAVE_PCIE_1
650
+
},
651
+
};
652
+
653
+
static struct qcom_icc_node qxm_pimem = {
654
+
.name = "qxm_pimem",
655
+
.id = SM8250_MASTER_PIMEM,
656
+
.channels = 1,
657
+
.buswidth = 8,
658
+
.num_links = 1,
659
+
.links = { SM8250_SLAVE_SNOC_GEM_NOC_GC },
660
+
};
661
+
662
+
static struct qcom_icc_node xm_gic = {
663
+
.name = "xm_gic",
664
+
.id = SM8250_MASTER_GIC,
665
+
.channels = 1,
666
+
.buswidth = 8,
667
+
.num_links = 1,
668
+
.links = { SM8250_SLAVE_SNOC_GEM_NOC_GC },
669
+
};
670
+
671
+
static struct qcom_icc_node qns_a1noc_snoc = {
672
+
.name = "qns_a1noc_snoc",
673
+
.id = SM8250_A1NOC_SNOC_SLV,
674
+
.channels = 1,
675
+
.buswidth = 16,
676
+
.num_links = 1,
677
+
.links = { SM8250_A1NOC_SNOC_MAS },
678
+
};
679
+
680
+
static struct qcom_icc_node qns_pcie_modem_mem_noc = {
681
+
.name = "qns_pcie_modem_mem_noc",
682
+
.id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1,
683
+
.channels = 1,
684
+
.buswidth = 16,
685
+
.num_links = 1,
686
+
.links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC },
687
+
};
688
+
689
+
static struct qcom_icc_node srvc_aggre1_noc = {
690
+
.name = "srvc_aggre1_noc",
691
+
.id = SM8250_SLAVE_SERVICE_A1NOC,
692
+
.channels = 1,
693
+
.buswidth = 4,
694
+
};
695
+
696
+
static struct qcom_icc_node qns_a2noc_snoc = {
697
+
.name = "qns_a2noc_snoc",
698
+
.id = SM8250_A2NOC_SNOC_SLV,
699
+
.channels = 1,
700
+
.buswidth = 16,
701
+
.num_links = 1,
702
+
.links = { SM8250_A2NOC_SNOC_MAS },
703
+
};
704
+
705
+
static struct qcom_icc_node qns_pcie_mem_noc = {
706
+
.name = "qns_pcie_mem_noc",
707
+
.id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC,
708
+
.channels = 1,
709
+
.buswidth = 16,
710
+
.num_links = 1,
711
+
.links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC },
712
+
};
713
+
714
+
static struct qcom_icc_node srvc_aggre2_noc = {
715
+
.name = "srvc_aggre2_noc",
716
+
.id = SM8250_SLAVE_SERVICE_A2NOC,
717
+
.channels = 1,
718
+
.buswidth = 4,
719
+
};
720
+
721
+
static struct qcom_icc_node qns_cdsp_mem_noc = {
722
+
.name = "qns_cdsp_mem_noc",
723
+
.id = SM8250_SLAVE_CDSP_MEM_NOC,
724
+
.channels = 2,
725
+
.buswidth = 32,
726
+
.num_links = 1,
727
+
.links = { SM8250_MASTER_COMPUTE_NOC },
728
+
};
729
+
730
+
static struct qcom_icc_node qhs_a1_noc_cfg = {
731
+
.name = "qhs_a1_noc_cfg",
732
+
.id = SM8250_SLAVE_A1NOC_CFG,
733
+
.channels = 1,
734
+
.buswidth = 4,
735
+
.num_links = 1,
736
+
.links = { SM8250_MASTER_A1NOC_CFG },
737
+
};
738
+
739
+
static struct qcom_icc_node qhs_a2_noc_cfg = {
740
+
.name = "qhs_a2_noc_cfg",
741
+
.id = SM8250_SLAVE_A2NOC_CFG,
742
+
.channels = 1,
743
+
.buswidth = 4,
744
+
.num_links = 1,
745
+
.links = { SM8250_MASTER_A2NOC_CFG },
746
+
};
747
+
748
+
static struct qcom_icc_node qhs_ahb2phy0 = {
749
+
.name = "qhs_ahb2phy0",
750
+
.id = SM8250_SLAVE_AHB2PHY_SOUTH,
751
+
.channels = 1,
752
+
.buswidth = 4,
753
+
};
754
+
755
+
static struct qcom_icc_node qhs_ahb2phy1 = {
756
+
.name = "qhs_ahb2phy1",
757
+
.id = SM8250_SLAVE_AHB2PHY_NORTH,
758
+
.channels = 1,
759
+
.buswidth = 4,
760
+
};
761
+
762
+
static struct qcom_icc_node qhs_aoss = {
763
+
.name = "qhs_aoss",
764
+
.id = SM8250_SLAVE_AOSS,
765
+
.channels = 1,
766
+
.buswidth = 4,
767
+
};
768
+
769
+
static struct qcom_icc_node qhs_camera_cfg = {
770
+
.name = "qhs_camera_cfg",
771
+
.id = SM8250_SLAVE_CAMERA_CFG,
772
+
.channels = 1,
773
+
.buswidth = 4,
774
+
};
775
+
776
+
static struct qcom_icc_node qhs_clk_ctl = {
777
+
.name = "qhs_clk_ctl",
778
+
.id = SM8250_SLAVE_CLK_CTL,
779
+
.channels = 1,
780
+
.buswidth = 4,
781
+
};
782
+
783
+
static struct qcom_icc_node qhs_compute_dsp = {
784
+
.name = "qhs_compute_dsp",
785
+
.id = SM8250_SLAVE_CDSP_CFG,
786
+
.channels = 1,
787
+
.buswidth = 4,
788
+
};
789
+
790
+
static struct qcom_icc_node qhs_cpr_cx = {
791
+
.name = "qhs_cpr_cx",
792
+
.id = SM8250_SLAVE_RBCPR_CX_CFG,
793
+
.channels = 1,
794
+
.buswidth = 4,
795
+
};
796
+
797
+
static struct qcom_icc_node qhs_cpr_mmcx = {
798
+
.name = "qhs_cpr_mmcx",
799
+
.id = SM8250_SLAVE_RBCPR_MMCX_CFG,
800
+
.channels = 1,
801
+
.buswidth = 4,
802
+
};
803
+
804
+
static struct qcom_icc_node qhs_cpr_mx = {
805
+
.name = "qhs_cpr_mx",
806
+
.id = SM8250_SLAVE_RBCPR_MX_CFG,
807
+
.channels = 1,
808
+
.buswidth = 4,
809
+
};
810
+
811
+
static struct qcom_icc_node qhs_crypto0_cfg = {
812
+
.name = "qhs_crypto0_cfg",
813
+
.id = SM8250_SLAVE_CRYPTO_0_CFG,
814
+
.channels = 1,
815
+
.buswidth = 4,
816
+
};
817
+
818
+
static struct qcom_icc_node qhs_cx_rdpm = {
819
+
.name = "qhs_cx_rdpm",
820
+
.id = SM8250_SLAVE_CX_RDPM,
821
+
.channels = 1,
822
+
.buswidth = 4,
823
+
};
824
+
825
+
static struct qcom_icc_node qhs_dcc_cfg = {
826
+
.name = "qhs_dcc_cfg",
827
+
.id = SM8250_SLAVE_DCC_CFG,
828
+
.channels = 1,
829
+
.buswidth = 4,
830
+
};
831
+
832
+
static struct qcom_icc_node qhs_ddrss_cfg = {
833
+
.name = "qhs_ddrss_cfg",
834
+
.id = SM8250_SLAVE_CNOC_DDRSS,
835
+
.channels = 1,
836
+
.buswidth = 4,
837
+
.num_links = 1,
838
+
.links = { SM8250_MASTER_CNOC_DC_NOC },
839
+
};
840
+
841
+
static struct qcom_icc_node qhs_display_cfg = {
842
+
.name = "qhs_display_cfg",
843
+
.id = SM8250_SLAVE_DISPLAY_CFG,
844
+
.channels = 1,
845
+
.buswidth = 4,
846
+
};
847
+
848
+
static struct qcom_icc_node qhs_gpuss_cfg = {
849
+
.name = "qhs_gpuss_cfg",
850
+
.id = SM8250_SLAVE_GRAPHICS_3D_CFG,
851
+
.channels = 1,
852
+
.buswidth = 8,
853
+
};
854
+
855
+
static struct qcom_icc_node qhs_imem_cfg = {
856
+
.name = "qhs_imem_cfg",
857
+
.id = SM8250_SLAVE_IMEM_CFG,
858
+
.channels = 1,
859
+
.buswidth = 4,
860
+
};
861
+
862
+
static struct qcom_icc_node qhs_ipa = {
863
+
.name = "qhs_ipa",
864
+
.id = SM8250_SLAVE_IPA_CFG,
865
+
.channels = 1,
866
+
.buswidth = 4,
867
+
};
868
+
869
+
static struct qcom_icc_node qhs_ipc_router = {
870
+
.name = "qhs_ipc_router",
871
+
.id = SM8250_SLAVE_IPC_ROUTER_CFG,
872
+
.channels = 1,
873
+
.buswidth = 4,
874
+
};
875
+
876
+
static struct qcom_icc_node qhs_lpass_cfg = {
877
+
.name = "qhs_lpass_cfg",
878
+
.id = SM8250_SLAVE_LPASS,
879
+
.channels = 1,
880
+
.buswidth = 4,
881
+
};
882
+
883
+
static struct qcom_icc_node qhs_mnoc_cfg = {
884
+
.name = "qhs_mnoc_cfg",
885
+
.id = SM8250_SLAVE_CNOC_MNOC_CFG,
886
+
.channels = 1,
887
+
.buswidth = 4,
888
+
.num_links = 1,
889
+
.links = { SM8250_MASTER_CNOC_MNOC_CFG },
890
+
};
891
+
892
+
static struct qcom_icc_node qhs_npu_cfg = {
893
+
.name = "qhs_npu_cfg",
894
+
.id = SM8250_SLAVE_NPU_CFG,
895
+
.channels = 1,
896
+
.buswidth = 4,
897
+
.num_links = 1,
898
+
.links = { SM8250_MASTER_NPU_NOC_CFG },
899
+
};
900
+
901
+
static struct qcom_icc_node qhs_pcie0_cfg = {
902
+
.name = "qhs_pcie0_cfg",
903
+
.id = SM8250_SLAVE_PCIE_0_CFG,
904
+
.channels = 1,
905
+
.buswidth = 4,
906
+
};
907
+
908
+
static struct qcom_icc_node qhs_pcie1_cfg = {
909
+
.name = "qhs_pcie1_cfg",
910
+
.id = SM8250_SLAVE_PCIE_1_CFG,
911
+
.channels = 1,
912
+
.buswidth = 4,
913
+
};
914
+
915
+
static struct qcom_icc_node qhs_pcie_modem_cfg = {
916
+
.name = "qhs_pcie_modem_cfg",
917
+
.id = SM8250_SLAVE_PCIE_2_CFG,
918
+
.channels = 1,
919
+
.buswidth = 4,
920
+
};
921
+
922
+
static struct qcom_icc_node qhs_pdm = {
923
+
.name = "qhs_pdm",
924
+
.id = SM8250_SLAVE_PDM,
925
+
.channels = 1,
926
+
.buswidth = 4,
927
+
};
928
+
929
+
static struct qcom_icc_node qhs_pimem_cfg = {
930
+
.name = "qhs_pimem_cfg",
931
+
.id = SM8250_SLAVE_PIMEM_CFG,
932
+
.channels = 1,
933
+
.buswidth = 4,
934
+
};
935
+
936
+
static struct qcom_icc_node qhs_prng = {
937
+
.name = "qhs_prng",
938
+
.id = SM8250_SLAVE_PRNG,
939
+
.channels = 1,
940
+
.buswidth = 4,
941
+
};
942
+
943
+
static struct qcom_icc_node qhs_qdss_cfg = {
944
+
.name = "qhs_qdss_cfg",
945
+
.id = SM8250_SLAVE_QDSS_CFG,
946
+
.channels = 1,
947
+
.buswidth = 4,
948
+
};
949
+
950
+
static struct qcom_icc_node qhs_qspi = {
951
+
.name = "qhs_qspi",
952
+
.id = SM8250_SLAVE_QSPI_0,
953
+
.channels = 1,
954
+
.buswidth = 4,
955
+
};
956
+
957
+
static struct qcom_icc_node qhs_qup0 = {
958
+
.name = "qhs_qup0",
959
+
.id = SM8250_SLAVE_QUP_0,
960
+
.channels = 1,
961
+
.buswidth = 4,
962
+
};
963
+
964
+
static struct qcom_icc_node qhs_qup1 = {
965
+
.name = "qhs_qup1",
966
+
.id = SM8250_SLAVE_QUP_1,
967
+
.channels = 1,
968
+
.buswidth = 4,
969
+
};
970
+
971
+
static struct qcom_icc_node qhs_qup2 = {
972
+
.name = "qhs_qup2",
973
+
.id = SM8250_SLAVE_QUP_2,
974
+
.channels = 1,
975
+
.buswidth = 4,
976
+
};
977
+
978
+
static struct qcom_icc_node qhs_sdc2 = {
979
+
.name = "qhs_sdc2",
980
+
.id = SM8250_SLAVE_SDCC_2,
981
+
.channels = 1,
982
+
.buswidth = 4,
983
+
};
984
+
985
+
static struct qcom_icc_node qhs_sdc4 = {
986
+
.name = "qhs_sdc4",
987
+
.id = SM8250_SLAVE_SDCC_4,
988
+
.channels = 1,
989
+
.buswidth = 4,
990
+
};
991
+
992
+
static struct qcom_icc_node qhs_snoc_cfg = {
993
+
.name = "qhs_snoc_cfg",
994
+
.id = SM8250_SLAVE_SNOC_CFG,
995
+
.channels = 1,
996
+
.buswidth = 4,
997
+
.num_links = 1,
998
+
.links = { SM8250_MASTER_SNOC_CFG },
999
+
};
1000
+
1001
+
static struct qcom_icc_node qhs_tcsr = {
1002
+
.name = "qhs_tcsr",
1003
+
.id = SM8250_SLAVE_TCSR,
1004
+
.channels = 1,
1005
+
.buswidth = 4,
1006
+
};
1007
+
1008
+
static struct qcom_icc_node qhs_tlmm0 = {
1009
+
.name = "qhs_tlmm0",
1010
+
.id = SM8250_SLAVE_TLMM_NORTH,
1011
+
.channels = 1,
1012
+
.buswidth = 4,
1013
+
};
1014
+
1015
+
static struct qcom_icc_node qhs_tlmm1 = {
1016
+
.name = "qhs_tlmm1",
1017
+
.id = SM8250_SLAVE_TLMM_SOUTH,
1018
+
.channels = 1,
1019
+
.buswidth = 4,
1020
+
};
1021
+
1022
+
static struct qcom_icc_node qhs_tlmm2 = {
1023
+
.name = "qhs_tlmm2",
1024
+
.id = SM8250_SLAVE_TLMM_WEST,
1025
+
.channels = 1,
1026
+
.buswidth = 4,
1027
+
};
1028
+
1029
+
static struct qcom_icc_node qhs_tsif = {
1030
+
.name = "qhs_tsif",
1031
+
.id = SM8250_SLAVE_TSIF,
1032
+
.channels = 1,
1033
+
.buswidth = 4,
1034
+
};
1035
+
1036
+
static struct qcom_icc_node qhs_ufs_card_cfg = {
1037
+
.name = "qhs_ufs_card_cfg",
1038
+
.id = SM8250_SLAVE_UFS_CARD_CFG,
1039
+
.channels = 1,
1040
+
.buswidth = 4,
1041
+
};
1042
+
1043
+
static struct qcom_icc_node qhs_ufs_mem_cfg = {
1044
+
.name = "qhs_ufs_mem_cfg",
1045
+
.id = SM8250_SLAVE_UFS_MEM_CFG,
1046
+
.channels = 1,
1047
+
.buswidth = 4,
1048
+
};
1049
+
1050
+
static struct qcom_icc_node qhs_usb3_0 = {
1051
+
.name = "qhs_usb3_0",
1052
+
.id = SM8250_SLAVE_USB3,
1053
+
.channels = 1,
1054
+
.buswidth = 4,
1055
+
};
1056
+
1057
+
static struct qcom_icc_node qhs_usb3_1 = {
1058
+
.name = "qhs_usb3_1",
1059
+
.id = SM8250_SLAVE_USB3_1,
1060
+
.channels = 1,
1061
+
.buswidth = 4,
1062
+
};
1063
+
1064
+
static struct qcom_icc_node qhs_venus_cfg = {
1065
+
.name = "qhs_venus_cfg",
1066
+
.id = SM8250_SLAVE_VENUS_CFG,
1067
+
.channels = 1,
1068
+
.buswidth = 4,
1069
+
};
1070
+
1071
+
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1072
+
.name = "qhs_vsense_ctrl_cfg",
1073
+
.id = SM8250_SLAVE_VSENSE_CTRL_CFG,
1074
+
.channels = 1,
1075
+
.buswidth = 4,
1076
+
};
1077
+
1078
+
static struct qcom_icc_node qns_cnoc_a2noc = {
1079
+
.name = "qns_cnoc_a2noc",
1080
+
.id = SM8250_SLAVE_CNOC_A2NOC,
1081
+
.channels = 1,
1082
+
.buswidth = 8,
1083
+
.num_links = 1,
1084
+
.links = { SM8250_MASTER_CNOC_A2NOC },
1085
+
};
1086
+
1087
+
static struct qcom_icc_node srvc_cnoc = {
1088
+
.name = "srvc_cnoc",
1089
+
.id = SM8250_SLAVE_SERVICE_CNOC,
1090
+
.channels = 1,
1091
+
.buswidth = 4,
1092
+
};
1093
+
1094
+
static struct qcom_icc_node qhs_llcc = {
1095
+
.name = "qhs_llcc",
1096
+
.id = SM8250_SLAVE_LLCC_CFG,
1097
+
.channels = 1,
1098
+
.buswidth = 4,
1099
+
};
1100
+
1101
+
static struct qcom_icc_node qhs_memnoc = {
1102
+
.name = "qhs_memnoc",
1103
+
.id = SM8250_SLAVE_GEM_NOC_CFG,
1104
+
.channels = 1,
1105
+
.buswidth = 4,
1106
+
.num_links = 1,
1107
+
.links = { SM8250_MASTER_GEM_NOC_CFG },
1108
+
};
1109
+
1110
+
static struct qcom_icc_node qns_gem_noc_snoc = {
1111
+
.name = "qns_gem_noc_snoc",
1112
+
.id = SM8250_SLAVE_GEM_NOC_SNOC,
1113
+
.channels = 1,
1114
+
.buswidth = 16,
1115
+
.num_links = 1,
1116
+
.links = { SM8250_MASTER_GEM_NOC_SNOC },
1117
+
};
1118
+
1119
+
static struct qcom_icc_node qns_llcc = {
1120
+
.name = "qns_llcc",
1121
+
.id = SM8250_SLAVE_LLCC,
1122
+
.channels = 4,
1123
+
.buswidth = 16,
1124
+
.num_links = 1,
1125
+
.links = { SM8250_MASTER_LLCC },
1126
+
};
1127
+
1128
+
static struct qcom_icc_node qns_sys_pcie = {
1129
+
.name = "qns_sys_pcie",
1130
+
.id = SM8250_SLAVE_MEM_NOC_PCIE_SNOC,
1131
+
.channels = 1,
1132
+
.buswidth = 8,
1133
+
.num_links = 1,
1134
+
.links = { SM8250_MASTER_GEM_NOC_PCIE_SNOC },
1135
+
};
1136
+
1137
+
static struct qcom_icc_node srvc_even_gemnoc = {
1138
+
.name = "srvc_even_gemnoc",
1139
+
.id = SM8250_SLAVE_SERVICE_GEM_NOC_1,
1140
+
.channels = 1,
1141
+
.buswidth = 4,
1142
+
};
1143
+
1144
+
static struct qcom_icc_node srvc_odd_gemnoc = {
1145
+
.name = "srvc_odd_gemnoc",
1146
+
.id = SM8250_SLAVE_SERVICE_GEM_NOC_2,
1147
+
.channels = 1,
1148
+
.buswidth = 4,
1149
+
};
1150
+
1151
+
static struct qcom_icc_node srvc_sys_gemnoc = {
1152
+
.name = "srvc_sys_gemnoc",
1153
+
.id = SM8250_SLAVE_SERVICE_GEM_NOC,
1154
+
.channels = 1,
1155
+
.buswidth = 4,
1156
+
};
1157
+
1158
+
static struct qcom_icc_node ebi = {
1159
+
.name = "ebi",
1160
+
.id = SM8250_SLAVE_EBI_CH0,
1161
+
.channels = 4,
1162
+
.buswidth = 4,
1163
+
};
1164
+
1165
+
static struct qcom_icc_node qns_mem_noc_hf = {
1166
+
.name = "qns_mem_noc_hf",
1167
+
.id = SM8250_SLAVE_MNOC_HF_MEM_NOC,
1168
+
.channels = 2,
1169
+
.buswidth = 32,
1170
+
.num_links = 1,
1171
+
.links = { SM8250_MASTER_MNOC_HF_MEM_NOC },
1172
+
};
1173
+
1174
+
static struct qcom_icc_node qns_mem_noc_sf = {
1175
+
.name = "qns_mem_noc_sf",
1176
+
.id = SM8250_SLAVE_MNOC_SF_MEM_NOC,
1177
+
.channels = 2,
1178
+
.buswidth = 32,
1179
+
.num_links = 1,
1180
+
.links = { SM8250_MASTER_MNOC_SF_MEM_NOC },
1181
+
};
1182
+
1183
+
static struct qcom_icc_node srvc_mnoc = {
1184
+
.name = "srvc_mnoc",
1185
+
.id = SM8250_SLAVE_SERVICE_MNOC,
1186
+
.channels = 1,
1187
+
.buswidth = 4,
1188
+
};
1189
+
1190
+
static struct qcom_icc_node qhs_cal_dp0 = {
1191
+
.name = "qhs_cal_dp0",
1192
+
.id = SM8250_SLAVE_NPU_CAL_DP0,
1193
+
.channels = 1,
1194
+
.buswidth = 4,
1195
+
};
1196
+
1197
+
static struct qcom_icc_node qhs_cal_dp1 = {
1198
+
.name = "qhs_cal_dp1",
1199
+
.id = SM8250_SLAVE_NPU_CAL_DP1,
1200
+
.channels = 1,
1201
+
.buswidth = 4,
1202
+
};
1203
+
1204
+
static struct qcom_icc_node qhs_cp = {
1205
+
.name = "qhs_cp",
1206
+
.id = SM8250_SLAVE_NPU_CP,
1207
+
.channels = 1,
1208
+
.buswidth = 4,
1209
+
};
1210
+
1211
+
static struct qcom_icc_node qhs_dma_bwmon = {
1212
+
.name = "qhs_dma_bwmon",
1213
+
.id = SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG,
1214
+
.channels = 1,
1215
+
.buswidth = 4,
1216
+
};
1217
+
1218
+
static struct qcom_icc_node qhs_dpm = {
1219
+
.name = "qhs_dpm",
1220
+
.id = SM8250_SLAVE_NPU_DPM,
1221
+
.channels = 1,
1222
+
.buswidth = 4,
1223
+
};
1224
+
1225
+
static struct qcom_icc_node qhs_isense = {
1226
+
.name = "qhs_isense",
1227
+
.id = SM8250_SLAVE_ISENSE_CFG,
1228
+
.channels = 1,
1229
+
.buswidth = 4,
1230
+
};
1231
+
1232
+
static struct qcom_icc_node qhs_llm = {
1233
+
.name = "qhs_llm",
1234
+
.id = SM8250_SLAVE_NPU_LLM_CFG,
1235
+
.channels = 1,
1236
+
.buswidth = 4,
1237
+
};
1238
+
1239
+
static struct qcom_icc_node qhs_tcm = {
1240
+
.name = "qhs_tcm",
1241
+
.id = SM8250_SLAVE_NPU_TCM,
1242
+
.channels = 1,
1243
+
.buswidth = 4,
1244
+
};
1245
+
1246
+
static struct qcom_icc_node qns_npu_sys = {
1247
+
.name = "qns_npu_sys",
1248
+
.id = SM8250_SLAVE_NPU_COMPUTE_NOC,
1249
+
.channels = 2,
1250
+
.buswidth = 32,
1251
+
};
1252
+
1253
+
static struct qcom_icc_node srvc_noc = {
1254
+
.name = "srvc_noc",
1255
+
.id = SM8250_SLAVE_SERVICE_NPU_NOC,
1256
+
.channels = 1,
1257
+
.buswidth = 4,
1258
+
};
1259
+
1260
+
static struct qcom_icc_node qhs_apss = {
1261
+
.name = "qhs_apss",
1262
+
.id = SM8250_SLAVE_APPSS,
1263
+
.channels = 1,
1264
+
.buswidth = 8,
1265
+
};
1266
+
1267
+
static struct qcom_icc_node qns_cnoc = {
1268
+
.name = "qns_cnoc",
1269
+
.id = SM8250_SNOC_CNOC_SLV,
1270
+
.channels = 1,
1271
+
.buswidth = 8,
1272
+
.num_links = 1,
1273
+
.links = { SM8250_SNOC_CNOC_MAS },
1274
+
};
1275
+
1276
+
static struct qcom_icc_node qns_gemnoc_gc = {
1277
+
.name = "qns_gemnoc_gc",
1278
+
.id = SM8250_SLAVE_SNOC_GEM_NOC_GC,
1279
+
.channels = 1,
1280
+
.buswidth = 8,
1281
+
.num_links = 1,
1282
+
.links = { SM8250_MASTER_SNOC_GC_MEM_NOC },
1283
+
};
1284
+
1285
+
static struct qcom_icc_node qns_gemnoc_sf = {
1286
+
.name = "qns_gemnoc_sf",
1287
+
.id = SM8250_SLAVE_SNOC_GEM_NOC_SF,
1288
+
.channels = 1,
1289
+
.buswidth = 16,
1290
+
.num_links = 1,
1291
+
.links = { SM8250_MASTER_SNOC_SF_MEM_NOC },
1292
+
};
1293
+
1294
+
static struct qcom_icc_node qxs_imem = {
1295
+
.name = "qxs_imem",
1296
+
.id = SM8250_SLAVE_OCIMEM,
1297
+
.channels = 1,
1298
+
.buswidth = 8,
1299
+
};
1300
+
1301
+
static struct qcom_icc_node qxs_pimem = {
1302
+
.name = "qxs_pimem",
1303
+
.id = SM8250_SLAVE_PIMEM,
1304
+
.channels = 1,
1305
+
.buswidth = 8,
1306
+
};
1307
+
1308
+
static struct qcom_icc_node srvc_snoc = {
1309
+
.name = "srvc_snoc",
1310
+
.id = SM8250_SLAVE_SERVICE_SNOC,
1311
+
.channels = 1,
1312
+
.buswidth = 4,
1313
+
};
1314
+
1315
+
static struct qcom_icc_node xs_pcie_0 = {
1316
+
.name = "xs_pcie_0",
1317
+
.id = SM8250_SLAVE_PCIE_0,
1318
+
.channels = 1,
1319
+
.buswidth = 8,
1320
+
};
1321
+
1322
+
static struct qcom_icc_node xs_pcie_1 = {
1323
+
.name = "xs_pcie_1",
1324
+
.id = SM8250_SLAVE_PCIE_1,
1325
+
.channels = 1,
1326
+
.buswidth = 8,
1327
+
};
1328
+
1329
+
static struct qcom_icc_node xs_pcie_modem = {
1330
+
.name = "xs_pcie_modem",
1331
+
.id = SM8250_SLAVE_PCIE_2,
1332
+
.channels = 1,
1333
+
.buswidth = 8,
1334
+
};
1335
+
1336
+
static struct qcom_icc_node xs_qdss_stm = {
1337
+
.name = "xs_qdss_stm",
1338
+
.id = SM8250_SLAVE_QDSS_STM,
1339
+
.channels = 1,
1340
+
.buswidth = 4,
1341
+
};
1342
+
1343
+
static struct qcom_icc_node xs_sys_tcu_cfg = {
1344
+
.name = "xs_sys_tcu_cfg",
1345
+
.id = SM8250_SLAVE_TCU,
1346
+
.channels = 1,
1347
+
.buswidth = 8,
1348
+
};
167
1349
168
1350
static struct qcom_icc_node qup0_core_master = {
169
1351
.name = "qup0_core_master",