Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'v6.13-armsoc/dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New SoCs: basic RK3528 support, RK3399S - a variant made specifically
for the Pinephone Pro and for consistencies sake it gets its own SoC
dtsi to not hide the specifics in the Pinephone Pro devicetree.
New boards: OrangePi-5b, NanoPi R3S, ArmSom Sige 5 (first rk3576 board),
Radxa e20c (first rk3528 board), Powkiddy RGB20SX, RK3588S-EVB1 and
the ArmSoM LM7 SoM with W3 carrier board.
HDMI support for rk3588 brings the first graphical output capability
there. This includes of course needed changes to a number of boards.
And finally a bunch of newly enabled peripherals on different boards,
as well as changes to adhere better to bindings and removal/change of
deprecated properties.
* tag 'v6.13-armsoc/dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (64 commits)
arm64: dts: rockchip: Add rk3588-orangepi-5b device tree
dt-bindings: arm: rockchip: Add Orange Pi 5b enum to Orange Pi 5 entry
arm64: dts: rockchip: refactor common Orange Pi 5 board
arm64: dts: rockchip: Remove 'enable-active-low' from two boards
arm64: dts: rockchip: add HDMI support to rk3588-jaguar
arm64: dts: rockchip: add HDMI support to rk3588-tiger-haikou
arm64: dts: rockchip: add HDMI pinctrl to rk3588-tiger SoM
arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S
arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S
arm64: dts: rockchip: sort props in pmu_io_domains node for NanoPi R3S
arm64: dts: rockchip: replace deprecated snps,reset props for NanoPi R3S
arm64: dts: rockchip: fix model name for FriendlyElec NanoPi R3S
arm64: dts: rockchip: Enable HDMI0 on rock-5a
arm64: dts: rockchip: Enable HDMI0 on rk3588-nanopc-t6
arm64: dts: rockchip: pwm-leds for Orange Pi 5
arm64: dts: rockchip: reorder audio/hdmi nodes in Orange Pi 5
arm64: dts: rockchip: analog audio on Orange Pi 5
arm64: dts: rockchip: Add dtsi file for RK3399S SoC variant
arm64: dts: rockchip: Convert dts files used as parents to dtsi files
arm64: dts: rockchip: fix the pcie refclock oscillator on Rock 5 ITX
...
Link: https://lore.kernel.org/r/12542111.O9o76ZdvQC@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+15260
-2981
+31
-1
Documentation/devicetree/bindings/arm/rockchip.yaml
+31
-1
Documentation/devicetree/bindings/arm/rockchip.yaml
···
49
49
- anbernic,rg-arc-s
50
50
- const: rockchip,rk3566
51
51
52
+
- description: ArmSoM Sige5 board
53
+
items:
54
+
- const: armsom,sige5
55
+
- const: rockchip,rk3576
56
+
52
57
- description: ArmSoM Sige7 board
53
58
items:
54
59
- const: armsom,sige7
60
+
- const: rockchip,rk3588
61
+
62
+
- description: ArmSoM LM7 SoM
63
+
items:
64
+
- enum:
65
+
- armsom,w3
66
+
- const: armsom,lm7
55
67
- const: rockchip,rk3588
56
68
57
69
- description: Asus Tinker board
···
243
231
- friendlyarm,nanopi-r2s
244
232
- friendlyarm,nanopi-r2s-plus
245
233
- const: rockchip,rk3328
234
+
235
+
- description: FriendlyElec NanoPi R3S
236
+
items:
237
+
- const: friendlyarm,nanopi-r3s
238
+
- const: rockchip,rk3566
246
239
247
240
- description: FriendlyElec NanoPi4 series boards
248
241
items:
···
777
760
items:
778
761
- enum:
779
762
- powkiddy,rgb10max3
763
+
- powkiddy,rgb20sx
780
764
- powkiddy,rgb30
781
765
- powkiddy,rk2023
782
766
- powkiddy,x55
···
806
788
- radxa,e25
807
789
- const: radxa,cm3i
808
790
- const: rockchip,rk3568
791
+
792
+
- description: Radxa E20C
793
+
items:
794
+
- const: radxa,e20c
795
+
- const: rockchip,rk3528
809
796
810
797
- description: Radxa Rock
811
798
items:
···
1001
978
- const: rockchip,rk3588-evb1-v10
1002
979
- const: rockchip,rk3588
1003
980
981
+
- description: Rockchip RK3588S Evaluation board
982
+
items:
983
+
- const: rockchip,rk3588s-evb1-v10
984
+
- const: rockchip,rk3588s
985
+
1004
986
- description: Rockchip RV1108 Evaluation board
1005
987
items:
1006
988
- const: rockchip,rv1108-evb
···
1079
1051
1080
1052
- description: Xunlong Orange Pi 5
1081
1053
items:
1082
-
- const: xunlong,orangepi-5
1054
+
- enum:
1055
+
- xunlong,orangepi-5
1056
+
- xunlong,orangepi-5b
1083
1057
- const: rockchip,rk3588s
1084
1058
1085
1059
- description: Zkmagic A95X Z2
+7
arch/arm64/boot/dts/rockchip/Makefile
+7
arch/arm64/boot/dts/rockchip/Makefile
···
76
76
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
77
77
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
78
78
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
79
+
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-radxa-e20c.dtb
79
80
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg-arc-d.dtb
80
81
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg-arc-s.dtb
81
82
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb
···
92
91
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinetab2-v0.1.dtb
93
92
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinetab2-v2.0.dtb
94
93
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rgb10max3.dtb
94
+
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rgb20sx.dtb
95
95
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rgb30.dtb
96
96
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rk2023.dtb
97
97
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-x55.dtb
···
109
107
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb
110
108
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lckfb-tspi.dtb
111
109
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb
110
+
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-nanopi-r3s.dtb
112
111
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
113
112
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
114
113
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
···
127
124
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb
128
125
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo
129
126
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo
127
+
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb
130
128
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb
129
+
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-w3.dtb
131
130
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-evb.dtb
132
131
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-genbook.dtb
133
132
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
···
151
146
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb
152
147
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb
153
148
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-coolpi-4b.dtb
149
+
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-v10.dtb
154
150
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-gameforce-ace.dtb
155
151
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb
156
152
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb
···
160
154
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
161
155
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb
162
156
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb
157
+
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb
+1
-1
arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/px30-evb.dts
+1
-1
arch/arm64/boot/dts/rockchip/px30-evb.dts
+1
-1
arch/arm64/boot/dts/rockchip/px30-firefly-jd4-core.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/px30-firefly-jd4-core.dtsi
+30
-7
arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
+30
-7
arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
···
9
9
10
10
/ {
11
11
aliases {
12
+
i2c10 = &i2c10;
12
13
mmc0 = &emmc;
13
14
mmc1 = &sdio;
14
15
rtc0 = &rtc_twi;
15
16
rtc1 = &rk809;
17
+
};
18
+
19
+
/* allows userspace to control the gate of the ATtiny UPDI pass FET via sysfs */
20
+
attiny-updi-gate-regulator {
21
+
compatible = "regulator-output";
22
+
vout-supply = <&vg_attiny_updi>;
16
23
};
17
24
18
25
emmc_pwrseq: emmc-pwrseq {
···
134
127
pinctrl-names = "default";
135
128
#clock-cells = <0>;
136
129
clock-output-names = "xin32k";
137
-
rockchip,system-power-controller;
130
+
system-power-controller;
138
131
wakeup-source;
139
132
140
133
vcc1-supply = <&vcc5v0_sys>;
···
288
281
regulator-suspend-microvolt = <1800000>;
289
282
};
290
283
};
284
+
285
+
/* supplies the gate of the ATtiny UPDI pass FET */
286
+
vg_attiny_updi: SWITCH_REG1 {
287
+
regulator-name = "vg_attiny_updi";
288
+
};
291
289
};
292
290
};
293
291
};
···
304
292
clock-frequency = <400000>;
305
293
306
294
fan: fan@18 {
307
-
compatible = "ti,amc6821";
295
+
compatible = "tsd,mule", "ti,amc6821";
308
296
reg = <0x18>;
309
-
#cooling-cells = <2>;
310
-
};
311
297
312
-
rtc_twi: rtc@6f {
313
-
compatible = "isil,isl1208";
314
-
reg = <0x6f>;
298
+
i2c-mux {
299
+
compatible = "tsd,mule-i2c-mux";
300
+
#address-cells = <1>;
301
+
#size-cells = <0>;
302
+
303
+
i2c10: i2c@0 {
304
+
reg = <0x0>;
305
+
#address-cells = <1>;
306
+
#size-cells = <0>;
307
+
308
+
rtc_twi: rtc@6f {
309
+
compatible = "isil,isl1208";
310
+
reg = <0x6f>;
311
+
};
312
+
};
313
+
};
315
314
};
316
315
};
317
316
+1
-1
arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dtsi
···
49
49
compatible = "simple-audio-card";
50
50
simple-audio-card,name = "rk817_int";
51
51
simple-audio-card,format = "i2s";
52
-
simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
52
+
simple-audio-card,hp-det-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
53
53
simple-audio-card,mclk-fs = <256>;
54
54
simple-audio-card,widgets =
55
55
"Microphone", "Mic Jack",
+1
-1
arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts
···
245
245
simple-audio-card,name = "rk817_ext";
246
246
simple-audio-card,aux-devs = <&spk_amp>;
247
247
simple-audio-card,format = "i2s";
248
-
simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
248
+
simple-audio-card,hp-det-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
249
249
simple-audio-card,mclk-fs = <256>;
250
250
simple-audio-card,widgets =
251
251
"Microphone", "Mic Jack",
+1
-1
arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
···
144
144
compatible = "simple-audio-card";
145
145
simple-audio-card,name = "rk817_int";
146
146
simple-audio-card,format = "i2s";
147
-
simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
147
+
simple-audio-card,hp-det-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
148
148
simple-audio-card,mclk-fs = <256>;
149
149
simple-audio-card,widgets =
150
150
"Microphone", "Mic Jack",
+1
-1
arch/arm64/boot/dts/rockchip/rk3328-a1.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3328-a1.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3328-evb.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3328-evb.dts
+394
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2.dtsi
+394
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2020 David Bauer <mail@david-bauer.net>
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include <dt-bindings/input/input.h>
9
+
#include <dt-bindings/gpio/gpio.h>
10
+
#include "rk3328.dtsi"
11
+
12
+
/ {
13
+
aliases {
14
+
ethernet0 = &gmac2io;
15
+
ethernet1 = &rtl8153;
16
+
mmc0 = &sdmmc;
17
+
};
18
+
19
+
chosen {
20
+
stdout-path = "serial2:1500000n8";
21
+
};
22
+
23
+
gmac_clk: gmac-clock {
24
+
compatible = "fixed-clock";
25
+
clock-frequency = <125000000>;
26
+
clock-output-names = "gmac_clkin";
27
+
#clock-cells = <0>;
28
+
};
29
+
30
+
keys {
31
+
compatible = "gpio-keys";
32
+
pinctrl-0 = <&reset_button_pin>;
33
+
pinctrl-names = "default";
34
+
35
+
key-reset {
36
+
label = "reset";
37
+
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
38
+
linux,code = <KEY_RESTART>;
39
+
debounce-interval = <50>;
40
+
};
41
+
};
42
+
43
+
leds {
44
+
compatible = "gpio-leds";
45
+
pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
46
+
pinctrl-names = "default";
47
+
48
+
lan_led: led-0 {
49
+
gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
50
+
label = "nanopi-r2s:green:lan";
51
+
};
52
+
53
+
sys_led: led-1 {
54
+
gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
55
+
label = "nanopi-r2s:red:sys";
56
+
default-state = "on";
57
+
};
58
+
59
+
wan_led: led-2 {
60
+
gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
61
+
label = "nanopi-r2s:green:wan";
62
+
};
63
+
};
64
+
65
+
vcc_io_sdio: sdmmcio-regulator {
66
+
compatible = "regulator-gpio";
67
+
enable-active-high;
68
+
gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
69
+
pinctrl-0 = <&sdio_vcc_pin>;
70
+
pinctrl-names = "default";
71
+
regulator-name = "vcc_io_sdio";
72
+
regulator-always-on;
73
+
regulator-min-microvolt = <1800000>;
74
+
regulator-max-microvolt = <3300000>;
75
+
regulator-settling-time-us = <5000>;
76
+
regulator-type = "voltage";
77
+
startup-delay-us = <2000>;
78
+
states = <1800000 0x1>,
79
+
<3300000 0x0>;
80
+
vin-supply = <&vcc_io_33>;
81
+
};
82
+
83
+
vcc_sd: sdmmc-regulator {
84
+
compatible = "regulator-fixed";
85
+
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
86
+
pinctrl-0 = <&sdmmc0m1_pin>;
87
+
pinctrl-names = "default";
88
+
regulator-name = "vcc_sd";
89
+
regulator-boot-on;
90
+
regulator-min-microvolt = <3300000>;
91
+
regulator-max-microvolt = <3300000>;
92
+
vin-supply = <&vcc_io_33>;
93
+
};
94
+
95
+
vdd_5v: vdd-5v {
96
+
compatible = "regulator-fixed";
97
+
regulator-name = "vdd_5v";
98
+
regulator-always-on;
99
+
regulator-boot-on;
100
+
regulator-min-microvolt = <5000000>;
101
+
regulator-max-microvolt = <5000000>;
102
+
};
103
+
104
+
vdd_5v_lan: vdd-5v-lan {
105
+
compatible = "regulator-fixed";
106
+
enable-active-high;
107
+
gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
108
+
pinctrl-0 = <&lan_vdd_pin>;
109
+
pinctrl-names = "default";
110
+
regulator-name = "vdd_5v_lan";
111
+
regulator-always-on;
112
+
regulator-boot-on;
113
+
vin-supply = <&vdd_5v>;
114
+
};
115
+
};
116
+
117
+
&cpu0 {
118
+
cpu-supply = <&vdd_arm>;
119
+
};
120
+
121
+
&cpu1 {
122
+
cpu-supply = <&vdd_arm>;
123
+
};
124
+
125
+
&cpu2 {
126
+
cpu-supply = <&vdd_arm>;
127
+
};
128
+
129
+
&cpu3 {
130
+
cpu-supply = <&vdd_arm>;
131
+
};
132
+
133
+
&display_subsystem {
134
+
status = "disabled";
135
+
};
136
+
137
+
&gmac2io {
138
+
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
139
+
assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
140
+
clock_in_out = "input";
141
+
phy-mode = "rgmii";
142
+
phy-supply = <&vcc_io_33>;
143
+
pinctrl-0 = <&rgmiim1_pins>;
144
+
pinctrl-names = "default";
145
+
snps,aal;
146
+
147
+
mdio {
148
+
compatible = "snps,dwmac-mdio";
149
+
#address-cells = <1>;
150
+
#size-cells = <0>;
151
+
};
152
+
};
153
+
154
+
&i2c1 {
155
+
status = "okay";
156
+
157
+
rk805: pmic@18 {
158
+
compatible = "rockchip,rk805";
159
+
reg = <0x18>;
160
+
interrupt-parent = <&gpio1>;
161
+
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
162
+
#clock-cells = <1>;
163
+
clock-output-names = "xin32k", "rk805-clkout2";
164
+
gpio-controller;
165
+
#gpio-cells = <2>;
166
+
pinctrl-0 = <&pmic_int_l>;
167
+
pinctrl-names = "default";
168
+
system-power-controller;
169
+
wakeup-source;
170
+
171
+
vcc1-supply = <&vdd_5v>;
172
+
vcc2-supply = <&vdd_5v>;
173
+
vcc3-supply = <&vdd_5v>;
174
+
vcc4-supply = <&vdd_5v>;
175
+
vcc5-supply = <&vcc_io_33>;
176
+
vcc6-supply = <&vdd_5v>;
177
+
178
+
regulators {
179
+
vdd_log: DCDC_REG1 {
180
+
regulator-name = "vdd_log";
181
+
regulator-always-on;
182
+
regulator-boot-on;
183
+
regulator-min-microvolt = <712500>;
184
+
regulator-max-microvolt = <1450000>;
185
+
regulator-ramp-delay = <12500>;
186
+
187
+
regulator-state-mem {
188
+
regulator-on-in-suspend;
189
+
regulator-suspend-microvolt = <1000000>;
190
+
};
191
+
};
192
+
193
+
vdd_arm: DCDC_REG2 {
194
+
regulator-name = "vdd_arm";
195
+
regulator-always-on;
196
+
regulator-boot-on;
197
+
regulator-min-microvolt = <712500>;
198
+
regulator-max-microvolt = <1450000>;
199
+
regulator-ramp-delay = <12500>;
200
+
201
+
regulator-state-mem {
202
+
regulator-on-in-suspend;
203
+
regulator-suspend-microvolt = <950000>;
204
+
};
205
+
};
206
+
207
+
vcc_ddr: DCDC_REG3 {
208
+
regulator-name = "vcc_ddr";
209
+
regulator-always-on;
210
+
regulator-boot-on;
211
+
212
+
regulator-state-mem {
213
+
regulator-on-in-suspend;
214
+
};
215
+
};
216
+
217
+
vcc_io_33: DCDC_REG4 {
218
+
regulator-name = "vcc_io_33";
219
+
regulator-always-on;
220
+
regulator-boot-on;
221
+
regulator-min-microvolt = <3300000>;
222
+
regulator-max-microvolt = <3300000>;
223
+
224
+
regulator-state-mem {
225
+
regulator-on-in-suspend;
226
+
regulator-suspend-microvolt = <3300000>;
227
+
};
228
+
};
229
+
230
+
vcc_18: LDO_REG1 {
231
+
regulator-name = "vcc_18";
232
+
regulator-always-on;
233
+
regulator-boot-on;
234
+
regulator-min-microvolt = <1800000>;
235
+
regulator-max-microvolt = <1800000>;
236
+
237
+
regulator-state-mem {
238
+
regulator-on-in-suspend;
239
+
regulator-suspend-microvolt = <1800000>;
240
+
};
241
+
};
242
+
243
+
vcc18_emmc: LDO_REG2 {
244
+
regulator-name = "vcc18_emmc";
245
+
regulator-always-on;
246
+
regulator-boot-on;
247
+
regulator-min-microvolt = <1800000>;
248
+
regulator-max-microvolt = <1800000>;
249
+
250
+
regulator-state-mem {
251
+
regulator-on-in-suspend;
252
+
regulator-suspend-microvolt = <1800000>;
253
+
};
254
+
};
255
+
256
+
vdd_10: LDO_REG3 {
257
+
regulator-name = "vdd_10";
258
+
regulator-always-on;
259
+
regulator-boot-on;
260
+
regulator-min-microvolt = <1000000>;
261
+
regulator-max-microvolt = <1000000>;
262
+
263
+
regulator-state-mem {
264
+
regulator-on-in-suspend;
265
+
regulator-suspend-microvolt = <1000000>;
266
+
};
267
+
};
268
+
};
269
+
};
270
+
};
271
+
272
+
&io_domains {
273
+
pmuio-supply = <&vcc_io_33>;
274
+
vccio1-supply = <&vcc_io_33>;
275
+
vccio2-supply = <&vcc18_emmc>;
276
+
vccio3-supply = <&vcc_io_sdio>;
277
+
vccio4-supply = <&vcc_18>;
278
+
vccio5-supply = <&vcc_io_33>;
279
+
vccio6-supply = <&vcc_io_33>;
280
+
status = "okay";
281
+
};
282
+
283
+
&pinctrl {
284
+
button {
285
+
reset_button_pin: reset-button-pin {
286
+
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
287
+
};
288
+
};
289
+
290
+
gmac2io {
291
+
eth_phy_reset_pin: eth-phy-reset-pin {
292
+
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
293
+
};
294
+
};
295
+
296
+
leds {
297
+
lan_led_pin: lan-led-pin {
298
+
rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
299
+
};
300
+
301
+
sys_led_pin: sys-led-pin {
302
+
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
303
+
};
304
+
305
+
wan_led_pin: wan-led-pin {
306
+
rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
307
+
};
308
+
};
309
+
310
+
lan {
311
+
lan_vdd_pin: lan-vdd-pin {
312
+
rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
313
+
};
314
+
};
315
+
316
+
pmic {
317
+
pmic_int_l: pmic-int-l {
318
+
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
319
+
};
320
+
};
321
+
322
+
sd {
323
+
sdio_vcc_pin: sdio-vcc-pin {
324
+
rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
325
+
};
326
+
};
327
+
};
328
+
329
+
&pwm2 {
330
+
status = "okay";
331
+
};
332
+
333
+
&sdmmc {
334
+
bus-width = <4>;
335
+
cap-sd-highspeed;
336
+
disable-wp;
337
+
pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
338
+
pinctrl-names = "default";
339
+
sd-uhs-sdr12;
340
+
sd-uhs-sdr25;
341
+
sd-uhs-sdr50;
342
+
sd-uhs-sdr104;
343
+
vmmc-supply = <&vcc_sd>;
344
+
vqmmc-supply = <&vcc_io_sdio>;
345
+
status = "okay";
346
+
};
347
+
348
+
&tsadc {
349
+
rockchip,hw-tshut-mode = <0>;
350
+
rockchip,hw-tshut-polarity = <0>;
351
+
status = "okay";
352
+
};
353
+
354
+
&u2phy {
355
+
status = "okay";
356
+
};
357
+
358
+
&u2phy_host {
359
+
status = "okay";
360
+
};
361
+
362
+
&u2phy_otg {
363
+
status = "okay";
364
+
};
365
+
366
+
&uart2 {
367
+
status = "okay";
368
+
};
369
+
370
+
&usb20_otg {
371
+
status = "okay";
372
+
dr_mode = "host";
373
+
};
374
+
375
+
&usbdrd3 {
376
+
dr_mode = "host";
377
+
status = "okay";
378
+
#address-cells = <1>;
379
+
#size-cells = <0>;
380
+
381
+
/* Second port is for USB 3.0 */
382
+
rtl8153: device@2 {
383
+
compatible = "usbbda,8153";
384
+
reg = <2>;
385
+
};
386
+
};
387
+
388
+
&usb_host0_ehci {
389
+
status = "okay";
390
+
};
391
+
392
+
&usb_host0_ohci {
393
+
status = "okay";
394
+
};
+2
-1
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
+2
-1
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
+2
-26
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
+2
-26
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
···
7
7
*/
8
8
9
9
/dts-v1/;
10
-
#include "rk3328-nanopi-r2s.dts"
10
+
11
+
#include "rk3328-nanopi-r2c.dtsi"
11
12
12
13
/ {
13
14
model = "FriendlyElec NanoPi R2C";
14
15
compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
15
-
};
16
-
17
-
&gmac2io {
18
-
phy-handle = <&yt8521s>;
19
-
tx_delay = <0x22>;
20
-
rx_delay = <0x12>;
21
-
22
-
mdio {
23
-
/delete-node/ ethernet-phy@1;
24
-
25
-
yt8521s: ethernet-phy@3 {
26
-
compatible = "ethernet-phy-ieee802.3-c22";
27
-
reg = <3>;
28
-
29
-
motorcomm,clk-out-frequency-hz = <125000000>;
30
-
motorcomm,keep-pll-enabled;
31
-
motorcomm,auto-sleep-disabled;
32
-
33
-
pinctrl-0 = <ð_phy_reset_pin>;
34
-
pinctrl-names = "default";
35
-
reset-assert-us = <10000>;
36
-
reset-deassert-us = <50000>;
37
-
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
38
-
};
39
-
};
40
16
};
+35
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dtsi
+35
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
4
+
* (http://www.friendlyarm.com)
5
+
*
6
+
* Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
7
+
*/
8
+
9
+
/dts-v1/;
10
+
11
+
#include "rk3328-nanopi-r2.dtsi"
12
+
13
+
&gmac2io {
14
+
phy-handle = <&yt8521s>;
15
+
tx_delay = <0x22>;
16
+
rx_delay = <0x12>;
17
+
status = "okay";
18
+
19
+
mdio {
20
+
yt8521s: ethernet-phy@3 {
21
+
compatible = "ethernet-phy-ieee802.3-c22";
22
+
reg = <3>;
23
+
24
+
motorcomm,clk-out-frequency-hz = <125000000>;
25
+
motorcomm,keep-pll-enabled;
26
+
motorcomm,auto-sleep-disabled;
27
+
28
+
pinctrl-0 = <ð_phy_reset_pin>;
29
+
pinctrl-names = "default";
30
+
reset-assert-us = <10000>;
31
+
reset-deassert-us = <50000>;
32
+
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
33
+
};
34
+
};
35
+
};
+19
-1
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts
+19
-1
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts
···
7
7
*/
8
8
9
9
/dts-v1/;
10
-
#include "rk3328-nanopi-r2s.dts"
10
+
11
+
#include "rk3328-nanopi-r2s.dtsi"
11
12
12
13
/ {
13
14
compatible = "friendlyarm,nanopi-r2s-plus", "rockchip,rk3328";
···
30
29
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
31
30
supports-emmc;
32
31
status = "okay";
32
+
};
33
+
34
+
&gmac2io {
35
+
phy-handle = <&rtl8211e>;
36
+
tx_delay = <0x24>;
37
+
rx_delay = <0x18>;
38
+
39
+
mdio {
40
+
rtl8211e: ethernet-phy@1 {
41
+
reg = <1>;
42
+
pinctrl-0 = <ð_phy_reset_pin>;
43
+
pinctrl-names = "default";
44
+
reset-assert-us = <10000>;
45
+
reset-deassert-us = <50000>;
46
+
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
47
+
};
48
+
};
33
49
};
+1
-398
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+1
-398
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
···
5
5
6
6
/dts-v1/;
7
7
8
-
#include <dt-bindings/input/input.h>
9
-
#include <dt-bindings/gpio/gpio.h>
10
-
#include "rk3328.dtsi"
8
+
#include "rk3328-nanopi-r2s.dtsi"
11
9
12
10
/ {
13
11
model = "FriendlyElec NanoPi R2S";
14
12
compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
15
-
16
-
aliases {
17
-
ethernet0 = &gmac2io;
18
-
ethernet1 = &rtl8153;
19
-
mmc0 = &sdmmc;
20
-
};
21
-
22
-
chosen {
23
-
stdout-path = "serial2:1500000n8";
24
-
};
25
-
26
-
gmac_clk: gmac-clock {
27
-
compatible = "fixed-clock";
28
-
clock-frequency = <125000000>;
29
-
clock-output-names = "gmac_clkin";
30
-
#clock-cells = <0>;
31
-
};
32
-
33
-
keys {
34
-
compatible = "gpio-keys";
35
-
pinctrl-0 = <&reset_button_pin>;
36
-
pinctrl-names = "default";
37
-
38
-
key-reset {
39
-
label = "reset";
40
-
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
41
-
linux,code = <KEY_RESTART>;
42
-
debounce-interval = <50>;
43
-
};
44
-
};
45
-
46
-
leds {
47
-
compatible = "gpio-leds";
48
-
pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
49
-
pinctrl-names = "default";
50
-
51
-
lan_led: led-0 {
52
-
gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
53
-
label = "nanopi-r2s:green:lan";
54
-
};
55
-
56
-
sys_led: led-1 {
57
-
gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
58
-
label = "nanopi-r2s:red:sys";
59
-
default-state = "on";
60
-
};
61
-
62
-
wan_led: led-2 {
63
-
gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
64
-
label = "nanopi-r2s:green:wan";
65
-
};
66
-
};
67
-
68
-
vcc_io_sdio: sdmmcio-regulator {
69
-
compatible = "regulator-gpio";
70
-
enable-active-high;
71
-
gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
72
-
pinctrl-0 = <&sdio_vcc_pin>;
73
-
pinctrl-names = "default";
74
-
regulator-name = "vcc_io_sdio";
75
-
regulator-always-on;
76
-
regulator-min-microvolt = <1800000>;
77
-
regulator-max-microvolt = <3300000>;
78
-
regulator-settling-time-us = <5000>;
79
-
regulator-type = "voltage";
80
-
startup-delay-us = <2000>;
81
-
states = <1800000 0x1>,
82
-
<3300000 0x0>;
83
-
vin-supply = <&vcc_io_33>;
84
-
};
85
-
86
-
vcc_sd: sdmmc-regulator {
87
-
compatible = "regulator-fixed";
88
-
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
89
-
pinctrl-0 = <&sdmmc0m1_pin>;
90
-
pinctrl-names = "default";
91
-
regulator-name = "vcc_sd";
92
-
regulator-boot-on;
93
-
regulator-min-microvolt = <3300000>;
94
-
regulator-max-microvolt = <3300000>;
95
-
vin-supply = <&vcc_io_33>;
96
-
};
97
-
98
-
vdd_5v: vdd-5v {
99
-
compatible = "regulator-fixed";
100
-
regulator-name = "vdd_5v";
101
-
regulator-always-on;
102
-
regulator-boot-on;
103
-
regulator-min-microvolt = <5000000>;
104
-
regulator-max-microvolt = <5000000>;
105
-
};
106
-
107
-
vdd_5v_lan: vdd-5v-lan {
108
-
compatible = "regulator-fixed";
109
-
enable-active-high;
110
-
gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
111
-
pinctrl-0 = <&lan_vdd_pin>;
112
-
pinctrl-names = "default";
113
-
regulator-name = "vdd_5v_lan";
114
-
regulator-always-on;
115
-
regulator-boot-on;
116
-
vin-supply = <&vdd_5v>;
117
-
};
118
-
};
119
-
120
-
&cpu0 {
121
-
cpu-supply = <&vdd_arm>;
122
-
};
123
-
124
-
&cpu1 {
125
-
cpu-supply = <&vdd_arm>;
126
-
};
127
-
128
-
&cpu2 {
129
-
cpu-supply = <&vdd_arm>;
130
-
};
131
-
132
-
&cpu3 {
133
-
cpu-supply = <&vdd_arm>;
134
-
};
135
-
136
-
&display_subsystem {
137
-
status = "disabled";
138
-
};
139
-
140
-
&gmac2io {
141
-
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
142
-
assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
143
-
clock_in_out = "input";
144
-
phy-handle = <&rtl8211e>;
145
-
phy-mode = "rgmii";
146
-
phy-supply = <&vcc_io_33>;
147
-
pinctrl-0 = <&rgmiim1_pins>;
148
-
pinctrl-names = "default";
149
-
rx_delay = <0x18>;
150
-
snps,aal;
151
-
tx_delay = <0x24>;
152
-
status = "okay";
153
-
154
-
mdio {
155
-
compatible = "snps,dwmac-mdio";
156
-
#address-cells = <1>;
157
-
#size-cells = <0>;
158
-
159
-
rtl8211e: ethernet-phy@1 {
160
-
reg = <1>;
161
-
pinctrl-0 = <ð_phy_reset_pin>;
162
-
pinctrl-names = "default";
163
-
reset-assert-us = <10000>;
164
-
reset-deassert-us = <50000>;
165
-
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
166
-
};
167
-
};
168
-
};
169
-
170
-
&i2c1 {
171
-
status = "okay";
172
-
173
-
rk805: pmic@18 {
174
-
compatible = "rockchip,rk805";
175
-
reg = <0x18>;
176
-
interrupt-parent = <&gpio1>;
177
-
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
178
-
#clock-cells = <1>;
179
-
clock-output-names = "xin32k", "rk805-clkout2";
180
-
gpio-controller;
181
-
#gpio-cells = <2>;
182
-
pinctrl-0 = <&pmic_int_l>;
183
-
pinctrl-names = "default";
184
-
rockchip,system-power-controller;
185
-
wakeup-source;
186
-
187
-
vcc1-supply = <&vdd_5v>;
188
-
vcc2-supply = <&vdd_5v>;
189
-
vcc3-supply = <&vdd_5v>;
190
-
vcc4-supply = <&vdd_5v>;
191
-
vcc5-supply = <&vcc_io_33>;
192
-
vcc6-supply = <&vdd_5v>;
193
-
194
-
regulators {
195
-
vdd_log: DCDC_REG1 {
196
-
regulator-name = "vdd_log";
197
-
regulator-always-on;
198
-
regulator-boot-on;
199
-
regulator-min-microvolt = <712500>;
200
-
regulator-max-microvolt = <1450000>;
201
-
regulator-ramp-delay = <12500>;
202
-
203
-
regulator-state-mem {
204
-
regulator-on-in-suspend;
205
-
regulator-suspend-microvolt = <1000000>;
206
-
};
207
-
};
208
-
209
-
vdd_arm: DCDC_REG2 {
210
-
regulator-name = "vdd_arm";
211
-
regulator-always-on;
212
-
regulator-boot-on;
213
-
regulator-min-microvolt = <712500>;
214
-
regulator-max-microvolt = <1450000>;
215
-
regulator-ramp-delay = <12500>;
216
-
217
-
regulator-state-mem {
218
-
regulator-on-in-suspend;
219
-
regulator-suspend-microvolt = <950000>;
220
-
};
221
-
};
222
-
223
-
vcc_ddr: DCDC_REG3 {
224
-
regulator-name = "vcc_ddr";
225
-
regulator-always-on;
226
-
regulator-boot-on;
227
-
228
-
regulator-state-mem {
229
-
regulator-on-in-suspend;
230
-
};
231
-
};
232
-
233
-
vcc_io_33: DCDC_REG4 {
234
-
regulator-name = "vcc_io_33";
235
-
regulator-always-on;
236
-
regulator-boot-on;
237
-
regulator-min-microvolt = <3300000>;
238
-
regulator-max-microvolt = <3300000>;
239
-
240
-
regulator-state-mem {
241
-
regulator-on-in-suspend;
242
-
regulator-suspend-microvolt = <3300000>;
243
-
};
244
-
};
245
-
246
-
vcc_18: LDO_REG1 {
247
-
regulator-name = "vcc_18";
248
-
regulator-always-on;
249
-
regulator-boot-on;
250
-
regulator-min-microvolt = <1800000>;
251
-
regulator-max-microvolt = <1800000>;
252
-
253
-
regulator-state-mem {
254
-
regulator-on-in-suspend;
255
-
regulator-suspend-microvolt = <1800000>;
256
-
};
257
-
};
258
-
259
-
vcc18_emmc: LDO_REG2 {
260
-
regulator-name = "vcc18_emmc";
261
-
regulator-always-on;
262
-
regulator-boot-on;
263
-
regulator-min-microvolt = <1800000>;
264
-
regulator-max-microvolt = <1800000>;
265
-
266
-
regulator-state-mem {
267
-
regulator-on-in-suspend;
268
-
regulator-suspend-microvolt = <1800000>;
269
-
};
270
-
};
271
-
272
-
vdd_10: LDO_REG3 {
273
-
regulator-name = "vdd_10";
274
-
regulator-always-on;
275
-
regulator-boot-on;
276
-
regulator-min-microvolt = <1000000>;
277
-
regulator-max-microvolt = <1000000>;
278
-
279
-
regulator-state-mem {
280
-
regulator-on-in-suspend;
281
-
regulator-suspend-microvolt = <1000000>;
282
-
};
283
-
};
284
-
};
285
-
};
286
-
};
287
-
288
-
&io_domains {
289
-
pmuio-supply = <&vcc_io_33>;
290
-
vccio1-supply = <&vcc_io_33>;
291
-
vccio2-supply = <&vcc18_emmc>;
292
-
vccio3-supply = <&vcc_io_sdio>;
293
-
vccio4-supply = <&vcc_18>;
294
-
vccio5-supply = <&vcc_io_33>;
295
-
vccio6-supply = <&vcc_io_33>;
296
-
status = "okay";
297
-
};
298
-
299
-
&pinctrl {
300
-
button {
301
-
reset_button_pin: reset-button-pin {
302
-
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
303
-
};
304
-
};
305
-
306
-
gmac2io {
307
-
eth_phy_reset_pin: eth-phy-reset-pin {
308
-
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
309
-
};
310
-
};
311
-
312
-
leds {
313
-
lan_led_pin: lan-led-pin {
314
-
rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
315
-
};
316
-
317
-
sys_led_pin: sys-led-pin {
318
-
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
319
-
};
320
-
321
-
wan_led_pin: wan-led-pin {
322
-
rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
323
-
};
324
-
};
325
-
326
-
lan {
327
-
lan_vdd_pin: lan-vdd-pin {
328
-
rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
329
-
};
330
-
};
331
-
332
-
pmic {
333
-
pmic_int_l: pmic-int-l {
334
-
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
335
-
};
336
-
};
337
-
338
-
sd {
339
-
sdio_vcc_pin: sdio-vcc-pin {
340
-
rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
341
-
};
342
-
};
343
-
};
344
-
345
-
&pwm2 {
346
-
status = "okay";
347
-
};
348
-
349
-
&sdmmc {
350
-
bus-width = <4>;
351
-
cap-sd-highspeed;
352
-
disable-wp;
353
-
pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
354
-
pinctrl-names = "default";
355
-
sd-uhs-sdr12;
356
-
sd-uhs-sdr25;
357
-
sd-uhs-sdr50;
358
-
sd-uhs-sdr104;
359
-
vmmc-supply = <&vcc_sd>;
360
-
vqmmc-supply = <&vcc_io_sdio>;
361
-
status = "okay";
362
-
};
363
-
364
-
&tsadc {
365
-
rockchip,hw-tshut-mode = <0>;
366
-
rockchip,hw-tshut-polarity = <0>;
367
-
status = "okay";
368
-
};
369
-
370
-
&u2phy {
371
-
status = "okay";
372
-
};
373
-
374
-
&u2phy_host {
375
-
status = "okay";
376
-
};
377
-
378
-
&u2phy_otg {
379
-
status = "okay";
380
-
};
381
-
382
-
&uart2 {
383
-
status = "okay";
384
-
};
385
-
386
-
&usb20_otg {
387
-
status = "okay";
388
-
dr_mode = "host";
389
-
};
390
-
391
-
&usbdrd3 {
392
-
dr_mode = "host";
393
-
status = "okay";
394
-
#address-cells = <1>;
395
-
#size-cells = <0>;
396
-
397
-
/* Second port is for USB 3.0 */
398
-
rtl8153: device@2 {
399
-
compatible = "usbbda,8153";
400
-
reg = <2>;
401
-
};
402
-
};
403
-
404
-
&usb_host0_ehci {
405
-
status = "okay";
406
-
};
407
-
408
-
&usb_host0_ohci {
409
-
status = "okay";
410
13
};
+29
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dtsi
+29
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* (C) Copyright 2018 FriendlyElec Computer Tech. Co., Ltd.
4
+
* (http://www.friendlyarm.com)
5
+
*
6
+
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
7
+
*/
8
+
9
+
/dts-v1/;
10
+
11
+
#include "rk3328-nanopi-r2.dtsi"
12
+
13
+
&gmac2io {
14
+
phy-handle = <&rtl8211e>;
15
+
tx_delay = <0x24>;
16
+
rx_delay = <0x18>;
17
+
status = "okay";
18
+
19
+
mdio {
20
+
rtl8211e: ethernet-phy@1 {
21
+
reg = <1>;
22
+
pinctrl-0 = <ð_phy_reset_pin>;
23
+
pinctrl-names = "default";
24
+
reset-assert-us = <10000>;
25
+
reset-deassert-us = <50000>;
26
+
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
27
+
};
28
+
};
29
+
};
+3
-3
arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
+3
-3
arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
···
7
7
*/
8
8
9
9
/dts-v1/;
10
-
#include "rk3328-orangepi-r1-plus.dts"
10
+
11
+
#include "rk3328-orangepi-r1-plus.dtsi"
11
12
12
13
/ {
13
14
model = "Xunlong Orange Pi R1 Plus LTS";
···
19
18
phy-handle = <&yt8531c>;
20
19
tx_delay = <0x19>;
21
20
rx_delay = <0x05>;
21
+
status = "okay";
22
22
23
23
mdio {
24
-
/delete-node/ ethernet-phy@1;
25
-
26
24
yt8531c: ethernet-phy@0 {
27
25
compatible = "ethernet-phy-ieee802.3-c22";
28
26
reg = <0>;
+2
-344
arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
+2
-344
arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
···
6
6
7
7
/dts-v1/;
8
8
9
-
#include <dt-bindings/gpio/gpio.h>
10
-
#include <dt-bindings/leds/common.h>
11
-
#include "rk3328.dtsi"
9
+
#include "rk3328-orangepi-r1-plus.dtsi"
12
10
13
11
/ {
14
12
model = "Xunlong Orange Pi R1 Plus";
15
13
compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
16
-
17
-
aliases {
18
-
ethernet0 = &gmac2io;
19
-
ethernet1 = &rtl8153;
20
-
mmc0 = &sdmmc;
21
-
};
22
-
23
-
chosen {
24
-
stdout-path = "serial2:1500000n8";
25
-
};
26
-
27
-
gmac_clk: gmac-clock {
28
-
compatible = "fixed-clock";
29
-
clock-frequency = <125000000>;
30
-
clock-output-names = "gmac_clkin";
31
-
#clock-cells = <0>;
32
-
};
33
-
34
-
leds {
35
-
compatible = "gpio-leds";
36
-
pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
37
-
pinctrl-names = "default";
38
-
39
-
led-0 {
40
-
function = LED_FUNCTION_LAN;
41
-
color = <LED_COLOR_ID_GREEN>;
42
-
gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
43
-
};
44
-
45
-
led-1 {
46
-
function = LED_FUNCTION_STATUS;
47
-
color = <LED_COLOR_ID_RED>;
48
-
gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
49
-
linux,default-trigger = "heartbeat";
50
-
};
51
-
52
-
led-2 {
53
-
function = LED_FUNCTION_WAN;
54
-
color = <LED_COLOR_ID_GREEN>;
55
-
gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
56
-
};
57
-
};
58
-
59
-
vcc_sd: sdmmc-regulator {
60
-
compatible = "regulator-fixed";
61
-
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
62
-
pinctrl-0 = <&sdmmc0m1_pin>;
63
-
pinctrl-names = "default";
64
-
regulator-name = "vcc_sd";
65
-
regulator-boot-on;
66
-
vin-supply = <&vcc_io>;
67
-
};
68
-
69
-
vcc_sys: vcc-sys-regulator {
70
-
compatible = "regulator-fixed";
71
-
regulator-name = "vcc_sys";
72
-
regulator-always-on;
73
-
regulator-boot-on;
74
-
regulator-min-microvolt = <5000000>;
75
-
regulator-max-microvolt = <5000000>;
76
-
};
77
-
78
-
vdd_5v_lan: vdd-5v-lan-regulator {
79
-
compatible = "regulator-fixed";
80
-
enable-active-high;
81
-
gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
82
-
pinctrl-0 = <&lan_vdd_pin>;
83
-
pinctrl-names = "default";
84
-
regulator-name = "vdd_5v_lan";
85
-
regulator-always-on;
86
-
regulator-boot-on;
87
-
vin-supply = <&vcc_sys>;
88
-
};
89
-
};
90
-
91
-
&cpu0 {
92
-
cpu-supply = <&vdd_arm>;
93
-
};
94
-
95
-
&cpu1 {
96
-
cpu-supply = <&vdd_arm>;
97
-
};
98
-
99
-
&cpu2 {
100
-
cpu-supply = <&vdd_arm>;
101
-
};
102
-
103
-
&cpu3 {
104
-
cpu-supply = <&vdd_arm>;
105
-
};
106
-
107
-
&display_subsystem {
108
-
status = "disabled";
109
14
};
110
15
111
16
&gmac2io {
112
-
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
113
-
assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
114
-
clock_in_out = "input";
115
17
phy-handle = <&rtl8211e>;
116
-
phy-mode = "rgmii";
117
-
phy-supply = <&vcc_io>;
118
-
pinctrl-0 = <&rgmiim1_pins>;
119
-
pinctrl-names = "default";
120
-
snps,aal;
121
-
rx_delay = <0x18>;
122
18
tx_delay = <0x24>;
19
+
rx_delay = <0x18>;
123
20
status = "okay";
124
21
125
22
mdio {
126
-
compatible = "snps,dwmac-mdio";
127
-
#address-cells = <1>;
128
-
#size-cells = <0>;
129
-
130
23
rtl8211e: ethernet-phy@1 {
131
24
reg = <1>;
132
25
pinctrl-0 = <ð_phy_reset_pin>;
···
29
136
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
30
137
};
31
138
};
32
-
};
33
-
34
-
&i2c1 {
35
-
status = "okay";
36
-
37
-
rk805: pmic@18 {
38
-
compatible = "rockchip,rk805";
39
-
reg = <0x18>;
40
-
interrupt-parent = <&gpio1>;
41
-
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
42
-
#clock-cells = <1>;
43
-
clock-output-names = "xin32k", "rk805-clkout2";
44
-
gpio-controller;
45
-
#gpio-cells = <2>;
46
-
pinctrl-0 = <&pmic_int_l>;
47
-
pinctrl-names = "default";
48
-
rockchip,system-power-controller;
49
-
wakeup-source;
50
-
51
-
vcc1-supply = <&vcc_sys>;
52
-
vcc2-supply = <&vcc_sys>;
53
-
vcc3-supply = <&vcc_sys>;
54
-
vcc4-supply = <&vcc_sys>;
55
-
vcc5-supply = <&vcc_io>;
56
-
vcc6-supply = <&vcc_sys>;
57
-
58
-
regulators {
59
-
vdd_log: DCDC_REG1 {
60
-
regulator-name = "vdd_log";
61
-
regulator-always-on;
62
-
regulator-boot-on;
63
-
regulator-min-microvolt = <712500>;
64
-
regulator-max-microvolt = <1450000>;
65
-
regulator-ramp-delay = <12500>;
66
-
67
-
regulator-state-mem {
68
-
regulator-on-in-suspend;
69
-
regulator-suspend-microvolt = <1000000>;
70
-
};
71
-
};
72
-
73
-
vdd_arm: DCDC_REG2 {
74
-
regulator-name = "vdd_arm";
75
-
regulator-always-on;
76
-
regulator-boot-on;
77
-
regulator-min-microvolt = <712500>;
78
-
regulator-max-microvolt = <1450000>;
79
-
regulator-ramp-delay = <12500>;
80
-
81
-
regulator-state-mem {
82
-
regulator-on-in-suspend;
83
-
regulator-suspend-microvolt = <950000>;
84
-
};
85
-
};
86
-
87
-
vcc_ddr: DCDC_REG3 {
88
-
regulator-name = "vcc_ddr";
89
-
regulator-always-on;
90
-
regulator-boot-on;
91
-
92
-
regulator-state-mem {
93
-
regulator-on-in-suspend;
94
-
};
95
-
};
96
-
97
-
vcc_io: DCDC_REG4 {
98
-
regulator-name = "vcc_io";
99
-
regulator-always-on;
100
-
regulator-boot-on;
101
-
regulator-min-microvolt = <3300000>;
102
-
regulator-max-microvolt = <3300000>;
103
-
104
-
regulator-state-mem {
105
-
regulator-on-in-suspend;
106
-
regulator-suspend-microvolt = <3300000>;
107
-
};
108
-
};
109
-
110
-
vcc_18: LDO_REG1 {
111
-
regulator-name = "vcc_18";
112
-
regulator-always-on;
113
-
regulator-boot-on;
114
-
regulator-min-microvolt = <1800000>;
115
-
regulator-max-microvolt = <1800000>;
116
-
117
-
regulator-state-mem {
118
-
regulator-on-in-suspend;
119
-
regulator-suspend-microvolt = <1800000>;
120
-
};
121
-
};
122
-
123
-
vcc18_emmc: LDO_REG2 {
124
-
regulator-name = "vcc18_emmc";
125
-
regulator-always-on;
126
-
regulator-boot-on;
127
-
regulator-min-microvolt = <1800000>;
128
-
regulator-max-microvolt = <1800000>;
129
-
130
-
regulator-state-mem {
131
-
regulator-on-in-suspend;
132
-
regulator-suspend-microvolt = <1800000>;
133
-
};
134
-
};
135
-
136
-
vdd_10: LDO_REG3 {
137
-
regulator-name = "vdd_10";
138
-
regulator-always-on;
139
-
regulator-boot-on;
140
-
regulator-min-microvolt = <1000000>;
141
-
regulator-max-microvolt = <1000000>;
142
-
143
-
regulator-state-mem {
144
-
regulator-on-in-suspend;
145
-
regulator-suspend-microvolt = <1000000>;
146
-
};
147
-
};
148
-
};
149
-
};
150
-
};
151
-
152
-
&io_domains {
153
-
pmuio-supply = <&vcc_io>;
154
-
vccio1-supply = <&vcc_io>;
155
-
vccio2-supply = <&vcc18_emmc>;
156
-
vccio3-supply = <&vcc_io>;
157
-
vccio4-supply = <&vcc_io>;
158
-
vccio5-supply = <&vcc_io>;
159
-
vccio6-supply = <&vcc_io>;
160
-
status = "okay";
161
-
};
162
-
163
-
&pinctrl {
164
-
gmac2io {
165
-
eth_phy_reset_pin: eth-phy-reset-pin {
166
-
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
167
-
};
168
-
};
169
-
170
-
leds {
171
-
lan_led_pin: lan-led-pin {
172
-
rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
173
-
};
174
-
175
-
sys_led_pin: sys-led-pin {
176
-
rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
177
-
};
178
-
179
-
wan_led_pin: wan-led-pin {
180
-
rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
181
-
};
182
-
};
183
-
184
-
lan {
185
-
lan_vdd_pin: lan-vdd-pin {
186
-
rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
187
-
};
188
-
};
189
-
190
-
pmic {
191
-
pmic_int_l: pmic-int-l {
192
-
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
193
-
};
194
-
};
195
-
};
196
-
197
-
&pwm2 {
198
-
status = "okay";
199
-
};
200
-
201
-
&sdmmc {
202
-
bus-width = <4>;
203
-
cap-sd-highspeed;
204
-
disable-wp;
205
-
pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
206
-
pinctrl-names = "default";
207
-
vmmc-supply = <&vcc_sd>;
208
-
status = "okay";
209
-
};
210
-
211
-
&spi0 {
212
-
status = "okay";
213
-
214
-
flash@0 {
215
-
compatible = "jedec,spi-nor";
216
-
reg = <0>;
217
-
spi-max-frequency = <50000000>;
218
-
};
219
-
};
220
-
221
-
&tsadc {
222
-
rockchip,hw-tshut-mode = <0>;
223
-
rockchip,hw-tshut-polarity = <0>;
224
-
status = "okay";
225
-
};
226
-
227
-
&u2phy {
228
-
status = "okay";
229
-
};
230
-
231
-
&u2phy_host {
232
-
status = "okay";
233
-
};
234
-
235
-
&u2phy_otg {
236
-
status = "okay";
237
-
};
238
-
239
-
&uart2 {
240
-
status = "okay";
241
-
};
242
-
243
-
&usb20_otg {
244
-
dr_mode = "host";
245
-
status = "okay";
246
-
};
247
-
248
-
&usbdrd3 {
249
-
dr_mode = "host";
250
-
status = "okay";
251
-
#address-cells = <1>;
252
-
#size-cells = <0>;
253
-
254
-
/* Second port is for USB 3.0 */
255
-
rtl8153: device@2 {
256
-
compatible = "usbbda,8153";
257
-
reg = <2>;
258
-
};
259
-
};
260
-
261
-
&usb_host0_ehci {
262
-
status = "okay";
263
-
};
264
-
265
-
&usb_host0_ohci {
266
-
status = "okay";
267
139
};
+358
arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi
+358
arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Based on rk3328-nanopi-r2s.dts, which is:
4
+
* Copyright (c) 2020 David Bauer <mail@david-bauer.net>
5
+
*/
6
+
7
+
/dts-v1/;
8
+
9
+
#include <dt-bindings/gpio/gpio.h>
10
+
#include <dt-bindings/leds/common.h>
11
+
#include "rk3328.dtsi"
12
+
13
+
/ {
14
+
aliases {
15
+
ethernet0 = &gmac2io;
16
+
ethernet1 = &rtl8153;
17
+
mmc0 = &sdmmc;
18
+
};
19
+
20
+
chosen {
21
+
stdout-path = "serial2:1500000n8";
22
+
};
23
+
24
+
gmac_clk: gmac-clock {
25
+
compatible = "fixed-clock";
26
+
clock-frequency = <125000000>;
27
+
clock-output-names = "gmac_clkin";
28
+
#clock-cells = <0>;
29
+
};
30
+
31
+
leds {
32
+
compatible = "gpio-leds";
33
+
pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
34
+
pinctrl-names = "default";
35
+
36
+
led-0 {
37
+
function = LED_FUNCTION_LAN;
38
+
color = <LED_COLOR_ID_GREEN>;
39
+
gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
40
+
};
41
+
42
+
led-1 {
43
+
function = LED_FUNCTION_STATUS;
44
+
color = <LED_COLOR_ID_RED>;
45
+
gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
46
+
linux,default-trigger = "heartbeat";
47
+
};
48
+
49
+
led-2 {
50
+
function = LED_FUNCTION_WAN;
51
+
color = <LED_COLOR_ID_GREEN>;
52
+
gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
53
+
};
54
+
};
55
+
56
+
vcc_sd: sdmmc-regulator {
57
+
compatible = "regulator-fixed";
58
+
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
59
+
pinctrl-0 = <&sdmmc0m1_pin>;
60
+
pinctrl-names = "default";
61
+
regulator-name = "vcc_sd";
62
+
regulator-boot-on;
63
+
vin-supply = <&vcc_io>;
64
+
};
65
+
66
+
vcc_sys: vcc-sys-regulator {
67
+
compatible = "regulator-fixed";
68
+
regulator-name = "vcc_sys";
69
+
regulator-always-on;
70
+
regulator-boot-on;
71
+
regulator-min-microvolt = <5000000>;
72
+
regulator-max-microvolt = <5000000>;
73
+
};
74
+
75
+
vdd_5v_lan: vdd-5v-lan-regulator {
76
+
compatible = "regulator-fixed";
77
+
enable-active-high;
78
+
gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
79
+
pinctrl-0 = <&lan_vdd_pin>;
80
+
pinctrl-names = "default";
81
+
regulator-name = "vdd_5v_lan";
82
+
regulator-always-on;
83
+
regulator-boot-on;
84
+
vin-supply = <&vcc_sys>;
85
+
};
86
+
};
87
+
88
+
&cpu0 {
89
+
cpu-supply = <&vdd_arm>;
90
+
};
91
+
92
+
&cpu1 {
93
+
cpu-supply = <&vdd_arm>;
94
+
};
95
+
96
+
&cpu2 {
97
+
cpu-supply = <&vdd_arm>;
98
+
};
99
+
100
+
&cpu3 {
101
+
cpu-supply = <&vdd_arm>;
102
+
};
103
+
104
+
&display_subsystem {
105
+
status = "disabled";
106
+
};
107
+
108
+
&gmac2io {
109
+
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
110
+
assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
111
+
clock_in_out = "input";
112
+
phy-mode = "rgmii";
113
+
phy-supply = <&vcc_io>;
114
+
pinctrl-0 = <&rgmiim1_pins>;
115
+
pinctrl-names = "default";
116
+
snps,aal;
117
+
118
+
mdio {
119
+
compatible = "snps,dwmac-mdio";
120
+
#address-cells = <1>;
121
+
#size-cells = <0>;
122
+
};
123
+
};
124
+
125
+
&i2c1 {
126
+
status = "okay";
127
+
128
+
rk805: pmic@18 {
129
+
compatible = "rockchip,rk805";
130
+
reg = <0x18>;
131
+
interrupt-parent = <&gpio1>;
132
+
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
133
+
#clock-cells = <1>;
134
+
clock-output-names = "xin32k", "rk805-clkout2";
135
+
gpio-controller;
136
+
#gpio-cells = <2>;
137
+
pinctrl-0 = <&pmic_int_l>;
138
+
pinctrl-names = "default";
139
+
system-power-controller;
140
+
wakeup-source;
141
+
142
+
vcc1-supply = <&vcc_sys>;
143
+
vcc2-supply = <&vcc_sys>;
144
+
vcc3-supply = <&vcc_sys>;
145
+
vcc4-supply = <&vcc_sys>;
146
+
vcc5-supply = <&vcc_io>;
147
+
vcc6-supply = <&vcc_sys>;
148
+
149
+
regulators {
150
+
vdd_log: DCDC_REG1 {
151
+
regulator-name = "vdd_log";
152
+
regulator-always-on;
153
+
regulator-boot-on;
154
+
regulator-min-microvolt = <712500>;
155
+
regulator-max-microvolt = <1450000>;
156
+
regulator-ramp-delay = <12500>;
157
+
158
+
regulator-state-mem {
159
+
regulator-on-in-suspend;
160
+
regulator-suspend-microvolt = <1000000>;
161
+
};
162
+
};
163
+
164
+
vdd_arm: DCDC_REG2 {
165
+
regulator-name = "vdd_arm";
166
+
regulator-always-on;
167
+
regulator-boot-on;
168
+
regulator-min-microvolt = <712500>;
169
+
regulator-max-microvolt = <1450000>;
170
+
regulator-ramp-delay = <12500>;
171
+
172
+
regulator-state-mem {
173
+
regulator-on-in-suspend;
174
+
regulator-suspend-microvolt = <950000>;
175
+
};
176
+
};
177
+
178
+
vcc_ddr: DCDC_REG3 {
179
+
regulator-name = "vcc_ddr";
180
+
regulator-always-on;
181
+
regulator-boot-on;
182
+
183
+
regulator-state-mem {
184
+
regulator-on-in-suspend;
185
+
};
186
+
};
187
+
188
+
vcc_io: DCDC_REG4 {
189
+
regulator-name = "vcc_io";
190
+
regulator-always-on;
191
+
regulator-boot-on;
192
+
regulator-min-microvolt = <3300000>;
193
+
regulator-max-microvolt = <3300000>;
194
+
195
+
regulator-state-mem {
196
+
regulator-on-in-suspend;
197
+
regulator-suspend-microvolt = <3300000>;
198
+
};
199
+
};
200
+
201
+
vcc_18: LDO_REG1 {
202
+
regulator-name = "vcc_18";
203
+
regulator-always-on;
204
+
regulator-boot-on;
205
+
regulator-min-microvolt = <1800000>;
206
+
regulator-max-microvolt = <1800000>;
207
+
208
+
regulator-state-mem {
209
+
regulator-on-in-suspend;
210
+
regulator-suspend-microvolt = <1800000>;
211
+
};
212
+
};
213
+
214
+
vcc18_emmc: LDO_REG2 {
215
+
regulator-name = "vcc18_emmc";
216
+
regulator-always-on;
217
+
regulator-boot-on;
218
+
regulator-min-microvolt = <1800000>;
219
+
regulator-max-microvolt = <1800000>;
220
+
221
+
regulator-state-mem {
222
+
regulator-on-in-suspend;
223
+
regulator-suspend-microvolt = <1800000>;
224
+
};
225
+
};
226
+
227
+
vdd_10: LDO_REG3 {
228
+
regulator-name = "vdd_10";
229
+
regulator-always-on;
230
+
regulator-boot-on;
231
+
regulator-min-microvolt = <1000000>;
232
+
regulator-max-microvolt = <1000000>;
233
+
234
+
regulator-state-mem {
235
+
regulator-on-in-suspend;
236
+
regulator-suspend-microvolt = <1000000>;
237
+
};
238
+
};
239
+
};
240
+
};
241
+
};
242
+
243
+
&io_domains {
244
+
pmuio-supply = <&vcc_io>;
245
+
vccio1-supply = <&vcc_io>;
246
+
vccio2-supply = <&vcc18_emmc>;
247
+
vccio3-supply = <&vcc_io>;
248
+
vccio4-supply = <&vcc_io>;
249
+
vccio5-supply = <&vcc_io>;
250
+
vccio6-supply = <&vcc_io>;
251
+
status = "okay";
252
+
};
253
+
254
+
&pinctrl {
255
+
gmac2io {
256
+
eth_phy_reset_pin: eth-phy-reset-pin {
257
+
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
258
+
};
259
+
};
260
+
261
+
leds {
262
+
lan_led_pin: lan-led-pin {
263
+
rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
264
+
};
265
+
266
+
sys_led_pin: sys-led-pin {
267
+
rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
268
+
};
269
+
270
+
wan_led_pin: wan-led-pin {
271
+
rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
272
+
};
273
+
};
274
+
275
+
lan {
276
+
lan_vdd_pin: lan-vdd-pin {
277
+
rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
278
+
};
279
+
};
280
+
281
+
pmic {
282
+
pmic_int_l: pmic-int-l {
283
+
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
284
+
};
285
+
};
286
+
};
287
+
288
+
&pwm2 {
289
+
status = "okay";
290
+
};
291
+
292
+
&sdmmc {
293
+
bus-width = <4>;
294
+
cap-sd-highspeed;
295
+
disable-wp;
296
+
pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
297
+
pinctrl-names = "default";
298
+
vmmc-supply = <&vcc_sd>;
299
+
status = "okay";
300
+
};
301
+
302
+
&spi0 {
303
+
status = "okay";
304
+
305
+
flash@0 {
306
+
compatible = "jedec,spi-nor";
307
+
reg = <0>;
308
+
spi-max-frequency = <50000000>;
309
+
};
310
+
};
311
+
312
+
&tsadc {
313
+
rockchip,hw-tshut-mode = <0>;
314
+
rockchip,hw-tshut-polarity = <0>;
315
+
status = "okay";
316
+
};
317
+
318
+
&u2phy {
319
+
status = "okay";
320
+
};
321
+
322
+
&u2phy_host {
323
+
status = "okay";
324
+
};
325
+
326
+
&u2phy_otg {
327
+
status = "okay";
328
+
};
329
+
330
+
&uart2 {
331
+
status = "okay";
332
+
};
333
+
334
+
&usb20_otg {
335
+
dr_mode = "host";
336
+
status = "okay";
337
+
};
338
+
339
+
&usbdrd3 {
340
+
dr_mode = "host";
341
+
status = "okay";
342
+
#address-cells = <1>;
343
+
#size-cells = <0>;
344
+
345
+
/* Second port is for USB 3.0 */
346
+
rtl8153: device@2 {
347
+
compatible = "usbbda,8153";
348
+
reg = <2>;
349
+
};
350
+
};
351
+
352
+
&usb_host0_ehci {
353
+
status = "okay";
354
+
};
355
+
356
+
&usb_host0_ohci {
357
+
status = "okay";
358
+
};
+11
-368
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+11
-368
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
···
4
4
*/
5
5
6
6
/dts-v1/;
7
-
#include "rk3328.dtsi"
7
+
8
+
#include <dt-bindings/input/input.h>
9
+
#include "rk3328-roc.dtsi"
8
10
9
11
/ {
10
-
model = "Firefly roc-rk3328-cc";
12
+
model = "Firefly ROC-RK3328-CC";
11
13
compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
12
-
13
-
aliases {
14
-
ethernet0 = &gmac2io;
15
-
mmc0 = &sdmmc;
16
-
mmc1 = &emmc;
17
-
};
18
-
19
-
chosen {
20
-
stdout-path = "serial2:1500000n8";
21
-
};
22
-
23
-
gmac_clkin: external-gmac-clock {
24
-
compatible = "fixed-clock";
25
-
clock-frequency = <125000000>;
26
-
clock-output-names = "gmac_clkin";
27
-
#clock-cells = <0>;
28
-
};
29
-
30
-
dc_12v: dc-12v {
31
-
compatible = "regulator-fixed";
32
-
regulator-name = "dc_12v";
33
-
regulator-always-on;
34
-
regulator-boot-on;
35
-
regulator-min-microvolt = <12000000>;
36
-
regulator-max-microvolt = <12000000>;
37
-
};
38
-
39
-
vcc_sd: sdmmc-regulator {
40
-
compatible = "regulator-fixed";
41
-
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
42
-
pinctrl-names = "default";
43
-
pinctrl-0 = <&sdmmc0m1_pin>;
44
-
regulator-boot-on;
45
-
regulator-name = "vcc_sd";
46
-
regulator-min-microvolt = <3300000>;
47
-
regulator-max-microvolt = <3300000>;
48
-
vin-supply = <&vcc_io>;
49
-
};
50
-
51
-
vcc_sdio: sdmmcio-regulator {
52
-
compatible = "regulator-gpio";
53
-
gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>;
54
-
states = <1800000 0x1>,
55
-
<3300000 0x0>;
56
-
regulator-name = "vcc_sdio";
57
-
regulator-type = "voltage";
58
-
regulator-min-microvolt = <1800000>;
59
-
regulator-max-microvolt = <3300000>;
60
-
regulator-always-on;
61
-
vin-supply = <&vcc_sys>;
62
-
};
63
-
64
-
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
65
-
compatible = "regulator-fixed";
66
-
enable-active-high;
67
-
gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
68
-
pinctrl-names = "default";
69
-
pinctrl-0 = <&usb20_host_drv>;
70
-
regulator-name = "vcc_host1_5v";
71
-
regulator-always-on;
72
-
vin-supply = <&vcc_sys>;
73
-
};
74
-
75
-
vcc_sys: vcc-sys {
76
-
compatible = "regulator-fixed";
77
-
regulator-name = "vcc_sys";
78
-
regulator-always-on;
79
-
regulator-boot-on;
80
-
regulator-min-microvolt = <5000000>;
81
-
regulator-max-microvolt = <5000000>;
82
-
vin-supply = <&dc_12v>;
83
-
};
84
-
85
-
vcc_phy: vcc-phy-regulator {
86
-
compatible = "regulator-fixed";
87
-
regulator-name = "vcc_phy";
88
-
regulator-always-on;
89
-
regulator-boot-on;
90
-
};
91
-
92
-
leds {
93
-
compatible = "gpio-leds";
94
-
95
-
power_led: led-0 {
96
-
label = "firefly:blue:power";
97
-
linux,default-trigger = "heartbeat";
98
-
gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
99
-
default-state = "on";
100
-
};
101
-
102
-
user_led: led-1 {
103
-
label = "firefly:yellow:user";
104
-
linux,default-trigger = "mmc1";
105
-
gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
106
-
default-state = "off";
107
-
};
108
-
};
109
14
};
110
15
111
-
&analog_sound {
112
-
status = "okay";
16
+
&rk805 {
17
+
interrupt-parent = <&gpio1>;
18
+
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
113
19
};
114
20
115
-
&codec {
116
-
status = "okay";
21
+
&vcc_host1_5v {
22
+
gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
117
23
};
118
24
119
-
&cpu0 {
120
-
cpu-supply = <&vdd_arm>;
121
-
};
122
-
123
-
&cpu1 {
124
-
cpu-supply = <&vdd_arm>;
125
-
};
126
-
127
-
&cpu2 {
128
-
cpu-supply = <&vdd_arm>;
129
-
};
130
-
131
-
&cpu3 {
132
-
cpu-supply = <&vdd_arm>;
133
-
};
134
-
135
-
&emmc {
136
-
bus-width = <8>;
137
-
cap-mmc-highspeed;
138
-
max-frequency = <150000000>;
139
-
mmc-ddr-1_8v;
140
-
mmc-hs200-1_8v;
141
-
non-removable;
142
-
pinctrl-names = "default";
143
-
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
144
-
vmmc-supply = <&vcc_io>;
145
-
vqmmc-supply = <&vcc18_emmc>;
146
-
status = "okay";
147
-
};
148
-
149
-
&gmac2io {
150
-
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
151
-
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
152
-
clock_in_out = "input";
153
-
phy-supply = <&vcc_phy>;
154
-
phy-mode = "rgmii";
155
-
pinctrl-names = "default";
156
-
pinctrl-0 = <&rgmiim1_pins>;
157
-
snps,aal;
158
-
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
159
-
snps,reset-active-low;
160
-
snps,reset-delays-us = <0 10000 50000>;
161
-
snps,rxpbl = <0x4>;
162
-
snps,txpbl = <0x4>;
163
-
tx_delay = <0x24>;
164
-
rx_delay = <0x18>;
165
-
status = "okay";
166
-
};
167
-
168
-
&hdmi {
169
-
status = "okay";
170
-
};
171
-
172
-
&hdmiphy {
173
-
status = "okay";
174
-
};
175
-
176
-
&hdmi_sound {
177
-
status = "okay";
178
-
};
179
-
180
-
&i2c1 {
181
-
status = "okay";
182
-
183
-
rk805: pmic@18 {
184
-
compatible = "rockchip,rk805";
185
-
reg = <0x18>;
186
-
interrupt-parent = <&gpio1>;
187
-
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
188
-
#clock-cells = <1>;
189
-
clock-output-names = "xin32k", "rk805-clkout2";
190
-
gpio-controller;
191
-
#gpio-cells = <2>;
192
-
pinctrl-names = "default";
193
-
pinctrl-0 = <&pmic_int_l>;
194
-
rockchip,system-power-controller;
195
-
wakeup-source;
196
-
197
-
vcc1-supply = <&vcc_sys>;
198
-
vcc2-supply = <&vcc_sys>;
199
-
vcc3-supply = <&vcc_sys>;
200
-
vcc4-supply = <&vcc_sys>;
201
-
vcc5-supply = <&vcc_io>;
202
-
vcc6-supply = <&vcc_io>;
203
-
204
-
regulators {
205
-
vdd_logic: DCDC_REG1 {
206
-
regulator-name = "vdd_logic";
207
-
regulator-min-microvolt = <712500>;
208
-
regulator-max-microvolt = <1450000>;
209
-
regulator-always-on;
210
-
regulator-boot-on;
211
-
regulator-state-mem {
212
-
regulator-on-in-suspend;
213
-
regulator-suspend-microvolt = <1000000>;
214
-
};
215
-
};
216
-
217
-
vdd_arm: DCDC_REG2 {
218
-
regulator-name = "vdd_arm";
219
-
regulator-min-microvolt = <712500>;
220
-
regulator-max-microvolt = <1450000>;
221
-
regulator-always-on;
222
-
regulator-boot-on;
223
-
regulator-state-mem {
224
-
regulator-on-in-suspend;
225
-
regulator-suspend-microvolt = <950000>;
226
-
};
227
-
};
228
-
229
-
vcc_ddr: DCDC_REG3 {
230
-
regulator-name = "vcc_ddr";
231
-
regulator-always-on;
232
-
regulator-boot-on;
233
-
regulator-state-mem {
234
-
regulator-on-in-suspend;
235
-
};
236
-
};
237
-
238
-
vcc_io: DCDC_REG4 {
239
-
regulator-name = "vcc_io";
240
-
regulator-min-microvolt = <3300000>;
241
-
regulator-max-microvolt = <3300000>;
242
-
regulator-always-on;
243
-
regulator-boot-on;
244
-
regulator-state-mem {
245
-
regulator-on-in-suspend;
246
-
regulator-suspend-microvolt = <3300000>;
247
-
};
248
-
};
249
-
250
-
vcc_18: LDO_REG1 {
251
-
regulator-name = "vcc_18";
252
-
regulator-min-microvolt = <1800000>;
253
-
regulator-max-microvolt = <1800000>;
254
-
regulator-always-on;
255
-
regulator-boot-on;
256
-
regulator-state-mem {
257
-
regulator-on-in-suspend;
258
-
regulator-suspend-microvolt = <1800000>;
259
-
};
260
-
};
261
-
262
-
vcc18_emmc: LDO_REG2 {
263
-
regulator-name = "vcc18_emmc";
264
-
regulator-min-microvolt = <1800000>;
265
-
regulator-max-microvolt = <1800000>;
266
-
regulator-always-on;
267
-
regulator-boot-on;
268
-
regulator-state-mem {
269
-
regulator-on-in-suspend;
270
-
regulator-suspend-microvolt = <1800000>;
271
-
};
272
-
};
273
-
274
-
vdd_10: LDO_REG3 {
275
-
regulator-name = "vdd_10";
276
-
regulator-min-microvolt = <1000000>;
277
-
regulator-max-microvolt = <1000000>;
278
-
regulator-always-on;
279
-
regulator-boot-on;
280
-
regulator-state-mem {
281
-
regulator-on-in-suspend;
282
-
regulator-suspend-microvolt = <1000000>;
283
-
};
284
-
};
285
-
};
286
-
};
287
-
};
288
-
289
-
&i2s0 {
290
-
status = "okay";
291
-
};
292
-
293
-
&i2s1 {
294
-
status = "okay";
295
-
};
296
-
297
-
&io_domains {
298
-
status = "okay";
299
-
300
-
vccio1-supply = <&vcc_io>;
301
-
vccio2-supply = <&vcc18_emmc>;
302
-
vccio3-supply = <&vcc_sdio>;
303
-
vccio4-supply = <&vcc_18>;
304
-
vccio5-supply = <&vcc_io>;
305
-
vccio6-supply = <&vcc_io>;
306
-
pmuio-supply = <&vcc_io>;
307
-
};
308
-
309
-
&pinctrl {
310
-
pmic {
311
-
pmic_int_l: pmic-int-l {
312
-
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
313
-
};
314
-
};
315
-
316
-
usb2 {
317
-
usb20_host_drv: usb20-host-drv {
318
-
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
319
-
};
320
-
};
321
-
};
322
-
323
-
&sdmmc {
324
-
bus-width = <4>;
325
-
cap-mmc-highspeed;
326
-
cap-sd-highspeed;
327
-
disable-wp;
328
-
max-frequency = <150000000>;
329
-
pinctrl-names = "default";
330
-
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
331
-
sd-uhs-sdr12;
332
-
sd-uhs-sdr25;
333
-
sd-uhs-sdr50;
334
-
sd-uhs-sdr104;
335
-
vmmc-supply = <&vcc_sd>;
336
-
vqmmc-supply = <&vcc_sdio>;
337
-
status = "okay";
338
-
};
339
-
340
-
&tsadc {
341
-
status = "okay";
342
-
};
343
-
344
-
&u2phy {
345
-
status = "okay";
346
-
};
347
-
348
-
&u2phy_host {
349
-
status = "okay";
350
-
};
351
-
352
-
&u2phy_otg {
353
-
status = "okay";
354
-
};
355
-
356
-
&uart2 {
357
-
status = "okay";
358
-
};
359
-
360
-
&usb20_otg {
361
-
dr_mode = "host";
362
-
status = "okay";
363
-
};
364
-
365
-
&usbdrd3 {
366
-
dr_mode = "host";
367
-
status = "okay";
368
-
};
369
-
370
-
&usb_host0_ehci {
371
-
status = "okay";
372
-
};
373
-
374
-
&usb_host0_ohci {
375
-
status = "okay";
376
-
};
377
-
378
-
&vop {
379
-
status = "okay";
380
-
};
381
-
382
-
&vop_mmu {
383
-
status = "okay";
25
+
&vcc_sdio {
26
+
gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>;
384
27
};
+1
-2
arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
+1
-2
arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
+377
arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
+377
arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
4
+
*/
5
+
6
+
/dts-v1/;
7
+
8
+
#include "rk3328.dtsi"
9
+
10
+
/ {
11
+
aliases {
12
+
ethernet0 = &gmac2io;
13
+
mmc0 = &sdmmc;
14
+
mmc1 = &emmc;
15
+
};
16
+
17
+
chosen {
18
+
stdout-path = "serial2:1500000n8";
19
+
};
20
+
21
+
gmac_clkin: external-gmac-clock {
22
+
compatible = "fixed-clock";
23
+
clock-frequency = <125000000>;
24
+
clock-output-names = "gmac_clkin";
25
+
#clock-cells = <0>;
26
+
};
27
+
28
+
dc_12v: dc-12v {
29
+
compatible = "regulator-fixed";
30
+
regulator-name = "dc_12v";
31
+
regulator-always-on;
32
+
regulator-boot-on;
33
+
regulator-min-microvolt = <12000000>;
34
+
regulator-max-microvolt = <12000000>;
35
+
};
36
+
37
+
vcc_sd: sdmmc-regulator {
38
+
compatible = "regulator-fixed";
39
+
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
40
+
pinctrl-names = "default";
41
+
pinctrl-0 = <&sdmmc0m1_pin>;
42
+
regulator-boot-on;
43
+
regulator-name = "vcc_sd";
44
+
regulator-min-microvolt = <3300000>;
45
+
regulator-max-microvolt = <3300000>;
46
+
vin-supply = <&vcc_io>;
47
+
};
48
+
49
+
vcc_sdio: sdmmcio-regulator {
50
+
compatible = "regulator-gpio";
51
+
states = <1800000 0x1>, <3300000 0x0>;
52
+
regulator-name = "vcc_sdio";
53
+
regulator-type = "voltage";
54
+
regulator-min-microvolt = <1800000>;
55
+
regulator-max-microvolt = <3300000>;
56
+
regulator-always-on;
57
+
vin-supply = <&vcc_sys>;
58
+
};
59
+
60
+
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
61
+
compatible = "regulator-fixed";
62
+
enable-active-high;
63
+
pinctrl-names = "default";
64
+
pinctrl-0 = <&usb20_host_drv>;
65
+
regulator-name = "vcc_host1_5v";
66
+
regulator-always-on;
67
+
vin-supply = <&vcc_sys>;
68
+
};
69
+
70
+
vcc_sys: vcc-sys {
71
+
compatible = "regulator-fixed";
72
+
regulator-name = "vcc_sys";
73
+
regulator-always-on;
74
+
regulator-boot-on;
75
+
regulator-min-microvolt = <5000000>;
76
+
regulator-max-microvolt = <5000000>;
77
+
vin-supply = <&dc_12v>;
78
+
};
79
+
80
+
vcc_phy: vcc-phy-regulator {
81
+
compatible = "regulator-fixed";
82
+
regulator-name = "vcc_phy";
83
+
regulator-always-on;
84
+
regulator-boot-on;
85
+
};
86
+
87
+
leds {
88
+
compatible = "gpio-leds";
89
+
90
+
power_led: led-0 {
91
+
label = "firefly:blue:power";
92
+
linux,default-trigger = "heartbeat";
93
+
gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
94
+
default-state = "on";
95
+
};
96
+
97
+
user_led: led-1 {
98
+
label = "firefly:yellow:user";
99
+
linux,default-trigger = "mmc1";
100
+
gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
101
+
default-state = "off";
102
+
};
103
+
};
104
+
};
105
+
106
+
&analog_sound {
107
+
status = "okay";
108
+
};
109
+
110
+
&codec {
111
+
status = "okay";
112
+
};
113
+
114
+
&cpu0 {
115
+
cpu-supply = <&vdd_arm>;
116
+
};
117
+
118
+
&cpu1 {
119
+
cpu-supply = <&vdd_arm>;
120
+
};
121
+
122
+
&cpu2 {
123
+
cpu-supply = <&vdd_arm>;
124
+
};
125
+
126
+
&cpu3 {
127
+
cpu-supply = <&vdd_arm>;
128
+
};
129
+
130
+
&emmc {
131
+
bus-width = <8>;
132
+
cap-mmc-highspeed;
133
+
max-frequency = <150000000>;
134
+
mmc-ddr-1_8v;
135
+
mmc-hs200-1_8v;
136
+
non-removable;
137
+
pinctrl-names = "default";
138
+
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
139
+
vmmc-supply = <&vcc_io>;
140
+
vqmmc-supply = <&vcc18_emmc>;
141
+
status = "okay";
142
+
};
143
+
144
+
&gmac2io {
145
+
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
146
+
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
147
+
clock_in_out = "input";
148
+
phy-supply = <&vcc_phy>;
149
+
phy-mode = "rgmii";
150
+
pinctrl-names = "default";
151
+
pinctrl-0 = <&rgmiim1_pins>;
152
+
snps,aal;
153
+
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
154
+
snps,reset-active-low;
155
+
snps,reset-delays-us = <0 10000 50000>;
156
+
snps,rxpbl = <0x4>;
157
+
snps,txpbl = <0x4>;
158
+
tx_delay = <0x24>;
159
+
rx_delay = <0x18>;
160
+
status = "okay";
161
+
};
162
+
163
+
&hdmi {
164
+
status = "okay";
165
+
};
166
+
167
+
&hdmiphy {
168
+
status = "okay";
169
+
};
170
+
171
+
&hdmi_sound {
172
+
status = "okay";
173
+
};
174
+
175
+
&i2c1 {
176
+
status = "okay";
177
+
178
+
rk805: pmic@18 {
179
+
compatible = "rockchip,rk805";
180
+
reg = <0x18>;
181
+
#clock-cells = <1>;
182
+
clock-output-names = "xin32k", "rk805-clkout2";
183
+
gpio-controller;
184
+
#gpio-cells = <2>;
185
+
pinctrl-names = "default";
186
+
pinctrl-0 = <&pmic_int_l>;
187
+
system-power-controller;
188
+
wakeup-source;
189
+
190
+
vcc1-supply = <&vcc_sys>;
191
+
vcc2-supply = <&vcc_sys>;
192
+
vcc3-supply = <&vcc_sys>;
193
+
vcc4-supply = <&vcc_sys>;
194
+
vcc5-supply = <&vcc_io>;
195
+
vcc6-supply = <&vcc_io>;
196
+
197
+
regulators {
198
+
vdd_logic: DCDC_REG1 {
199
+
regulator-name = "vdd_logic";
200
+
regulator-min-microvolt = <712500>;
201
+
regulator-max-microvolt = <1450000>;
202
+
regulator-always-on;
203
+
regulator-boot-on;
204
+
regulator-state-mem {
205
+
regulator-on-in-suspend;
206
+
regulator-suspend-microvolt = <1000000>;
207
+
};
208
+
};
209
+
210
+
vdd_arm: DCDC_REG2 {
211
+
regulator-name = "vdd_arm";
212
+
regulator-min-microvolt = <712500>;
213
+
regulator-max-microvolt = <1450000>;
214
+
regulator-always-on;
215
+
regulator-boot-on;
216
+
regulator-state-mem {
217
+
regulator-on-in-suspend;
218
+
regulator-suspend-microvolt = <950000>;
219
+
};
220
+
};
221
+
222
+
vcc_ddr: DCDC_REG3 {
223
+
regulator-name = "vcc_ddr";
224
+
regulator-always-on;
225
+
regulator-boot-on;
226
+
regulator-state-mem {
227
+
regulator-on-in-suspend;
228
+
};
229
+
};
230
+
231
+
vcc_io: DCDC_REG4 {
232
+
regulator-name = "vcc_io";
233
+
regulator-min-microvolt = <3300000>;
234
+
regulator-max-microvolt = <3300000>;
235
+
regulator-always-on;
236
+
regulator-boot-on;
237
+
regulator-state-mem {
238
+
regulator-on-in-suspend;
239
+
regulator-suspend-microvolt = <3300000>;
240
+
};
241
+
};
242
+
243
+
vcc_18: LDO_REG1 {
244
+
regulator-name = "vcc_18";
245
+
regulator-min-microvolt = <1800000>;
246
+
regulator-max-microvolt = <1800000>;
247
+
regulator-always-on;
248
+
regulator-boot-on;
249
+
regulator-state-mem {
250
+
regulator-on-in-suspend;
251
+
regulator-suspend-microvolt = <1800000>;
252
+
};
253
+
};
254
+
255
+
vcc18_emmc: LDO_REG2 {
256
+
regulator-name = "vcc18_emmc";
257
+
regulator-min-microvolt = <1800000>;
258
+
regulator-max-microvolt = <1800000>;
259
+
regulator-always-on;
260
+
regulator-boot-on;
261
+
regulator-state-mem {
262
+
regulator-on-in-suspend;
263
+
regulator-suspend-microvolt = <1800000>;
264
+
};
265
+
};
266
+
267
+
vdd_10: LDO_REG3 {
268
+
regulator-name = "vdd_10";
269
+
regulator-min-microvolt = <1000000>;
270
+
regulator-max-microvolt = <1000000>;
271
+
regulator-always-on;
272
+
regulator-boot-on;
273
+
regulator-state-mem {
274
+
regulator-on-in-suspend;
275
+
regulator-suspend-microvolt = <1000000>;
276
+
};
277
+
};
278
+
};
279
+
};
280
+
};
281
+
282
+
&i2s0 {
283
+
status = "okay";
284
+
};
285
+
286
+
&i2s1 {
287
+
status = "okay";
288
+
};
289
+
290
+
&io_domains {
291
+
status = "okay";
292
+
293
+
vccio1-supply = <&vcc_io>;
294
+
vccio2-supply = <&vcc18_emmc>;
295
+
vccio3-supply = <&vcc_sdio>;
296
+
vccio4-supply = <&vcc_18>;
297
+
vccio5-supply = <&vcc_io>;
298
+
vccio6-supply = <&vcc_io>;
299
+
pmuio-supply = <&vcc_io>;
300
+
};
301
+
302
+
&pinctrl {
303
+
pmic {
304
+
pmic_int_l: pmic-int-l {
305
+
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
306
+
};
307
+
};
308
+
309
+
usb2 {
310
+
usb20_host_drv: usb20-host-drv {
311
+
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
312
+
};
313
+
};
314
+
};
315
+
316
+
&sdmmc {
317
+
bus-width = <4>;
318
+
cap-mmc-highspeed;
319
+
cap-sd-highspeed;
320
+
disable-wp;
321
+
max-frequency = <150000000>;
322
+
pinctrl-names = "default";
323
+
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
324
+
sd-uhs-sdr12;
325
+
sd-uhs-sdr25;
326
+
sd-uhs-sdr50;
327
+
sd-uhs-sdr104;
328
+
vmmc-supply = <&vcc_sd>;
329
+
vqmmc-supply = <&vcc_sdio>;
330
+
status = "okay";
331
+
};
332
+
333
+
&tsadc {
334
+
status = "okay";
335
+
};
336
+
337
+
&u2phy {
338
+
status = "okay";
339
+
};
340
+
341
+
&u2phy_host {
342
+
status = "okay";
343
+
};
344
+
345
+
&u2phy_otg {
346
+
status = "okay";
347
+
};
348
+
349
+
&uart2 {
350
+
status = "okay";
351
+
};
352
+
353
+
&usb20_otg {
354
+
dr_mode = "host";
355
+
status = "okay";
356
+
};
357
+
358
+
&usbdrd3 {
359
+
dr_mode = "host";
360
+
status = "okay";
361
+
};
362
+
363
+
&usb_host0_ehci {
364
+
status = "okay";
365
+
};
366
+
367
+
&usb_host0_ohci {
368
+
status = "okay";
369
+
};
370
+
371
+
&vop {
372
+
status = "okay";
373
+
};
374
+
375
+
&vop_mmu {
376
+
status = "okay";
377
+
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+3
-1
arch/arm64/boot/dts/rockchip/rk3328.dtsi
+3
-1
arch/arm64/boot/dts/rockchip/rk3328.dtsi
···
813
813
};
814
814
815
815
cru: clock-controller@ff440000 {
816
-
compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
816
+
compatible = "rockchip,rk3328-cru";
817
817
reg = <0x0 0xff440000 0x0 0x1000>;
818
+
clocks = <&xin24m>;
819
+
clock-names = "xin24m";
818
820
rockchip,grf = <&grf>;
819
821
#clock-cells = <1>;
820
822
#reset-cells = <1>;
+1
-1
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
···
113
113
pinctrl-0 = <&pmic_int>, <&pmic_sleep>;
114
114
interrupt-parent = <&gpio0>;
115
115
interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
116
-
rockchip,system-power-controller;
116
+
system-power-controller;
117
117
vcc1-supply = <&vcc_sys>;
118
118
vcc2-supply = <&vcc_sys>;
119
119
vcc3-supply = <&vcc_sys>;
+1
-1
arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3368-lba3368.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
+2
-2
arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts
+2
-2
arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts
···
309
309
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
310
310
pinctrl-names = "default";
311
311
pinctrl-0 = <&pmic_int_l>;
312
-
rockchip,system-power-controller;
312
+
system-power-controller;
313
313
wakeup-source;
314
314
#clock-cells = <1>;
315
315
clock-output-names = "xin32k", "rk808-clkout2";
···
545
545
reg = <0x1a>;
546
546
clocks = <&cru SCLK_I2S_8CH_OUT>;
547
547
clock-names = "mclk";
548
-
hp-det-gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
548
+
hp-det-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
549
549
spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
550
550
#sound-dai-cells = <0>;
551
551
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-evb.dts
···
178
178
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
179
179
pinctrl-names = "default";
180
180
pinctrl-0 = <&pmic_int_l>;
181
-
rockchip,system-power-controller;
181
+
system-power-controller;
182
182
wakeup-source;
183
183
#clock-cells = <1>;
184
184
clock-output-names = "rk808-clkout1", "rk808-clkout2";
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
···
309
309
clock-output-names = "xin32k", "rk808-clkout2";
310
310
pinctrl-names = "default";
311
311
pinctrl-0 = <&pmic_int_l>;
312
-
rockchip,system-power-controller;
312
+
system-power-controller;
313
313
vcc1-supply = <&vcc5v0_sys>;
314
314
vcc2-supply = <&vcc5v0_sys>;
315
315
vcc3-supply = <&vcc5v0_sys>;
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts
+2
-45
arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts
+2
-45
arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dts
···
10
10
*/
11
11
12
12
/dts-v1/;
13
-
#include "rk3399-nanopi4.dtsi"
13
+
14
+
#include "rk3399-nanopi-m4.dtsi"
14
15
15
16
/ {
16
17
model = "FriendlyElec NanoPi M4";
17
18
compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
18
-
19
-
vdd_5v: vdd-5v {
20
-
compatible = "regulator-fixed";
21
-
regulator-name = "vdd_5v";
22
-
regulator-always-on;
23
-
regulator-boot-on;
24
-
};
25
-
26
-
vcc5v0_core: vcc5v0-core {
27
-
compatible = "regulator-fixed";
28
-
regulator-name = "vcc5v0_core";
29
-
regulator-always-on;
30
-
regulator-boot-on;
31
-
vin-supply = <&vdd_5v>;
32
-
};
33
-
34
-
vcc5v0_usb1: vcc5v0-usb1 {
35
-
compatible = "regulator-fixed";
36
-
regulator-name = "vcc5v0_usb1";
37
-
regulator-always-on;
38
-
regulator-boot-on;
39
-
vin-supply = <&vcc5v0_sys>;
40
-
};
41
-
42
-
vcc5v0_usb2: vcc5v0-usb2 {
43
-
compatible = "regulator-fixed";
44
-
regulator-name = "vcc5v0_usb2";
45
-
regulator-always-on;
46
-
regulator-boot-on;
47
-
vin-supply = <&vcc5v0_sys>;
48
-
};
49
-
};
50
-
51
-
&vcc3v3_sys {
52
-
vin-supply = <&vcc5v0_core>;
53
19
};
54
20
55
21
&u2phy0_host {
56
22
phy-supply = <&vcc5v0_usb1>;
57
-
};
58
-
59
-
&u2phy1_host {
60
-
phy-supply = <&vcc5v0_usb2>;
61
-
};
62
-
63
-
&vbus_typec {
64
-
regulator-always-on;
65
-
vin-supply = <&vdd_5v>;
66
23
};
+60
arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dtsi
+60
arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* FriendlyElec NanoPi M4 board device tree source
4
+
*
5
+
* Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
6
+
* (http://www.friendlyarm.com)
7
+
*
8
+
* Copyright (c) 2018 Collabora Ltd.
9
+
* Copyright (c) 2019 Arm Ltd.
10
+
*/
11
+
12
+
/dts-v1/;
13
+
14
+
#include "rk3399-nanopi4.dtsi"
15
+
16
+
/ {
17
+
vdd_5v: vdd-5v {
18
+
compatible = "regulator-fixed";
19
+
regulator-name = "vdd_5v";
20
+
regulator-always-on;
21
+
regulator-boot-on;
22
+
};
23
+
24
+
vcc5v0_core: vcc5v0-core {
25
+
compatible = "regulator-fixed";
26
+
regulator-name = "vcc5v0_core";
27
+
regulator-always-on;
28
+
regulator-boot-on;
29
+
vin-supply = <&vdd_5v>;
30
+
};
31
+
32
+
vcc5v0_usb1: vcc5v0-usb1 {
33
+
compatible = "regulator-fixed";
34
+
regulator-name = "vcc5v0_usb1";
35
+
regulator-always-on;
36
+
regulator-boot-on;
37
+
vin-supply = <&vcc5v0_sys>;
38
+
};
39
+
40
+
vcc5v0_usb2: vcc5v0-usb2 {
41
+
compatible = "regulator-fixed";
42
+
regulator-name = "vcc5v0_usb2";
43
+
regulator-always-on;
44
+
regulator-boot-on;
45
+
vin-supply = <&vcc5v0_sys>;
46
+
};
47
+
};
48
+
49
+
&vcc3v3_sys {
50
+
vin-supply = <&vcc5v0_core>;
51
+
};
52
+
53
+
&u2phy1_host {
54
+
phy-supply = <&vcc5v0_usb2>;
55
+
};
56
+
57
+
&vbus_typec {
58
+
regulator-always-on;
59
+
vin-supply = <&vdd_5v>;
60
+
};
+2
-1
arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4b.dts
+2
-1
arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4b.dts
+2
-1
arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts
+2
-1
arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts
+2
-122
arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+2
-122
arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
···
1
1
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
2
/*
3
-
* FriendlyElec NanoPC-T4 board device tree source
4
-
*
5
3
* Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
6
-
* (http://www.friendlyarm.com)
7
-
*
8
-
* Copyright (c) 2018 Collabora Ltd.
9
-
*
10
-
* Copyright (c) 2020 Jensen Huang <jensenhuang@friendlyarm.com>
11
-
* Copyright (c) 2020 Marty Jones <mj8263788@gmail.com>
12
-
* Copyright (c) 2021 Tianling Shen <cnsztl@gmail.com>
13
4
*/
14
5
15
6
/dts-v1/;
16
-
#include "rk3399-nanopi4.dtsi"
7
+
8
+
#include "rk3399-nanopi-r4s.dtsi"
17
9
18
10
/ {
19
11
model = "FriendlyElec NanoPi R4S";
20
12
compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
21
-
22
-
/delete-node/ display-subsystem;
23
-
24
-
gpio-leds {
25
-
pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
26
-
27
-
/delete-node/ led-0;
28
-
29
-
lan_led: led-lan {
30
-
gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
31
-
label = "green:lan";
32
-
};
33
-
34
-
sys_led: led-sys {
35
-
gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
36
-
label = "red:power";
37
-
default-state = "on";
38
-
};
39
-
40
-
wan_led: led-wan {
41
-
gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
42
-
label = "green:wan";
43
-
};
44
-
};
45
-
46
-
gpio-keys {
47
-
pinctrl-0 = <&reset_button_pin>;
48
-
49
-
/delete-node/ key-power;
50
-
51
-
key-reset {
52
-
debounce-interval = <50>;
53
-
gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
54
-
label = "reset";
55
-
linux,code = <KEY_RESTART>;
56
-
};
57
-
};
58
-
59
-
vdd_5v: vdd-5v {
60
-
compatible = "regulator-fixed";
61
-
regulator-name = "vdd_5v";
62
-
regulator-always-on;
63
-
regulator-boot-on;
64
-
};
65
-
};
66
-
67
-
&emmc_phy {
68
-
status = "disabled";
69
-
};
70
-
71
-
&i2c4 {
72
-
status = "disabled";
73
-
};
74
-
75
-
&pcie0 {
76
-
max-link-speed = <1>;
77
-
num-lanes = <1>;
78
-
vpcie3v3-supply = <&vcc3v3_sys>;
79
-
};
80
-
81
-
&pinctrl {
82
-
gpio-leds {
83
-
/delete-node/ status-led-pin;
84
-
85
-
lan_led_pin: lan-led-pin {
86
-
rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
87
-
};
88
-
89
-
sys_led_pin: sys-led-pin {
90
-
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
91
-
};
92
-
93
-
wan_led_pin: wan-led-pin {
94
-
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
95
-
};
96
-
};
97
-
98
-
rockchip-key {
99
-
/delete-node/ power-key;
100
-
101
-
reset_button_pin: reset-button-pin {
102
-
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
103
-
};
104
-
};
105
-
};
106
-
107
-
&sdhci {
108
-
status = "disabled";
109
-
};
110
-
111
-
&sdio0 {
112
-
status = "disabled";
113
-
};
114
-
115
-
&u2phy0_host {
116
-
phy-supply = <&vdd_5v>;
117
-
};
118
-
119
-
&u2phy1_host {
120
-
status = "disabled";
121
-
};
122
-
123
-
&uart0 {
124
-
status = "disabled";
125
-
};
126
-
127
-
&usbdrd_dwc3_0 {
128
-
dr_mode = "host";
129
-
};
130
-
131
-
&vcc3v3_sys {
132
-
vin-supply = <&vcc5v0_sys>;
133
13
};
+131
arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi
+131
arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* FriendlyElec NanoPC-R4 board device tree source
4
+
*
5
+
* Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
6
+
* (http://www.friendlyarm.com)
7
+
*
8
+
* Copyright (c) 2018 Collabora Ltd.
9
+
*
10
+
* Copyright (c) 2020 Jensen Huang <jensenhuang@friendlyarm.com>
11
+
* Copyright (c) 2020 Marty Jones <mj8263788@gmail.com>
12
+
* Copyright (c) 2021 Tianling Shen <cnsztl@gmail.com>
13
+
*/
14
+
15
+
/dts-v1/;
16
+
17
+
#include "rk3399-nanopi4.dtsi"
18
+
19
+
/ {
20
+
/delete-node/ display-subsystem;
21
+
22
+
gpio-leds {
23
+
pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
24
+
25
+
/delete-node/ led-0;
26
+
27
+
lan_led: led-lan {
28
+
gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
29
+
label = "green:lan";
30
+
};
31
+
32
+
sys_led: led-sys {
33
+
gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
34
+
label = "red:power";
35
+
default-state = "on";
36
+
};
37
+
38
+
wan_led: led-wan {
39
+
gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
40
+
label = "green:wan";
41
+
};
42
+
};
43
+
44
+
gpio-keys {
45
+
pinctrl-0 = <&reset_button_pin>;
46
+
47
+
/delete-node/ key-power;
48
+
49
+
key-reset {
50
+
debounce-interval = <50>;
51
+
gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
52
+
label = "reset";
53
+
linux,code = <KEY_RESTART>;
54
+
};
55
+
};
56
+
57
+
vdd_5v: vdd-5v {
58
+
compatible = "regulator-fixed";
59
+
regulator-name = "vdd_5v";
60
+
regulator-always-on;
61
+
regulator-boot-on;
62
+
};
63
+
};
64
+
65
+
&emmc_phy {
66
+
status = "disabled";
67
+
};
68
+
69
+
&i2c4 {
70
+
status = "disabled";
71
+
};
72
+
73
+
&pcie0 {
74
+
max-link-speed = <1>;
75
+
num-lanes = <1>;
76
+
vpcie3v3-supply = <&vcc3v3_sys>;
77
+
};
78
+
79
+
&pinctrl {
80
+
gpio-leds {
81
+
/delete-node/ status-led-pin;
82
+
83
+
lan_led_pin: lan-led-pin {
84
+
rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
85
+
};
86
+
87
+
sys_led_pin: sys-led-pin {
88
+
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
89
+
};
90
+
91
+
wan_led_pin: wan-led-pin {
92
+
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
93
+
};
94
+
};
95
+
96
+
rockchip-key {
97
+
/delete-node/ power-key;
98
+
99
+
reset_button_pin: reset-button-pin {
100
+
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
101
+
};
102
+
};
103
+
};
104
+
105
+
&sdhci {
106
+
status = "disabled";
107
+
};
108
+
109
+
&sdio0 {
110
+
status = "disabled";
111
+
};
112
+
113
+
&u2phy0_host {
114
+
phy-supply = <&vdd_5v>;
115
+
};
116
+
117
+
&u2phy1_host {
118
+
status = "disabled";
119
+
};
120
+
121
+
&uart0 {
122
+
status = "disabled";
123
+
};
124
+
125
+
&usbdrd_dwc3_0 {
126
+
dr_mode = "host";
127
+
};
128
+
129
+
&vcc3v3_sys {
130
+
vin-supply = <&vcc5v0_sys>;
131
+
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts
+2
-2
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+2
-2
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
···
150
150
"Speaker", "Speaker Amplifier OUTL",
151
151
"Speaker", "Speaker Amplifier OUTR";
152
152
153
-
simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
153
+
simple-audio-card,hp-det-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
154
154
simple-audio-card,aux-devs = <&speaker_amp>;
155
155
simple-audio-card,pin-switches = "Speaker";
156
156
···
447
447
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
448
448
pinctrl-names = "default";
449
449
pinctrl-0 = <&pmic_int_l_pin>;
450
-
rockchip,system-power-controller;
450
+
system-power-controller;
451
451
wakeup-source;
452
452
453
453
vcc1-supply = <&vcc_sysin>;
+2
-23
arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+2
-23
arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
···
13
13
#include <dt-bindings/input/gpio-keys.h>
14
14
#include <dt-bindings/input/linux-event-codes.h>
15
15
#include <dt-bindings/leds/common.h>
16
-
#include "rk3399.dtsi"
16
+
#include "rk3399-s.dtsi"
17
17
18
18
/ {
19
19
model = "Pine64 PinePhone Pro";
···
243
243
clock-output-names = "xin32k", "rk808-clkout2";
244
244
pinctrl-names = "default";
245
245
pinctrl-0 = <&pmic_int_l>;
246
-
rockchip,system-power-controller;
246
+
system-power-controller;
247
247
wakeup-source;
248
248
249
249
vcc1-supply = <&vcc_sys>;
···
453
453
interrupt-parent = <&gpio1>;
454
454
interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>;
455
455
vddio-supply = <&vcc_1v8>;
456
-
};
457
-
};
458
-
459
-
&cluster0_opp {
460
-
opp04 {
461
-
status = "disabled";
462
-
};
463
-
464
-
opp05 {
465
-
status = "disabled";
466
-
};
467
-
};
468
-
469
-
&cluster1_opp {
470
-
opp06 {
471
-
opp-hz = /bits/ 64 <1500000000>;
472
-
opp-microvolt = <1100000 1100000 1150000>;
473
-
};
474
-
475
-
opp07 {
476
-
status = "disabled";
477
456
};
478
457
};
479
458
+8
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
+8
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
···
30
30
linux,code = <KEY_BATTERY>;
31
31
};
32
32
33
+
button-pwrbtn-n {
34
+
gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
35
+
label = "PWRBTN#";
36
+
linux,code = <KEY_POWER>;
37
+
};
38
+
33
39
button-slp-btn-n {
34
40
gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
35
41
label = "SLP_BTN#";
···
209
203
buttons {
210
204
haikou_keys_pin: haikou-keys-pin {
211
205
rockchip,pins =
206
+
/* PWRBTN# */
207
+
<0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
212
208
/* LID_BTN */
213
209
<0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
214
210
/* BATLOW# */
+19
-7
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
+19
-7
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
···
9
9
/ {
10
10
aliases {
11
11
ethernet0 = &gmac;
12
+
i2c10 = &i2c10;
12
13
mmc0 = &sdhci;
13
14
};
14
15
···
206
205
clock-output-names = "xin32k", "rk808-clkout2";
207
206
pinctrl-names = "default";
208
207
pinctrl-0 = <&pmic_int_l>;
209
-
rockchip,system-power-controller;
208
+
system-power-controller;
210
209
wakeup-source;
211
210
212
211
vcc1-supply = <&vcc5v0_sys>;
···
394
393
clock-frequency = <400000>;
395
394
396
395
fan: fan@18 {
397
-
compatible = "ti,amc6821";
396
+
compatible = "tsd,mule", "ti,amc6821";
398
397
reg = <0x18>;
399
-
#cooling-cells = <2>;
400
-
};
401
398
402
-
rtc_twi: rtc@6f {
403
-
compatible = "isil,isl1208";
404
-
reg = <0x6f>;
399
+
i2c-mux {
400
+
compatible = "tsd,mule-i2c-mux";
401
+
#address-cells = <1>;
402
+
#size-cells = <0>;
403
+
404
+
i2c10: i2c@0 {
405
+
reg = <0x0>;
406
+
#address-cells = <1>;
407
+
#size-cells = <0>;
408
+
409
+
rtc_twi: rtc@6f {
410
+
compatible = "isil,isl1208";
411
+
reg = <0x6f>;
412
+
};
413
+
};
414
+
};
405
415
};
406
416
};
407
417
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts
···
51
51
"Headphone Amp INR", "ROUT2",
52
52
"Headphones", "Headphone Amp OUTL",
53
53
"Headphones", "Headphone Amp OUTR";
54
-
simple-audio-card,hp-det-gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>;
54
+
simple-audio-card,hp-det-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>;
55
55
simple-audio-card,aux-devs = <&headphones_amp>;
56
56
simple-audio-card,pin-switches = "Headphones";
57
57
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+123
arch/arm64/boot/dts/rockchip/rk3399-s.dtsi
+123
arch/arm64/boot/dts/rockchip/rk3399-s.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
4
+
*/
5
+
6
+
#include "rk3399-base.dtsi"
7
+
8
+
/ {
9
+
cluster0_opp: opp-table-0 {
10
+
compatible = "operating-points-v2";
11
+
opp-shared;
12
+
13
+
opp00 {
14
+
opp-hz = /bits/ 64 <408000000>;
15
+
opp-microvolt = <825000 825000 1250000>;
16
+
clock-latency-ns = <40000>;
17
+
};
18
+
opp01 {
19
+
opp-hz = /bits/ 64 <600000000>;
20
+
opp-microvolt = <825000 825000 1250000>;
21
+
};
22
+
opp02 {
23
+
opp-hz = /bits/ 64 <816000000>;
24
+
opp-microvolt = <850000 850000 1250000>;
25
+
};
26
+
opp03 {
27
+
opp-hz = /bits/ 64 <1008000000>;
28
+
opp-microvolt = <925000 925000 1250000>;
29
+
};
30
+
};
31
+
32
+
cluster1_opp: opp-table-1 {
33
+
compatible = "operating-points-v2";
34
+
opp-shared;
35
+
36
+
opp00 {
37
+
opp-hz = /bits/ 64 <408000000>;
38
+
opp-microvolt = <825000 825000 1250000>;
39
+
clock-latency-ns = <40000>;
40
+
};
41
+
opp01 {
42
+
opp-hz = /bits/ 64 <600000000>;
43
+
opp-microvolt = <825000 825000 1250000>;
44
+
};
45
+
opp02 {
46
+
opp-hz = /bits/ 64 <816000000>;
47
+
opp-microvolt = <825000 825000 1250000>;
48
+
};
49
+
opp03 {
50
+
opp-hz = /bits/ 64 <1008000000>;
51
+
opp-microvolt = <875000 875000 1250000>;
52
+
};
53
+
opp04 {
54
+
opp-hz = /bits/ 64 <1200000000>;
55
+
opp-microvolt = <950000 950000 1250000>;
56
+
};
57
+
opp05 {
58
+
opp-hz = /bits/ 64 <1416000000>;
59
+
opp-microvolt = <1025000 1025000 1250000>;
60
+
};
61
+
opp06 {
62
+
opp-hz = /bits/ 64 <1500000000>;
63
+
opp-microvolt = <1100000 1100000 1150000>;
64
+
};
65
+
};
66
+
67
+
gpu_opp_table: opp-table-2 {
68
+
compatible = "operating-points-v2";
69
+
70
+
opp00 {
71
+
opp-hz = /bits/ 64 <200000000>;
72
+
opp-microvolt = <825000 825000 1150000>;
73
+
};
74
+
opp01 {
75
+
opp-hz = /bits/ 64 <297000000>;
76
+
opp-microvolt = <825000 825000 1150000>;
77
+
};
78
+
opp02 {
79
+
opp-hz = /bits/ 64 <400000000>;
80
+
opp-microvolt = <825000 825000 1150000>;
81
+
};
82
+
opp03 {
83
+
opp-hz = /bits/ 64 <500000000>;
84
+
opp-microvolt = <875000 875000 1150000>;
85
+
};
86
+
opp04 {
87
+
opp-hz = /bits/ 64 <600000000>;
88
+
opp-microvolt = <925000 925000 1150000>;
89
+
};
90
+
opp05 {
91
+
opp-hz = /bits/ 64 <800000000>;
92
+
opp-microvolt = <1100000 1100000 1150000>;
93
+
};
94
+
};
95
+
};
96
+
97
+
&cpu_l0 {
98
+
operating-points-v2 = <&cluster0_opp>;
99
+
};
100
+
101
+
&cpu_l1 {
102
+
operating-points-v2 = <&cluster0_opp>;
103
+
};
104
+
105
+
&cpu_l2 {
106
+
operating-points-v2 = <&cluster0_opp>;
107
+
};
108
+
109
+
&cpu_l3 {
110
+
operating-points-v2 = <&cluster0_opp>;
111
+
};
112
+
113
+
&cpu_b0 {
114
+
operating-points-v2 = <&cluster1_opp>;
115
+
};
116
+
117
+
&cpu_b1 {
118
+
operating-points-v2 = <&cluster1_opp>;
119
+
};
120
+
121
+
&gpu {
122
+
operating-points-v2 = <&gpu_opp_table>;
123
+
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
···
167
167
reg = <0x1a>;
168
168
clocks = <&cru SCLK_I2S_8CH_OUT>;
169
169
clock-names = "mclk";
170
-
hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
170
+
hp-det-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
171
171
spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
172
172
#sound-dai-cells = <0>;
173
173
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+22
arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+22
arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Copyright (c) 2020 Rockchip Electronics Co., Ltd
4
+
* Copyright (c) 2024 Radxa Limited
5
+
* Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
6
+
*/
7
+
8
+
/dts-v1/;
9
+
#include "rk3528.dtsi"
10
+
11
+
/ {
12
+
model = "Radxa E20C";
13
+
compatible = "radxa,e20c", "rockchip,rk3528";
14
+
15
+
chosen {
16
+
stdout-path = "serial0:1500000n8";
17
+
};
18
+
};
19
+
20
+
&uart0 {
21
+
status = "okay";
22
+
};
+189
arch/arm64/boot/dts/rockchip/rk3528.dtsi
+189
arch/arm64/boot/dts/rockchip/rk3528.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4
+
* Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
5
+
*/
6
+
7
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
8
+
#include <dt-bindings/interrupt-controller/irq.h>
9
+
10
+
/ {
11
+
compatible = "rockchip,rk3528";
12
+
13
+
interrupt-parent = <&gic>;
14
+
#address-cells = <2>;
15
+
#size-cells = <2>;
16
+
17
+
aliases {
18
+
serial0 = &uart0;
19
+
serial1 = &uart1;
20
+
serial2 = &uart2;
21
+
serial3 = &uart3;
22
+
serial4 = &uart4;
23
+
serial5 = &uart5;
24
+
serial6 = &uart6;
25
+
serial7 = &uart7;
26
+
};
27
+
28
+
cpus {
29
+
#address-cells = <1>;
30
+
#size-cells = <0>;
31
+
32
+
cpu-map {
33
+
cluster0 {
34
+
core0 {
35
+
cpu = <&cpu0>;
36
+
};
37
+
core1 {
38
+
cpu = <&cpu1>;
39
+
};
40
+
core2 {
41
+
cpu = <&cpu2>;
42
+
};
43
+
core3 {
44
+
cpu = <&cpu3>;
45
+
};
46
+
};
47
+
};
48
+
49
+
cpu0: cpu@0 {
50
+
compatible = "arm,cortex-a53";
51
+
reg = <0x0>;
52
+
device_type = "cpu";
53
+
enable-method = "psci";
54
+
};
55
+
56
+
cpu1: cpu@1 {
57
+
compatible = "arm,cortex-a53";
58
+
reg = <0x1>;
59
+
device_type = "cpu";
60
+
enable-method = "psci";
61
+
};
62
+
63
+
cpu2: cpu@2 {
64
+
compatible = "arm,cortex-a53";
65
+
reg = <0x2>;
66
+
device_type = "cpu";
67
+
enable-method = "psci";
68
+
};
69
+
70
+
cpu3: cpu@3 {
71
+
compatible = "arm,cortex-a53";
72
+
reg = <0x3>;
73
+
device_type = "cpu";
74
+
enable-method = "psci";
75
+
};
76
+
};
77
+
78
+
psci {
79
+
compatible = "arm,psci-1.0", "arm,psci-0.2";
80
+
method = "smc";
81
+
};
82
+
83
+
timer {
84
+
compatible = "arm,armv8-timer";
85
+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
86
+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
87
+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
88
+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
89
+
};
90
+
91
+
xin24m: clock-xin24m {
92
+
compatible = "fixed-clock";
93
+
clock-frequency = <24000000>;
94
+
clock-output-names = "xin24m";
95
+
#clock-cells = <0>;
96
+
};
97
+
98
+
soc {
99
+
compatible = "simple-bus";
100
+
ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
101
+
#address-cells = <2>;
102
+
#size-cells = <2>;
103
+
104
+
gic: interrupt-controller@fed01000 {
105
+
compatible = "arm,gic-400";
106
+
reg = <0x0 0xfed01000 0 0x1000>,
107
+
<0x0 0xfed02000 0 0x2000>,
108
+
<0x0 0xfed04000 0 0x2000>,
109
+
<0x0 0xfed06000 0 0x2000>;
110
+
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
111
+
IRQ_TYPE_LEVEL_LOW)>;
112
+
interrupt-controller;
113
+
#address-cells = <0>;
114
+
#interrupt-cells = <3>;
115
+
};
116
+
117
+
uart0: serial@ff9f0000 {
118
+
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
119
+
reg = <0x0 0xff9f0000 0x0 0x100>;
120
+
clock-frequency = <24000000>;
121
+
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
122
+
reg-io-width = <4>;
123
+
reg-shift = <2>;
124
+
status = "disabled";
125
+
};
126
+
127
+
uart1: serial@ff9f8000 {
128
+
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
129
+
reg = <0x0 0xff9f8000 0x0 0x100>;
130
+
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
131
+
reg-io-width = <4>;
132
+
reg-shift = <2>;
133
+
status = "disabled";
134
+
};
135
+
136
+
uart2: serial@ffa00000 {
137
+
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
138
+
reg = <0x0 0xffa00000 0x0 0x100>;
139
+
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
140
+
reg-io-width = <4>;
141
+
reg-shift = <2>;
142
+
status = "disabled";
143
+
};
144
+
145
+
uart3: serial@ffa08000 {
146
+
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
147
+
reg = <0x0 0xffa08000 0x0 0x100>;
148
+
reg-io-width = <4>;
149
+
reg-shift = <2>;
150
+
status = "disabled";
151
+
};
152
+
153
+
uart4: serial@ffa10000 {
154
+
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
155
+
reg = <0x0 0xffa10000 0x0 0x100>;
156
+
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
157
+
reg-io-width = <4>;
158
+
reg-shift = <2>;
159
+
status = "disabled";
160
+
};
161
+
162
+
uart5: serial@ffa18000 {
163
+
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
164
+
reg = <0x0 0xffa18000 0x0 0x100>;
165
+
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
166
+
reg-io-width = <4>;
167
+
reg-shift = <2>;
168
+
status = "disabled";
169
+
};
170
+
171
+
uart6: serial@ffa20000 {
172
+
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
173
+
reg = <0x0 0xffa20000 0x0 0x100>;
174
+
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
175
+
reg-io-width = <4>;
176
+
reg-shift = <2>;
177
+
status = "disabled";
178
+
};
179
+
180
+
uart7: serial@ffa28000 {
181
+
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
182
+
reg = <0x0 0xffa28000 0x0 0x100>;
183
+
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
184
+
reg-io-width = <4>;
185
+
reg-shift = <2>;
186
+
status = "disabled";
187
+
};
188
+
};
189
+
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg-arc.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg-arc.dtsi
···
41
41
simple-audio-card,name = "rk817_ext";
42
42
simple-audio-card,aux-devs = <&spk_amp>;
43
43
simple-audio-card,format = "i2s";
44
-
simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
44
+
simple-audio-card,hp-det-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
45
45
simple-audio-card,mclk-fs = <256>;
46
46
simple-audio-card,widgets =
47
47
"Microphone", "Mic Jack",
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts
···
43
43
simple-audio-card,name = "rk817_ext";
44
44
simple-audio-card,aux-devs = <&spk_amp>;
45
45
simple-audio-card,format = "i2s";
46
-
simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
46
+
simple-audio-card,hp-det-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
47
47
simple-audio-card,mclk-fs = <256>;
48
48
simple-audio-card,widgets =
49
49
"Microphone", "Mic Jack",
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts
···
42
42
simple-audio-card,name = "rk817_ext";
43
43
simple-audio-card,aux-devs = <&spk_amp>;
44
44
simple-audio-card,format = "i2s";
45
-
simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
45
+
simple-audio-card,hp-det-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
46
46
simple-audio-card,mclk-fs = <256>;
47
47
simple-audio-card,widgets =
48
48
"Microphone", "Mic Jack",
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts
···
42
42
compatible = "simple-audio-card";
43
43
simple-audio-card,name = "rk817_int";
44
44
simple-audio-card,format = "i2s";
45
-
simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
45
+
simple-audio-card,hp-det-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
46
46
simple-audio-card,mclk-fs = <256>;
47
47
simple-audio-card,widgets =
48
48
"Microphone", "Mic Jack",
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts
···
41
41
compatible = "simple-audio-card";
42
42
simple-audio-card,name = "rk817_int";
43
43
simple-audio-card,format = "i2s";
44
-
simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
44
+
simple-audio-card,hp-det-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
45
45
simple-audio-card,mclk-fs = <256>;
46
46
simple-audio-card,widgets =
47
47
"Microphone", "Mic Jack",
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
···
132
132
simple-audio-card,name = "rk817_ext";
133
133
simple-audio-card,aux-devs = <&spk_amp>;
134
134
simple-audio-card,format = "i2s";
135
-
simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
135
+
simple-audio-card,hp-det-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
136
136
simple-audio-card,mclk-fs = <256>;
137
137
simple-audio-card,widgets =
138
138
"Microphone", "Mic Jack",
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-lckfb-tspi.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-lckfb-tspi.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts
+554
arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+554
arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
+
/*
3
+
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4
+
*
5
+
* Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
6
+
* (http://www.friendlyelec.com)
7
+
*
8
+
* Copyright (c) 2024 Tianling Shen <cnsztl@gmail.com>
9
+
*/
10
+
11
+
/dts-v1/;
12
+
#include <dt-bindings/gpio/gpio.h>
13
+
#include <dt-bindings/input/input.h>
14
+
#include <dt-bindings/leds/common.h>
15
+
#include <dt-bindings/pinctrl/rockchip.h>
16
+
#include <dt-bindings/soc/rockchip,vop2.h>
17
+
#include "rk3566.dtsi"
18
+
19
+
/ {
20
+
model = "FriendlyElec NanoPi R3S";
21
+
compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566";
22
+
23
+
aliases {
24
+
ethernet0 = &gmac1;
25
+
mmc0 = &sdhci;
26
+
mmc1 = &sdmmc0;
27
+
};
28
+
29
+
chosen: chosen {
30
+
stdout-path = "serial2:1500000n8";
31
+
};
32
+
33
+
gpio-keys {
34
+
compatible = "gpio-keys";
35
+
pinctrl-names = "default";
36
+
pinctrl-0 = <&reset_button_pin>;
37
+
38
+
button-reset {
39
+
label = "reset";
40
+
gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
41
+
linux,code = <KEY_RESTART>;
42
+
debounce-interval = <50>;
43
+
};
44
+
};
45
+
46
+
gpio-leds {
47
+
compatible = "gpio-leds";
48
+
pinctrl-names = "default";
49
+
pinctrl-0 = <&power_led_pin>, <&lan_led_pin>, <&wan_led_pin>;
50
+
51
+
power_led: led-0 {
52
+
color = <LED_COLOR_ID_RED>;
53
+
function = LED_FUNCTION_POWER;
54
+
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
55
+
default-state = "on";
56
+
};
57
+
58
+
lan_led: led-1 {
59
+
color = <LED_COLOR_ID_GREEN>;
60
+
function = LED_FUNCTION_LAN;
61
+
gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
62
+
};
63
+
64
+
wan_led: led-2 {
65
+
color = <LED_COLOR_ID_GREEN>;
66
+
function = LED_FUNCTION_WAN;
67
+
gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
68
+
};
69
+
};
70
+
71
+
vcc3v3_sys: regulator-vcc3v3-sys {
72
+
compatible = "regulator-fixed";
73
+
regulator-name = "vcc3v3_sys";
74
+
regulator-always-on;
75
+
regulator-boot-on;
76
+
regulator-min-microvolt = <3300000>;
77
+
regulator-max-microvolt = <3300000>;
78
+
vin-supply = <&vcc5v0_sys>;
79
+
};
80
+
81
+
vcc5v0_sys: regulator-vcc5v0-sys {
82
+
compatible = "regulator-fixed";
83
+
regulator-name = "vcc5v0_sys";
84
+
regulator-always-on;
85
+
regulator-boot-on;
86
+
regulator-min-microvolt = <5000000>;
87
+
regulator-max-microvolt = <5000000>;
88
+
vin-supply = <&vdd_usbc>;
89
+
};
90
+
91
+
vcc5v0_usb: regulator-vcc5v0_usb {
92
+
compatible = "regulator-fixed";
93
+
enable-active-high;
94
+
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
95
+
pinctrl-names = "default";
96
+
pinctrl-0 = <&vcc5v0_usb_host_en>;
97
+
regulator-name = "vcc5v0_usb";
98
+
regulator-always-on;
99
+
regulator-boot-on;
100
+
regulator-min-microvolt = <5000000>;
101
+
regulator-max-microvolt = <5000000>;
102
+
vin-supply = <&vcc5v0_sys>;
103
+
};
104
+
105
+
vdd_usbc: regulator-vdd-usbc {
106
+
compatible = "regulator-fixed";
107
+
regulator-name = "vdd_usbc";
108
+
regulator-always-on;
109
+
regulator-boot-on;
110
+
regulator-min-microvolt = <5000000>;
111
+
regulator-max-microvolt = <5000000>;
112
+
};
113
+
};
114
+
115
+
&combphy1 {
116
+
status = "okay";
117
+
};
118
+
119
+
&combphy2 {
120
+
status = "okay";
121
+
};
122
+
123
+
&cpu0 {
124
+
cpu-supply = <&vdd_cpu>;
125
+
};
126
+
127
+
&cpu1 {
128
+
cpu-supply = <&vdd_cpu>;
129
+
};
130
+
131
+
&cpu2 {
132
+
cpu-supply = <&vdd_cpu>;
133
+
};
134
+
135
+
&cpu3 {
136
+
cpu-supply = <&vdd_cpu>;
137
+
};
138
+
139
+
&gmac1 {
140
+
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
141
+
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
142
+
assigned-clock-rates = <0>, <125000000>;
143
+
clock_in_out = "output";
144
+
phy-mode = "rgmii-id";
145
+
phy-handle = <&rgmii_phy1>;
146
+
pinctrl-names = "default";
147
+
pinctrl-0 = <&gmac1m0_miim
148
+
&gmac1m0_tx_bus2_level3
149
+
&gmac1m0_rx_bus2
150
+
&gmac1m0_rgmii_clk_level2
151
+
&gmac1m0_rgmii_bus_level3>;
152
+
status = "okay";
153
+
};
154
+
155
+
&gpu {
156
+
mali-supply = <&vdd_gpu>;
157
+
status = "okay";
158
+
};
159
+
160
+
&i2c0 {
161
+
status = "okay";
162
+
163
+
vdd_cpu: regulator@1c {
164
+
compatible = "tcs,tcs4525";
165
+
reg = <0x1c>;
166
+
fcs,suspend-voltage-selector = <1>;
167
+
regulator-name = "vdd_cpu";
168
+
regulator-always-on;
169
+
regulator-boot-on;
170
+
regulator-min-microvolt = <800000>;
171
+
regulator-max-microvolt = <1150000>;
172
+
regulator-ramp-delay = <2300>;
173
+
vin-supply = <&vcc5v0_sys>;
174
+
175
+
regulator-state-mem {
176
+
regulator-off-in-suspend;
177
+
};
178
+
};
179
+
180
+
rk809: pmic@20 {
181
+
compatible = "rockchip,rk809";
182
+
reg = <0x20>;
183
+
interrupt-parent = <&gpio0>;
184
+
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
185
+
#clock-cells = <1>;
186
+
pinctrl-names = "default";
187
+
pinctrl-0 = <&pmic_int>;
188
+
system-power-controller;
189
+
vcc1-supply = <&vcc3v3_sys>;
190
+
vcc2-supply = <&vcc3v3_sys>;
191
+
vcc3-supply = <&vcc3v3_sys>;
192
+
vcc4-supply = <&vcc3v3_sys>;
193
+
vcc5-supply = <&vcc3v3_sys>;
194
+
vcc6-supply = <&vcc3v3_sys>;
195
+
vcc7-supply = <&vcc3v3_sys>;
196
+
vcc8-supply = <&vcc3v3_sys>;
197
+
vcc9-supply = <&vcc3v3_sys>;
198
+
wakeup-source;
199
+
200
+
regulators {
201
+
vdd_logic: DCDC_REG1 {
202
+
regulator-name = "vdd_logic";
203
+
regulator-always-on;
204
+
regulator-boot-on;
205
+
regulator-initial-mode = <0x2>;
206
+
regulator-min-microvolt = <500000>;
207
+
regulator-max-microvolt = <1350000>;
208
+
regulator-ramp-delay = <6001>;
209
+
210
+
regulator-state-mem {
211
+
regulator-off-in-suspend;
212
+
};
213
+
};
214
+
215
+
vdd_gpu: DCDC_REG2 {
216
+
regulator-name = "vdd_gpu";
217
+
regulator-always-on;
218
+
regulator-initial-mode = <0x2>;
219
+
regulator-min-microvolt = <500000>;
220
+
regulator-max-microvolt = <1350000>;
221
+
regulator-ramp-delay = <6001>;
222
+
223
+
regulator-state-mem {
224
+
regulator-off-in-suspend;
225
+
};
226
+
};
227
+
228
+
vcc_ddr: DCDC_REG3 {
229
+
regulator-name = "vcc_ddr";
230
+
regulator-always-on;
231
+
regulator-boot-on;
232
+
regulator-initial-mode = <0x2>;
233
+
234
+
regulator-state-mem {
235
+
regulator-on-in-suspend;
236
+
};
237
+
};
238
+
239
+
vdd_npu: DCDC_REG4 {
240
+
regulator-name = "vdd_npu";
241
+
regulator-initial-mode = <0x2>;
242
+
regulator-min-microvolt = <500000>;
243
+
regulator-max-microvolt = <1350000>;
244
+
regulator-ramp-delay = <6001>;
245
+
246
+
regulator-state-mem {
247
+
regulator-off-in-suspend;
248
+
};
249
+
};
250
+
251
+
vcc_1v8: DCDC_REG5 {
252
+
regulator-name = "vcc_1v8";
253
+
regulator-always-on;
254
+
regulator-boot-on;
255
+
regulator-min-microvolt = <1800000>;
256
+
regulator-max-microvolt = <1800000>;
257
+
258
+
regulator-state-mem {
259
+
regulator-off-in-suspend;
260
+
};
261
+
};
262
+
263
+
vdda0v9_image: LDO_REG1 {
264
+
regulator-name = "vdda0v9_image";
265
+
regulator-min-microvolt = <950000>;
266
+
regulator-max-microvolt = <950000>;
267
+
268
+
regulator-state-mem {
269
+
regulator-off-in-suspend;
270
+
};
271
+
};
272
+
273
+
vdda_0v9: LDO_REG2 {
274
+
regulator-name = "vdda_0v9";
275
+
regulator-always-on;
276
+
regulator-boot-on;
277
+
regulator-min-microvolt = <900000>;
278
+
regulator-max-microvolt = <900000>;
279
+
280
+
regulator-state-mem {
281
+
regulator-off-in-suspend;
282
+
};
283
+
};
284
+
285
+
vdda0v9_pmu: LDO_REG3 {
286
+
regulator-name = "vdda0v9_pmu";
287
+
regulator-always-on;
288
+
regulator-boot-on;
289
+
regulator-min-microvolt = <900000>;
290
+
regulator-max-microvolt = <900000>;
291
+
292
+
regulator-state-mem {
293
+
regulator-on-in-suspend;
294
+
regulator-suspend-microvolt = <900000>;
295
+
};
296
+
};
297
+
298
+
vccio_acodec: LDO_REG4 {
299
+
regulator-name = "vccio_acodec";
300
+
regulator-min-microvolt = <3300000>;
301
+
regulator-max-microvolt = <3300000>;
302
+
303
+
regulator-state-mem {
304
+
regulator-off-in-suspend;
305
+
};
306
+
};
307
+
308
+
vccio_sd: LDO_REG5 {
309
+
regulator-name = "vccio_sd";
310
+
regulator-min-microvolt = <1800000>;
311
+
regulator-max-microvolt = <3300000>;
312
+
313
+
regulator-state-mem {
314
+
regulator-off-in-suspend;
315
+
};
316
+
};
317
+
318
+
vcc3v3_pmu: LDO_REG6 {
319
+
regulator-name = "vcc3v3_pmu";
320
+
regulator-always-on;
321
+
regulator-boot-on;
322
+
regulator-min-microvolt = <3300000>;
323
+
regulator-max-microvolt = <3300000>;
324
+
325
+
regulator-state-mem {
326
+
regulator-on-in-suspend;
327
+
regulator-suspend-microvolt = <3300000>;
328
+
};
329
+
};
330
+
331
+
vcca_1v8: LDO_REG7 {
332
+
regulator-name = "vcca_1v8";
333
+
regulator-always-on;
334
+
regulator-boot-on;
335
+
regulator-min-microvolt = <1800000>;
336
+
regulator-max-microvolt = <1800000>;
337
+
338
+
regulator-state-mem {
339
+
regulator-off-in-suspend;
340
+
};
341
+
};
342
+
343
+
vcca1v8_pmu: LDO_REG8 {
344
+
regulator-name = "vcca1v8_pmu";
345
+
regulator-always-on;
346
+
regulator-boot-on;
347
+
regulator-min-microvolt = <1800000>;
348
+
regulator-max-microvolt = <1800000>;
349
+
350
+
regulator-state-mem {
351
+
regulator-on-in-suspend;
352
+
regulator-suspend-microvolt = <1800000>;
353
+
};
354
+
};
355
+
356
+
vcca1v8_image: LDO_REG9 {
357
+
regulator-name = "vcca1v8_image";
358
+
regulator-min-microvolt = <1800000>;
359
+
regulator-max-microvolt = <1800000>;
360
+
361
+
regulator-state-mem {
362
+
regulator-off-in-suspend;
363
+
};
364
+
};
365
+
366
+
vcc_3v3: SWITCH_REG1 {
367
+
regulator-name = "vcc_3v3";
368
+
regulator-always-on;
369
+
regulator-boot-on;
370
+
371
+
regulator-state-mem {
372
+
regulator-off-in-suspend;
373
+
};
374
+
};
375
+
376
+
vcc3v3_sd: SWITCH_REG2 {
377
+
regulator-name = "vcc3v3_sd";
378
+
regulator-always-on;
379
+
regulator-boot-on;
380
+
381
+
regulator-state-mem {
382
+
regulator-off-in-suspend;
383
+
};
384
+
};
385
+
};
386
+
};
387
+
};
388
+
389
+
&i2c1 {
390
+
status = "okay";
391
+
392
+
hym8563: rtc@51 {
393
+
compatible = "haoyu,hym8563";
394
+
reg = <0x51>;
395
+
#clock-cells = <0>;
396
+
clock-output-names = "hym8563";
397
+
pinctrl-names = "default";
398
+
pinctrl-0 = <&hym8563_int>;
399
+
interrupt-parent = <&gpio0>;
400
+
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
401
+
wakeup-source;
402
+
};
403
+
};
404
+
405
+
&mdio1 {
406
+
rgmii_phy1: ethernet-phy@1 {
407
+
compatible = "ethernet-phy-ieee802.3-c22";
408
+
reg = <1>;
409
+
interrupt-parent = <&gpio4>;
410
+
interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
411
+
pinctrl-names = "default";
412
+
pinctrl-0 = <ð_phy_reset_pin>;
413
+
reset-assert-us = <20000>;
414
+
reset-deassert-us = <100000>;
415
+
reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
416
+
};
417
+
};
418
+
419
+
&pcie2x1 {
420
+
pinctrl-names = "default";
421
+
pinctrl-0 = <&pcie_reset_h>;
422
+
reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
423
+
status = "okay";
424
+
};
425
+
426
+
&pinctrl {
427
+
gpio-leds {
428
+
lan_led_pin: lan-led-pin {
429
+
rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
430
+
};
431
+
432
+
power_led_pin: power-led-pin {
433
+
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
434
+
};
435
+
436
+
wan_led_pin: wan-led-pin {
437
+
rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
438
+
};
439
+
};
440
+
441
+
gmac {
442
+
eth_phy_reset_pin: eth-phy-reset-pin {
443
+
rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
444
+
};
445
+
};
446
+
447
+
pcie {
448
+
pcie_reset_h: pcie-reset-h {
449
+
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
450
+
};
451
+
};
452
+
453
+
pmic {
454
+
pmic_int: pmic-int {
455
+
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
456
+
};
457
+
};
458
+
459
+
rockchip-key {
460
+
reset_button_pin: reset-button-pin {
461
+
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
462
+
};
463
+
};
464
+
465
+
rtc {
466
+
hym8563_int: hym8563-int {
467
+
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
468
+
};
469
+
};
470
+
471
+
usb {
472
+
vcc5v0_usb_host_en: vcc5v0-usb-host-en {
473
+
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
474
+
};
475
+
};
476
+
};
477
+
478
+
&pmu_io_domains {
479
+
pmuio1-supply = <&vcc3v3_pmu>;
480
+
pmuio2-supply = <&vcc3v3_pmu>;
481
+
vccio1-supply = <&vccio_acodec>;
482
+
vccio2-supply = <&vcc_1v8>;
483
+
vccio3-supply = <&vccio_sd>;
484
+
vccio4-supply = <&vcc_3v3>;
485
+
vccio5-supply = <&vcc_1v8>;
486
+
vccio6-supply = <&vcc_3v3>;
487
+
vccio7-supply = <&vcc_3v3>;
488
+
status = "okay";
489
+
};
490
+
491
+
&sdhci {
492
+
bus-width = <8>;
493
+
max-frequency = <200000000>;
494
+
mmc-hs200-1_8v;
495
+
non-removable;
496
+
pinctrl-names = "default";
497
+
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
498
+
status = "okay";
499
+
};
500
+
501
+
&sdmmc0 {
502
+
bus-width = <4>;
503
+
cap-mmc-highspeed;
504
+
cap-sd-highspeed;
505
+
disable-wp;
506
+
no-sdio;
507
+
no-mmc;
508
+
pinctrl-names = "default";
509
+
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
510
+
sd-uhs-sdr50;
511
+
vmmc-supply = <&vcc3v3_sd>;
512
+
vqmmc-supply = <&vccio_sd>;
513
+
status = "okay";
514
+
};
515
+
516
+
&tsadc {
517
+
status = "okay";
518
+
};
519
+
520
+
&uart2 {
521
+
status = "okay";
522
+
};
523
+
524
+
&usb2phy0 {
525
+
status = "okay";
526
+
};
527
+
528
+
&usb2phy0_host {
529
+
phy-supply = <&vcc5v0_usb>;
530
+
status = "okay";
531
+
};
532
+
533
+
&usb2phy0_otg {
534
+
status = "okay";
535
+
};
536
+
537
+
&usb_host0_xhci {
538
+
extcon = <&usb2phy0>;
539
+
status = "okay";
540
+
};
541
+
542
+
&usb_host1_xhci {
543
+
status = "okay";
544
+
};
545
+
546
+
&vop {
547
+
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
548
+
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
549
+
status = "okay";
550
+
};
551
+
552
+
&vop_mmu {
553
+
status = "okay";
554
+
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
+2
-2
arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi
+2
-2
arch/arm64/boot/dts/rockchip/rk3566-pinetab2.dtsi
···
121
121
"Internal Speakers", "Speaker Amplifier OUTR",
122
122
"Speaker Amplifier INL", "HPOL",
123
123
"Speaker Amplifier INR", "HPOR";
124
-
simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
124
+
simple-audio-card,hp-det-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
125
125
simple-audio-card,aux-devs = <&speaker_amp>;
126
126
simple-audio-card,pin-switches = "Internal Speakers";
127
127
···
370
370
#clock-cells = <1>;
371
371
pinctrl-names = "default";
372
372
pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
373
-
rockchip,system-power-controller;
373
+
system-power-controller;
374
374
#sound-dai-cells = <0>;
375
375
wakeup-source;
376
376
+89
arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb20sx.dts
+89
arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb20sx.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
3
+
/dts-v1/;
4
+
5
+
#include <dt-bindings/gpio/gpio.h>
6
+
#include <dt-bindings/input/linux-event-codes.h>
7
+
#include <dt-bindings/pinctrl/rockchip.h>
8
+
#include "rk3566-powkiddy-rk2023.dtsi"
9
+
10
+
/ {
11
+
model = "Powkiddy RGB20SX";
12
+
compatible = "powkiddy,rgb20sx", "rockchip,rk3566";
13
+
14
+
chosen: chosen {
15
+
stdout-path = "serial2:1500000n8";
16
+
};
17
+
18
+
adc_keys: adc-keys {
19
+
compatible = "adc-keys";
20
+
io-channels = <&saradc 0>;
21
+
io-channel-names = "buttons";
22
+
keyup-threshold-microvolt = <1800000>;
23
+
poll-interval = <60>;
24
+
25
+
/*
26
+
* Button is labelled as FN, but according to input
27
+
* guidelines it should be mode.
28
+
*/
29
+
button-mode {
30
+
label = "MODE";
31
+
linux,code = <BTN_MODE>;
32
+
press-threshold-microvolt = <1750>;
33
+
};
34
+
};
35
+
};
36
+
37
+
&battery {
38
+
charge-full-design-microamp-hours = <5000000>;
39
+
};
40
+
41
+
&bluetooth {
42
+
compatible = "realtek,rtl8723ds-bt";
43
+
};
44
+
45
+
&cru {
46
+
assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
47
+
<&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
48
+
assigned-clock-rates = <32768>, <1200000000>,
49
+
<200000000>, <292500000>;
50
+
};
51
+
52
+
&dsi0 {
53
+
panel: panel@0 {
54
+
compatible = "powkiddy,rgb30-panel";
55
+
reg = <0>;
56
+
backlight = <&backlight>;
57
+
pinctrl-names = "default";
58
+
pinctrl-0 = <&lcd_rst>;
59
+
reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
60
+
vcc-supply = <&vcc3v3_lcd0_n>;
61
+
iovcc-supply = <&vcc3v3_lcd0_n>;
62
+
63
+
port {
64
+
mipi_in_panel: endpoint {
65
+
remote-endpoint = <&mipi_out_panel>;
66
+
};
67
+
};
68
+
};
69
+
};
70
+
71
+
&i2c0 {
72
+
vdd_cpu: regulator@1c {
73
+
compatible = "tcs,tcs4525";
74
+
reg = <0x1c>;
75
+
fcs,suspend-voltage-selector = <1>;
76
+
regulator-min-microvolt = <712500>;
77
+
regulator-max-microvolt = <1390000>;
78
+
regulator-name = "vdd_cpu";
79
+
regulator-ramp-delay = <2300>;
80
+
vin-supply = <&vcc_sys>;
81
+
regulator-state-mem {
82
+
regulator-off-in-suspend;
83
+
};
84
+
};
85
+
};
86
+
87
+
&uart2 {
88
+
status = "okay";
89
+
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts
···
269
269
simple-audio-card,name = "rk817_ext";
270
270
simple-audio-card,aux-devs = <&spk_amp>;
271
271
simple-audio-card,format = "i2s";
272
-
simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
272
+
simple-audio-card,hp-det-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
273
273
simple-audio-card,mclk-fs = <256>;
274
274
simple-audio-card,widgets =
275
275
"Microphone", "Mic Jack",
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
···
275
275
clocks = <&cru I2S1_MCLKOUT_TX>;
276
276
pinctrl-names = "default";
277
277
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
278
-
rockchip,system-power-controller;
278
+
system-power-controller;
279
279
#sound-dai-cells = <0>;
280
280
vcc1-supply = <&vcc3v3_sys>;
281
281
vcc2-supply = <&vcc3v3_sys>;
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
+2
-2
arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+2
-2
arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
···
84
84
pinctrl-0 = <&hp_det_pin>;
85
85
simple-audio-card,name = "Analog RK817";
86
86
simple-audio-card,format = "i2s";
87
-
simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
87
+
simple-audio-card,hp-det-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
88
88
simple-audio-card,mclk-fs = <256>;
89
89
simple-audio-card,widgets =
90
90
"Headphone", "Headphones",
···
273
273
clocks = <&cru I2S1_MCLKOUT_TX>;
274
274
pinctrl-names = "default";
275
275
pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
276
-
rockchip,system-power-controller;
276
+
system-power-controller;
277
277
#sound-dai-cells = <0>;
278
278
vcc1-supply = <&vcc3v3_sys>;
279
279
vcc2-supply = <&vcc3v3_sys>;
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
+1
arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+1
arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
···
333
333
clocks = <&cru I2S1_MCLKOUT_TX>;
334
334
pinctrl-names = "default";
335
335
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
336
-
rockchip,system-power-controller;
336
+
system-power-controller;
337
337
#sound-dai-cells = <0>;
338
338
vcc1-supply = <&vcc3v3_sys>;
339
339
vcc2-supply = <&vcc3v3_sys>;
-1
arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso
-1
arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5.dts
+659
arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts
+659
arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4
+
*
5
+
*/
6
+
7
+
/dts-v1/;
8
+
9
+
#include <dt-bindings/gpio/gpio.h>
10
+
#include <dt-bindings/leds/common.h>
11
+
#include <dt-bindings/pinctrl/rockchip.h>
12
+
#include <dt-bindings/pwm/pwm.h>
13
+
#include <dt-bindings/usb/pd.h>
14
+
#include "rk3576.dtsi"
15
+
16
+
/ {
17
+
model = "ArmSoM Sige5";
18
+
compatible = "armsom,sige5", "rockchip,rk3576";
19
+
20
+
aliases {
21
+
ethernet0 = &gmac0;
22
+
ethernet1 = &gmac1;
23
+
};
24
+
25
+
chosen {
26
+
stdout-path = "serial0:1500000n8";
27
+
};
28
+
29
+
leds: leds {
30
+
compatible = "gpio-leds";
31
+
32
+
green_led: green-led {
33
+
color = <LED_COLOR_ID_GREEN>;
34
+
function = LED_FUNCTION_HEARTBEAT;
35
+
gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
36
+
linux,default-trigger = "heartbeat";
37
+
};
38
+
39
+
red_led: red-led {
40
+
color = <LED_COLOR_ID_RED>;
41
+
function = LED_FUNCTION_STATUS;
42
+
gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
43
+
linux,default-trigger = "default-on";
44
+
};
45
+
};
46
+
47
+
vcc_12v0_dcin: regulator-vcc-12v0-dcin {
48
+
compatible = "regulator-fixed";
49
+
regulator-name = "vcc_12v0_dcin";
50
+
regulator-always-on;
51
+
regulator-boot-on;
52
+
regulator-min-microvolt = <12000000>;
53
+
regulator-max-microvolt = <12000000>;
54
+
};
55
+
56
+
vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
57
+
compatible = "regulator-fixed";
58
+
regulator-name = "vcc_1v1_nldo_s3";
59
+
regulator-boot-on;
60
+
regulator-always-on;
61
+
regulator-min-microvolt = <1100000>;
62
+
regulator-max-microvolt = <1100000>;
63
+
vin-supply = <&vcc_5v0_sys>;
64
+
};
65
+
66
+
vcc_1v2_ufs_vccq_s0: regulator-vcc-1v2-ufs-vccq-s0 {
67
+
compatible = "regulator-fixed";
68
+
regulator-name = "vcc_1v2_ufs_vccq_s0";
69
+
regulator-boot-on;
70
+
regulator-always-on;
71
+
regulator-min-microvolt = <1200000>;
72
+
regulator-max-microvolt = <1200000>;
73
+
vin-supply = <&vcc_5v0_sys>;
74
+
};
75
+
76
+
vcc_1v8_s0: regulator-vcc-1v8-s0 {
77
+
compatible = "regulator-fixed";
78
+
regulator-name = "vcc_1v8_s0";
79
+
regulator-boot-on;
80
+
regulator-always-on;
81
+
regulator-min-microvolt = <1800000>;
82
+
regulator-max-microvolt = <1800000>;
83
+
vin-supply = <&vcc_1v8_s3>;
84
+
};
85
+
86
+
vcc_1v8_ufs_vccq2_s0: regulator-vcc-1v8-ufs-vccq2-s0 {
87
+
compatible = "regulator-fixed";
88
+
regulator-name = "vcc_1v8_ufs_vccq2_s0";
89
+
regulator-boot-on;
90
+
regulator-always-on;
91
+
regulator-min-microvolt = <1800000>;
92
+
regulator-max-microvolt = <1800000>;
93
+
vin-supply = <&vcc_1v8_s3>;
94
+
};
95
+
96
+
vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
97
+
compatible = "regulator-fixed";
98
+
regulator-name = "vcc_2v0_pldo_s3";
99
+
regulator-boot-on;
100
+
regulator-always-on;
101
+
regulator-min-microvolt = <2000000>;
102
+
regulator-max-microvolt = <2000000>;
103
+
vin-supply = <&vcc_5v0_sys>;
104
+
};
105
+
106
+
vcc_3v3_pcie: regulator-vcc-3v3-pcie {
107
+
compatible = "regulator-fixed";
108
+
regulator-name = "vcc_3v3_pcie";
109
+
regulator-min-microvolt = <3300000>;
110
+
regulator-max-microvolt = <3300000>;
111
+
enable-active-high;
112
+
gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
113
+
startup-delay-us = <5000>;
114
+
vin-supply = <&vcc_5v0_sys>;
115
+
};
116
+
117
+
vcc_3v3_rtc_s5: regulator-vcc-3v3-rtc-s5 {
118
+
compatible = "regulator-fixed";
119
+
regulator-name = "vcc_3v3_rtc_s5";
120
+
regulator-boot-on;
121
+
regulator-always-on;
122
+
regulator-min-microvolt = <3300000>;
123
+
regulator-max-microvolt = <3300000>;
124
+
vin-supply = <&vcc_5v0_sys>;
125
+
};
126
+
127
+
vcc_3v3_s0: regulator-vcc-3v3-s0 {
128
+
compatible = "regulator-fixed";
129
+
regulator-name = "vcc_3v3_s0";
130
+
regulator-boot-on;
131
+
regulator-always-on;
132
+
regulator-min-microvolt = <3300000>;
133
+
regulator-max-microvolt = <3300000>;
134
+
vin-supply = <&vcc_3v3_s3>;
135
+
};
136
+
137
+
vcc_5v0_sys: regulator-vcc-5v0-sys {
138
+
compatible = "regulator-fixed";
139
+
regulator-name = "vcc_5v0_sys";
140
+
regulator-always-on;
141
+
regulator-boot-on;
142
+
regulator-min-microvolt = <5000000>;
143
+
regulator-max-microvolt = <5000000>;
144
+
vin-supply = <&vcc_12v0_dcin>;
145
+
};
146
+
147
+
vcc_5v0_device: regulator-vcc-5v0-device {
148
+
compatible = "regulator-fixed";
149
+
regulator-name = "vcc_5v0_device";
150
+
regulator-always-on;
151
+
regulator-boot-on;
152
+
regulator-min-microvolt = <5000000>;
153
+
regulator-max-microvolt = <5000000>;
154
+
vin-supply = <&vcc_12v0_dcin>;
155
+
};
156
+
157
+
vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 {
158
+
compatible = "regulator-fixed";
159
+
regulator-name = "vcc_3v3_ufs_s0";
160
+
regulator-boot-on;
161
+
regulator-always-on;
162
+
regulator-min-microvolt = <3300000>;
163
+
regulator-max-microvolt = <3300000>;
164
+
vin-supply = <&vcc_5v0_sys>;
165
+
};
166
+
};
167
+
168
+
&cpu_l0 {
169
+
cpu-supply = <&vdd_cpu_lit_s0>;
170
+
};
171
+
172
+
&gmac0 {
173
+
phy-mode = "rgmii-id";
174
+
clock_in_out = "output";
175
+
176
+
snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
177
+
snps,reset-active-low;
178
+
snps,reset-delays-us = <0 20000 100000>;
179
+
180
+
pinctrl-names = "default";
181
+
pinctrl-0 = <ð0m0_miim
182
+
ð0m0_tx_bus2
183
+
ð0m0_rx_bus2
184
+
ð0m0_rgmii_clk
185
+
ð0m0_rgmii_bus
186
+
ðm0_clk0_25m_out>;
187
+
188
+
phy-handle = <&rgmii_phy0>;
189
+
status = "okay";
190
+
};
191
+
192
+
&gmac1 {
193
+
phy-mode = "rgmii-id";
194
+
clock_in_out = "output";
195
+
196
+
snps,reset-gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
197
+
snps,reset-active-low;
198
+
snps,reset-delays-us = <0 20000 100000>;
199
+
200
+
pinctrl-names = "default";
201
+
pinctrl-0 = <ð1m0_miim
202
+
ð1m0_tx_bus2
203
+
ð1m0_rx_bus2
204
+
ð1m0_rgmii_clk
205
+
ð1m0_rgmii_bus
206
+
ðm0_clk1_25m_out>;
207
+
208
+
phy-handle = <&rgmii_phy1>;
209
+
status = "okay";
210
+
};
211
+
212
+
&gpu {
213
+
mali-supply = <&vdd_gpu_s0>;
214
+
status = "okay";
215
+
};
216
+
217
+
&i2c1 {
218
+
status = "okay";
219
+
220
+
pmic@23 {
221
+
compatible = "rockchip,rk806";
222
+
reg = <0x23>;
223
+
224
+
interrupt-parent = <&gpio0>;
225
+
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
226
+
227
+
pinctrl-names = "default";
228
+
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
229
+
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
230
+
231
+
system-power-controller;
232
+
233
+
vcc1-supply = <&vcc_5v0_sys>;
234
+
vcc2-supply = <&vcc_5v0_sys>;
235
+
vcc3-supply = <&vcc_5v0_sys>;
236
+
vcc4-supply = <&vcc_5v0_sys>;
237
+
vcc5-supply = <&vcc_5v0_sys>;
238
+
vcc6-supply = <&vcc_5v0_sys>;
239
+
vcc7-supply = <&vcc_5v0_sys>;
240
+
vcc8-supply = <&vcc_5v0_sys>;
241
+
vcc9-supply = <&vcc_5v0_sys>;
242
+
vcc10-supply = <&vcc_5v0_sys>;
243
+
vcc11-supply = <&vcc_2v0_pldo_s3>;
244
+
vcc12-supply = <&vcc_5v0_sys>;
245
+
vcc13-supply = <&vcc_1v1_nldo_s3>;
246
+
vcc14-supply = <&vcc_1v1_nldo_s3>;
247
+
vcca-supply = <&vcc_5v0_sys>;
248
+
249
+
gpio-controller;
250
+
#gpio-cells = <2>;
251
+
252
+
rk806_dvs1_null: dvs1-null-pins {
253
+
pins = "gpio_pwrctrl1";
254
+
function = "pin_fun0";
255
+
};
256
+
257
+
rk806_dvs2_null: dvs2-null-pins {
258
+
pins = "gpio_pwrctrl2";
259
+
function = "pin_fun0";
260
+
};
261
+
262
+
rk806_dvs3_null: dvs3-null-pins {
263
+
pins = "gpio_pwrctrl3";
264
+
function = "pin_fun0";
265
+
};
266
+
267
+
rk806_dvs1_slp: dvs1-slp-pins {
268
+
pins = "gpio_pwrctrl1";
269
+
function = "pin_fun1";
270
+
};
271
+
272
+
rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
273
+
pins = "gpio_pwrctrl1";
274
+
function = "pin_fun2";
275
+
};
276
+
277
+
rk806_dvs1_rst: dvs1-rst-pins {
278
+
pins = "gpio_pwrctrl1";
279
+
function = "pin_fun3";
280
+
};
281
+
282
+
rk806_dvs2_slp: dvs2-slp-pins {
283
+
pins = "gpio_pwrctrl2";
284
+
function = "pin_fun1";
285
+
};
286
+
287
+
rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
288
+
pins = "gpio_pwrctrl2";
289
+
function = "pin_fun2";
290
+
};
291
+
292
+
rk806_dvs2_rst: dvs2-rst-pins {
293
+
pins = "gpio_pwrctrl2";
294
+
function = "pin_fun3";
295
+
};
296
+
297
+
rk806_dvs2_dvs: dvs2-dvs-pins {
298
+
pins = "gpio_pwrctrl2";
299
+
function = "pin_fun4";
300
+
};
301
+
302
+
rk806_dvs2_gpio: dvs2-gpio-pins {
303
+
pins = "gpio_pwrctrl2";
304
+
function = "pin_fun5";
305
+
};
306
+
307
+
rk806_dvs3_slp: dvs3-slp-pins {
308
+
pins = "gpio_pwrctrl3";
309
+
function = "pin_fun1";
310
+
};
311
+
312
+
rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
313
+
pins = "gpio_pwrctrl3";
314
+
function = "pin_fun2";
315
+
};
316
+
317
+
rk806_dvs3_rst: dvs3-rst-pins {
318
+
pins = "gpio_pwrctrl3";
319
+
function = "pin_fun3";
320
+
};
321
+
322
+
rk806_dvs3_dvs: dvs3-dvs-pins {
323
+
pins = "gpio_pwrctrl3";
324
+
function = "pin_fun4";
325
+
};
326
+
327
+
rk806_dvs3_gpio: dvs3-gpio-pins {
328
+
pins = "gpio_pwrctrl3";
329
+
function = "pin_fun5";
330
+
};
331
+
332
+
regulators {
333
+
vdd_cpu_big_s0: dcdc-reg1 {
334
+
regulator-always-on;
335
+
regulator-boot-on;
336
+
regulator-min-microvolt = <550000>;
337
+
regulator-max-microvolt = <950000>;
338
+
regulator-ramp-delay = <12500>;
339
+
regulator-name = "vdd_cpu_big_s0";
340
+
regulator-enable-ramp-delay = <400>;
341
+
regulator-state-mem {
342
+
regulator-off-in-suspend;
343
+
};
344
+
};
345
+
346
+
vdd_npu_s0: dcdc-reg2 {
347
+
regulator-boot-on;
348
+
regulator-min-microvolt = <550000>;
349
+
regulator-max-microvolt = <950000>;
350
+
regulator-ramp-delay = <12500>;
351
+
regulator-name = "vdd_npu_s0";
352
+
regulator-enable-ramp-delay = <400>;
353
+
regulator-state-mem {
354
+
regulator-off-in-suspend;
355
+
};
356
+
};
357
+
358
+
vdd_cpu_lit_s0: dcdc-reg3 {
359
+
regulator-always-on;
360
+
regulator-boot-on;
361
+
regulator-min-microvolt = <550000>;
362
+
regulator-max-microvolt = <950000>;
363
+
regulator-ramp-delay = <12500>;
364
+
regulator-name = "vdd_cpu_lit_s0";
365
+
regulator-state-mem {
366
+
regulator-off-in-suspend;
367
+
regulator-suspend-microvolt = <750000>;
368
+
};
369
+
};
370
+
371
+
vcc_3v3_s3: dcdc-reg4 {
372
+
regulator-always-on;
373
+
regulator-boot-on;
374
+
regulator-min-microvolt = <3300000>;
375
+
regulator-max-microvolt = <3300000>;
376
+
regulator-name = "vcc_3v3_s3";
377
+
regulator-state-mem {
378
+
regulator-on-in-suspend;
379
+
regulator-suspend-microvolt = <3300000>;
380
+
};
381
+
};
382
+
383
+
vdd_gpu_s0: dcdc-reg5 {
384
+
regulator-boot-on;
385
+
regulator-min-microvolt = <550000>;
386
+
regulator-max-microvolt = <900000>;
387
+
regulator-ramp-delay = <12500>;
388
+
regulator-name = "vdd_gpu_s0";
389
+
regulator-enable-ramp-delay = <400>;
390
+
regulator-state-mem {
391
+
regulator-off-in-suspend;
392
+
regulator-suspend-microvolt = <850000>;
393
+
};
394
+
};
395
+
396
+
vddq_ddr_s0: dcdc-reg6 {
397
+
regulator-always-on;
398
+
regulator-boot-on;
399
+
regulator-name = "vddq_ddr_s0";
400
+
regulator-state-mem {
401
+
regulator-off-in-suspend;
402
+
};
403
+
};
404
+
405
+
vdd_logic_s0: dcdc-reg7 {
406
+
regulator-always-on;
407
+
regulator-boot-on;
408
+
regulator-min-microvolt = <550000>;
409
+
regulator-max-microvolt = <800000>;
410
+
regulator-name = "vdd_logic_s0";
411
+
regulator-state-mem {
412
+
regulator-off-in-suspend;
413
+
};
414
+
};
415
+
416
+
vcc_1v8_s3: dcdc-reg8 {
417
+
regulator-always-on;
418
+
regulator-boot-on;
419
+
regulator-min-microvolt = <1800000>;
420
+
regulator-max-microvolt = <1800000>;
421
+
regulator-name = "vcc_1v8_s3";
422
+
regulator-state-mem {
423
+
regulator-on-in-suspend;
424
+
regulator-suspend-microvolt = <1800000>;
425
+
};
426
+
};
427
+
428
+
vdd2_ddr_s3: dcdc-reg9 {
429
+
regulator-always-on;
430
+
regulator-boot-on;
431
+
regulator-name = "vdd2_ddr_s3";
432
+
regulator-state-mem {
433
+
regulator-on-in-suspend;
434
+
};
435
+
};
436
+
437
+
vdd_ddr_s0: dcdc-reg10 {
438
+
regulator-always-on;
439
+
regulator-boot-on;
440
+
regulator-min-microvolt = <550000>;
441
+
regulator-max-microvolt = <1200000>;
442
+
regulator-name = "vdd_ddr_s0";
443
+
regulator-state-mem {
444
+
regulator-off-in-suspend;
445
+
};
446
+
};
447
+
448
+
vcca_1v8_s0: pldo-reg1 {
449
+
regulator-always-on;
450
+
regulator-boot-on;
451
+
regulator-min-microvolt = <1800000>;
452
+
regulator-max-microvolt = <1800000>;
453
+
regulator-name = "vcca_1v8_s0";
454
+
regulator-state-mem {
455
+
regulator-off-in-suspend;
456
+
};
457
+
};
458
+
459
+
vcca1v8_pldo2_s0: pldo-reg2 {
460
+
regulator-always-on;
461
+
regulator-boot-on;
462
+
regulator-min-microvolt = <1800000>;
463
+
regulator-max-microvolt = <1800000>;
464
+
regulator-name = "vcca1v8_pldo2_s0";
465
+
regulator-state-mem {
466
+
regulator-off-in-suspend;
467
+
};
468
+
};
469
+
470
+
vdda_1v2_s0: pldo-reg3 {
471
+
regulator-always-on;
472
+
regulator-boot-on;
473
+
regulator-min-microvolt = <1200000>;
474
+
regulator-max-microvolt = <1200000>;
475
+
regulator-name = "vdda_1v2_s0";
476
+
regulator-state-mem {
477
+
regulator-off-in-suspend;
478
+
};
479
+
};
480
+
481
+
vcca_3v3_s0: pldo-reg4 {
482
+
regulator-always-on;
483
+
regulator-boot-on;
484
+
regulator-min-microvolt = <3300000>;
485
+
regulator-max-microvolt = <3300000>;
486
+
regulator-name = "vcca_3v3_s0";
487
+
regulator-state-mem {
488
+
regulator-off-in-suspend;
489
+
};
490
+
};
491
+
492
+
vccio_sd_s0: pldo-reg5 {
493
+
regulator-always-on;
494
+
regulator-boot-on;
495
+
regulator-min-microvolt = <1800000>;
496
+
regulator-max-microvolt = <3300000>;
497
+
regulator-name = "vccio_sd_s0";
498
+
regulator-state-mem {
499
+
regulator-off-in-suspend;
500
+
};
501
+
};
502
+
503
+
vcca1v8_pldo6_s3: pldo-reg6 {
504
+
regulator-always-on;
505
+
regulator-boot-on;
506
+
regulator-min-microvolt = <1800000>;
507
+
regulator-max-microvolt = <1800000>;
508
+
regulator-name = "vcca1v8_pldo6_s3";
509
+
regulator-state-mem {
510
+
regulator-on-in-suspend;
511
+
regulator-suspend-microvolt = <1800000>;
512
+
};
513
+
};
514
+
515
+
vdd_0v75_s3: nldo-reg1 {
516
+
regulator-always-on;
517
+
regulator-boot-on;
518
+
regulator-min-microvolt = <750000>;
519
+
regulator-max-microvolt = <750000>;
520
+
regulator-name = "vdd_0v75_s3";
521
+
regulator-state-mem {
522
+
regulator-on-in-suspend;
523
+
regulator-suspend-microvolt = <750000>;
524
+
};
525
+
};
526
+
527
+
vdda_ddr_pll_s0: nldo-reg2 {
528
+
regulator-always-on;
529
+
regulator-boot-on;
530
+
regulator-min-microvolt = <850000>;
531
+
regulator-max-microvolt = <850000>;
532
+
regulator-name = "vdda_ddr_pll_s0";
533
+
regulator-state-mem {
534
+
regulator-off-in-suspend;
535
+
};
536
+
};
537
+
538
+
vdda0v75_hdmi_s0: nldo-reg3 {
539
+
regulator-always-on;
540
+
regulator-boot-on;
541
+
regulator-min-microvolt = <837500>;
542
+
regulator-max-microvolt = <837500>;
543
+
regulator-name = "vdda0v75_hdmi_s0";
544
+
regulator-state-mem {
545
+
regulator-off-in-suspend;
546
+
};
547
+
};
548
+
549
+
vdda_0v85_s0: nldo-reg4 {
550
+
regulator-always-on;
551
+
regulator-boot-on;
552
+
regulator-min-microvolt = <850000>;
553
+
regulator-max-microvolt = <850000>;
554
+
regulator-name = "vdda_0v85_s0";
555
+
regulator-state-mem {
556
+
regulator-off-in-suspend;
557
+
};
558
+
};
559
+
560
+
vdda_0v75_s0: nldo-reg5 {
561
+
regulator-always-on;
562
+
regulator-boot-on;
563
+
regulator-min-microvolt = <750000>;
564
+
regulator-max-microvolt = <750000>;
565
+
regulator-name = "vdda_0v75_s0";
566
+
regulator-state-mem {
567
+
regulator-off-in-suspend;
568
+
};
569
+
};
570
+
};
571
+
};
572
+
};
573
+
574
+
&i2c2 {
575
+
status = "okay";
576
+
577
+
hym8563: rtc@51 {
578
+
compatible = "haoyu,hym8563";
579
+
reg = <0x51>;
580
+
clock-output-names = "hym8563";
581
+
interrupt-parent = <&gpio0>;
582
+
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
583
+
pinctrl-names = "default";
584
+
pinctrl-0 = <&hym8563_int>;
585
+
wakeup-source;
586
+
#clock-cells = <0>;
587
+
};
588
+
};
589
+
590
+
&mdio0 {
591
+
rgmii_phy0: phy@1 {
592
+
compatible = "ethernet-phy-ieee802.3-c22";
593
+
reg = <0x1>;
594
+
clocks = <&cru REFCLKO25M_GMAC0_OUT>;
595
+
};
596
+
};
597
+
598
+
&mdio1 {
599
+
rgmii_phy1: phy@1 {
600
+
compatible = "ethernet-phy-ieee802.3-c22";
601
+
reg = <0x1>;
602
+
clocks = <&cru REFCLKO25M_GMAC1_OUT>;
603
+
};
604
+
};
605
+
606
+
&pinctrl {
607
+
headphone {
608
+
hp_det: hp-det {
609
+
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
610
+
};
611
+
};
612
+
613
+
hym8563 {
614
+
hym8563_int: hym8563-int {
615
+
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
616
+
};
617
+
};
618
+
619
+
leds {
620
+
led_rgb_r: led-red-en {
621
+
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
622
+
};
623
+
led_rgb_g: led-green-en {
624
+
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
625
+
};
626
+
};
627
+
};
628
+
629
+
&sdhci {
630
+
bus-width = <8>;
631
+
full-pwr-cycle-in-suspend;
632
+
max-frequency = <200000000>;
633
+
mmc-hs400-1_8v;
634
+
mmc-hs400-enhanced-strobe;
635
+
no-sdio;
636
+
no-sd;
637
+
non-removable;
638
+
status = "okay";
639
+
};
640
+
641
+
&sdmmc {
642
+
bus-width = <4>;
643
+
cap-mmc-highspeed;
644
+
cap-sd-highspeed;
645
+
disable-wp;
646
+
max-frequency = <200000000>;
647
+
no-sdio;
648
+
no-mmc;
649
+
non-removable;
650
+
sd-uhs-sdr104;
651
+
vmmc-supply = <&vcc_3v3_s3>;
652
+
vqmmc-supply = <&vccio_sd_s0>;
653
+
status = "okay";
654
+
};
655
+
656
+
&uart0 {
657
+
pinctrl-0 = <&uart0m0_xfer>;
658
+
status = "okay";
659
+
};
+5775
arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi
+5775
arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4
+
*/
5
+
6
+
#include <dt-bindings/pinctrl/rockchip.h>
7
+
#include "rockchip-pinconf.dtsi"
8
+
9
+
/*
10
+
* This file is auto generated by pin2dts tool, please keep these code
11
+
* by adding changes at end of this file.
12
+
*/
13
+
&pinctrl {
14
+
aupll_clk {
15
+
/omit-if-no-ref/
16
+
aupll_clkm0_pins: aupll_clkm0-pins {
17
+
rockchip,pins =
18
+
/* aupll_clk_in_m0 */
19
+
<0 RK_PA0 3 &pcfg_pull_none>;
20
+
};
21
+
22
+
/omit-if-no-ref/
23
+
aupll_clkm1_pins: aupll_clkm1-pins {
24
+
rockchip,pins =
25
+
/* aupll_clk_in_m1 */
26
+
<0 RK_PB0 3 &pcfg_pull_none>;
27
+
};
28
+
29
+
/omit-if-no-ref/
30
+
aupll_clkm2_pins: aupll_clkm2-pins {
31
+
rockchip,pins =
32
+
/* aupll_clk_in_m2 */
33
+
<4 RK_PA2 3 &pcfg_pull_none>;
34
+
};
35
+
};
36
+
37
+
cam_clk0 {
38
+
/omit-if-no-ref/
39
+
cam_clk0m0_clk0: cam_clk0m0-clk0 {
40
+
rockchip,pins =
41
+
/* cam_clk0_out_m0 */
42
+
<3 RK_PD7 3 &pcfg_pull_none>;
43
+
};
44
+
45
+
/omit-if-no-ref/
46
+
cam_clk0m1_clk0: cam_clk0m1-clk0 {
47
+
rockchip,pins =
48
+
/* cam_clk0_out_m1 */
49
+
<2 RK_PD2 1 &pcfg_pull_none>;
50
+
};
51
+
};
52
+
53
+
cam_clk1 {
54
+
/omit-if-no-ref/
55
+
cam_clk1m0_clk1: cam_clk1m0-clk1 {
56
+
rockchip,pins =
57
+
/* cam_clk1_out_m0 */
58
+
<4 RK_PA0 3 &pcfg_pull_none>;
59
+
};
60
+
61
+
/omit-if-no-ref/
62
+
cam_clk1m1_clk1: cam_clk1m1-clk1 {
63
+
rockchip,pins =
64
+
/* cam_clk1_out_m1 */
65
+
<2 RK_PD6 1 &pcfg_pull_none>;
66
+
};
67
+
};
68
+
69
+
cam_clk2 {
70
+
/omit-if-no-ref/
71
+
cam_clk2m0_clk2: cam_clk2m0-clk2 {
72
+
rockchip,pins =
73
+
/* cam_clk2_out_m0 */
74
+
<4 RK_PA1 3 &pcfg_pull_none>;
75
+
};
76
+
77
+
/omit-if-no-ref/
78
+
cam_clk2m1_clk2: cam_clk2m1-clk2 {
79
+
rockchip,pins =
80
+
/* cam_clk2_out_m1 */
81
+
<2 RK_PD7 1 &pcfg_pull_none>;
82
+
};
83
+
};
84
+
85
+
can0 {
86
+
/omit-if-no-ref/
87
+
can0m0_pins: can0m0-pins {
88
+
rockchip,pins =
89
+
/* can0_rx_m0 */
90
+
<2 RK_PA0 13 &pcfg_pull_none>,
91
+
/* can0_tx_m0 */
92
+
<2 RK_PA1 13 &pcfg_pull_none>;
93
+
};
94
+
95
+
/omit-if-no-ref/
96
+
can0m1_pins: can0m1-pins {
97
+
rockchip,pins =
98
+
/* can0_rx_m1 */
99
+
<4 RK_PC3 12 &pcfg_pull_none>,
100
+
/* can0_tx_m1 */
101
+
<4 RK_PC2 12 &pcfg_pull_none>;
102
+
};
103
+
104
+
/omit-if-no-ref/
105
+
can0m2_pins: can0m2-pins {
106
+
rockchip,pins =
107
+
/* can0_rx_m2 */
108
+
<4 RK_PA6 13 &pcfg_pull_none>,
109
+
/* can0_tx_m2 */
110
+
<4 RK_PA4 13 &pcfg_pull_none>;
111
+
};
112
+
113
+
/omit-if-no-ref/
114
+
can0m3_pins: can0m3-pins {
115
+
rockchip,pins =
116
+
/* can0_rx_m3 */
117
+
<3 RK_PC1 12 &pcfg_pull_none>,
118
+
/* can0_tx_m3 */
119
+
<3 RK_PC4 12 &pcfg_pull_none>;
120
+
};
121
+
};
122
+
123
+
can1 {
124
+
/omit-if-no-ref/
125
+
can1m0_pins: can1m0-pins {
126
+
rockchip,pins =
127
+
/* can1_rx_m0 */
128
+
<2 RK_PA2 13 &pcfg_pull_none>,
129
+
/* can1_tx_m0 */
130
+
<2 RK_PA3 13 &pcfg_pull_none>;
131
+
};
132
+
133
+
/omit-if-no-ref/
134
+
can1m1_pins: can1m1-pins {
135
+
rockchip,pins =
136
+
/* can1_rx_m1 */
137
+
<4 RK_PC7 13 &pcfg_pull_none>,
138
+
/* can1_tx_m1 */
139
+
<4 RK_PC6 13 &pcfg_pull_none>;
140
+
};
141
+
142
+
/omit-if-no-ref/
143
+
can1m2_pins: can1m2-pins {
144
+
rockchip,pins =
145
+
/* can1_rx_m2 */
146
+
<4 RK_PB4 13 &pcfg_pull_none>,
147
+
/* can1_tx_m2 */
148
+
<4 RK_PB5 13 &pcfg_pull_none>;
149
+
};
150
+
151
+
/omit-if-no-ref/
152
+
can1m3_pins: can1m3-pins {
153
+
rockchip,pins =
154
+
/* can1_rx_m3 */
155
+
<3 RK_PA3 11 &pcfg_pull_none>,
156
+
/* can1_tx_m3 */
157
+
<3 RK_PA2 11 &pcfg_pull_none>;
158
+
};
159
+
};
160
+
161
+
clk0_32k {
162
+
/omit-if-no-ref/
163
+
clk0_32k_pins: clk0_32k-pins {
164
+
rockchip,pins =
165
+
/* clk0_32k_out */
166
+
<0 RK_PA2 10 &pcfg_pull_none>;
167
+
};
168
+
};
169
+
170
+
clk1_32k {
171
+
/omit-if-no-ref/
172
+
clk1_32k_pins: clk1_32k-pins {
173
+
rockchip,pins =
174
+
/* clk1_32k_out */
175
+
<1 RK_PD5 13 &pcfg_pull_none>;
176
+
};
177
+
};
178
+
179
+
clk_32k {
180
+
/omit-if-no-ref/
181
+
clk_32k_pins: clk_32k-pins {
182
+
rockchip,pins =
183
+
/* clk_32k_in */
184
+
<0 RK_PA2 9 &pcfg_pull_none>;
185
+
};
186
+
};
187
+
188
+
cpubig {
189
+
/omit-if-no-ref/
190
+
cpubig_pins: cpubig-pins {
191
+
rockchip,pins =
192
+
/* cpubig_avs */
193
+
<0 RK_PD2 11 &pcfg_pull_none>;
194
+
};
195
+
};
196
+
197
+
cpulit {
198
+
/omit-if-no-ref/
199
+
cpulit_pins: cpulit-pins {
200
+
rockchip,pins =
201
+
/* cpulit_avs */
202
+
<0 RK_PC0 11 &pcfg_pull_none>;
203
+
};
204
+
};
205
+
206
+
debug0_test {
207
+
/omit-if-no-ref/
208
+
debug0_test_pins: debug0_test-pins {
209
+
rockchip,pins =
210
+
/* debug0_test_out */
211
+
<1 RK_PC4 7 &pcfg_pull_none>;
212
+
};
213
+
};
214
+
215
+
debug1_test {
216
+
/omit-if-no-ref/
217
+
debug1_test_pins: debug1_test-pins {
218
+
rockchip,pins =
219
+
/* debug1_test_out */
220
+
<1 RK_PC5 7 &pcfg_pull_none>;
221
+
};
222
+
};
223
+
224
+
debug2_test {
225
+
/omit-if-no-ref/
226
+
debug2_test_pins: debug2_test-pins {
227
+
rockchip,pins =
228
+
/* debug2_test_out */
229
+
<1 RK_PC6 7 &pcfg_pull_none>;
230
+
};
231
+
};
232
+
233
+
debug3_test {
234
+
/omit-if-no-ref/
235
+
debug3_test_pins: debug3_test-pins {
236
+
rockchip,pins =
237
+
/* debug3_test_out */
238
+
<1 RK_PC7 7 &pcfg_pull_none>;
239
+
};
240
+
};
241
+
242
+
debug4_test {
243
+
/omit-if-no-ref/
244
+
debug4_test_pins: debug4_test-pins {
245
+
rockchip,pins =
246
+
/* debug4_test_out */
247
+
<1 RK_PD0 7 &pcfg_pull_none>;
248
+
};
249
+
};
250
+
251
+
debug5_test {
252
+
/omit-if-no-ref/
253
+
debug5_test_pins: debug5_test-pins {
254
+
rockchip,pins =
255
+
/* debug5_test_out */
256
+
<1 RK_PD1 7 &pcfg_pull_none>;
257
+
};
258
+
};
259
+
260
+
debug6_test {
261
+
/omit-if-no-ref/
262
+
debug6_test_pins: debug6_test-pins {
263
+
rockchip,pins =
264
+
/* debug6_test_out */
265
+
<1 RK_PD2 7 &pcfg_pull_none>;
266
+
};
267
+
};
268
+
269
+
debug7_test {
270
+
/omit-if-no-ref/
271
+
debug7_test_pins: debug7_test-pins {
272
+
rockchip,pins =
273
+
/* debug7_test_out */
274
+
<1 RK_PD3 7 &pcfg_pull_none>;
275
+
};
276
+
};
277
+
278
+
dp {
279
+
/omit-if-no-ref/
280
+
dpm0_pins: dpm0-pins {
281
+
rockchip,pins =
282
+
/* dp_hpdin_m0 */
283
+
<4 RK_PC4 10 &pcfg_pull_none>;
284
+
};
285
+
286
+
/omit-if-no-ref/
287
+
dpm1_pins: dpm1-pins {
288
+
rockchip,pins =
289
+
/* dp_hpdin_m1 */
290
+
<0 RK_PC5 9 &pcfg_pull_none>;
291
+
};
292
+
};
293
+
294
+
dsm_aud {
295
+
/omit-if-no-ref/
296
+
dsm_audm0_ln: dsm_audm0-ln {
297
+
rockchip,pins =
298
+
/* dsm_aud_ln_m0 */
299
+
<2 RK_PA1 3 &pcfg_pull_none>;
300
+
};
301
+
302
+
/omit-if-no-ref/
303
+
dsm_audm0_lp: dsm_audm0-lp {
304
+
rockchip,pins =
305
+
/* dsm_aud_lp_m0 */
306
+
<2 RK_PA0 3 &pcfg_pull_none>;
307
+
};
308
+
309
+
/omit-if-no-ref/
310
+
dsm_audm0_rn: dsm_audm0-rn {
311
+
rockchip,pins =
312
+
/* dsm_aud_rn_m0 */
313
+
<2 RK_PA3 3 &pcfg_pull_none>;
314
+
};
315
+
316
+
/omit-if-no-ref/
317
+
dsm_audm0_rp: dsm_audm0-rp {
318
+
rockchip,pins =
319
+
/* dsm_aud_rp_m0 */
320
+
<2 RK_PA2 3 &pcfg_pull_none>;
321
+
};
322
+
323
+
/omit-if-no-ref/
324
+
dsm_audm1_ln: dsm_audm1-ln {
325
+
rockchip,pins =
326
+
/* dsm_aud_ln_m1 */
327
+
<4 RK_PC1 1 &pcfg_pull_none>;
328
+
};
329
+
330
+
/omit-if-no-ref/
331
+
dsm_audm1_lp: dsm_audm1-lp {
332
+
rockchip,pins =
333
+
/* dsm_aud_lp_m1 */
334
+
<4 RK_PC0 1 &pcfg_pull_none>;
335
+
};
336
+
337
+
/omit-if-no-ref/
338
+
dsm_audm1_rn: dsm_audm1-rn {
339
+
rockchip,pins =
340
+
/* dsm_aud_rn_m1 */
341
+
<4 RK_PC3 1 &pcfg_pull_none>;
342
+
};
343
+
344
+
/omit-if-no-ref/
345
+
dsm_audm1_rp: dsm_audm1-rp {
346
+
rockchip,pins =
347
+
/* dsm_aud_rp_m1 */
348
+
<4 RK_PC2 1 &pcfg_pull_none>;
349
+
};
350
+
};
351
+
352
+
dsmc {
353
+
/omit-if-no-ref/
354
+
dsmc_clkn: dsmc-clkn {
355
+
rockchip,pins =
356
+
/* dsmc_clkn */
357
+
<3 RK_PD6 5 &pcfg_pull_none>;
358
+
};
359
+
/omit-if-no-ref/
360
+
dsmc_clkp: dsmc-clkp {
361
+
rockchip,pins =
362
+
/* dsmc_clkp */
363
+
<3 RK_PD5 5 &pcfg_pull_none>;
364
+
};
365
+
/omit-if-no-ref/
366
+
dsmc_csn0: dsmc-csn0 {
367
+
rockchip,pins =
368
+
/* dsmc_csn0 */
369
+
<3 RK_PD3 5 &pcfg_pull_none>;
370
+
};
371
+
/omit-if-no-ref/
372
+
dsmc_csn1: dsmc-csn1 {
373
+
rockchip,pins =
374
+
/* dsmc_csn1 */
375
+
<3 RK_PB0 5 &pcfg_pull_none>;
376
+
};
377
+
/omit-if-no-ref/
378
+
dsmc_csn2: dsmc-csn2 {
379
+
rockchip,pins =
380
+
/* dsmc_csn2 */
381
+
<3 RK_PD1 5 &pcfg_pull_none>;
382
+
};
383
+
/omit-if-no-ref/
384
+
dsmc_csn3: dsmc-csn3 {
385
+
rockchip,pins =
386
+
/* dsmc_csn3 */
387
+
<3 RK_PD2 5 &pcfg_pull_none>;
388
+
};
389
+
/omit-if-no-ref/
390
+
dsmc_data0: dsmc-data0 {
391
+
rockchip,pins =
392
+
/* dsmc_data0 */
393
+
<3 RK_PD4 5 &pcfg_pull_none>;
394
+
};
395
+
/omit-if-no-ref/
396
+
dsmc_data1: dsmc-data1 {
397
+
rockchip,pins =
398
+
/* dsmc_data1 */
399
+
<3 RK_PD0 5 &pcfg_pull_none>;
400
+
};
401
+
/omit-if-no-ref/
402
+
dsmc_data2: dsmc-data2 {
403
+
rockchip,pins =
404
+
/* dsmc_data2 */
405
+
<3 RK_PC7 5 &pcfg_pull_none>;
406
+
};
407
+
/omit-if-no-ref/
408
+
dsmc_data3: dsmc-data3 {
409
+
rockchip,pins =
410
+
/* dsmc_data3 */
411
+
<3 RK_PC6 5 &pcfg_pull_none>;
412
+
};
413
+
/omit-if-no-ref/
414
+
dsmc_data4: dsmc-data4 {
415
+
rockchip,pins =
416
+
/* dsmc_data4 */
417
+
<3 RK_PC5 5 &pcfg_pull_none>;
418
+
};
419
+
/omit-if-no-ref/
420
+
dsmc_data5: dsmc-data5 {
421
+
rockchip,pins =
422
+
/* dsmc_data5 */
423
+
<3 RK_PC4 5 &pcfg_pull_none>;
424
+
};
425
+
/omit-if-no-ref/
426
+
dsmc_data6: dsmc-data6 {
427
+
rockchip,pins =
428
+
/* dsmc_data6 */
429
+
<3 RK_PC1 5 &pcfg_pull_none>;
430
+
};
431
+
/omit-if-no-ref/
432
+
dsmc_data7: dsmc-data7 {
433
+
rockchip,pins =
434
+
/* dsmc_data7 */
435
+
<3 RK_PC0 5 &pcfg_pull_none>;
436
+
};
437
+
/omit-if-no-ref/
438
+
dsmc_data8: dsmc-data8 {
439
+
rockchip,pins =
440
+
/* dsmc_data8 */
441
+
<3 RK_PB5 5 &pcfg_pull_none>;
442
+
};
443
+
/omit-if-no-ref/
444
+
dsmc_data9: dsmc-data9 {
445
+
rockchip,pins =
446
+
/* dsmc_data9 */
447
+
<3 RK_PB4 5 &pcfg_pull_none>;
448
+
};
449
+
/omit-if-no-ref/
450
+
dsmc_data10: dsmc-data10 {
451
+
rockchip,pins =
452
+
/* dsmc_data10 */
453
+
<3 RK_PB3 5 &pcfg_pull_none>;
454
+
};
455
+
/omit-if-no-ref/
456
+
dsmc_data11: dsmc-data11 {
457
+
rockchip,pins =
458
+
/* dsmc_data11 */
459
+
<3 RK_PB2 5 &pcfg_pull_none>;
460
+
};
461
+
/omit-if-no-ref/
462
+
dsmc_data12: dsmc-data12 {
463
+
rockchip,pins =
464
+
/* dsmc_data12 */
465
+
<3 RK_PB1 5 &pcfg_pull_none>;
466
+
};
467
+
/omit-if-no-ref/
468
+
dsmc_data13: dsmc-data13 {
469
+
rockchip,pins =
470
+
/* dsmc_data13 */
471
+
<3 RK_PA7 5 &pcfg_pull_none>;
472
+
};
473
+
/omit-if-no-ref/
474
+
dsmc_data14: dsmc-data14 {
475
+
rockchip,pins =
476
+
/* dsmc_data14 */
477
+
<3 RK_PA6 5 &pcfg_pull_none>;
478
+
};
479
+
/omit-if-no-ref/
480
+
dsmc_data15: dsmc-data15 {
481
+
rockchip,pins =
482
+
/* dsmc_data15 */
483
+
<3 RK_PA5 5 &pcfg_pull_none>;
484
+
};
485
+
/omit-if-no-ref/
486
+
dsmc_dqs0: dsmc-dqs0 {
487
+
rockchip,pins =
488
+
/* dsmc_dqs0 */
489
+
<3 RK_PB7 5 &pcfg_pull_none>;
490
+
};
491
+
/omit-if-no-ref/
492
+
dsmc_dqs1: dsmc-dqs1 {
493
+
rockchip,pins =
494
+
/* dsmc_dqs1 */
495
+
<3 RK_PB6 5 &pcfg_pull_none>;
496
+
};
497
+
/omit-if-no-ref/
498
+
dsmc_int0: dsmc-int0 {
499
+
rockchip,pins =
500
+
/* dsmc_int0 */
501
+
<4 RK_PA0 5 &pcfg_pull_none>;
502
+
};
503
+
/omit-if-no-ref/
504
+
dsmc_int1: dsmc-int1 {
505
+
rockchip,pins =
506
+
/* dsmc_int1 */
507
+
<3 RK_PC2 5 &pcfg_pull_none>;
508
+
};
509
+
/omit-if-no-ref/
510
+
dsmc_int2: dsmc-int2 {
511
+
rockchip,pins =
512
+
/* dsmc_int2 */
513
+
<4 RK_PA1 5 &pcfg_pull_none>;
514
+
};
515
+
/omit-if-no-ref/
516
+
dsmc_int3: dsmc-int3 {
517
+
rockchip,pins =
518
+
/* dsmc_int3 */
519
+
<3 RK_PC3 5 &pcfg_pull_none>;
520
+
};
521
+
/omit-if-no-ref/
522
+
dsmc_rdyn: dsmc-rdyn {
523
+
rockchip,pins =
524
+
/* dsmc_rdyn */
525
+
<3 RK_PA4 5 &pcfg_pull_none>;
526
+
};
527
+
/omit-if-no-ref/
528
+
dsmc_resetn: dsmc-resetn {
529
+
rockchip,pins =
530
+
/* dsmc_resetn */
531
+
<3 RK_PD7 5 &pcfg_pull_none>;
532
+
};
533
+
};
534
+
535
+
dsmc_testclk {
536
+
/omit-if-no-ref/
537
+
dsmc_testclk_out: dsmc-testclk-out {
538
+
rockchip,pins =
539
+
/* dsmc_testclk_out */
540
+
<3 RK_PC2 7 &pcfg_pull_none>;
541
+
};
542
+
};
543
+
544
+
dsmc_testdata {
545
+
/omit-if-no-ref/
546
+
dsmc_testdata_out: dsmc-testdata-out {
547
+
rockchip,pins =
548
+
/* dsmc_testdata_out */
549
+
<3 RK_PC3 7 &pcfg_pull_none>;
550
+
};
551
+
};
552
+
553
+
edp_tx {
554
+
/omit-if-no-ref/
555
+
edp_txm0_pins: edp_txm0-pins {
556
+
rockchip,pins =
557
+
/* edp_tx_hpdin_m0 */
558
+
<4 RK_PC1 12 &pcfg_pull_none>;
559
+
};
560
+
561
+
/omit-if-no-ref/
562
+
edp_txm1_pins: edp_txm1-pins {
563
+
rockchip,pins =
564
+
/* edp_tx_hpdin_m1 */
565
+
<0 RK_PB6 10 &pcfg_pull_none>;
566
+
};
567
+
};
568
+
569
+
emmc {
570
+
/omit-if-no-ref/
571
+
emmc_rstnout: emmc-rstnout {
572
+
rockchip,pins =
573
+
/* emmc_rstn */
574
+
<1 RK_PB3 1 &pcfg_pull_none>;
575
+
};
576
+
577
+
/omit-if-no-ref/
578
+
emmc_bus8: emmc-bus8 {
579
+
rockchip,pins =
580
+
/* emmc_d0 */
581
+
<1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
582
+
/* emmc_d1 */
583
+
<1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
584
+
/* emmc_d2 */
585
+
<1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
586
+
/* emmc_d3 */
587
+
<1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
588
+
/* emmc_d4 */
589
+
<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
590
+
/* emmc_d5 */
591
+
<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
592
+
/* emmc_d6 */
593
+
<1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
594
+
/* emmc_d7 */
595
+
<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
596
+
};
597
+
598
+
/omit-if-no-ref/
599
+
emmc_clk: emmc-clk {
600
+
rockchip,pins =
601
+
/* emmc_clk */
602
+
<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
603
+
};
604
+
605
+
/omit-if-no-ref/
606
+
emmc_cmd: emmc-cmd {
607
+
rockchip,pins =
608
+
/* emmc_cmd */
609
+
<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
610
+
};
611
+
612
+
/omit-if-no-ref/
613
+
emmc_strb: emmc-strb {
614
+
rockchip,pins =
615
+
/* emmc_strb */
616
+
<1 RK_PB2 1 &pcfg_pull_none>;
617
+
};
618
+
};
619
+
620
+
emmc_testclk {
621
+
/omit-if-no-ref/
622
+
emmc_testclk_test: emmc_testclk-test {
623
+
rockchip,pins =
624
+
/* emmc_testclk_out */
625
+
<1 RK_PB3 6 &pcfg_pull_none>;
626
+
};
627
+
};
628
+
629
+
emmc_testdata {
630
+
/omit-if-no-ref/
631
+
emmc_testdata_test: emmc_testdata-test {
632
+
rockchip,pins =
633
+
/* emmc_testdata_out */
634
+
<1 RK_PB7 5 &pcfg_pull_none>;
635
+
};
636
+
};
637
+
638
+
eth0 {
639
+
/omit-if-no-ref/
640
+
eth0m0_miim: eth0m0-miim {
641
+
rockchip,pins =
642
+
/* eth0_mdc_m0 */
643
+
<3 RK_PA6 3 &pcfg_pull_none>,
644
+
/* eth0_mdio_m0 */
645
+
<3 RK_PA5 3 &pcfg_pull_none>;
646
+
};
647
+
648
+
/omit-if-no-ref/
649
+
eth0m0_rx_bus2: eth0m0-rx_bus2 {
650
+
rockchip,pins =
651
+
/* eth0_rxctl_m0 */
652
+
<3 RK_PA7 3 &pcfg_pull_none>,
653
+
/* eth0_rxd0_m0 */
654
+
<3 RK_PB2 3 &pcfg_pull_none>,
655
+
/* eth0_rxd1_m0 */
656
+
<3 RK_PB1 3 &pcfg_pull_none>;
657
+
};
658
+
659
+
/omit-if-no-ref/
660
+
eth0m0_tx_bus2: eth0m0-tx_bus2 {
661
+
rockchip,pins =
662
+
/* eth0_txctl_m0 */
663
+
<3 RK_PB3 3 &pcfg_pull_none>,
664
+
/* eth0_txd0_m0 */
665
+
<3 RK_PB5 3 &pcfg_pull_none>,
666
+
/* eth0_txd1_m0 */
667
+
<3 RK_PB4 3 &pcfg_pull_none>;
668
+
};
669
+
670
+
/omit-if-no-ref/
671
+
eth0m0_rgmii_clk: eth0m0-rgmii_clk {
672
+
rockchip,pins =
673
+
/* eth0_rxclk_m0 */
674
+
<3 RK_PD1 3 &pcfg_pull_none>,
675
+
/* eth0_txclk_m0 */
676
+
<3 RK_PB6 3 &pcfg_pull_none>;
677
+
};
678
+
679
+
/omit-if-no-ref/
680
+
eth0m0_rgmii_bus: eth0m0-rgmii_bus {
681
+
rockchip,pins =
682
+
/* eth0_rxd2_m0 */
683
+
<3 RK_PD3 3 &pcfg_pull_none>,
684
+
/* eth0_rxd3_m0 */
685
+
<3 RK_PD2 3 &pcfg_pull_none>,
686
+
/* eth0_txd2_m0 */
687
+
<3 RK_PC3 3 &pcfg_pull_none>,
688
+
/* eth0_txd3_m0 */
689
+
<3 RK_PC2 3 &pcfg_pull_none>;
690
+
};
691
+
692
+
/omit-if-no-ref/
693
+
eth0m0_mclk: eth0m0-mclk {
694
+
rockchip,pins =
695
+
/* eth0m0_mclk */
696
+
<3 RK_PB0 3 &pcfg_pull_none>;
697
+
};
698
+
/omit-if-no-ref/
699
+
eth0m0_ppsclk: eth0m0-ppsclk {
700
+
rockchip,pins =
701
+
/* eth0m0_ppsclk */
702
+
<3 RK_PC0 3 &pcfg_pull_none>;
703
+
};
704
+
/omit-if-no-ref/
705
+
eth0m0_ppstrig: eth0m0-ppstrig {
706
+
rockchip,pins =
707
+
/* eth0m0_ppstrig */
708
+
<3 RK_PB7 3 &pcfg_pull_none>;
709
+
};
710
+
711
+
/omit-if-no-ref/
712
+
eth0m1_miim: eth0m1-miim {
713
+
rockchip,pins =
714
+
/* eth0_mdc_m1 */
715
+
<3 RK_PA1 3 &pcfg_pull_none>,
716
+
/* eth0_mdio_m1 */
717
+
<3 RK_PA0 3 &pcfg_pull_none>;
718
+
};
719
+
720
+
/omit-if-no-ref/
721
+
eth0m1_rx_bus2: eth0m1-rx_bus2 {
722
+
rockchip,pins =
723
+
/* eth0_rxctl_m1 */
724
+
<3 RK_PA2 3 &pcfg_pull_none>,
725
+
/* eth0_rxd0_m1 */
726
+
<2 RK_PA6 3 &pcfg_pull_none>,
727
+
/* eth0_rxd1_m1 */
728
+
<3 RK_PA3 3 &pcfg_pull_none>;
729
+
};
730
+
731
+
/omit-if-no-ref/
732
+
eth0m1_tx_bus2: eth0m1-tx_bus2 {
733
+
rockchip,pins =
734
+
/* eth0_txctl_m1 */
735
+
<2 RK_PA7 3 &pcfg_pull_none>,
736
+
/* eth0_txd0_m1 */
737
+
<2 RK_PB1 3 &pcfg_pull_none>,
738
+
/* eth0_txd1_m1 */
739
+
<2 RK_PB0 3 &pcfg_pull_none>;
740
+
};
741
+
742
+
/omit-if-no-ref/
743
+
eth0m1_rgmii_clk: eth0m1-rgmii_clk {
744
+
rockchip,pins =
745
+
/* eth0_rxclk_m1 */
746
+
<2 RK_PB5 3 &pcfg_pull_none>,
747
+
/* eth0_txclk_m1 */
748
+
<2 RK_PB3 3 &pcfg_pull_none>;
749
+
};
750
+
751
+
/omit-if-no-ref/
752
+
eth0m1_rgmii_bus: eth0m1-rgmii_bus {
753
+
rockchip,pins =
754
+
/* eth0_rxd2_m1 */
755
+
<2 RK_PB7 3 &pcfg_pull_none>,
756
+
/* eth0_rxd3_m1 */
757
+
<2 RK_PB6 3 &pcfg_pull_none>,
758
+
/* eth0_txd2_m1 */
759
+
<2 RK_PB4 3 &pcfg_pull_none>,
760
+
/* eth0_txd3_m1 */
761
+
<2 RK_PB2 3 &pcfg_pull_none>;
762
+
};
763
+
764
+
/omit-if-no-ref/
765
+
eth0m1_mclk: eth0m1-mclk {
766
+
rockchip,pins =
767
+
/* eth0m1_mclk */
768
+
<2 RK_PD6 3 &pcfg_pull_none>;
769
+
};
770
+
/omit-if-no-ref/
771
+
eth0m1_ppsclk: eth0m1-ppsclk {
772
+
rockchip,pins =
773
+
/* eth0m1_ppsclk */
774
+
<2 RK_PC1 3 &pcfg_pull_none>;
775
+
};
776
+
/omit-if-no-ref/
777
+
eth0m1_ppstrig: eth0m1-ppstrig {
778
+
rockchip,pins =
779
+
/* eth0m1_ppstrig */
780
+
<2 RK_PC2 3 &pcfg_pull_none>;
781
+
};
782
+
};
783
+
784
+
eth1 {
785
+
/omit-if-no-ref/
786
+
eth1m0_miim: eth1m0-miim {
787
+
rockchip,pins =
788
+
/* eth1_mdc_m0 */
789
+
<2 RK_PD4 2 &pcfg_pull_none>,
790
+
/* eth1_mdio_m0 */
791
+
<2 RK_PD5 2 &pcfg_pull_none>;
792
+
};
793
+
794
+
/omit-if-no-ref/
795
+
eth1m0_rx_bus2: eth1m0-rx_bus2 {
796
+
rockchip,pins =
797
+
/* eth1_rxctl_m0 */
798
+
<2 RK_PD3 2 &pcfg_pull_none>,
799
+
/* eth1_rxd0_m0 */
800
+
<2 RK_PD1 2 &pcfg_pull_none>,
801
+
/* eth1_rxd1_m0 */
802
+
<2 RK_PD2 2 &pcfg_pull_none>;
803
+
};
804
+
805
+
/omit-if-no-ref/
806
+
eth1m0_tx_bus2: eth1m0-tx_bus2 {
807
+
rockchip,pins =
808
+
/* eth1_txctl_m0 */
809
+
<2 RK_PD0 2 &pcfg_pull_none>,
810
+
/* eth1_txd0_m0 */
811
+
<2 RK_PC6 2 &pcfg_pull_none>,
812
+
/* eth1_txd1_m0 */
813
+
<2 RK_PC7 2 &pcfg_pull_none>;
814
+
};
815
+
816
+
/omit-if-no-ref/
817
+
eth1m0_rgmii_clk: eth1m0-rgmii_clk {
818
+
rockchip,pins =
819
+
/* eth1_rxclk_m0 */
820
+
<2 RK_PC2 2 &pcfg_pull_none>,
821
+
/* eth1_txclk_m0 */
822
+
<2 RK_PC5 2 &pcfg_pull_none>;
823
+
};
824
+
825
+
/omit-if-no-ref/
826
+
eth1m0_rgmii_bus: eth1m0-rgmii_bus {
827
+
rockchip,pins =
828
+
/* eth1_rxd2_m0 */
829
+
<2 RK_PC0 2 &pcfg_pull_none>,
830
+
/* eth1_rxd3_m0 */
831
+
<2 RK_PC1 2 &pcfg_pull_none>,
832
+
/* eth1_txd2_m0 */
833
+
<2 RK_PC3 2 &pcfg_pull_none>,
834
+
/* eth1_txd3_m0 */
835
+
<2 RK_PC4 2 &pcfg_pull_none>;
836
+
};
837
+
838
+
/omit-if-no-ref/
839
+
eth1m0_mclk: eth1m0-mclk {
840
+
rockchip,pins =
841
+
/* eth1m0_mclk */
842
+
<2 RK_PD7 2 &pcfg_pull_none>;
843
+
};
844
+
/omit-if-no-ref/
845
+
eth1m0_ppsclk: eth1m0-ppsclk {
846
+
rockchip,pins =
847
+
/* eth1m0_ppsclk */
848
+
<3 RK_PA2 2 &pcfg_pull_none>;
849
+
};
850
+
/omit-if-no-ref/
851
+
eth1m0_ppstrig: eth1m0-ppstrig {
852
+
rockchip,pins =
853
+
/* eth1m0_ppstrig */
854
+
<3 RK_PA1 2 &pcfg_pull_none>;
855
+
};
856
+
857
+
/omit-if-no-ref/
858
+
eth1m1_miim: eth1m1-miim {
859
+
rockchip,pins =
860
+
/* eth1_mdc_m1 */
861
+
<1 RK_PD2 1 &pcfg_pull_none>,
862
+
/* eth1_mdio_m1 */
863
+
<1 RK_PD3 1 &pcfg_pull_none>;
864
+
};
865
+
866
+
/omit-if-no-ref/
867
+
eth1m1_rx_bus2: eth1m1-rx_bus2 {
868
+
rockchip,pins =
869
+
/* eth1_rxctl_m1 */
870
+
<1 RK_PD1 1 &pcfg_pull_none>,
871
+
/* eth1_rxd0_m1 */
872
+
<1 RK_PC7 1 &pcfg_pull_none>,
873
+
/* eth1_rxd1_m1 */
874
+
<1 RK_PD0 1 &pcfg_pull_none>;
875
+
};
876
+
877
+
/omit-if-no-ref/
878
+
eth1m1_tx_bus2: eth1m1-tx_bus2 {
879
+
rockchip,pins =
880
+
/* eth1_txctl_m1 */
881
+
<1 RK_PC6 1 &pcfg_pull_none>,
882
+
/* eth1_txd0_m1 */
883
+
<1 RK_PC4 1 &pcfg_pull_none>,
884
+
/* eth1_txd1_m1 */
885
+
<1 RK_PC5 1 &pcfg_pull_none>;
886
+
};
887
+
888
+
/omit-if-no-ref/
889
+
eth1m1_rgmii_clk: eth1m1-rgmii_clk {
890
+
rockchip,pins =
891
+
/* eth1_rxclk_m1 */
892
+
<1 RK_PB6 1 &pcfg_pull_none>,
893
+
/* eth1_txclk_m1 */
894
+
<1 RK_PC1 1 &pcfg_pull_none>;
895
+
};
896
+
897
+
/omit-if-no-ref/
898
+
eth1m1_rgmii_bus: eth1m1-rgmii_bus {
899
+
rockchip,pins =
900
+
/* eth1_rxd2_m1 */
901
+
<1 RK_PB4 1 &pcfg_pull_none>,
902
+
/* eth1_rxd3_m1 */
903
+
<1 RK_PB5 1 &pcfg_pull_none>,
904
+
/* eth1_txd2_m1 */
905
+
<1 RK_PB7 1 &pcfg_pull_none>,
906
+
/* eth1_txd3_m1 */
907
+
<1 RK_PC0 1 &pcfg_pull_none>;
908
+
};
909
+
910
+
/omit-if-no-ref/
911
+
eth1m1_mclk: eth1m1-mclk {
912
+
rockchip,pins =
913
+
/* eth1m1_mclk */
914
+
<1 RK_PD4 1 &pcfg_pull_none>;
915
+
};
916
+
/omit-if-no-ref/
917
+
eth1m1_ppsclk: eth1m1-ppsclk {
918
+
rockchip,pins =
919
+
/* eth1m1_ppsclk */
920
+
<1 RK_PC2 1 &pcfg_pull_none>;
921
+
};
922
+
/omit-if-no-ref/
923
+
eth1m1_ppstrig: eth1m1-ppstrig {
924
+
rockchip,pins =
925
+
/* eth1m1_ppstrig */
926
+
<1 RK_PC3 1 &pcfg_pull_none>;
927
+
};
928
+
};
929
+
930
+
eth0_ptp {
931
+
/omit-if-no-ref/
932
+
eth0m0_ptp_refclk: eth0m0-ptp-refclk {
933
+
rockchip,pins =
934
+
/* eth0m0_ptp_refclk */
935
+
<3 RK_PC1 3 &pcfg_pull_none>;
936
+
};
937
+
938
+
/omit-if-no-ref/
939
+
eth0m1_ptp_refclk: eth0m1-ptp-refclk {
940
+
rockchip,pins =
941
+
/* eth0m1_ptp_refclk */
942
+
<2 RK_PC0 3 &pcfg_pull_none>;
943
+
};
944
+
};
945
+
946
+
eth0_testrxclk {
947
+
/omit-if-no-ref/
948
+
eth0_testrxclkm0_test: eth0_testrxclkm0-test {
949
+
rockchip,pins =
950
+
/* eth0_testrxclk_out_m0 */
951
+
<3 RK_PC7 3 &pcfg_pull_none>;
952
+
};
953
+
954
+
/omit-if-no-ref/
955
+
eth0_testrxclkm1_test: eth0_testrxclkm1-test {
956
+
rockchip,pins =
957
+
/* eth0_testrxclk_out_m1 */
958
+
<2 RK_PC5 6 &pcfg_pull_none>;
959
+
};
960
+
};
961
+
962
+
eth0_testrxd {
963
+
/omit-if-no-ref/
964
+
eth0_testrxdm0_test: eth0_testrxdm0-test {
965
+
rockchip,pins =
966
+
/* eth0_testrxd_out_m0 */
967
+
<3 RK_PD0 3 &pcfg_pull_none>;
968
+
};
969
+
970
+
/omit-if-no-ref/
971
+
eth0_testrxdm1_test: eth0_testrxdm1-test {
972
+
rockchip,pins =
973
+
/* eth0_testrxd_out_m1 */
974
+
<2 RK_PC4 6 &pcfg_pull_none>;
975
+
};
976
+
};
977
+
978
+
eth1_ptp {
979
+
/omit-if-no-ref/
980
+
eth1m0_ptp_refclk: eth1m0-ptp-refclk {
981
+
rockchip,pins =
982
+
/* eth1m0_ptp_refclk */
983
+
<3 RK_PA3 2 &pcfg_pull_none>;
984
+
};
985
+
986
+
/omit-if-no-ref/
987
+
eth1m1_ptp_refclk: eth1m1-ptp-refclk {
988
+
rockchip,pins =
989
+
/* eth1m1_ptp_refclk */
990
+
<2 RK_PB6 2 &pcfg_pull_none>;
991
+
};
992
+
};
993
+
994
+
eth1_testrxclk {
995
+
/omit-if-no-ref/
996
+
eth1_testrxclkm0_test: eth1_testrxclkm0-test {
997
+
rockchip,pins =
998
+
/* eth1_testrxclk_out_m0 */
999
+
<3 RK_PA1 6 &pcfg_pull_none>;
1000
+
};
1001
+
1002
+
/omit-if-no-ref/
1003
+
eth1_testrxclkm1_test: eth1_testrxclkm1-test {
1004
+
rockchip,pins =
1005
+
/* eth1_testrxclk_out_m1 */
1006
+
<1 RK_PC3 6 &pcfg_pull_none>;
1007
+
};
1008
+
};
1009
+
1010
+
eth1_testrxd {
1011
+
/omit-if-no-ref/
1012
+
eth1_testrxdm0_test: eth1_testrxdm0-test {
1013
+
rockchip,pins =
1014
+
/* eth1_testrxd_out_m0 */
1015
+
<3 RK_PA0 6 &pcfg_pull_none>;
1016
+
};
1017
+
1018
+
/omit-if-no-ref/
1019
+
eth1_testrxdm1_test: eth1_testrxdm1-test {
1020
+
rockchip,pins =
1021
+
/* eth1_testrxd_out_m1 */
1022
+
<1 RK_PC2 6 &pcfg_pull_none>;
1023
+
};
1024
+
};
1025
+
1026
+
eth_clk0_25m {
1027
+
/omit-if-no-ref/
1028
+
ethm0_clk0_25m_out: ethm0-clk0-25m-out {
1029
+
rockchip,pins =
1030
+
/* ethm0_clk0_25m_out */
1031
+
<3 RK_PA4 3 &pcfg_pull_none>;
1032
+
};
1033
+
1034
+
/omit-if-no-ref/
1035
+
ethm1_clk0_25m_out: ethm1-clk0-25m-out {
1036
+
rockchip,pins =
1037
+
/* ethm1_clk0_25m_out */
1038
+
<2 RK_PD7 3 &pcfg_pull_none>;
1039
+
};
1040
+
};
1041
+
1042
+
eth_clk1_25m {
1043
+
/omit-if-no-ref/
1044
+
ethm0_clk1_25m_out: ethm0-clk1-25m-out {
1045
+
rockchip,pins =
1046
+
/* ethm0_clk1_25m_out */
1047
+
<2 RK_PD6 2 &pcfg_pull_none>;
1048
+
};
1049
+
1050
+
/omit-if-no-ref/
1051
+
ethm1_clk1_25m_out: ethm1-clk1-25m-out {
1052
+
rockchip,pins =
1053
+
/* ethm1_clk1_25m_out */
1054
+
<1 RK_PD5 1 &pcfg_pull_none>;
1055
+
};
1056
+
};
1057
+
1058
+
flexbus0 {
1059
+
/omit-if-no-ref/
1060
+
flexbus0m0_csn: flexbus0m0-csn {
1061
+
rockchip,pins =
1062
+
/* flexbus0_csn_m0 */
1063
+
<3 RK_PA4 8 &pcfg_pull_none>;
1064
+
};
1065
+
1066
+
/omit-if-no-ref/
1067
+
flexbus0m0_d13: flexbus0m0-d13 {
1068
+
rockchip,pins =
1069
+
/* flexbus0_d13_m0 */
1070
+
<4 RK_PA0 6 &pcfg_pull_none>;
1071
+
};
1072
+
1073
+
/omit-if-no-ref/
1074
+
flexbus0m0_d14: flexbus0m0-d14 {
1075
+
rockchip,pins =
1076
+
/* flexbus0_d14_m0 */
1077
+
<4 RK_PA1 6 &pcfg_pull_none>;
1078
+
};
1079
+
1080
+
/omit-if-no-ref/
1081
+
flexbus0m0_d15: flexbus0m0-d15 {
1082
+
rockchip,pins =
1083
+
/* flexbus0_d15_m0 */
1084
+
<3 RK_PD7 6 &pcfg_pull_none>;
1085
+
};
1086
+
1087
+
/omit-if-no-ref/
1088
+
flexbus0m1_csn: flexbus0m1-csn {
1089
+
rockchip,pins =
1090
+
/* flexbus0_csn_m1 */
1091
+
<4 RK_PA1 8 &pcfg_pull_none>;
1092
+
};
1093
+
1094
+
/omit-if-no-ref/
1095
+
flexbus0m1_d13: flexbus0m1-d13 {
1096
+
rockchip,pins =
1097
+
/* flexbus0_d13_m1 */
1098
+
<4 RK_PA4 4 &pcfg_pull_none>;
1099
+
};
1100
+
1101
+
/omit-if-no-ref/
1102
+
flexbus0m1_d14: flexbus0m1-d14 {
1103
+
rockchip,pins =
1104
+
/* flexbus0_d14_m1 */
1105
+
<4 RK_PA6 4 &pcfg_pull_none>;
1106
+
};
1107
+
1108
+
/omit-if-no-ref/
1109
+
flexbus0m1_d15: flexbus0m1-d15 {
1110
+
rockchip,pins =
1111
+
/* flexbus0_d15_m1 */
1112
+
<4 RK_PB5 4 &pcfg_pull_none>;
1113
+
};
1114
+
1115
+
/omit-if-no-ref/
1116
+
flexbus0m2_csn: flexbus0m2-csn {
1117
+
rockchip,pins =
1118
+
/* flexbus0_csn_m2 */
1119
+
<3 RK_PC3 8 &pcfg_pull_none>;
1120
+
};
1121
+
1122
+
/omit-if-no-ref/
1123
+
flexbus0m3_csn: flexbus0m3-csn {
1124
+
rockchip,pins =
1125
+
/* flexbus0_csn_m3 */
1126
+
<3 RK_PD2 8 &pcfg_pull_none>;
1127
+
};
1128
+
1129
+
/omit-if-no-ref/
1130
+
flexbus0m4_csn: flexbus0m4-csn {
1131
+
rockchip,pins =
1132
+
/* flexbus0_csn_m4 */
1133
+
<4 RK_PB4 4 &pcfg_pull_none>;
1134
+
};
1135
+
1136
+
/omit-if-no-ref/
1137
+
flexbus0_clk: flexbus0-clk {
1138
+
rockchip,pins =
1139
+
/* flexbus0_clk */
1140
+
<3 RK_PB6 6 &pcfg_pull_none>;
1141
+
};
1142
+
1143
+
/omit-if-no-ref/
1144
+
flexbus0_d10: flexbus0-d10 {
1145
+
rockchip,pins =
1146
+
/* flexbus0_d10 */
1147
+
<3 RK_PC3 6 &pcfg_pull_none>;
1148
+
};
1149
+
1150
+
/omit-if-no-ref/
1151
+
flexbus0_d11: flexbus0-d11 {
1152
+
rockchip,pins =
1153
+
/* flexbus0_d11 */
1154
+
<3 RK_PD1 6 &pcfg_pull_none>;
1155
+
};
1156
+
1157
+
/omit-if-no-ref/
1158
+
flexbus0_d12: flexbus0-d12 {
1159
+
rockchip,pins =
1160
+
/* flexbus0_d12 */
1161
+
<3 RK_PD2 6 &pcfg_pull_none>;
1162
+
};
1163
+
1164
+
/omit-if-no-ref/
1165
+
flexbus0_d0: flexbus0-d0 {
1166
+
rockchip,pins =
1167
+
/* flexbus0_d0 */
1168
+
<3 RK_PB5 6 &pcfg_pull_none>;
1169
+
};
1170
+
1171
+
/omit-if-no-ref/
1172
+
flexbus0_d1: flexbus0-d1 {
1173
+
rockchip,pins =
1174
+
/* flexbus0_d1 */
1175
+
<3 RK_PB4 6 &pcfg_pull_none>;
1176
+
};
1177
+
1178
+
/omit-if-no-ref/
1179
+
flexbus0_d2: flexbus0-d2 {
1180
+
rockchip,pins =
1181
+
/* flexbus0_d2 */
1182
+
<3 RK_PB3 6 &pcfg_pull_none>;
1183
+
};
1184
+
1185
+
/omit-if-no-ref/
1186
+
flexbus0_d3: flexbus0-d3 {
1187
+
rockchip,pins =
1188
+
/* flexbus0_d3 */
1189
+
<3 RK_PB2 6 &pcfg_pull_none>;
1190
+
};
1191
+
1192
+
/omit-if-no-ref/
1193
+
flexbus0_d4: flexbus0-d4 {
1194
+
rockchip,pins =
1195
+
/* flexbus0_d4 */
1196
+
<3 RK_PB1 6 &pcfg_pull_none>;
1197
+
};
1198
+
1199
+
/omit-if-no-ref/
1200
+
flexbus0_d5: flexbus0-d5 {
1201
+
rockchip,pins =
1202
+
/* flexbus0_d5 */
1203
+
<3 RK_PA7 6 &pcfg_pull_none>;
1204
+
};
1205
+
1206
+
/omit-if-no-ref/
1207
+
flexbus0_d6: flexbus0-d6 {
1208
+
rockchip,pins =
1209
+
/* flexbus0_d6 */
1210
+
<3 RK_PA6 6 &pcfg_pull_none>;
1211
+
};
1212
+
1213
+
/omit-if-no-ref/
1214
+
flexbus0_d7: flexbus0-d7 {
1215
+
rockchip,pins =
1216
+
/* flexbus0_d7 */
1217
+
<3 RK_PA5 6 &pcfg_pull_none>;
1218
+
};
1219
+
1220
+
/omit-if-no-ref/
1221
+
flexbus0_d8: flexbus0-d8 {
1222
+
rockchip,pins =
1223
+
/* flexbus0_d8 */
1224
+
<3 RK_PB0 6 &pcfg_pull_none>;
1225
+
};
1226
+
1227
+
/omit-if-no-ref/
1228
+
flexbus0_d9: flexbus0-d9 {
1229
+
rockchip,pins =
1230
+
/* flexbus0_d9 */
1231
+
<3 RK_PC2 6 &pcfg_pull_none>;
1232
+
};
1233
+
};
1234
+
1235
+
flexbus1 {
1236
+
/omit-if-no-ref/
1237
+
flexbus1m0_csn: flexbus1m0-csn {
1238
+
rockchip,pins =
1239
+
/* flexbus1_csn_m0 */
1240
+
<3 RK_PB7 8 &pcfg_pull_none>;
1241
+
};
1242
+
1243
+
/omit-if-no-ref/
1244
+
flexbus1m0_d12: flexbus1m0-d12 {
1245
+
rockchip,pins =
1246
+
/* flexbus1_d12_m0 */
1247
+
<3 RK_PD7 7 &pcfg_pull_none>;
1248
+
};
1249
+
1250
+
/omit-if-no-ref/
1251
+
flexbus1m0_d13: flexbus1m0-d13 {
1252
+
rockchip,pins =
1253
+
/* flexbus1_d13_m0 */
1254
+
<4 RK_PA1 7 &pcfg_pull_none>;
1255
+
};
1256
+
1257
+
/omit-if-no-ref/
1258
+
flexbus1m0_d14: flexbus1m0-d14 {
1259
+
rockchip,pins =
1260
+
/* flexbus1_d14_m0 */
1261
+
<4 RK_PA0 7 &pcfg_pull_none>;
1262
+
};
1263
+
1264
+
/omit-if-no-ref/
1265
+
flexbus1m0_d15: flexbus1m0-d15 {
1266
+
rockchip,pins =
1267
+
/* flexbus1_d15_m0 */
1268
+
<3 RK_PD2 7 &pcfg_pull_none>;
1269
+
};
1270
+
1271
+
/omit-if-no-ref/
1272
+
flexbus1m1_csn: flexbus1m1-csn {
1273
+
rockchip,pins =
1274
+
/* flexbus1_csn_m1 */
1275
+
<3 RK_PD7 8 &pcfg_pull_none>;
1276
+
};
1277
+
1278
+
/omit-if-no-ref/
1279
+
flexbus1m1_d12: flexbus1m1-d12 {
1280
+
rockchip,pins =
1281
+
/* flexbus1_d12_m1 */
1282
+
<4 RK_PA5 4 &pcfg_pull_none>;
1283
+
};
1284
+
1285
+
/omit-if-no-ref/
1286
+
flexbus1m1_d13: flexbus1m1-d13 {
1287
+
rockchip,pins =
1288
+
/* flexbus1_d13_m1 */
1289
+
<4 RK_PB0 4 &pcfg_pull_none>;
1290
+
};
1291
+
1292
+
/omit-if-no-ref/
1293
+
flexbus1m1_d14: flexbus1m1-d14 {
1294
+
rockchip,pins =
1295
+
/* flexbus1_d14_m1 */
1296
+
<4 RK_PB1 4 &pcfg_pull_none>;
1297
+
};
1298
+
1299
+
/omit-if-no-ref/
1300
+
flexbus1m1_d15: flexbus1m1-d15 {
1301
+
rockchip,pins =
1302
+
/* flexbus1_d15_m1 */
1303
+
<4 RK_PB2 4 &pcfg_pull_none>;
1304
+
};
1305
+
1306
+
/omit-if-no-ref/
1307
+
flexbus1m2_csn: flexbus1m2-csn {
1308
+
rockchip,pins =
1309
+
/* flexbus1_csn_m2 */
1310
+
<3 RK_PD1 8 &pcfg_pull_none>;
1311
+
};
1312
+
1313
+
/omit-if-no-ref/
1314
+
flexbus1m3_csn: flexbus1m3-csn {
1315
+
rockchip,pins =
1316
+
/* flexbus1_csn_m3 */
1317
+
<4 RK_PA0 8 &pcfg_pull_none>;
1318
+
};
1319
+
1320
+
/omit-if-no-ref/
1321
+
flexbus1m4_csn: flexbus1m4-csn {
1322
+
rockchip,pins =
1323
+
/* flexbus1_csn_m4 */
1324
+
<4 RK_PA3 4 &pcfg_pull_none>;
1325
+
};
1326
+
1327
+
/omit-if-no-ref/
1328
+
flexbus1_clk: flexbus1-clk {
1329
+
rockchip,pins =
1330
+
/* flexbus1_clk */
1331
+
<3 RK_PD6 6 &pcfg_pull_none>;
1332
+
};
1333
+
1334
+
/omit-if-no-ref/
1335
+
flexbus1_d10: flexbus1-d10 {
1336
+
rockchip,pins =
1337
+
/* flexbus1_d10 */
1338
+
<3 RK_PB7 6 &pcfg_pull_none>;
1339
+
};
1340
+
1341
+
/omit-if-no-ref/
1342
+
flexbus1_d11: flexbus1-d11 {
1343
+
rockchip,pins =
1344
+
/* flexbus1_d11 */
1345
+
<3 RK_PA4 6 &pcfg_pull_none>;
1346
+
};
1347
+
1348
+
/omit-if-no-ref/
1349
+
flexbus1_d0: flexbus1-d0 {
1350
+
rockchip,pins =
1351
+
/* flexbus1_d0 */
1352
+
<3 RK_PD5 6 &pcfg_pull_none>;
1353
+
};
1354
+
1355
+
/omit-if-no-ref/
1356
+
flexbus1_d1: flexbus1-d1 {
1357
+
rockchip,pins =
1358
+
/* flexbus1_d1 */
1359
+
<3 RK_PD4 6 &pcfg_pull_none>;
1360
+
};
1361
+
1362
+
/omit-if-no-ref/
1363
+
flexbus1_d2: flexbus1-d2 {
1364
+
rockchip,pins =
1365
+
/* flexbus1_d2 */
1366
+
<3 RK_PD3 6 &pcfg_pull_none>;
1367
+
};
1368
+
1369
+
/omit-if-no-ref/
1370
+
flexbus1_d3: flexbus1-d3 {
1371
+
rockchip,pins =
1372
+
/* flexbus1_d3 */
1373
+
<3 RK_PD0 6 &pcfg_pull_none>;
1374
+
};
1375
+
1376
+
/omit-if-no-ref/
1377
+
flexbus1_d4: flexbus1-d4 {
1378
+
rockchip,pins =
1379
+
/* flexbus1_d4 */
1380
+
<3 RK_PC7 6 &pcfg_pull_none>;
1381
+
};
1382
+
1383
+
/omit-if-no-ref/
1384
+
flexbus1_d5: flexbus1-d5 {
1385
+
rockchip,pins =
1386
+
/* flexbus1_d5 */
1387
+
<3 RK_PC6 6 &pcfg_pull_none>;
1388
+
};
1389
+
1390
+
/omit-if-no-ref/
1391
+
flexbus1_d6: flexbus1-d6 {
1392
+
rockchip,pins =
1393
+
/* flexbus1_d6 */
1394
+
<3 RK_PC5 6 &pcfg_pull_none>;
1395
+
};
1396
+
1397
+
/omit-if-no-ref/
1398
+
flexbus1_d7: flexbus1-d7 {
1399
+
rockchip,pins =
1400
+
/* flexbus1_d7 */
1401
+
<3 RK_PC4 6 &pcfg_pull_none>;
1402
+
};
1403
+
1404
+
/omit-if-no-ref/
1405
+
flexbus1_d8: flexbus1-d8 {
1406
+
rockchip,pins =
1407
+
/* flexbus1_d8 */
1408
+
<3 RK_PC1 6 &pcfg_pull_none>;
1409
+
};
1410
+
1411
+
/omit-if-no-ref/
1412
+
flexbus1_d9: flexbus1-d9 {
1413
+
rockchip,pins =
1414
+
/* flexbus1_d9 */
1415
+
<3 RK_PC0 6 &pcfg_pull_none>;
1416
+
};
1417
+
};
1418
+
1419
+
flexbus0_testclk {
1420
+
/omit-if-no-ref/
1421
+
flexbus0_testclk_testclk: flexbus0_testclk-testclk {
1422
+
rockchip,pins =
1423
+
/* flexbus0_testclk_out */
1424
+
<2 RK_PA3 6 &pcfg_pull_none>;
1425
+
};
1426
+
};
1427
+
1428
+
flexbus0_testdata {
1429
+
/omit-if-no-ref/
1430
+
flexbus0_testdata_testdata: flexbus0_testdata-testdata {
1431
+
rockchip,pins =
1432
+
/* flexbus0_testdata_out */
1433
+
<2 RK_PA2 6 &pcfg_pull_none>;
1434
+
};
1435
+
};
1436
+
1437
+
flexbus1_testclk {
1438
+
/omit-if-no-ref/
1439
+
flexbus1_testclk_testclk: flexbus1_testclk-testclk {
1440
+
rockchip,pins =
1441
+
/* flexbus1_testclk_out */
1442
+
<2 RK_PA5 6 &pcfg_pull_none>;
1443
+
};
1444
+
};
1445
+
1446
+
flexbus1_testdata {
1447
+
/omit-if-no-ref/
1448
+
flexbus1_testdata_testdata: flexbus1_testdata-testdata {
1449
+
rockchip,pins =
1450
+
/* flexbus1_testdata_out */
1451
+
<2 RK_PA4 6 &pcfg_pull_none>;
1452
+
};
1453
+
};
1454
+
1455
+
fspi0 {
1456
+
/omit-if-no-ref/
1457
+
fspi0_pins: fspi0-pins {
1458
+
rockchip,pins =
1459
+
/* fspi0_clk */
1460
+
<1 RK_PB1 2 &pcfg_pull_none>,
1461
+
/* fspi0_d0 */
1462
+
<1 RK_PA0 2 &pcfg_pull_none>,
1463
+
/* fspi0_d1 */
1464
+
<1 RK_PA1 2 &pcfg_pull_none>,
1465
+
/* fspi0_d2 */
1466
+
<1 RK_PA2 2 &pcfg_pull_none>,
1467
+
/* fspi0_d3 */
1468
+
<1 RK_PA3 2 &pcfg_pull_none>,
1469
+
/* fspi0_d4 */
1470
+
<1 RK_PA4 2 &pcfg_pull_none>,
1471
+
/* fspi0_d5 */
1472
+
<1 RK_PA5 2 &pcfg_pull_none>,
1473
+
/* fspi0_d6 */
1474
+
<1 RK_PA6 2 &pcfg_pull_none>,
1475
+
/* fspi0_d7 */
1476
+
<1 RK_PA7 2 &pcfg_pull_none>,
1477
+
/* fspi0_dqs */
1478
+
<1 RK_PB2 2 &pcfg_pull_none>;
1479
+
};
1480
+
1481
+
/omit-if-no-ref/
1482
+
fspi0_csn0: fspi0-csn0 {
1483
+
rockchip,pins =
1484
+
/* fspi0_csn0 */
1485
+
<1 RK_PB3 2 &pcfg_pull_none>;
1486
+
};
1487
+
/omit-if-no-ref/
1488
+
fspi0_csn1: fspi0-csn1 {
1489
+
rockchip,pins =
1490
+
/* fspi0_csn1 */
1491
+
<1 RK_PB0 2 &pcfg_pull_none>;
1492
+
};
1493
+
};
1494
+
1495
+
fspi1 {
1496
+
/omit-if-no-ref/
1497
+
fspi1m0_pins: fspi1m0-pins {
1498
+
rockchip,pins =
1499
+
/* fspi1_clk_m0 */
1500
+
<2 RK_PA5 2 &pcfg_pull_none>,
1501
+
/* fspi1_d0_m0 */
1502
+
<2 RK_PA0 2 &pcfg_pull_none>,
1503
+
/* fspi1_d1_m0 */
1504
+
<2 RK_PA1 2 &pcfg_pull_none>,
1505
+
/* fspi1_d2_m0 */
1506
+
<2 RK_PA2 2 &pcfg_pull_none>,
1507
+
/* fspi1_d3_m0 */
1508
+
<2 RK_PA3 2 &pcfg_pull_none>;
1509
+
};
1510
+
1511
+
/omit-if-no-ref/
1512
+
fspi1m0_csn0: fspi1m0-csn0 {
1513
+
rockchip,pins =
1514
+
/* fspi1m0_csn0 */
1515
+
<2 RK_PA4 2 &pcfg_pull_none>;
1516
+
};
1517
+
1518
+
/omit-if-no-ref/
1519
+
fspi1m1_pins: fspi1m1-pins {
1520
+
rockchip,pins =
1521
+
/* fspi1_clk_m1 */
1522
+
<1 RK_PD5 3 &pcfg_pull_none>,
1523
+
/* fspi1_d0_m1 */
1524
+
<1 RK_PC4 3 &pcfg_pull_none>,
1525
+
/* fspi1_d1_m1 */
1526
+
<1 RK_PC5 3 &pcfg_pull_none>,
1527
+
/* fspi1_d2_m1 */
1528
+
<1 RK_PC6 3 &pcfg_pull_none>,
1529
+
/* fspi1_d3_m1 */
1530
+
<1 RK_PC7 3 &pcfg_pull_none>,
1531
+
/* fspi1_d4_m1 */
1532
+
<1 RK_PD0 3 &pcfg_pull_none>,
1533
+
/* fspi1_d5_m1 */
1534
+
<1 RK_PD1 3 &pcfg_pull_none>,
1535
+
/* fspi1_d6_m1 */
1536
+
<1 RK_PD2 3 &pcfg_pull_none>,
1537
+
/* fspi1_d7_m1 */
1538
+
<1 RK_PD3 3 &pcfg_pull_none>,
1539
+
/* fspi1_dqs_m1 */
1540
+
<1 RK_PD4 3 &pcfg_pull_none>;
1541
+
};
1542
+
1543
+
/omit-if-no-ref/
1544
+
fspi1m1_csn0: fspi1m1-csn0 {
1545
+
rockchip,pins =
1546
+
/* fspi1m1_csn0 */
1547
+
<1 RK_PC3 3 &pcfg_pull_none>;
1548
+
};
1549
+
/omit-if-no-ref/
1550
+
fspi1m1_csn1: fspi1m1-csn1 {
1551
+
rockchip,pins =
1552
+
/* fspi1m1_csn1 */
1553
+
<1 RK_PC2 3 &pcfg_pull_none>;
1554
+
};
1555
+
};
1556
+
1557
+
fspi0_testclk {
1558
+
/omit-if-no-ref/
1559
+
fspi0_testclk_test: fspi0_testclk-test {
1560
+
rockchip,pins =
1561
+
/* fspi0_testclk_out */
1562
+
<1 RK_PB0 6 &pcfg_pull_none>;
1563
+
};
1564
+
};
1565
+
1566
+
fspi0_testdata {
1567
+
/omit-if-no-ref/
1568
+
fspi0_testdata_test: fspi0_testdata-test {
1569
+
rockchip,pins =
1570
+
/* fspi0_testdata_out */
1571
+
<1 RK_PB7 6 &pcfg_pull_none>;
1572
+
};
1573
+
};
1574
+
1575
+
fspi1_testclk {
1576
+
/omit-if-no-ref/
1577
+
fspi1_testclkm1_test: fspi1_testclkm1-test {
1578
+
rockchip,pins =
1579
+
/* fspi1_testclk_out_m1 */
1580
+
<1 RK_PC1 7 &pcfg_pull_none>;
1581
+
};
1582
+
};
1583
+
1584
+
fspi1_testdata {
1585
+
/omit-if-no-ref/
1586
+
fspi1_testdatam1_test: fspi1_testdatam1-test {
1587
+
rockchip,pins =
1588
+
/* fspi1_testdata_out_m1 */
1589
+
<1 RK_PB7 7 &pcfg_pull_none>;
1590
+
};
1591
+
};
1592
+
1593
+
gpu {
1594
+
/omit-if-no-ref/
1595
+
gpu_pins: gpu-pins {
1596
+
rockchip,pins =
1597
+
/* gpu_avs */
1598
+
<0 RK_PD3 11 &pcfg_pull_none>;
1599
+
};
1600
+
};
1601
+
1602
+
hdmi_tx {
1603
+
/omit-if-no-ref/
1604
+
hdmi_txm0_pins: hdmi_txm0-pins {
1605
+
rockchip,pins =
1606
+
/* hdmi_tx_cec_m0 */
1607
+
<4 RK_PC0 9 &pcfg_pull_none>,
1608
+
/* hdmi_tx_hpdin_m0 */
1609
+
<4 RK_PC1 9 &pcfg_pull_none>;
1610
+
};
1611
+
1612
+
/omit-if-no-ref/
1613
+
hdmi_txm1_pins: hdmi_txm1-pins {
1614
+
rockchip,pins =
1615
+
/* hdmi_tx_cec_m1 */
1616
+
<0 RK_PC3 9 &pcfg_pull_none>,
1617
+
/* hdmi_tx_hpdin_m1 */
1618
+
<0 RK_PB6 9 &pcfg_pull_none>;
1619
+
};
1620
+
1621
+
/omit-if-no-ref/
1622
+
hdmi_tx_scl: hdmi-tx-scl {
1623
+
rockchip,pins =
1624
+
/* hdmi_tx_scl */
1625
+
<4 RK_PC2 9 &pcfg_pull_none>;
1626
+
};
1627
+
/omit-if-no-ref/
1628
+
hdmi_tx_sda: hdmi-tx-sda {
1629
+
rockchip,pins =
1630
+
/* hdmi_tx_sda */
1631
+
<4 RK_PC3 9 &pcfg_pull_none>;
1632
+
};
1633
+
};
1634
+
1635
+
i2c0 {
1636
+
/omit-if-no-ref/
1637
+
i2c0m0_xfer: i2c0m0-xfer {
1638
+
rockchip,pins =
1639
+
/* i2c0_scl_m0 */
1640
+
<0 RK_PB0 11 &pcfg_pull_none_smt>,
1641
+
/* i2c0_sda_m0 */
1642
+
<0 RK_PB1 11 &pcfg_pull_none_smt>;
1643
+
};
1644
+
1645
+
/omit-if-no-ref/
1646
+
i2c0m1_xfer: i2c0m1-xfer {
1647
+
rockchip,pins =
1648
+
/* i2c0_scl_m1 */
1649
+
<0 RK_PC1 9 &pcfg_pull_none_smt>,
1650
+
/* i2c0_sda_m1 */
1651
+
<0 RK_PC2 9 &pcfg_pull_none_smt>;
1652
+
};
1653
+
};
1654
+
1655
+
i2c1 {
1656
+
/omit-if-no-ref/
1657
+
i2c1m0_xfer: i2c1m0-xfer {
1658
+
rockchip,pins =
1659
+
/* i2c1_scl_m0 */
1660
+
<0 RK_PB2 11 &pcfg_pull_none_smt>,
1661
+
/* i2c1_sda_m0 */
1662
+
<0 RK_PB3 11 &pcfg_pull_none_smt>;
1663
+
};
1664
+
1665
+
/omit-if-no-ref/
1666
+
i2c1m1_xfer: i2c1m1-xfer {
1667
+
rockchip,pins =
1668
+
/* i2c1_scl_m1 */
1669
+
<0 RK_PB4 9 &pcfg_pull_none_smt>,
1670
+
/* i2c1_sda_m1 */
1671
+
<0 RK_PB5 9 &pcfg_pull_none_smt>;
1672
+
};
1673
+
};
1674
+
1675
+
i2c2 {
1676
+
/omit-if-no-ref/
1677
+
i2c2m0_xfer: i2c2m0-xfer {
1678
+
rockchip,pins =
1679
+
/* i2c2_scl_m0 */
1680
+
<0 RK_PB7 9 &pcfg_pull_none_smt>,
1681
+
/* i2c2_sda_m0 */
1682
+
<0 RK_PC0 9 &pcfg_pull_none_smt>;
1683
+
};
1684
+
1685
+
/omit-if-no-ref/
1686
+
i2c2m1_xfer: i2c2m1-xfer {
1687
+
rockchip,pins =
1688
+
/* i2c2_scl_m1 */
1689
+
<1 RK_PA0 10 &pcfg_pull_none_smt>,
1690
+
/* i2c2_sda_m1 */
1691
+
<1 RK_PA1 10 &pcfg_pull_none_smt>;
1692
+
};
1693
+
1694
+
/omit-if-no-ref/
1695
+
i2c2m2_xfer: i2c2m2-xfer {
1696
+
rockchip,pins =
1697
+
/* i2c2_scl_m2 */
1698
+
<4 RK_PA3 11 &pcfg_pull_none_smt>,
1699
+
/* i2c2_sda_m2 */
1700
+
<4 RK_PA5 11 &pcfg_pull_none_smt>;
1701
+
};
1702
+
1703
+
/omit-if-no-ref/
1704
+
i2c2m3_xfer: i2c2m3-xfer {
1705
+
rockchip,pins =
1706
+
/* i2c2_scl_m3 */
1707
+
<4 RK_PC2 11 &pcfg_pull_none_smt>,
1708
+
/* i2c2_sda_m3 */
1709
+
<4 RK_PC3 11 &pcfg_pull_none_smt>;
1710
+
};
1711
+
};
1712
+
1713
+
i2c3 {
1714
+
/omit-if-no-ref/
1715
+
i2c3m0_xfer: i2c3m0-xfer {
1716
+
rockchip,pins =
1717
+
/* i2c3_scl_m0 */
1718
+
<4 RK_PB5 11 &pcfg_pull_none_smt>,
1719
+
/* i2c3_sda_m0 */
1720
+
<4 RK_PB4 11 &pcfg_pull_none_smt>;
1721
+
};
1722
+
1723
+
/omit-if-no-ref/
1724
+
i2c3m1_xfer: i2c3m1-xfer {
1725
+
rockchip,pins =
1726
+
/* i2c3_scl_m1 */
1727
+
<0 RK_PC6 9 &pcfg_pull_none_smt>,
1728
+
/* i2c3_sda_m1 */
1729
+
<0 RK_PC7 9 &pcfg_pull_none_smt>;
1730
+
};
1731
+
1732
+
/omit-if-no-ref/
1733
+
i2c3m2_xfer: i2c3m2-xfer {
1734
+
rockchip,pins =
1735
+
/* i2c3_scl_m2 */
1736
+
<3 RK_PD4 11 &pcfg_pull_none_smt>,
1737
+
/* i2c3_sda_m2 */
1738
+
<3 RK_PD5 11 &pcfg_pull_none_smt>;
1739
+
};
1740
+
1741
+
/omit-if-no-ref/
1742
+
i2c3m3_xfer: i2c3m3-xfer {
1743
+
rockchip,pins =
1744
+
/* i2c3_scl_m3 */
1745
+
<4 RK_PC4 11 &pcfg_pull_none_smt>,
1746
+
/* i2c3_sda_m3 */
1747
+
<4 RK_PC5 11 &pcfg_pull_none_smt>;
1748
+
};
1749
+
};
1750
+
1751
+
i2c4 {
1752
+
/omit-if-no-ref/
1753
+
i2c4m0_xfer: i2c4m0-xfer {
1754
+
rockchip,pins =
1755
+
/* i2c4_scl_m0 */
1756
+
<0 RK_PD2 9 &pcfg_pull_none_smt>,
1757
+
/* i2c4_sda_m0 */
1758
+
<0 RK_PD3 9 &pcfg_pull_none_smt>;
1759
+
};
1760
+
1761
+
/omit-if-no-ref/
1762
+
i2c4m1_xfer: i2c4m1-xfer {
1763
+
rockchip,pins =
1764
+
/* i2c4_scl_m1 */
1765
+
<4 RK_PA4 11 &pcfg_pull_none_smt>,
1766
+
/* i2c4_sda_m1 */
1767
+
<4 RK_PA6 11 &pcfg_pull_none_smt>;
1768
+
};
1769
+
1770
+
/omit-if-no-ref/
1771
+
i2c4m2_xfer: i2c4m2-xfer {
1772
+
rockchip,pins =
1773
+
/* i2c4_scl_m2 */
1774
+
<2 RK_PA6 11 &pcfg_pull_none_smt>,
1775
+
/* i2c4_sda_m2 */
1776
+
<2 RK_PA7 11 &pcfg_pull_none_smt>;
1777
+
};
1778
+
1779
+
/omit-if-no-ref/
1780
+
i2c4m3_xfer: i2c4m3-xfer {
1781
+
rockchip,pins =
1782
+
/* i2c4_scl_m3 */
1783
+
<3 RK_PC0 11 &pcfg_pull_none_smt>,
1784
+
/* i2c4_sda_m3 */
1785
+
<3 RK_PB7 11 &pcfg_pull_none_smt>;
1786
+
};
1787
+
};
1788
+
1789
+
i2c5 {
1790
+
/omit-if-no-ref/
1791
+
i2c5m0_xfer: i2c5m0-xfer {
1792
+
rockchip,pins =
1793
+
/* i2c5_scl_m0 */
1794
+
<2 RK_PA5 11 &pcfg_pull_none_smt>,
1795
+
/* i2c5_sda_m0 */
1796
+
<2 RK_PA4 11 &pcfg_pull_none_smt>;
1797
+
};
1798
+
1799
+
/omit-if-no-ref/
1800
+
i2c5m1_xfer: i2c5m1-xfer {
1801
+
rockchip,pins =
1802
+
/* i2c5_scl_m1 */
1803
+
<1 RK_PD4 10 &pcfg_pull_none_smt>,
1804
+
/* i2c5_sda_m1 */
1805
+
<1 RK_PD5 10 &pcfg_pull_none_smt>;
1806
+
};
1807
+
1808
+
/omit-if-no-ref/
1809
+
i2c5m2_xfer: i2c5m2-xfer {
1810
+
rockchip,pins =
1811
+
/* i2c5_scl_m2 */
1812
+
<2 RK_PC6 11 &pcfg_pull_none_smt>,
1813
+
/* i2c5_sda_m2 */
1814
+
<2 RK_PC7 11 &pcfg_pull_none_smt>;
1815
+
};
1816
+
1817
+
/omit-if-no-ref/
1818
+
i2c5m3_xfer: i2c5m3-xfer {
1819
+
rockchip,pins =
1820
+
/* i2c5_scl_m3 */
1821
+
<3 RK_PC4 11 &pcfg_pull_none_smt>,
1822
+
/* i2c5_sda_m3 */
1823
+
<3 RK_PC1 11 &pcfg_pull_none_smt>;
1824
+
};
1825
+
};
1826
+
1827
+
i2c6 {
1828
+
/omit-if-no-ref/
1829
+
i2c6m0_xfer: i2c6m0-xfer {
1830
+
rockchip,pins =
1831
+
/* i2c6_scl_m0 */
1832
+
<0 RK_PA2 11 &pcfg_pull_none_smt>,
1833
+
/* i2c6_sda_m0 */
1834
+
<0 RK_PA5 11 &pcfg_pull_none_smt>;
1835
+
};
1836
+
1837
+
/omit-if-no-ref/
1838
+
i2c6m1_xfer: i2c6m1-xfer {
1839
+
rockchip,pins =
1840
+
/* i2c6_scl_m1 */
1841
+
<1 RK_PC2 10 &pcfg_pull_none_smt>,
1842
+
/* i2c6_sda_m1 */
1843
+
<1 RK_PC3 10 &pcfg_pull_none_smt>;
1844
+
};
1845
+
1846
+
/omit-if-no-ref/
1847
+
i2c6m2_xfer: i2c6m2-xfer {
1848
+
rockchip,pins =
1849
+
/* i2c6_scl_m2 */
1850
+
<2 RK_PD0 11 &pcfg_pull_none_smt>,
1851
+
/* i2c6_sda_m2 */
1852
+
<2 RK_PD1 11 &pcfg_pull_none_smt>;
1853
+
};
1854
+
1855
+
/omit-if-no-ref/
1856
+
i2c6m3_xfer: i2c6m3-xfer {
1857
+
rockchip,pins =
1858
+
/* i2c6_scl_m3 */
1859
+
<4 RK_PC6 11 &pcfg_pull_none_smt>,
1860
+
/* i2c6_sda_m3 */
1861
+
<4 RK_PC7 11 &pcfg_pull_none_smt>;
1862
+
};
1863
+
};
1864
+
1865
+
i2c7 {
1866
+
/omit-if-no-ref/
1867
+
i2c7m0_xfer: i2c7m0-xfer {
1868
+
rockchip,pins =
1869
+
/* i2c7_scl_m0 */
1870
+
<1 RK_PB0 10 &pcfg_pull_none_smt>,
1871
+
/* i2c7_sda_m0 */
1872
+
<1 RK_PB3 10 &pcfg_pull_none_smt>;
1873
+
};
1874
+
1875
+
/omit-if-no-ref/
1876
+
i2c7m1_xfer: i2c7m1-xfer {
1877
+
rockchip,pins =
1878
+
/* i2c7_scl_m1 */
1879
+
<3 RK_PA0 11 &pcfg_pull_none_smt>,
1880
+
/* i2c7_sda_m1 */
1881
+
<3 RK_PA1 11 &pcfg_pull_none_smt>;
1882
+
};
1883
+
1884
+
/omit-if-no-ref/
1885
+
i2c7m2_xfer: i2c7m2-xfer {
1886
+
rockchip,pins =
1887
+
/* i2c7_scl_m2 */
1888
+
<4 RK_PA0 11 &pcfg_pull_none_smt>,
1889
+
/* i2c7_sda_m2 */
1890
+
<4 RK_PA1 11 &pcfg_pull_none_smt>;
1891
+
};
1892
+
1893
+
/omit-if-no-ref/
1894
+
i2c7m3_xfer: i2c7m3-xfer {
1895
+
rockchip,pins =
1896
+
/* i2c7_scl_m3 */
1897
+
<4 RK_PC0 11 &pcfg_pull_none_smt>,
1898
+
/* i2c7_sda_m3 */
1899
+
<4 RK_PC1 11 &pcfg_pull_none_smt>;
1900
+
};
1901
+
};
1902
+
1903
+
i2c8 {
1904
+
/omit-if-no-ref/
1905
+
i2c8m0_xfer: i2c8m0-xfer {
1906
+
rockchip,pins =
1907
+
/* i2c8_scl_m0 */
1908
+
<2 RK_PA0 11 &pcfg_pull_none_smt>,
1909
+
/* i2c8_sda_m0 */
1910
+
<2 RK_PA1 11 &pcfg_pull_none_smt>;
1911
+
};
1912
+
1913
+
/omit-if-no-ref/
1914
+
i2c8m1_xfer: i2c8m1-xfer {
1915
+
rockchip,pins =
1916
+
/* i2c8_scl_m1 */
1917
+
<1 RK_PC6 10 &pcfg_pull_none_smt>,
1918
+
/* i2c8_sda_m1 */
1919
+
<1 RK_PC7 10 &pcfg_pull_none_smt>;
1920
+
};
1921
+
1922
+
/omit-if-no-ref/
1923
+
i2c8m2_xfer: i2c8m2-xfer {
1924
+
rockchip,pins =
1925
+
/* i2c8_scl_m2 */
1926
+
<2 RK_PB6 11 &pcfg_pull_none_smt>,
1927
+
/* i2c8_sda_m2 */
1928
+
<2 RK_PB7 11 &pcfg_pull_none_smt>;
1929
+
};
1930
+
1931
+
/omit-if-no-ref/
1932
+
i2c8m3_xfer: i2c8m3-xfer {
1933
+
rockchip,pins =
1934
+
/* i2c8_scl_m3 */
1935
+
<3 RK_PB3 11 &pcfg_pull_none_smt>,
1936
+
/* i2c8_sda_m3 */
1937
+
<3 RK_PB2 11 &pcfg_pull_none_smt>;
1938
+
};
1939
+
};
1940
+
1941
+
i2c9 {
1942
+
/omit-if-no-ref/
1943
+
i2c9m0_xfer: i2c9m0-xfer {
1944
+
rockchip,pins =
1945
+
/* i2c9_scl_m0 */
1946
+
<1 RK_PA5 10 &pcfg_pull_none_smt>,
1947
+
/* i2c9_sda_m0 */
1948
+
<1 RK_PA6 10 &pcfg_pull_none_smt>;
1949
+
};
1950
+
1951
+
/omit-if-no-ref/
1952
+
i2c9m1_xfer: i2c9m1-xfer {
1953
+
rockchip,pins =
1954
+
/* i2c9_scl_m1 */
1955
+
<1 RK_PB5 10 &pcfg_pull_none_smt>,
1956
+
/* i2c9_sda_m1 */
1957
+
<1 RK_PB4 10 &pcfg_pull_none_smt>;
1958
+
};
1959
+
1960
+
/omit-if-no-ref/
1961
+
i2c9m2_xfer: i2c9m2-xfer {
1962
+
rockchip,pins =
1963
+
/* i2c9_scl_m2 */
1964
+
<2 RK_PD5 11 &pcfg_pull_none_smt>,
1965
+
/* i2c9_sda_m2 */
1966
+
<2 RK_PD4 11 &pcfg_pull_none_smt>;
1967
+
};
1968
+
1969
+
/omit-if-no-ref/
1970
+
i2c9m3_xfer: i2c9m3-xfer {
1971
+
rockchip,pins =
1972
+
/* i2c9_scl_m3 */
1973
+
<3 RK_PC2 11 &pcfg_pull_none_smt>,
1974
+
/* i2c9_sda_m3 */
1975
+
<3 RK_PC3 11 &pcfg_pull_none_smt>;
1976
+
};
1977
+
};
1978
+
1979
+
i3c0 {
1980
+
/omit-if-no-ref/
1981
+
i3c0m0_xfer: i3c0m0-xfer {
1982
+
rockchip,pins =
1983
+
/* i3c0_scl_m0 */
1984
+
<0 RK_PC1 11 &pcfg_pull_none_smt>,
1985
+
/* i3c0_sda_m0 */
1986
+
<0 RK_PC2 11 &pcfg_pull_none_smt>;
1987
+
};
1988
+
1989
+
/omit-if-no-ref/
1990
+
i3c0m1_xfer: i3c0m1-xfer {
1991
+
rockchip,pins =
1992
+
/* i3c0_scl_m1 */
1993
+
<1 RK_PD2 10 &pcfg_pull_none_smt>,
1994
+
/* i3c0_sda_m1 */
1995
+
<1 RK_PD3 10 &pcfg_pull_none_smt>;
1996
+
};
1997
+
};
1998
+
1999
+
i3c1 {
2000
+
/omit-if-no-ref/
2001
+
i3c1m0_xfer: i3c1m0-xfer {
2002
+
rockchip,pins =
2003
+
/* i3c1_scl_m0 */
2004
+
<2 RK_PD2 12 &pcfg_pull_none_smt>,
2005
+
/* i3c1_sda_m0 */
2006
+
<2 RK_PD3 12 &pcfg_pull_none_smt>;
2007
+
};
2008
+
2009
+
/omit-if-no-ref/
2010
+
i3c1m1_xfer: i3c1m1-xfer {
2011
+
rockchip,pins =
2012
+
/* i3c1_scl_m1 */
2013
+
<2 RK_PA2 14 &pcfg_pull_none_smt>,
2014
+
/* i3c1_sda_m1 */
2015
+
<2 RK_PA3 14 &pcfg_pull_none_smt>;
2016
+
};
2017
+
2018
+
/omit-if-no-ref/
2019
+
i3c1m2_xfer: i3c1m2-xfer {
2020
+
rockchip,pins =
2021
+
/* i3c1_scl_m2 */
2022
+
<3 RK_PD3 11 &pcfg_pull_none_smt>,
2023
+
/* i3c1_sda_m2 */
2024
+
<3 RK_PD2 11 &pcfg_pull_none_smt>;
2025
+
};
2026
+
};
2027
+
2028
+
i3c0_sda {
2029
+
/omit-if-no-ref/
2030
+
i3c0_sdam0_pu: i3c0_sdam0-pu {
2031
+
rockchip,pins =
2032
+
/* i3c0_sda_pu_m0 */
2033
+
<0 RK_PC5 11 &pcfg_pull_none>;
2034
+
};
2035
+
2036
+
/omit-if-no-ref/
2037
+
i3c0_sdam1_pu: i3c0_sdam1-pu {
2038
+
rockchip,pins =
2039
+
/* i3c0_sda_pu_m1 */
2040
+
<1 RK_PD1 10 &pcfg_pull_none>;
2041
+
};
2042
+
};
2043
+
2044
+
i3c1_sda {
2045
+
/omit-if-no-ref/
2046
+
i3c1_sdam0_pu: i3c1_sdam0-pu {
2047
+
rockchip,pins =
2048
+
/* i3c1_sda_pu_m0 */
2049
+
<2 RK_PD6 12 &pcfg_pull_none>;
2050
+
};
2051
+
2052
+
/omit-if-no-ref/
2053
+
i3c1_sdam1_pu: i3c1_sdam1-pu {
2054
+
rockchip,pins =
2055
+
/* i3c1_sda_pu_m1 */
2056
+
<2 RK_PA5 14 &pcfg_pull_none>;
2057
+
};
2058
+
2059
+
/omit-if-no-ref/
2060
+
i3c1_sdam2_pu: i3c1_sdam2-pu {
2061
+
rockchip,pins =
2062
+
/* i3c1_sda_pu_m2 */
2063
+
<3 RK_PD1 11 &pcfg_pull_none>;
2064
+
};
2065
+
};
2066
+
2067
+
isp_flash {
2068
+
/omit-if-no-ref/
2069
+
isp_flashm0_pins: isp_flashm0-pins {
2070
+
rockchip,pins =
2071
+
/* isp_flash_trigout_m0 */
2072
+
<2 RK_PD5 1 &pcfg_pull_none>;
2073
+
};
2074
+
2075
+
/omit-if-no-ref/
2076
+
isp_flashm1_pins: isp_flashm1-pins {
2077
+
rockchip,pins =
2078
+
/* isp_flash_trigout_m1 */
2079
+
<4 RK_PC5 1 &pcfg_pull_none>;
2080
+
};
2081
+
};
2082
+
2083
+
isp_prelight {
2084
+
/omit-if-no-ref/
2085
+
isp_prelightm0_pins: isp_prelightm0-pins {
2086
+
rockchip,pins =
2087
+
/* isp_prelight_trig_m0 */
2088
+
<2 RK_PD4 1 &pcfg_pull_none>;
2089
+
};
2090
+
2091
+
/omit-if-no-ref/
2092
+
isp_prelightm1_pins: isp_prelightm1-pins {
2093
+
rockchip,pins =
2094
+
/* isp_prelight_trig_m1 */
2095
+
<4 RK_PC4 1 &pcfg_pull_none>;
2096
+
};
2097
+
};
2098
+
2099
+
jtag {
2100
+
/omit-if-no-ref/
2101
+
jtagm0_pins: jtagm0-pins {
2102
+
rockchip,pins =
2103
+
/* jtag_tck_m0 */
2104
+
<2 RK_PA2 9 &pcfg_pull_none>,
2105
+
/* jtag_tms_m0 */
2106
+
<2 RK_PA3 9 &pcfg_pull_none>;
2107
+
};
2108
+
2109
+
/omit-if-no-ref/
2110
+
jtagm1_pins: jtagm1-pins {
2111
+
rockchip,pins =
2112
+
/* jtag_tck_m1 */
2113
+
<0 RK_PD4 10 &pcfg_pull_none>,
2114
+
/* jtag_tms_m1 */
2115
+
<0 RK_PD5 10 &pcfg_pull_none>;
2116
+
};
2117
+
};
2118
+
2119
+
mipi {
2120
+
/omit-if-no-ref/
2121
+
mipim0_pins: mipim0-pins {
2122
+
rockchip,pins =
2123
+
/* mipi_te_m0 */
2124
+
<4 RK_PB2 11 &pcfg_pull_none>;
2125
+
};
2126
+
2127
+
/omit-if-no-ref/
2128
+
mipim1_pins: mipim1-pins {
2129
+
rockchip,pins =
2130
+
/* mipi_te_m1 */
2131
+
<3 RK_PA2 12 &pcfg_pull_none>;
2132
+
};
2133
+
2134
+
/omit-if-no-ref/
2135
+
mipim2_pins: mipim2-pins {
2136
+
rockchip,pins =
2137
+
/* mipi_te_m2 */
2138
+
<4 RK_PA0 12 &pcfg_pull_none>;
2139
+
};
2140
+
2141
+
/omit-if-no-ref/
2142
+
mipim3_pins: mipim3-pins {
2143
+
rockchip,pins =
2144
+
/* mipi_te_m3 */
2145
+
<1 RK_PB3 11 &pcfg_pull_none>;
2146
+
};
2147
+
};
2148
+
2149
+
npu {
2150
+
/omit-if-no-ref/
2151
+
npu_pins: npu-pins {
2152
+
rockchip,pins =
2153
+
/* npu_avs */
2154
+
<0 RK_PB7 11 &pcfg_pull_none>;
2155
+
};
2156
+
};
2157
+
2158
+
pcie0 {
2159
+
/omit-if-no-ref/
2160
+
pcie0m0_pins: pcie0m0-pins {
2161
+
rockchip,pins =
2162
+
/* pcie21_port0_clkreq_m0 */
2163
+
<2 RK_PB2 11 &pcfg_pull_up>;
2164
+
};
2165
+
2166
+
/omit-if-no-ref/
2167
+
pcie0m1_pins: pcie0m1-pins {
2168
+
rockchip,pins =
2169
+
/* pcie0_clkreq_m1 */
2170
+
<1 RK_PB6 12 &pcfg_pull_up>;
2171
+
};
2172
+
2173
+
/omit-if-no-ref/
2174
+
pcie0m2_pins: pcie0m2-pins {
2175
+
rockchip,pins =
2176
+
/* pcie0_clkreq_m2 */
2177
+
<4 RK_PB5 12 &pcfg_pull_up>;
2178
+
};
2179
+
2180
+
/omit-if-no-ref/
2181
+
pcie0m3_pins: pcie0m3-pins {
2182
+
rockchip,pins =
2183
+
/* pcie0_clkreq_m3 */
2184
+
<4 RK_PC6 9 &pcfg_pull_up>;
2185
+
};
2186
+
2187
+
/omit-if-no-ref/
2188
+
pcie0_buttonrst: pcie21-port0-buttonrst {
2189
+
rockchip,pins =
2190
+
/* pcie0_buttonrst */
2191
+
<1 RK_PC4 12 &pcfg_pull_none>;
2192
+
};
2193
+
};
2194
+
2195
+
pcie1 {
2196
+
/omit-if-no-ref/
2197
+
pcie1m0_pins: pcie1m0-pins {
2198
+
rockchip,pins =
2199
+
/* pcie1_clkreq_m0 */
2200
+
<2 RK_PB3 11 &pcfg_pull_up>;
2201
+
};
2202
+
2203
+
/omit-if-no-ref/
2204
+
pcie1m1_pins: pcie1m1-pins {
2205
+
rockchip,pins =
2206
+
/* pcie1_clkreq_m1 */
2207
+
<1 RK_PB4 12 &pcfg_pull_up>;
2208
+
};
2209
+
2210
+
/omit-if-no-ref/
2211
+
pcie1m2_pins: pcie1m2-pins {
2212
+
rockchip,pins =
2213
+
/* pcie1_clkreq_m2 */
2214
+
<4 RK_PA5 12 &pcfg_pull_up>;
2215
+
};
2216
+
2217
+
/omit-if-no-ref/
2218
+
pcie1m3_pins: pcie1m3-pins {
2219
+
rockchip,pins =
2220
+
/* pcie1_clkreq_m3 */
2221
+
<4 RK_PC1 10 &pcfg_pull_up>;
2222
+
};
2223
+
2224
+
/omit-if-no-ref/
2225
+
pcie1_buttonrst: pcie21-port1-buttonrst {
2226
+
rockchip,pins =
2227
+
/* pcie1_buttonrst */
2228
+
<1 RK_PC5 12 &pcfg_pull_none>;
2229
+
};
2230
+
};
2231
+
2232
+
pdm0 {
2233
+
/omit-if-no-ref/
2234
+
pdm0m0_clk0: pdm0m0-clk0 {
2235
+
rockchip,pins =
2236
+
/* pdm0_clk0_m0 */
2237
+
<0 RK_PC4 3 &pcfg_pull_none>;
2238
+
};
2239
+
2240
+
/omit-if-no-ref/
2241
+
pdm0m0_clk1: pdm0m0-clk1 {
2242
+
rockchip,pins =
2243
+
/* pdm0_clk1_m0 */
2244
+
<0 RK_PC3 3 &pcfg_pull_none>;
2245
+
};
2246
+
2247
+
/omit-if-no-ref/
2248
+
pdm0m0_sdi0: pdm0m0-sdi0 {
2249
+
rockchip,pins =
2250
+
/* pdm0_sdi0_m0 */
2251
+
<0 RK_PD0 3 &pcfg_pull_none>;
2252
+
};
2253
+
2254
+
/omit-if-no-ref/
2255
+
pdm0m0_sdi1: pdm0m0-sdi1 {
2256
+
rockchip,pins =
2257
+
/* pdm0_sdi1_m0 */
2258
+
<0 RK_PD1 3 &pcfg_pull_none>;
2259
+
};
2260
+
2261
+
/omit-if-no-ref/
2262
+
pdm0m0_sdi2: pdm0m0-sdi2 {
2263
+
rockchip,pins =
2264
+
/* pdm0_sdi2_m0 */
2265
+
<0 RK_PD2 3 &pcfg_pull_none>;
2266
+
};
2267
+
2268
+
/omit-if-no-ref/
2269
+
pdm0m0_sdi3: pdm0m0-sdi3 {
2270
+
rockchip,pins =
2271
+
/* pdm0_sdi3_m0 */
2272
+
<0 RK_PD3 3 &pcfg_pull_none>;
2273
+
};
2274
+
2275
+
/omit-if-no-ref/
2276
+
pdm0m1_clk0: pdm0m1-clk0 {
2277
+
rockchip,pins =
2278
+
/* pdm0_clk0_m1 */
2279
+
<1 RK_PB1 5 &pcfg_pull_none>;
2280
+
};
2281
+
2282
+
/omit-if-no-ref/
2283
+
pdm0m1_clk1: pdm0m1-clk1 {
2284
+
rockchip,pins =
2285
+
/* pdm0_clk1_m1 */
2286
+
<1 RK_PA6 5 &pcfg_pull_none>;
2287
+
};
2288
+
2289
+
/omit-if-no-ref/
2290
+
pdm0m1_sdi0: pdm0m1-sdi0 {
2291
+
rockchip,pins =
2292
+
/* pdm0_sdi0_m1 */
2293
+
<1 RK_PB2 5 &pcfg_pull_none>;
2294
+
};
2295
+
2296
+
/omit-if-no-ref/
2297
+
pdm0m1_sdi1: pdm0m1-sdi1 {
2298
+
rockchip,pins =
2299
+
/* pdm0_sdi1_m1 */
2300
+
<1 RK_PA3 5 &pcfg_pull_none>;
2301
+
};
2302
+
2303
+
/omit-if-no-ref/
2304
+
pdm0m1_sdi2: pdm0m1-sdi2 {
2305
+
rockchip,pins =
2306
+
/* pdm0_sdi2_m1 */
2307
+
<1 RK_PA5 5 &pcfg_pull_none>;
2308
+
};
2309
+
2310
+
/omit-if-no-ref/
2311
+
pdm0m1_sdi3: pdm0m1-sdi3 {
2312
+
rockchip,pins =
2313
+
/* pdm0_sdi3_m1 */
2314
+
<1 RK_PA2 5 &pcfg_pull_none>;
2315
+
};
2316
+
2317
+
/omit-if-no-ref/
2318
+
pdm0m2_clk0: pdm0m2-clk0 {
2319
+
rockchip,pins =
2320
+
/* pdm0_clk0_m2 */
2321
+
<1 RK_PC1 5 &pcfg_pull_none>;
2322
+
};
2323
+
2324
+
/omit-if-no-ref/
2325
+
pdm0m2_clk1: pdm0m2-clk1 {
2326
+
rockchip,pins =
2327
+
/* pdm0_clk1_m2 */
2328
+
<1 RK_PD5 5 &pcfg_pull_none>;
2329
+
};
2330
+
2331
+
/omit-if-no-ref/
2332
+
pdm0m2_sdi0: pdm0m2-sdi0 {
2333
+
rockchip,pins =
2334
+
/* pdm0_sdi0_m2 */
2335
+
<1 RK_PC6 5 &pcfg_pull_none>;
2336
+
};
2337
+
2338
+
/omit-if-no-ref/
2339
+
pdm0m2_sdi1: pdm0m2-sdi1 {
2340
+
rockchip,pins =
2341
+
/* pdm0_sdi1_m2 */
2342
+
<1 RK_PC7 5 &pcfg_pull_none>;
2343
+
};
2344
+
2345
+
/omit-if-no-ref/
2346
+
pdm0m2_sdi2: pdm0m2-sdi2 {
2347
+
rockchip,pins =
2348
+
/* pdm0_sdi2_m2 */
2349
+
<1 RK_PC0 5 &pcfg_pull_none>;
2350
+
};
2351
+
2352
+
/omit-if-no-ref/
2353
+
pdm0m2_sdi3: pdm0m2-sdi3 {
2354
+
rockchip,pins =
2355
+
/* pdm0_sdi3_m2 */
2356
+
<1 RK_PD4 5 &pcfg_pull_none>;
2357
+
};
2358
+
2359
+
/omit-if-no-ref/
2360
+
pdm0m3_clk0: pdm0m3-clk0 {
2361
+
rockchip,pins =
2362
+
/* pdm0_clk0_m3 */
2363
+
<2 RK_PB5 5 &pcfg_pull_none>;
2364
+
};
2365
+
2366
+
/omit-if-no-ref/
2367
+
pdm0m3_clk1: pdm0m3-clk1 {
2368
+
rockchip,pins =
2369
+
/* pdm0_clk1_m3 */
2370
+
<2 RK_PB3 5 &pcfg_pull_none>;
2371
+
};
2372
+
2373
+
/omit-if-no-ref/
2374
+
pdm0m3_sdi0: pdm0m3-sdi0 {
2375
+
rockchip,pins =
2376
+
/* pdm0_sdi0_m3 */
2377
+
<2 RK_PB4 5 &pcfg_pull_none>;
2378
+
};
2379
+
2380
+
/omit-if-no-ref/
2381
+
pdm0m3_sdi1: pdm0m3-sdi1 {
2382
+
rockchip,pins =
2383
+
/* pdm0_sdi1_m3 */
2384
+
<2 RK_PB2 5 &pcfg_pull_none>;
2385
+
};
2386
+
2387
+
/omit-if-no-ref/
2388
+
pdm0m3_sdi2: pdm0m3-sdi2 {
2389
+
rockchip,pins =
2390
+
/* pdm0_sdi2_m3 */
2391
+
<2 RK_PB1 5 &pcfg_pull_none>;
2392
+
};
2393
+
2394
+
/omit-if-no-ref/
2395
+
pdm0m3_sdi3: pdm0m3-sdi3 {
2396
+
rockchip,pins =
2397
+
/* pdm0_sdi3_m3 */
2398
+
<2 RK_PB0 5 &pcfg_pull_none>;
2399
+
};
2400
+
};
2401
+
2402
+
pdm1 {
2403
+
/omit-if-no-ref/
2404
+
pdm1m0_clk0: pdm1m0-clk0 {
2405
+
rockchip,pins =
2406
+
/* pdm1_clk0_m0 */
2407
+
<2 RK_PC5 5 &pcfg_pull_none>;
2408
+
};
2409
+
2410
+
/omit-if-no-ref/
2411
+
pdm1m0_clk1: pdm1m0-clk1 {
2412
+
rockchip,pins =
2413
+
/* pdm1_clk1_m0 */
2414
+
<2 RK_PC1 5 &pcfg_pull_none>;
2415
+
};
2416
+
2417
+
/omit-if-no-ref/
2418
+
pdm1m0_sdi0: pdm1m0-sdi0 {
2419
+
rockchip,pins =
2420
+
/* pdm1_sdi0_m0 */
2421
+
<2 RK_PC4 5 &pcfg_pull_none>;
2422
+
};
2423
+
2424
+
/omit-if-no-ref/
2425
+
pdm1m0_sdi1: pdm1m0-sdi1 {
2426
+
rockchip,pins =
2427
+
/* pdm1_sdi1_m0 */
2428
+
<2 RK_PC0 5 &pcfg_pull_none>;
2429
+
};
2430
+
2431
+
/omit-if-no-ref/
2432
+
pdm1m0_sdi2: pdm1m0-sdi2 {
2433
+
rockchip,pins =
2434
+
/* pdm1_sdi2_m0 */
2435
+
<2 RK_PC2 5 &pcfg_pull_none>;
2436
+
};
2437
+
2438
+
/omit-if-no-ref/
2439
+
pdm1m0_sdi3: pdm1m0-sdi3 {
2440
+
rockchip,pins =
2441
+
/* pdm1_sdi3_m0 */
2442
+
<2 RK_PC3 5 &pcfg_pull_none>;
2443
+
};
2444
+
2445
+
/omit-if-no-ref/
2446
+
pdm1m1_clk0: pdm1m1-clk0 {
2447
+
rockchip,pins =
2448
+
/* pdm1_clk0_m1 */
2449
+
<4 RK_PA6 3 &pcfg_pull_none>;
2450
+
};
2451
+
2452
+
/omit-if-no-ref/
2453
+
pdm1m1_clk1: pdm1m1-clk1 {
2454
+
rockchip,pins =
2455
+
/* pdm1_clk1_m1 */
2456
+
<4 RK_PB0 3 &pcfg_pull_none>;
2457
+
};
2458
+
2459
+
/omit-if-no-ref/
2460
+
pdm1m1_sdi0: pdm1m1-sdi0 {
2461
+
rockchip,pins =
2462
+
/* pdm1_sdi0_m1 */
2463
+
<4 RK_PB3 3 &pcfg_pull_none>;
2464
+
};
2465
+
2466
+
/omit-if-no-ref/
2467
+
pdm1m1_sdi1: pdm1m1-sdi1 {
2468
+
rockchip,pins =
2469
+
/* pdm1_sdi1_m1 */
2470
+
<4 RK_PB2 3 &pcfg_pull_none>;
2471
+
};
2472
+
2473
+
/omit-if-no-ref/
2474
+
pdm1m1_sdi2: pdm1m1-sdi2 {
2475
+
rockchip,pins =
2476
+
/* pdm1_sdi2_m1 */
2477
+
<4 RK_PB1 3 &pcfg_pull_none>;
2478
+
};
2479
+
2480
+
/omit-if-no-ref/
2481
+
pdm1m1_sdi3: pdm1m1-sdi3 {
2482
+
rockchip,pins =
2483
+
/* pdm1_sdi3_m1 */
2484
+
<4 RK_PA4 3 &pcfg_pull_none>;
2485
+
};
2486
+
2487
+
/omit-if-no-ref/
2488
+
pdm1m2_clk0: pdm1m2-clk0 {
2489
+
rockchip,pins =
2490
+
/* pdm1_clk0_m2 */
2491
+
<3 RK_PB1 4 &pcfg_pull_none>;
2492
+
};
2493
+
2494
+
/omit-if-no-ref/
2495
+
pdm1m2_clk1: pdm1m2-clk1 {
2496
+
rockchip,pins =
2497
+
/* pdm1_clk1_m2 */
2498
+
<3 RK_PA7 4 &pcfg_pull_none>;
2499
+
};
2500
+
2501
+
/omit-if-no-ref/
2502
+
pdm1m2_sdi0: pdm1m2-sdi0 {
2503
+
rockchip,pins =
2504
+
/* pdm1_sdi0_m2 */
2505
+
<3 RK_PB3 4 &pcfg_pull_none>;
2506
+
};
2507
+
2508
+
/omit-if-no-ref/
2509
+
pdm1m2_sdi1: pdm1m2-sdi1 {
2510
+
rockchip,pins =
2511
+
/* pdm1_sdi1_m2 */
2512
+
<3 RK_PB2 4 &pcfg_pull_none>;
2513
+
};
2514
+
2515
+
/omit-if-no-ref/
2516
+
pdm1m2_sdi2: pdm1m2-sdi2 {
2517
+
rockchip,pins =
2518
+
/* pdm1_sdi2_m2 */
2519
+
<3 RK_PA6 4 &pcfg_pull_none>;
2520
+
};
2521
+
2522
+
/omit-if-no-ref/
2523
+
pdm1m2_sdi3: pdm1m2-sdi3 {
2524
+
rockchip,pins =
2525
+
/* pdm1_sdi3_m2 */
2526
+
<3 RK_PA5 4 &pcfg_pull_none>;
2527
+
};
2528
+
};
2529
+
2530
+
pmu_debug_test {
2531
+
/omit-if-no-ref/
2532
+
pmu_debug_test_pins: pmu_debug_test-pins {
2533
+
rockchip,pins =
2534
+
/* pmu_debug_test_out */
2535
+
<0 RK_PB0 2 &pcfg_pull_none>;
2536
+
};
2537
+
};
2538
+
2539
+
pwm0 {
2540
+
/omit-if-no-ref/
2541
+
pwm0m0_ch0: pwm0m0-ch0 {
2542
+
rockchip,pins =
2543
+
/* pwm0_ch0_m0 */
2544
+
<0 RK_PC4 12 &pcfg_pull_none_drv_level_2>;
2545
+
};
2546
+
2547
+
/omit-if-no-ref/
2548
+
pwm0m0_ch1: pwm0m0-ch1 {
2549
+
rockchip,pins =
2550
+
/* pwm0_ch1_m0 */
2551
+
<0 RK_PC3 12 &pcfg_pull_none_drv_level_2>;
2552
+
};
2553
+
2554
+
/omit-if-no-ref/
2555
+
pwm0m1_ch0: pwm0m1-ch0 {
2556
+
rockchip,pins =
2557
+
/* pwm0_ch0_m1 */
2558
+
<1 RK_PC0 13 &pcfg_pull_none_drv_level_2>;
2559
+
};
2560
+
2561
+
/omit-if-no-ref/
2562
+
pwm0m1_ch1: pwm0m1-ch1 {
2563
+
rockchip,pins =
2564
+
/* pwm0_ch1_m1 */
2565
+
<4 RK_PC1 14 &pcfg_pull_none_drv_level_2>;
2566
+
};
2567
+
2568
+
/omit-if-no-ref/
2569
+
pwm0m2_ch0: pwm0m2-ch0 {
2570
+
rockchip,pins =
2571
+
/* pwm0_ch0_m2 */
2572
+
<2 RK_PC3 13 &pcfg_pull_none_drv_level_2>;
2573
+
};
2574
+
2575
+
/omit-if-no-ref/
2576
+
pwm0m2_ch1: pwm0m2-ch1 {
2577
+
rockchip,pins =
2578
+
/* pwm0_ch1_m2 */
2579
+
<2 RK_PC7 13 &pcfg_pull_none_drv_level_2>;
2580
+
};
2581
+
2582
+
/omit-if-no-ref/
2583
+
pwm0m3_ch0: pwm0m3-ch0 {
2584
+
rockchip,pins =
2585
+
/* pwm0_ch0_m3 */
2586
+
<3 RK_PB0 12 &pcfg_pull_none_drv_level_2>;
2587
+
};
2588
+
2589
+
/omit-if-no-ref/
2590
+
pwm0m3_ch1: pwm0m3-ch1 {
2591
+
rockchip,pins =
2592
+
/* pwm0_ch1_m3 */
2593
+
<3 RK_PB6 12 &pcfg_pull_none_drv_level_2>;
2594
+
};
2595
+
};
2596
+
2597
+
pwm1 {
2598
+
/omit-if-no-ref/
2599
+
pwm1m0_ch0: pwm1m0-ch0 {
2600
+
rockchip,pins =
2601
+
/* pwm1_ch0_m0 */
2602
+
<0 RK_PB4 12 &pcfg_pull_none>;
2603
+
};
2604
+
2605
+
/omit-if-no-ref/
2606
+
pwm1m0_ch1: pwm1m0-ch1 {
2607
+
rockchip,pins =
2608
+
/* pwm1_ch1_m0 */
2609
+
<0 RK_PB5 12 &pcfg_pull_none>;
2610
+
};
2611
+
2612
+
/omit-if-no-ref/
2613
+
pwm1m0_ch2: pwm1m0-ch2 {
2614
+
rockchip,pins =
2615
+
/* pwm1_ch2_m0 */
2616
+
<0 RK_PB6 12 &pcfg_pull_none>;
2617
+
};
2618
+
2619
+
/omit-if-no-ref/
2620
+
pwm1m0_ch3: pwm1m0-ch3 {
2621
+
rockchip,pins =
2622
+
/* pwm1_ch3_m0 */
2623
+
<0 RK_PC0 12 &pcfg_pull_none>;
2624
+
};
2625
+
2626
+
/omit-if-no-ref/
2627
+
pwm1m0_ch4: pwm1m0-ch4 {
2628
+
rockchip,pins =
2629
+
/* pwm1_ch4_m0 */
2630
+
<0 RK_PB7 12 &pcfg_pull_none>;
2631
+
};
2632
+
2633
+
/omit-if-no-ref/
2634
+
pwm1m0_ch5: pwm1m0-ch5 {
2635
+
rockchip,pins =
2636
+
/* pwm1_ch5_m0 */
2637
+
<0 RK_PD2 12 &pcfg_pull_none>;
2638
+
};
2639
+
2640
+
/omit-if-no-ref/
2641
+
pwm1m1_ch0: pwm1m1-ch0 {
2642
+
rockchip,pins =
2643
+
/* pwm1_ch0_m1 */
2644
+
<1 RK_PB4 13 &pcfg_pull_none>;
2645
+
};
2646
+
2647
+
/omit-if-no-ref/
2648
+
pwm1m1_ch1: pwm1m1-ch1 {
2649
+
rockchip,pins =
2650
+
/* pwm1_ch1_m1 */
2651
+
<1 RK_PB5 13 &pcfg_pull_none>;
2652
+
};
2653
+
2654
+
/omit-if-no-ref/
2655
+
pwm1m1_ch2: pwm1m1-ch2 {
2656
+
rockchip,pins =
2657
+
/* pwm1_ch2_m1 */
2658
+
<1 RK_PC2 13 &pcfg_pull_none>;
2659
+
};
2660
+
2661
+
/omit-if-no-ref/
2662
+
pwm1m1_ch3: pwm1m1-ch3 {
2663
+
rockchip,pins =
2664
+
/* pwm1_ch3_m1 */
2665
+
<1 RK_PD2 13 &pcfg_pull_none>;
2666
+
};
2667
+
2668
+
/omit-if-no-ref/
2669
+
pwm1m1_ch4: pwm1m1-ch4 {
2670
+
rockchip,pins =
2671
+
/* pwm1_ch4_m1 */
2672
+
<1 RK_PD3 13 &pcfg_pull_none>;
2673
+
};
2674
+
2675
+
/omit-if-no-ref/
2676
+
pwm1m1_ch5: pwm1m1-ch5 {
2677
+
rockchip,pins =
2678
+
/* pwm1_ch5_m1 */
2679
+
<4 RK_PC0 14 &pcfg_pull_none>;
2680
+
};
2681
+
2682
+
/omit-if-no-ref/
2683
+
pwm1m2_ch0: pwm1m2-ch0 {
2684
+
rockchip,pins =
2685
+
/* pwm1_ch0_m2 */
2686
+
<2 RK_PC0 13 &pcfg_pull_none>;
2687
+
};
2688
+
2689
+
/omit-if-no-ref/
2690
+
pwm1m2_ch1: pwm1m2-ch1 {
2691
+
rockchip,pins =
2692
+
/* pwm1_ch1_m2 */
2693
+
<2 RK_PC1 13 &pcfg_pull_none>;
2694
+
};
2695
+
2696
+
/omit-if-no-ref/
2697
+
pwm1m2_ch2: pwm1m2-ch2 {
2698
+
rockchip,pins =
2699
+
/* pwm1_ch2_m2 */
2700
+
<2 RK_PC2 13 &pcfg_pull_none>;
2701
+
};
2702
+
2703
+
/omit-if-no-ref/
2704
+
pwm1m2_ch3: pwm1m2-ch3 {
2705
+
rockchip,pins =
2706
+
/* pwm1_ch3_m2 */
2707
+
<2 RK_PC4 13 &pcfg_pull_none>;
2708
+
};
2709
+
2710
+
/omit-if-no-ref/
2711
+
pwm1m2_ch4: pwm1m2-ch4 {
2712
+
rockchip,pins =
2713
+
/* pwm1_ch4_m2 */
2714
+
<2 RK_PC5 13 &pcfg_pull_none>;
2715
+
};
2716
+
2717
+
/omit-if-no-ref/
2718
+
pwm1m2_ch5: pwm1m2-ch5 {
2719
+
rockchip,pins =
2720
+
/* pwm1_ch5_m2 */
2721
+
<2 RK_PC6 13 &pcfg_pull_none>;
2722
+
};
2723
+
2724
+
/omit-if-no-ref/
2725
+
pwm1m3_ch0: pwm1m3-ch0 {
2726
+
rockchip,pins =
2727
+
/* pwm1_ch0_m3 */
2728
+
<3 RK_PA4 12 &pcfg_pull_none>;
2729
+
};
2730
+
2731
+
/omit-if-no-ref/
2732
+
pwm1m3_ch1: pwm1m3-ch1 {
2733
+
rockchip,pins =
2734
+
/* pwm1_ch1_m3 */
2735
+
<3 RK_PA5 12 &pcfg_pull_none>;
2736
+
};
2737
+
2738
+
/omit-if-no-ref/
2739
+
pwm1m3_ch2: pwm1m3-ch2 {
2740
+
rockchip,pins =
2741
+
/* pwm1_ch2_m3 */
2742
+
<3 RK_PA6 12 &pcfg_pull_none>;
2743
+
};
2744
+
2745
+
/omit-if-no-ref/
2746
+
pwm1m3_ch3: pwm1m3-ch3 {
2747
+
rockchip,pins =
2748
+
/* pwm1_ch3_m3 */
2749
+
<3 RK_PB1 12 &pcfg_pull_none>;
2750
+
};
2751
+
2752
+
/omit-if-no-ref/
2753
+
pwm1m3_ch4: pwm1m3-ch4 {
2754
+
rockchip,pins =
2755
+
/* pwm1_ch4_m3 */
2756
+
<3 RK_PB4 12 &pcfg_pull_none>;
2757
+
};
2758
+
2759
+
/omit-if-no-ref/
2760
+
pwm1m3_ch5: pwm1m3-ch5 {
2761
+
rockchip,pins =
2762
+
/* pwm1_ch5_m3 */
2763
+
<3 RK_PB5 12 &pcfg_pull_none>;
2764
+
};
2765
+
};
2766
+
2767
+
pwm2 {
2768
+
/omit-if-no-ref/
2769
+
pwm2m0_ch0: pwm2m0-ch0 {
2770
+
rockchip,pins =
2771
+
/* pwm2_ch0_m0 */
2772
+
<0 RK_PD3 12 &pcfg_pull_none_drv_level_2>;
2773
+
};
2774
+
2775
+
/omit-if-no-ref/
2776
+
pwm2m0_ch1: pwm2m0-ch1 {
2777
+
rockchip,pins =
2778
+
/* pwm2_ch1_m0 */
2779
+
<1 RK_PB3 12 &pcfg_pull_none_drv_level_2>;
2780
+
};
2781
+
2782
+
/omit-if-no-ref/
2783
+
pwm2m0_ch2: pwm2m0-ch2 {
2784
+
rockchip,pins =
2785
+
/* pwm2_ch2_m0 */
2786
+
<2 RK_PA0 14 &pcfg_pull_none_drv_level_2>;
2787
+
};
2788
+
2789
+
/omit-if-no-ref/
2790
+
pwm2m0_ch3: pwm2m0-ch3 {
2791
+
rockchip,pins =
2792
+
/* pwm2_ch3_m0 */
2793
+
<2 RK_PA1 14 &pcfg_pull_none_drv_level_2>;
2794
+
};
2795
+
2796
+
/omit-if-no-ref/
2797
+
pwm2m0_ch4: pwm2m0-ch4 {
2798
+
rockchip,pins =
2799
+
/* pwm2_ch4_m0 */
2800
+
<2 RK_PA4 14 &pcfg_pull_none_drv_level_2>;
2801
+
};
2802
+
2803
+
/omit-if-no-ref/
2804
+
pwm2m0_ch5: pwm2m0-ch5 {
2805
+
rockchip,pins =
2806
+
/* pwm2_ch5_m0 */
2807
+
<4 RK_PA2 13 &pcfg_pull_none_drv_level_2>;
2808
+
};
2809
+
2810
+
/omit-if-no-ref/
2811
+
pwm2m0_ch6: pwm2m0-ch6 {
2812
+
rockchip,pins =
2813
+
/* pwm2_ch6_m0 */
2814
+
<4 RK_PA7 13 &pcfg_pull_none_drv_level_2>;
2815
+
};
2816
+
2817
+
/omit-if-no-ref/
2818
+
pwm2m0_ch7: pwm2m0-ch7 {
2819
+
rockchip,pins =
2820
+
/* pwm2_ch7_m0 */
2821
+
<4 RK_PB3 13 &pcfg_pull_none_drv_level_2>;
2822
+
};
2823
+
2824
+
/omit-if-no-ref/
2825
+
pwm2m1_ch0: pwm2m1-ch0 {
2826
+
rockchip,pins =
2827
+
/* pwm2_ch0_m1 */
2828
+
<4 RK_PC2 14 &pcfg_pull_none_drv_level_2>;
2829
+
};
2830
+
2831
+
/omit-if-no-ref/
2832
+
pwm2m1_ch1: pwm2m1-ch1 {
2833
+
rockchip,pins =
2834
+
/* pwm2_ch1_m1 */
2835
+
<4 RK_PC3 14 &pcfg_pull_none_drv_level_2>;
2836
+
};
2837
+
2838
+
/omit-if-no-ref/
2839
+
pwm2m1_ch2: pwm2m1-ch2 {
2840
+
rockchip,pins =
2841
+
/* pwm2_ch2_m1 */
2842
+
<4 RK_PC6 14 &pcfg_pull_none_drv_level_2>;
2843
+
};
2844
+
2845
+
/omit-if-no-ref/
2846
+
pwm2m1_ch3: pwm2m1-ch3 {
2847
+
rockchip,pins =
2848
+
/* pwm2_ch3_m1 */
2849
+
<4 RK_PC7 14 &pcfg_pull_none_drv_level_2>;
2850
+
};
2851
+
2852
+
/omit-if-no-ref/
2853
+
pwm2m1_ch4: pwm2m1-ch4 {
2854
+
rockchip,pins =
2855
+
/* pwm2_ch4_m1 */
2856
+
<4 RK_PA3 13 &pcfg_pull_none_drv_level_2>;
2857
+
};
2858
+
2859
+
/omit-if-no-ref/
2860
+
pwm2m1_ch5: pwm2m1-ch5 {
2861
+
rockchip,pins =
2862
+
/* pwm2_ch5_m1 */
2863
+
<4 RK_PC5 14 &pcfg_pull_none_drv_level_2>;
2864
+
};
2865
+
2866
+
/omit-if-no-ref/
2867
+
pwm2m1_ch6: pwm2m1-ch6 {
2868
+
rockchip,pins =
2869
+
/* pwm2_ch6_m1 */
2870
+
<4 RK_PC4 14 &pcfg_pull_none_drv_level_2>;
2871
+
};
2872
+
2873
+
/omit-if-no-ref/
2874
+
pwm2m1_ch7: pwm2m1-ch7 {
2875
+
rockchip,pins =
2876
+
/* pwm2_ch7_m1 */
2877
+
<1 RK_PB1 12 &pcfg_pull_none_drv_level_2>;
2878
+
};
2879
+
2880
+
/omit-if-no-ref/
2881
+
pwm2m2_ch0: pwm2m2-ch0 {
2882
+
rockchip,pins =
2883
+
/* pwm2_ch0_m2 */
2884
+
<2 RK_PD0 13 &pcfg_pull_none_drv_level_2>;
2885
+
};
2886
+
2887
+
/omit-if-no-ref/
2888
+
pwm2m2_ch1: pwm2m2-ch1 {
2889
+
rockchip,pins =
2890
+
/* pwm2_ch1_m2 */
2891
+
<2 RK_PD1 13 &pcfg_pull_none_drv_level_2>;
2892
+
};
2893
+
2894
+
/omit-if-no-ref/
2895
+
pwm2m2_ch2: pwm2m2-ch2 {
2896
+
rockchip,pins =
2897
+
/* pwm2_ch2_m2 */
2898
+
<2 RK_PD2 13 &pcfg_pull_none_drv_level_2>;
2899
+
};
2900
+
2901
+
/omit-if-no-ref/
2902
+
pwm2m2_ch3: pwm2m2-ch3 {
2903
+
rockchip,pins =
2904
+
/* pwm2_ch3_m2 */
2905
+
<2 RK_PD3 13 &pcfg_pull_none_drv_level_2>;
2906
+
};
2907
+
2908
+
/omit-if-no-ref/
2909
+
pwm2m2_ch4: pwm2m2-ch4 {
2910
+
rockchip,pins =
2911
+
/* pwm2_ch4_m2 */
2912
+
<2 RK_PD4 13 &pcfg_pull_none_drv_level_2>;
2913
+
};
2914
+
2915
+
/omit-if-no-ref/
2916
+
pwm2m2_ch5: pwm2m2-ch5 {
2917
+
rockchip,pins =
2918
+
/* pwm2_ch5_m2 */
2919
+
<2 RK_PD5 13 &pcfg_pull_none_drv_level_2>;
2920
+
};
2921
+
2922
+
/omit-if-no-ref/
2923
+
pwm2m2_ch6: pwm2m2-ch6 {
2924
+
rockchip,pins =
2925
+
/* pwm2_ch6_m2 */
2926
+
<2 RK_PD6 13 &pcfg_pull_none_drv_level_2>;
2927
+
};
2928
+
2929
+
/omit-if-no-ref/
2930
+
pwm2m2_ch7: pwm2m2-ch7 {
2931
+
rockchip,pins =
2932
+
/* pwm2_ch7_m2 */
2933
+
<2 RK_PD7 13 &pcfg_pull_none_drv_level_2>;
2934
+
};
2935
+
2936
+
/omit-if-no-ref/
2937
+
pwm2m3_ch0: pwm2m3-ch0 {
2938
+
rockchip,pins =
2939
+
/* pwm2_ch0_m3 */
2940
+
<3 RK_PC2 12 &pcfg_pull_none_drv_level_2>;
2941
+
};
2942
+
2943
+
/omit-if-no-ref/
2944
+
pwm2m3_ch1: pwm2m3-ch1 {
2945
+
rockchip,pins =
2946
+
/* pwm2_ch1_m3 */
2947
+
<3 RK_PC3 12 &pcfg_pull_none_drv_level_2>;
2948
+
};
2949
+
2950
+
/omit-if-no-ref/
2951
+
pwm2m3_ch2: pwm2m3-ch2 {
2952
+
rockchip,pins =
2953
+
/* pwm2_ch2_m3 */
2954
+
<3 RK_PC5 12 &pcfg_pull_none_drv_level_2>;
2955
+
};
2956
+
2957
+
/omit-if-no-ref/
2958
+
pwm2m3_ch3: pwm2m3-ch3 {
2959
+
rockchip,pins =
2960
+
/* pwm2_ch3_m3 */
2961
+
<3 RK_PD0 12 &pcfg_pull_none_drv_level_2>;
2962
+
};
2963
+
2964
+
/omit-if-no-ref/
2965
+
pwm2m3_ch4: pwm2m3-ch4 {
2966
+
rockchip,pins =
2967
+
/* pwm2_ch4_m3 */
2968
+
<3 RK_PD2 12 &pcfg_pull_none_drv_level_2>;
2969
+
};
2970
+
2971
+
/omit-if-no-ref/
2972
+
pwm2m3_ch5: pwm2m3-ch5 {
2973
+
rockchip,pins =
2974
+
/* pwm2_ch5_m3 */
2975
+
<3 RK_PD3 12 &pcfg_pull_none_drv_level_2>;
2976
+
};
2977
+
2978
+
/omit-if-no-ref/
2979
+
pwm2m3_ch6: pwm2m3-ch6 {
2980
+
rockchip,pins =
2981
+
/* pwm2_ch6_m3 */
2982
+
<3 RK_PD6 12 &pcfg_pull_none_drv_level_2>;
2983
+
};
2984
+
2985
+
/omit-if-no-ref/
2986
+
pwm2m3_ch7: pwm2m3-ch7 {
2987
+
rockchip,pins =
2988
+
/* pwm2_ch7_m3 */
2989
+
<3 RK_PD7 12 &pcfg_pull_none_drv_level_2>;
2990
+
};
2991
+
};
2992
+
2993
+
ref_clk0 {
2994
+
/omit-if-no-ref/
2995
+
ref_clk0_clk0: ref_clk0-clk0 {
2996
+
rockchip,pins =
2997
+
/* ref_clk0_out */
2998
+
<0 RK_PA0 1 &pcfg_pull_none>;
2999
+
};
3000
+
};
3001
+
3002
+
ref_clk1 {
3003
+
/omit-if-no-ref/
3004
+
ref_clk1_clk1: ref_clk1-clk1 {
3005
+
rockchip,pins =
3006
+
/* ref_clk1_out */
3007
+
<0 RK_PB4 1 &pcfg_pull_none>;
3008
+
};
3009
+
};
3010
+
3011
+
ref_clk2 {
3012
+
/omit-if-no-ref/
3013
+
ref_clk2_clk2: ref_clk2-clk2 {
3014
+
rockchip,pins =
3015
+
/* ref_clk2_out */
3016
+
<0 RK_PB5 1 &pcfg_pull_none>;
3017
+
};
3018
+
};
3019
+
3020
+
sai0 {
3021
+
/omit-if-no-ref/
3022
+
sai0m0_lrck: sai0m0-lrck {
3023
+
rockchip,pins =
3024
+
/* sai0_lrck_m0 */
3025
+
<2 RK_PB7 4 &pcfg_pull_none>;
3026
+
};
3027
+
3028
+
/omit-if-no-ref/
3029
+
sai0m0_mclk: sai0m0-mclk {
3030
+
rockchip,pins =
3031
+
/* sai0_mclk_m0 */
3032
+
<2 RK_PB5 4 &pcfg_pull_none>;
3033
+
};
3034
+
3035
+
/omit-if-no-ref/
3036
+
sai0m0_sclk: sai0m0-sclk {
3037
+
rockchip,pins =
3038
+
/* sai0_sclk_m0 */
3039
+
<2 RK_PB6 4 &pcfg_pull_none>;
3040
+
};
3041
+
3042
+
/omit-if-no-ref/
3043
+
sai0m0_sdi0: sai0m0-sdi0 {
3044
+
rockchip,pins =
3045
+
/* sai0_sdi0_m0 */
3046
+
<2 RK_PB0 4 &pcfg_pull_none>;
3047
+
};
3048
+
3049
+
/omit-if-no-ref/
3050
+
sai0m0_sdi1: sai0m0-sdi1 {
3051
+
rockchip,pins =
3052
+
/* sai0_sdi1_m0 */
3053
+
<2 RK_PB1 4 &pcfg_pull_none>;
3054
+
};
3055
+
3056
+
/omit-if-no-ref/
3057
+
sai0m0_sdi2: sai0m0-sdi2 {
3058
+
rockchip,pins =
3059
+
/* sai0_sdi2_m0 */
3060
+
<2 RK_PB2 4 &pcfg_pull_none>;
3061
+
};
3062
+
3063
+
/omit-if-no-ref/
3064
+
sai0m0_sdi3: sai0m0-sdi3 {
3065
+
rockchip,pins =
3066
+
/* sai0_sdi3_m0 */
3067
+
<2 RK_PB4 4 &pcfg_pull_none>;
3068
+
};
3069
+
3070
+
/omit-if-no-ref/
3071
+
sai0m0_sdo0: sai0m0-sdo0 {
3072
+
rockchip,pins =
3073
+
/* sai0_sdo0_m0 */
3074
+
<2 RK_PA6 4 &pcfg_pull_none>;
3075
+
};
3076
+
3077
+
/omit-if-no-ref/
3078
+
sai0m0_sdo1: sai0m0-sdo1 {
3079
+
rockchip,pins =
3080
+
/* sai0_sdo1_m0 */
3081
+
<2 RK_PA7 4 &pcfg_pull_none>;
3082
+
};
3083
+
3084
+
/omit-if-no-ref/
3085
+
sai0m0_sdo2: sai0m0-sdo2 {
3086
+
rockchip,pins =
3087
+
/* sai0_sdo2_m0 */
3088
+
<2 RK_PB3 4 &pcfg_pull_none>;
3089
+
};
3090
+
3091
+
/omit-if-no-ref/
3092
+
sai0m0_sdo3: sai0m0-sdo3 {
3093
+
rockchip,pins =
3094
+
/* sai0_sdo3_m0 */
3095
+
<2 RK_PD7 4 &pcfg_pull_none>;
3096
+
};
3097
+
3098
+
/omit-if-no-ref/
3099
+
sai0m1_lrck: sai0m1-lrck {
3100
+
rockchip,pins =
3101
+
/* sai0_lrck_m1 */
3102
+
<0 RK_PC7 1 &pcfg_pull_none>;
3103
+
};
3104
+
3105
+
/omit-if-no-ref/
3106
+
sai0m1_mclk: sai0m1-mclk {
3107
+
rockchip,pins =
3108
+
/* sai0_mclk_m1 */
3109
+
<0 RK_PC4 1 &pcfg_pull_none>;
3110
+
};
3111
+
3112
+
/omit-if-no-ref/
3113
+
sai0m1_sclk: sai0m1-sclk {
3114
+
rockchip,pins =
3115
+
/* sai0_sclk_m1 */
3116
+
<0 RK_PC6 1 &pcfg_pull_none>;
3117
+
};
3118
+
3119
+
/omit-if-no-ref/
3120
+
sai0m1_sdi0: sai0m1-sdi0 {
3121
+
rockchip,pins =
3122
+
/* sai0_sdi0_m1 */
3123
+
<0 RK_PD0 1 &pcfg_pull_none>;
3124
+
};
3125
+
3126
+
/omit-if-no-ref/
3127
+
sai0m1_sdi1: sai0m1-sdi1 {
3128
+
rockchip,pins =
3129
+
/* sai0_sdi1_m1 */
3130
+
<0 RK_PD1 1 &pcfg_pull_none>;
3131
+
};
3132
+
3133
+
/omit-if-no-ref/
3134
+
sai0m1_sdi2: sai0m1-sdi2 {
3135
+
rockchip,pins =
3136
+
/* sai0_sdi2_m1 */
3137
+
<0 RK_PD2 1 &pcfg_pull_none>;
3138
+
};
3139
+
3140
+
/omit-if-no-ref/
3141
+
sai0m1_sdi3: sai0m1-sdi3 {
3142
+
rockchip,pins =
3143
+
/* sai0_sdi3_m1 */
3144
+
<0 RK_PD3 1 &pcfg_pull_none>;
3145
+
};
3146
+
3147
+
/omit-if-no-ref/
3148
+
sai0m1_sdo0: sai0m1-sdo0 {
3149
+
rockchip,pins =
3150
+
/* sai0_sdo0_m1 */
3151
+
<0 RK_PC5 1 &pcfg_pull_none>;
3152
+
};
3153
+
3154
+
/omit-if-no-ref/
3155
+
sai0m1_sdo1: sai0m1-sdo1 {
3156
+
rockchip,pins =
3157
+
/* sai0_sdo1_m1 */
3158
+
<0 RK_PD3 2 &pcfg_pull_none>;
3159
+
};
3160
+
3161
+
/omit-if-no-ref/
3162
+
sai0m1_sdo2: sai0m1-sdo2 {
3163
+
rockchip,pins =
3164
+
/* sai0_sdo2_m1 */
3165
+
<0 RK_PD2 2 &pcfg_pull_none>;
3166
+
};
3167
+
3168
+
/omit-if-no-ref/
3169
+
sai0m1_sdo3: sai0m1-sdo3 {
3170
+
rockchip,pins =
3171
+
/* sai0_sdo3_m1 */
3172
+
<0 RK_PD1 2 &pcfg_pull_none>;
3173
+
};
3174
+
3175
+
/omit-if-no-ref/
3176
+
sai0m2_lrck: sai0m2-lrck {
3177
+
rockchip,pins =
3178
+
/* sai0_lrck_m2 */
3179
+
<1 RK_PA1 3 &pcfg_pull_none>;
3180
+
};
3181
+
3182
+
/omit-if-no-ref/
3183
+
sai0m2_mclk: sai0m2-mclk {
3184
+
rockchip,pins =
3185
+
/* sai0_mclk_m2 */
3186
+
<1 RK_PA4 3 &pcfg_pull_none>;
3187
+
};
3188
+
3189
+
/omit-if-no-ref/
3190
+
sai0m2_sclk: sai0m2-sclk {
3191
+
rockchip,pins =
3192
+
/* sai0_sclk_m2 */
3193
+
<1 RK_PA0 3 &pcfg_pull_none>;
3194
+
};
3195
+
3196
+
/omit-if-no-ref/
3197
+
sai0m2_sdi0: sai0m2-sdi0 {
3198
+
rockchip,pins =
3199
+
/* sai0_sdi0_m2 */
3200
+
<1 RK_PB2 3 &pcfg_pull_none>;
3201
+
};
3202
+
3203
+
/omit-if-no-ref/
3204
+
sai0m2_sdi1: sai0m2-sdi1 {
3205
+
rockchip,pins =
3206
+
/* sai0_sdi1_m2 */
3207
+
<1 RK_PB1 4 &pcfg_pull_none>;
3208
+
};
3209
+
3210
+
/omit-if-no-ref/
3211
+
sai0m2_sdi2: sai0m2-sdi2 {
3212
+
rockchip,pins =
3213
+
/* sai0_sdi2_m2 */
3214
+
<1 RK_PA3 4 &pcfg_pull_none>;
3215
+
};
3216
+
3217
+
/omit-if-no-ref/
3218
+
sai0m2_sdi3: sai0m2-sdi3 {
3219
+
rockchip,pins =
3220
+
/* sai0_sdi3_m2 */
3221
+
<1 RK_PA2 4 &pcfg_pull_none>;
3222
+
};
3223
+
3224
+
/omit-if-no-ref/
3225
+
sai0m2_sdo0: sai0m2-sdo0 {
3226
+
rockchip,pins =
3227
+
/* sai0_sdo0_m2 */
3228
+
<1 RK_PA7 3 &pcfg_pull_none>;
3229
+
};
3230
+
3231
+
/omit-if-no-ref/
3232
+
sai0m2_sdo1: sai0m2-sdo1 {
3233
+
rockchip,pins =
3234
+
/* sai0_sdo1_m2 */
3235
+
<1 RK_PA2 3 &pcfg_pull_none>;
3236
+
};
3237
+
3238
+
/omit-if-no-ref/
3239
+
sai0m2_sdo2: sai0m2-sdo2 {
3240
+
rockchip,pins =
3241
+
/* sai0_sdo2_m2 */
3242
+
<1 RK_PA3 3 &pcfg_pull_none>;
3243
+
};
3244
+
3245
+
/omit-if-no-ref/
3246
+
sai0m2_sdo3: sai0m2-sdo3 {
3247
+
rockchip,pins =
3248
+
/* sai0_sdo3_m2 */
3249
+
<1 RK_PB1 3 &pcfg_pull_none>;
3250
+
};
3251
+
};
3252
+
3253
+
sai1 {
3254
+
/omit-if-no-ref/
3255
+
sai1m0_lrck: sai1m0-lrck {
3256
+
rockchip,pins =
3257
+
/* sai1_lrck_m0 */
3258
+
<4 RK_PA5 1 &pcfg_pull_none>;
3259
+
};
3260
+
3261
+
/omit-if-no-ref/
3262
+
sai1m0_mclk: sai1m0-mclk {
3263
+
rockchip,pins =
3264
+
/* sai1_mclk_m0 */
3265
+
<4 RK_PA2 1 &pcfg_pull_none>;
3266
+
};
3267
+
3268
+
/omit-if-no-ref/
3269
+
sai1m0_sclk: sai1m0-sclk {
3270
+
rockchip,pins =
3271
+
/* sai1_sclk_m0 */
3272
+
<4 RK_PA3 1 &pcfg_pull_none>;
3273
+
};
3274
+
3275
+
/omit-if-no-ref/
3276
+
sai1m0_sdi0: sai1m0-sdi0 {
3277
+
rockchip,pins =
3278
+
/* sai1_sdi0_m0 */
3279
+
<4 RK_PB3 1 &pcfg_pull_none>;
3280
+
};
3281
+
3282
+
/omit-if-no-ref/
3283
+
sai1m0_sdi1: sai1m0-sdi1 {
3284
+
rockchip,pins =
3285
+
/* sai1_sdi1_m0 */
3286
+
<4 RK_PB2 2 &pcfg_pull_none>;
3287
+
};
3288
+
3289
+
/omit-if-no-ref/
3290
+
sai1m0_sdi2: sai1m0-sdi2 {
3291
+
rockchip,pins =
3292
+
/* sai1_sdi2_m0 */
3293
+
<4 RK_PB1 2 &pcfg_pull_none>;
3294
+
};
3295
+
3296
+
/omit-if-no-ref/
3297
+
sai1m0_sdi3: sai1m0-sdi3 {
3298
+
rockchip,pins =
3299
+
/* sai1_sdi3_m0 */
3300
+
<4 RK_PB0 2 &pcfg_pull_none>;
3301
+
};
3302
+
3303
+
/omit-if-no-ref/
3304
+
sai1m0_sdo0: sai1m0-sdo0 {
3305
+
rockchip,pins =
3306
+
/* sai1_sdo0_m0 */
3307
+
<4 RK_PA7 1 &pcfg_pull_none>;
3308
+
};
3309
+
3310
+
/omit-if-no-ref/
3311
+
sai1m0_sdo1: sai1m0-sdo1 {
3312
+
rockchip,pins =
3313
+
/* sai1_sdo1_m0 */
3314
+
<4 RK_PB0 1 &pcfg_pull_none>;
3315
+
};
3316
+
3317
+
/omit-if-no-ref/
3318
+
sai1m0_sdo2: sai1m0-sdo2 {
3319
+
rockchip,pins =
3320
+
/* sai1_sdo2_m0 */
3321
+
<4 RK_PB1 1 &pcfg_pull_none>;
3322
+
};
3323
+
3324
+
/omit-if-no-ref/
3325
+
sai1m0_sdo3: sai1m0-sdo3 {
3326
+
rockchip,pins =
3327
+
/* sai1_sdo3_m0 */
3328
+
<4 RK_PB2 1 &pcfg_pull_none>;
3329
+
};
3330
+
3331
+
/omit-if-no-ref/
3332
+
sai1m1_lrck: sai1m1-lrck {
3333
+
rockchip,pins =
3334
+
/* sai1_lrck_m1 */
3335
+
<3 RK_PC6 4 &pcfg_pull_none>;
3336
+
};
3337
+
3338
+
/omit-if-no-ref/
3339
+
sai1m1_mclk: sai1m1-mclk {
3340
+
rockchip,pins =
3341
+
/* sai1_mclk_m1 */
3342
+
<3 RK_PD0 4 &pcfg_pull_none>;
3343
+
};
3344
+
3345
+
/omit-if-no-ref/
3346
+
sai1m1_sclk: sai1m1-sclk {
3347
+
rockchip,pins =
3348
+
/* sai1_sclk_m1 */
3349
+
<3 RK_PC7 4 &pcfg_pull_none>;
3350
+
};
3351
+
3352
+
/omit-if-no-ref/
3353
+
sai1m1_sdi0: sai1m1-sdi0 {
3354
+
rockchip,pins =
3355
+
/* sai1_sdi0_m1 */
3356
+
<3 RK_PB7 4 &pcfg_pull_none>;
3357
+
};
3358
+
3359
+
/omit-if-no-ref/
3360
+
sai1m1_sdi1: sai1m1-sdi1 {
3361
+
rockchip,pins =
3362
+
/* sai1_sdi1_m1 */
3363
+
<3 RK_PD4 4 &pcfg_pull_none>;
3364
+
};
3365
+
3366
+
/omit-if-no-ref/
3367
+
sai1m1_sdi2: sai1m1-sdi2 {
3368
+
rockchip,pins =
3369
+
/* sai1_sdi2_m1 */
3370
+
<3 RK_PD5 4 &pcfg_pull_none>;
3371
+
};
3372
+
3373
+
/omit-if-no-ref/
3374
+
sai1m1_sdi3: sai1m1-sdi3 {
3375
+
rockchip,pins =
3376
+
/* sai1_sdi3_m1 */
3377
+
<3 RK_PD6 4 &pcfg_pull_none>;
3378
+
};
3379
+
3380
+
/omit-if-no-ref/
3381
+
sai1m1_sdo0: sai1m1-sdo0 {
3382
+
rockchip,pins =
3383
+
/* sai1_sdo0_m1 */
3384
+
<3 RK_PC5 4 &pcfg_pull_none>;
3385
+
};
3386
+
3387
+
/omit-if-no-ref/
3388
+
sai1m1_sdo1: sai1m1-sdo1 {
3389
+
rockchip,pins =
3390
+
/* sai1_sdo1_m1 */
3391
+
<3 RK_PC4 4 &pcfg_pull_none>;
3392
+
};
3393
+
3394
+
/omit-if-no-ref/
3395
+
sai1m1_sdo2: sai1m1-sdo2 {
3396
+
rockchip,pins =
3397
+
/* sai1_sdo2_m1 */
3398
+
<3 RK_PC1 4 &pcfg_pull_none>;
3399
+
};
3400
+
3401
+
/omit-if-no-ref/
3402
+
sai1m1_sdo3: sai1m1-sdo3 {
3403
+
rockchip,pins =
3404
+
/* sai1_sdo3_m1 */
3405
+
<3 RK_PC0 4 &pcfg_pull_none>;
3406
+
};
3407
+
};
3408
+
3409
+
sai2 {
3410
+
/omit-if-no-ref/
3411
+
sai2m0_lrck: sai2m0-lrck {
3412
+
rockchip,pins =
3413
+
/* sai2_lrck_m0 */
3414
+
<1 RK_PD2 4 &pcfg_pull_none>;
3415
+
};
3416
+
3417
+
/omit-if-no-ref/
3418
+
sai2m0_mclk: sai2m0-mclk {
3419
+
rockchip,pins =
3420
+
/* sai2_mclk_m0 */
3421
+
<1 RK_PD4 4 &pcfg_pull_none>;
3422
+
};
3423
+
3424
+
/omit-if-no-ref/
3425
+
sai2m0_sclk: sai2m0-sclk {
3426
+
rockchip,pins =
3427
+
/* sai2_sclk_m0 */
3428
+
<1 RK_PD1 4 &pcfg_pull_none>;
3429
+
};
3430
+
3431
+
/omit-if-no-ref/
3432
+
sai2m0_sdi: sai2m0-sdi {
3433
+
rockchip,pins =
3434
+
/* sai2m0_sdi */
3435
+
<1 RK_PD3 4 &pcfg_pull_none>;
3436
+
};
3437
+
/omit-if-no-ref/
3438
+
sai2m0_sdo: sai2m0-sdo {
3439
+
rockchip,pins =
3440
+
/* sai2m0_sdo */
3441
+
<1 RK_PD0 4 &pcfg_pull_none>;
3442
+
};
3443
+
3444
+
/omit-if-no-ref/
3445
+
sai2m1_lrck: sai2m1-lrck {
3446
+
rockchip,pins =
3447
+
/* sai2_lrck_m1 */
3448
+
<2 RK_PC3 4 &pcfg_pull_none>;
3449
+
};
3450
+
3451
+
/omit-if-no-ref/
3452
+
sai2m1_mclk: sai2m1-mclk {
3453
+
rockchip,pins =
3454
+
/* sai2_mclk_m1 */
3455
+
<2 RK_PC1 4 &pcfg_pull_none>;
3456
+
};
3457
+
3458
+
/omit-if-no-ref/
3459
+
sai2m1_sclk: sai2m1-sclk {
3460
+
rockchip,pins =
3461
+
/* sai2_sclk_m1 */
3462
+
<2 RK_PC2 4 &pcfg_pull_none>;
3463
+
};
3464
+
3465
+
/omit-if-no-ref/
3466
+
sai2m1_sdi: sai2m1-sdi {
3467
+
rockchip,pins =
3468
+
/* sai2m1_sdi */
3469
+
<2 RK_PC5 4 &pcfg_pull_none>;
3470
+
};
3471
+
/omit-if-no-ref/
3472
+
sai2m1_sdo: sai2m1-sdo {
3473
+
rockchip,pins =
3474
+
/* sai2m1_sdo */
3475
+
<2 RK_PC4 4 &pcfg_pull_none>;
3476
+
};
3477
+
3478
+
/omit-if-no-ref/
3479
+
sai2m2_lrck: sai2m2-lrck {
3480
+
rockchip,pins =
3481
+
/* sai2_lrck_m2 */
3482
+
<3 RK_PC3 4 &pcfg_pull_none>;
3483
+
};
3484
+
3485
+
/omit-if-no-ref/
3486
+
sai2m2_mclk: sai2m2-mclk {
3487
+
rockchip,pins =
3488
+
/* sai2_mclk_m2 */
3489
+
<3 RK_PD1 4 &pcfg_pull_none>;
3490
+
};
3491
+
3492
+
/omit-if-no-ref/
3493
+
sai2m2_sclk: sai2m2-sclk {
3494
+
rockchip,pins =
3495
+
/* sai2_sclk_m2 */
3496
+
<3 RK_PC2 4 &pcfg_pull_none>;
3497
+
};
3498
+
3499
+
/omit-if-no-ref/
3500
+
sai2m2_sdi: sai2m2-sdi {
3501
+
rockchip,pins =
3502
+
/* sai2m2_sdi */
3503
+
<3 RK_PD2 4 &pcfg_pull_none>;
3504
+
};
3505
+
/omit-if-no-ref/
3506
+
sai2m2_sdo: sai2m2-sdo {
3507
+
rockchip,pins =
3508
+
/* sai2m2_sdo */
3509
+
<3 RK_PD3 4 &pcfg_pull_none>;
3510
+
};
3511
+
};
3512
+
3513
+
sai3 {
3514
+
/omit-if-no-ref/
3515
+
sai3m0_lrck: sai3m0-lrck {
3516
+
rockchip,pins =
3517
+
/* sai3_lrck_m0 */
3518
+
<1 RK_PA6 4 &pcfg_pull_none>;
3519
+
};
3520
+
3521
+
/omit-if-no-ref/
3522
+
sai3m0_mclk: sai3m0-mclk {
3523
+
rockchip,pins =
3524
+
/* sai3_mclk_m0 */
3525
+
<1 RK_PA4 4 &pcfg_pull_none>;
3526
+
};
3527
+
3528
+
/omit-if-no-ref/
3529
+
sai3m0_sclk: sai3m0-sclk {
3530
+
rockchip,pins =
3531
+
/* sai3_sclk_m0 */
3532
+
<1 RK_PA5 4 &pcfg_pull_none>;
3533
+
};
3534
+
3535
+
/omit-if-no-ref/
3536
+
sai3m0_sdi: sai3m0-sdi {
3537
+
rockchip,pins =
3538
+
/* sai3m0_sdi */
3539
+
<1 RK_PA7 4 &pcfg_pull_none>;
3540
+
};
3541
+
/omit-if-no-ref/
3542
+
sai3m0_sdo: sai3m0-sdo {
3543
+
rockchip,pins =
3544
+
/* sai3m0_sdo */
3545
+
<1 RK_PB2 4 &pcfg_pull_none>;
3546
+
};
3547
+
3548
+
/omit-if-no-ref/
3549
+
sai3m1_lrck: sai3m1-lrck {
3550
+
rockchip,pins =
3551
+
/* sai3_lrck_m1 */
3552
+
<1 RK_PB5 4 &pcfg_pull_none>;
3553
+
};
3554
+
3555
+
/omit-if-no-ref/
3556
+
sai3m1_mclk: sai3m1-mclk {
3557
+
rockchip,pins =
3558
+
/* sai3_mclk_m1 */
3559
+
<1 RK_PC1 4 &pcfg_pull_none>;
3560
+
};
3561
+
3562
+
/omit-if-no-ref/
3563
+
sai3m1_sclk: sai3m1-sclk {
3564
+
rockchip,pins =
3565
+
/* sai3_sclk_m1 */
3566
+
<1 RK_PB4 4 &pcfg_pull_none>;
3567
+
};
3568
+
3569
+
/omit-if-no-ref/
3570
+
sai3m1_sdi: sai3m1-sdi {
3571
+
rockchip,pins =
3572
+
/* sai3m1_sdi */
3573
+
<1 RK_PB7 4 &pcfg_pull_none>;
3574
+
};
3575
+
/omit-if-no-ref/
3576
+
sai3m1_sdo: sai3m1-sdo {
3577
+
rockchip,pins =
3578
+
/* sai3m1_sdo */
3579
+
<1 RK_PB6 4 &pcfg_pull_none>;
3580
+
};
3581
+
3582
+
/omit-if-no-ref/
3583
+
sai3m2_lrck: sai3m2-lrck {
3584
+
rockchip,pins =
3585
+
/* sai3_lrck_m2 */
3586
+
<3 RK_PA1 4 &pcfg_pull_none>;
3587
+
};
3588
+
3589
+
/omit-if-no-ref/
3590
+
sai3m2_mclk: sai3m2-mclk {
3591
+
rockchip,pins =
3592
+
/* sai3_mclk_m2 */
3593
+
<2 RK_PD6 4 &pcfg_pull_none>;
3594
+
};
3595
+
3596
+
/omit-if-no-ref/
3597
+
sai3m2_sclk: sai3m2-sclk {
3598
+
rockchip,pins =
3599
+
/* sai3_sclk_m2 */
3600
+
<3 RK_PA0 4 &pcfg_pull_none>;
3601
+
};
3602
+
3603
+
/omit-if-no-ref/
3604
+
sai3m2_sdi: sai3m2-sdi {
3605
+
rockchip,pins =
3606
+
/* sai3m2_sdi */
3607
+
<3 RK_PA3 4 &pcfg_pull_none>;
3608
+
};
3609
+
/omit-if-no-ref/
3610
+
sai3m2_sdo: sai3m2-sdo {
3611
+
rockchip,pins =
3612
+
/* sai3m2_sdo */
3613
+
<3 RK_PA2 4 &pcfg_pull_none>;
3614
+
};
3615
+
3616
+
/omit-if-no-ref/
3617
+
sai3m3_lrck: sai3m3-lrck {
3618
+
rockchip,pins =
3619
+
/* sai3_lrck_m3 */
3620
+
<2 RK_PA2 4 &pcfg_pull_none>;
3621
+
};
3622
+
3623
+
/omit-if-no-ref/
3624
+
sai3m3_mclk: sai3m3-mclk {
3625
+
rockchip,pins =
3626
+
/* sai3_mclk_m3 */
3627
+
<2 RK_PA1 4 &pcfg_pull_none>;
3628
+
};
3629
+
3630
+
/omit-if-no-ref/
3631
+
sai3m3_sclk: sai3m3-sclk {
3632
+
rockchip,pins =
3633
+
/* sai3_sclk_m3 */
3634
+
<2 RK_PA5 4 &pcfg_pull_none>;
3635
+
};
3636
+
3637
+
/omit-if-no-ref/
3638
+
sai3m3_sdi: sai3m3-sdi {
3639
+
rockchip,pins =
3640
+
/* sai3m3_sdi */
3641
+
<2 RK_PA3 4 &pcfg_pull_none>;
3642
+
};
3643
+
/omit-if-no-ref/
3644
+
sai3m3_sdo: sai3m3-sdo {
3645
+
rockchip,pins =
3646
+
/* sai3m3_sdo */
3647
+
<2 RK_PA4 4 &pcfg_pull_none>;
3648
+
};
3649
+
};
3650
+
3651
+
sai4 {
3652
+
/omit-if-no-ref/
3653
+
sai4m0_lrck: sai4m0-lrck {
3654
+
rockchip,pins =
3655
+
/* sai4_lrck_m0 */
3656
+
<4 RK_PA6 2 &pcfg_pull_none>;
3657
+
};
3658
+
3659
+
/omit-if-no-ref/
3660
+
sai4m0_mclk: sai4m0-mclk {
3661
+
rockchip,pins =
3662
+
/* sai4_mclk_m0 */
3663
+
<4 RK_PA2 2 &pcfg_pull_none>;
3664
+
};
3665
+
3666
+
/omit-if-no-ref/
3667
+
sai4m0_sclk: sai4m0-sclk {
3668
+
rockchip,pins =
3669
+
/* sai4_sclk_m0 */
3670
+
<4 RK_PA4 2 &pcfg_pull_none>;
3671
+
};
3672
+
3673
+
/omit-if-no-ref/
3674
+
sai4m0_sdi: sai4m0-sdi {
3675
+
rockchip,pins =
3676
+
/* sai4m0_sdi */
3677
+
<4 RK_PA7 2 &pcfg_pull_none>;
3678
+
};
3679
+
/omit-if-no-ref/
3680
+
sai4m0_sdo: sai4m0-sdo {
3681
+
rockchip,pins =
3682
+
/* sai4m0_sdo */
3683
+
<4 RK_PB3 2 &pcfg_pull_none>;
3684
+
};
3685
+
3686
+
/omit-if-no-ref/
3687
+
sai4m1_lrck: sai4m1-lrck {
3688
+
rockchip,pins =
3689
+
/* sai4_lrck_m1 */
3690
+
<4 RK_PA0 4 &pcfg_pull_none>;
3691
+
};
3692
+
3693
+
/omit-if-no-ref/
3694
+
sai4m1_mclk: sai4m1-mclk {
3695
+
rockchip,pins =
3696
+
/* sai4_mclk_m1 */
3697
+
<3 RK_PB0 4 &pcfg_pull_none>;
3698
+
};
3699
+
3700
+
/omit-if-no-ref/
3701
+
sai4m1_sclk: sai4m1-sclk {
3702
+
rockchip,pins =
3703
+
/* sai4_sclk_m1 */
3704
+
<3 RK_PD7 4 &pcfg_pull_none>;
3705
+
};
3706
+
3707
+
/omit-if-no-ref/
3708
+
sai4m1_sdi: sai4m1-sdi {
3709
+
rockchip,pins =
3710
+
/* sai4m1_sdi */
3711
+
<3 RK_PA4 4 &pcfg_pull_none>;
3712
+
};
3713
+
/omit-if-no-ref/
3714
+
sai4m1_sdo: sai4m1-sdo {
3715
+
rockchip,pins =
3716
+
/* sai4m1_sdo */
3717
+
<4 RK_PA1 4 &pcfg_pull_none>;
3718
+
};
3719
+
3720
+
/omit-if-no-ref/
3721
+
sai4m2_lrck: sai4m2-lrck {
3722
+
rockchip,pins =
3723
+
/* sai4_lrck_m2 */
3724
+
<4 RK_PC4 2 &pcfg_pull_none>;
3725
+
};
3726
+
3727
+
/omit-if-no-ref/
3728
+
sai4m2_mclk: sai4m2-mclk {
3729
+
rockchip,pins =
3730
+
/* sai4_mclk_m2 */
3731
+
<4 RK_PC0 2 &pcfg_pull_none>;
3732
+
};
3733
+
3734
+
/omit-if-no-ref/
3735
+
sai4m2_sclk: sai4m2-sclk {
3736
+
rockchip,pins =
3737
+
/* sai4_sclk_m2 */
3738
+
<4 RK_PC7 2 &pcfg_pull_none>;
3739
+
};
3740
+
3741
+
/omit-if-no-ref/
3742
+
sai4m2_sdi: sai4m2-sdi {
3743
+
rockchip,pins =
3744
+
/* sai4m2_sdi */
3745
+
<4 RK_PC6 2 &pcfg_pull_none>;
3746
+
};
3747
+
/omit-if-no-ref/
3748
+
sai4m2_sdo: sai4m2-sdo {
3749
+
rockchip,pins =
3750
+
/* sai4m2_sdo */
3751
+
<4 RK_PC5 2 &pcfg_pull_none>;
3752
+
};
3753
+
3754
+
/omit-if-no-ref/
3755
+
sai4m3_lrck: sai4m3-lrck {
3756
+
rockchip,pins =
3757
+
/* sai4_lrck_m3 */
3758
+
<2 RK_PC7 4 &pcfg_pull_none>;
3759
+
};
3760
+
3761
+
/omit-if-no-ref/
3762
+
sai4m3_mclk: sai4m3-mclk {
3763
+
rockchip,pins =
3764
+
/* sai4_mclk_m3 */
3765
+
<2 RK_PD2 4 &pcfg_pull_none>;
3766
+
};
3767
+
3768
+
/omit-if-no-ref/
3769
+
sai4m3_sclk: sai4m3-sclk {
3770
+
rockchip,pins =
3771
+
/* sai4_sclk_m3 */
3772
+
<2 RK_PC6 4 &pcfg_pull_none>;
3773
+
};
3774
+
3775
+
/omit-if-no-ref/
3776
+
sai4m3_sdi: sai4m3-sdi {
3777
+
rockchip,pins =
3778
+
/* sai4m3_sdi */
3779
+
<2 RK_PD0 4 &pcfg_pull_none>;
3780
+
};
3781
+
/omit-if-no-ref/
3782
+
sai4m3_sdo: sai4m3-sdo {
3783
+
rockchip,pins =
3784
+
/* sai4m3_sdo */
3785
+
<2 RK_PD1 4 &pcfg_pull_none>;
3786
+
};
3787
+
};
3788
+
3789
+
sata30 {
3790
+
/omit-if-no-ref/
3791
+
sata30_sata: sata30-sata {
3792
+
rockchip,pins =
3793
+
/* sata30_cpdet */
3794
+
<1 RK_PC7 12 &pcfg_pull_none>,
3795
+
/* sata30_cppod */
3796
+
<1 RK_PC6 12 &pcfg_pull_none>,
3797
+
/* sata30_mpswit */
3798
+
<1 RK_PD5 12 &pcfg_pull_none>;
3799
+
};
3800
+
};
3801
+
3802
+
sata30_port0 {
3803
+
/omit-if-no-ref/
3804
+
sata30_port0m0_port0: sata30_port0m0-port0 {
3805
+
rockchip,pins =
3806
+
/* sata30_port0_actled_m0 */
3807
+
<2 RK_PB4 12 &pcfg_pull_none>;
3808
+
};
3809
+
3810
+
/omit-if-no-ref/
3811
+
sata30_port0m1_port0: sata30_port0m1-port0 {
3812
+
rockchip,pins =
3813
+
/* sata30_port0_actled_m1 */
3814
+
<4 RK_PC6 10 &pcfg_pull_none>;
3815
+
};
3816
+
};
3817
+
3818
+
sata30_port1 {
3819
+
/omit-if-no-ref/
3820
+
sata30_port1m0_port1: sata30_port1m0-port1 {
3821
+
rockchip,pins =
3822
+
/* sata30_port1_actled_m0 */
3823
+
<2 RK_PB5 12 &pcfg_pull_none>;
3824
+
};
3825
+
3826
+
/omit-if-no-ref/
3827
+
sata30_port1m1_port1: sata30_port1m1-port1 {
3828
+
rockchip,pins =
3829
+
/* sata30_port1_actled_m1 */
3830
+
<4 RK_PC5 10 &pcfg_pull_none>;
3831
+
};
3832
+
};
3833
+
3834
+
sdmmc0 {
3835
+
/omit-if-no-ref/
3836
+
sdmmc0_bus4: sdmmc0-bus4 {
3837
+
rockchip,pins =
3838
+
/* sdmmc0_d0 */
3839
+
<2 RK_PA0 1 &pcfg_pull_up_drv_level_3>,
3840
+
/* sdmmc0_d1 */
3841
+
<2 RK_PA1 1 &pcfg_pull_up_drv_level_3>,
3842
+
/* sdmmc0_d2 */
3843
+
<2 RK_PA2 1 &pcfg_pull_up_drv_level_3>,
3844
+
/* sdmmc0_d3 */
3845
+
<2 RK_PA3 1 &pcfg_pull_up_drv_level_3>;
3846
+
};
3847
+
3848
+
/omit-if-no-ref/
3849
+
sdmmc0_clk: sdmmc0-clk {
3850
+
rockchip,pins =
3851
+
/* sdmmc0_clk */
3852
+
<2 RK_PA5 1 &pcfg_pull_up_drv_level_3>;
3853
+
};
3854
+
3855
+
/omit-if-no-ref/
3856
+
sdmmc0_cmd: sdmmc0-cmd {
3857
+
rockchip,pins =
3858
+
/* sdmmc0_cmd */
3859
+
<2 RK_PA4 1 &pcfg_pull_up_drv_level_3>;
3860
+
};
3861
+
3862
+
/omit-if-no-ref/
3863
+
sdmmc0_det: sdmmc0-det {
3864
+
rockchip,pins =
3865
+
/* sdmmc0_detn */
3866
+
<0 RK_PA7 1 &pcfg_pull_up>;
3867
+
};
3868
+
3869
+
/omit-if-no-ref/
3870
+
sdmmc0_pwren: sdmmc0-pwren {
3871
+
rockchip,pins =
3872
+
/* sdmmc0_pwren */
3873
+
<0 RK_PB6 1 &pcfg_pull_none>;
3874
+
};
3875
+
};
3876
+
3877
+
sdmmc1 {
3878
+
/omit-if-no-ref/
3879
+
sdmmc1m0_bus4: sdmmc1m0-bus4 {
3880
+
rockchip,pins =
3881
+
/* sdmmc1_d0_m0 */
3882
+
<1 RK_PB4 2 &pcfg_pull_up_drv_level_2>,
3883
+
/* sdmmc1_d1_m0 */
3884
+
<1 RK_PB5 2 &pcfg_pull_up_drv_level_2>,
3885
+
/* sdmmc1_d2_m0 */
3886
+
<1 RK_PB6 2 &pcfg_pull_up_drv_level_2>,
3887
+
/* sdmmc1_d3_m0 */
3888
+
<1 RK_PB7 2 &pcfg_pull_up_drv_level_2>;
3889
+
};
3890
+
3891
+
/omit-if-no-ref/
3892
+
sdmmc1m0_clk: sdmmc1m0-clk {
3893
+
rockchip,pins =
3894
+
/* sdmmc1_clk_m0 */
3895
+
<1 RK_PC1 2 &pcfg_pull_up_drv_level_2>;
3896
+
};
3897
+
3898
+
/omit-if-no-ref/
3899
+
sdmmc1m0_cmd: sdmmc1m0-cmd {
3900
+
rockchip,pins =
3901
+
/* sdmmc1_cmd_m0 */
3902
+
<1 RK_PC0 2 &pcfg_pull_up_drv_level_2>;
3903
+
};
3904
+
3905
+
/omit-if-no-ref/
3906
+
sdmmc1m0_det: sdmmc1m0-det {
3907
+
rockchip,pins =
3908
+
/* sdmmc1_detn_m0 */
3909
+
<1 RK_PC3 2 &pcfg_pull_up>;
3910
+
};
3911
+
3912
+
/omit-if-no-ref/
3913
+
sdmmc1m0_pwren: sdmmc1m0-pwren {
3914
+
rockchip,pins =
3915
+
/* sdmmc1m0_pwren */
3916
+
<1 RK_PC2 2 &pcfg_pull_none>;
3917
+
};
3918
+
3919
+
/omit-if-no-ref/
3920
+
sdmmc1m1_bus4: sdmmc1m1-bus4 {
3921
+
rockchip,pins =
3922
+
/* sdmmc1_d0_m1 */
3923
+
<2 RK_PA6 2 &pcfg_pull_up_drv_level_2>,
3924
+
/* sdmmc1_d1_m1 */
3925
+
<2 RK_PA7 2 &pcfg_pull_up_drv_level_2>,
3926
+
/* sdmmc1_d2_m1 */
3927
+
<2 RK_PB0 2 &pcfg_pull_up_drv_level_2>,
3928
+
/* sdmmc1_d3_m1 */
3929
+
<2 RK_PB1 2 &pcfg_pull_up_drv_level_2>;
3930
+
};
3931
+
3932
+
/omit-if-no-ref/
3933
+
sdmmc1m1_clk: sdmmc1m1-clk {
3934
+
rockchip,pins =
3935
+
/* sdmmc1_clk_m1 */
3936
+
<2 RK_PB3 2 &pcfg_pull_up_drv_level_2>;
3937
+
};
3938
+
3939
+
/omit-if-no-ref/
3940
+
sdmmc1m1_cmd: sdmmc1m1-cmd {
3941
+
rockchip,pins =
3942
+
/* sdmmc1_cmd_m1 */
3943
+
<2 RK_PB2 2 &pcfg_pull_up_drv_level_2>;
3944
+
};
3945
+
3946
+
/omit-if-no-ref/
3947
+
sdmmc1m1_det: sdmmc1m1-det {
3948
+
rockchip,pins =
3949
+
/* sdmmc1_detn_m1 */
3950
+
<2 RK_PB5 2 &pcfg_pull_up>;
3951
+
};
3952
+
3953
+
/omit-if-no-ref/
3954
+
sdmmc1m1_pwren: sdmmc1m1-pwren {
3955
+
rockchip,pins =
3956
+
/* sdmmc1m1_pwren */
3957
+
<2 RK_PB4 2 &pcfg_pull_none>;
3958
+
};
3959
+
3960
+
/omit-if-no-ref/
3961
+
sdmmc1m2_det: sdmmc1m2-det {
3962
+
rockchip,pins =
3963
+
/* sdmmc1_detn_m2 */
3964
+
<0 RK_PB6 2 &pcfg_pull_up>;
3965
+
};
3966
+
};
3967
+
3968
+
sdmmc0_testclk {
3969
+
/omit-if-no-ref/
3970
+
sdmmc0_testclk_test: sdmmc0_testclk-test {
3971
+
rockchip,pins =
3972
+
/* sdmmc0_testclk_out */
3973
+
<1 RK_PC4 6 &pcfg_pull_none>;
3974
+
};
3975
+
};
3976
+
3977
+
sdmmc0_testdata {
3978
+
/omit-if-no-ref/
3979
+
sdmmc0_testdata_test: sdmmc0_testdata-test {
3980
+
rockchip,pins =
3981
+
/* sdmmc0_testdata_out */
3982
+
<1 RK_PC5 6 &pcfg_pull_none>;
3983
+
};
3984
+
};
3985
+
3986
+
sdmmc1_testclk {
3987
+
/omit-if-no-ref/
3988
+
sdmmc1_testclkm0_test: sdmmc1_testclkm0-test {
3989
+
rockchip,pins =
3990
+
/* sdmmc1_testclk_out_m0 */
3991
+
<1 RK_PC4 5 &pcfg_pull_none>;
3992
+
};
3993
+
};
3994
+
3995
+
sdmmc1_testdata {
3996
+
/omit-if-no-ref/
3997
+
sdmmc1_testdatam0_test: sdmmc1_testdatam0-test {
3998
+
rockchip,pins =
3999
+
/* sdmmc1_testdata_out_m0 */
4000
+
<1 RK_PC5 5 &pcfg_pull_none>;
4001
+
};
4002
+
};
4003
+
4004
+
spdif {
4005
+
/omit-if-no-ref/
4006
+
spdifm0_rx0: spdifm0-rx0 {
4007
+
rockchip,pins =
4008
+
/* spdif_rx0_m0 */
4009
+
<4 RK_PB4 1 &pcfg_pull_none>;
4010
+
};
4011
+
4012
+
/omit-if-no-ref/
4013
+
spdifm0_rx1: spdifm0-rx1 {
4014
+
rockchip,pins =
4015
+
/* spdif_rx1_m0 */
4016
+
<3 RK_PB4 4 &pcfg_pull_none>;
4017
+
};
4018
+
4019
+
/omit-if-no-ref/
4020
+
spdifm0_tx0: spdifm0-tx0 {
4021
+
rockchip,pins =
4022
+
/* spdif_tx0_m0 */
4023
+
<4 RK_PB5 1 &pcfg_pull_none>;
4024
+
};
4025
+
4026
+
/omit-if-no-ref/
4027
+
spdifm0_tx1: spdifm0-tx1 {
4028
+
rockchip,pins =
4029
+
/* spdif_tx1_m0 */
4030
+
<3 RK_PB5 4 &pcfg_pull_none>;
4031
+
};
4032
+
4033
+
/omit-if-no-ref/
4034
+
spdifm1_rx0: spdifm1-rx0 {
4035
+
rockchip,pins =
4036
+
/* spdif_rx0_m1 */
4037
+
<4 RK_PA0 2 &pcfg_pull_none>;
4038
+
};
4039
+
4040
+
/omit-if-no-ref/
4041
+
spdifm1_rx1: spdifm1-rx1 {
4042
+
rockchip,pins =
4043
+
/* spdif_rx1_m1 */
4044
+
<3 RK_PA2 5 &pcfg_pull_none>;
4045
+
};
4046
+
4047
+
/omit-if-no-ref/
4048
+
spdifm1_tx0: spdifm1-tx0 {
4049
+
rockchip,pins =
4050
+
/* spdif_tx0_m1 */
4051
+
<4 RK_PA1 2 &pcfg_pull_none>;
4052
+
};
4053
+
4054
+
/omit-if-no-ref/
4055
+
spdifm1_tx1: spdifm1-tx1 {
4056
+
rockchip,pins =
4057
+
/* spdif_tx1_m1 */
4058
+
<3 RK_PA3 5 &pcfg_pull_none>;
4059
+
};
4060
+
4061
+
/omit-if-no-ref/
4062
+
spdifm2_rx0: spdifm2-rx0 {
4063
+
rockchip,pins =
4064
+
/* spdif_rx0_m2 */
4065
+
<2 RK_PD6 5 &pcfg_pull_none>;
4066
+
};
4067
+
4068
+
/omit-if-no-ref/
4069
+
spdifm2_rx1: spdifm2-rx1 {
4070
+
rockchip,pins =
4071
+
/* spdif_rx1_m2 */
4072
+
<1 RK_PD4 6 &pcfg_pull_none>;
4073
+
};
4074
+
4075
+
/omit-if-no-ref/
4076
+
spdifm2_tx0: spdifm2-tx0 {
4077
+
rockchip,pins =
4078
+
/* spdif_tx0_m2 */
4079
+
<2 RK_PD7 5 &pcfg_pull_none>;
4080
+
};
4081
+
4082
+
/omit-if-no-ref/
4083
+
spdifm2_tx1: spdifm2-tx1 {
4084
+
rockchip,pins =
4085
+
/* spdif_tx1_m2 */
4086
+
<1 RK_PD5 6 &pcfg_pull_none>;
4087
+
};
4088
+
};
4089
+
4090
+
spi0 {
4091
+
/omit-if-no-ref/
4092
+
spi0m0_pins: spi0m0-pins {
4093
+
rockchip,pins =
4094
+
/* spi0_clk_m0 */
4095
+
<0 RK_PC7 11 &pcfg_pull_none>,
4096
+
/* spi0_miso_m0 */
4097
+
<0 RK_PD1 11 &pcfg_pull_none>,
4098
+
/* spi0_mosi_m0 */
4099
+
<0 RK_PD0 11 &pcfg_pull_none>;
4100
+
};
4101
+
4102
+
/omit-if-no-ref/
4103
+
spi0m0_csn0: spi0m0-csn0 {
4104
+
rockchip,pins =
4105
+
/* spi0m0_csn0 */
4106
+
<0 RK_PC6 11 &pcfg_pull_none>;
4107
+
};
4108
+
/omit-if-no-ref/
4109
+
spi0m0_csn1: spi0m0-csn1 {
4110
+
rockchip,pins =
4111
+
/* spi0m0_csn1 */
4112
+
<0 RK_PC3 11 &pcfg_pull_none>;
4113
+
};
4114
+
4115
+
/omit-if-no-ref/
4116
+
spi0m1_pins: spi0m1-pins {
4117
+
rockchip,pins =
4118
+
/* spi0_clk_m1 */
4119
+
<2 RK_PA5 12 &pcfg_pull_none>,
4120
+
/* spi0_miso_m1 */
4121
+
<2 RK_PA1 12 &pcfg_pull_none>,
4122
+
/* spi0_mosi_m1 */
4123
+
<2 RK_PA0 12 &pcfg_pull_none>;
4124
+
};
4125
+
4126
+
/omit-if-no-ref/
4127
+
spi0m1_csn0: spi0m1-csn0 {
4128
+
rockchip,pins =
4129
+
/* spi0m1_csn0 */
4130
+
<2 RK_PA4 12 &pcfg_pull_none>;
4131
+
};
4132
+
/omit-if-no-ref/
4133
+
spi0m1_csn1: spi0m1-csn1 {
4134
+
rockchip,pins =
4135
+
/* spi0m1_csn1 */
4136
+
<2 RK_PA2 12 &pcfg_pull_none>;
4137
+
};
4138
+
4139
+
/omit-if-no-ref/
4140
+
spi0m2_pins: spi0m2-pins {
4141
+
rockchip,pins =
4142
+
/* spi0_clk_m2 */
4143
+
<1 RK_PA7 9 &pcfg_pull_none>,
4144
+
/* spi0_miso_m2 */
4145
+
<1 RK_PA6 9 &pcfg_pull_none>,
4146
+
/* spi0_mosi_m2 */
4147
+
<1 RK_PA5 9 &pcfg_pull_none>;
4148
+
};
4149
+
4150
+
/omit-if-no-ref/
4151
+
spi0m2_csn0: spi0m2-csn0 {
4152
+
rockchip,pins =
4153
+
/* spi0m2_csn0 */
4154
+
<1 RK_PA4 9 &pcfg_pull_none>;
4155
+
};
4156
+
/omit-if-no-ref/
4157
+
spi0m2_csn1: spi0m2-csn1 {
4158
+
rockchip,pins =
4159
+
/* spi0m2_csn1 */
4160
+
<1 RK_PB2 9 &pcfg_pull_none>;
4161
+
};
4162
+
};
4163
+
4164
+
spi1 {
4165
+
/omit-if-no-ref/
4166
+
spi1m0_pins: spi1m0-pins {
4167
+
rockchip,pins =
4168
+
/* spi1_clk_m0 */
4169
+
<1 RK_PB4 11 &pcfg_pull_none>,
4170
+
/* spi1_miso_m0 */
4171
+
<1 RK_PB6 11 &pcfg_pull_none>,
4172
+
/* spi1_mosi_m0 */
4173
+
<1 RK_PB5 11 &pcfg_pull_none>;
4174
+
};
4175
+
4176
+
/omit-if-no-ref/
4177
+
spi1m0_csn0: spi1m0-csn0 {
4178
+
rockchip,pins =
4179
+
/* spi1m0_csn0 */
4180
+
<1 RK_PB7 11 &pcfg_pull_none>;
4181
+
};
4182
+
/omit-if-no-ref/
4183
+
spi1m0_csn1: spi1m0-csn1 {
4184
+
rockchip,pins =
4185
+
/* spi1m0_csn1 */
4186
+
<1 RK_PC0 11 &pcfg_pull_none>;
4187
+
};
4188
+
4189
+
/omit-if-no-ref/
4190
+
spi1m1_pins: spi1m1-pins {
4191
+
rockchip,pins =
4192
+
/* spi1_clk_m1 */
4193
+
<2 RK_PC5 10 &pcfg_pull_none>,
4194
+
/* spi1_miso_m1 */
4195
+
<2 RK_PC3 10 &pcfg_pull_none>,
4196
+
/* spi1_mosi_m1 */
4197
+
<2 RK_PC2 10 &pcfg_pull_none>;
4198
+
};
4199
+
4200
+
/omit-if-no-ref/
4201
+
spi1m1_csn0: spi1m1-csn0 {
4202
+
rockchip,pins =
4203
+
/* spi1m1_csn0 */
4204
+
<2 RK_PC4 10 &pcfg_pull_none>;
4205
+
};
4206
+
/omit-if-no-ref/
4207
+
spi1m1_csn1: spi1m1-csn1 {
4208
+
rockchip,pins =
4209
+
/* spi1m1_csn1 */
4210
+
<2 RK_PC1 10 &pcfg_pull_none>;
4211
+
};
4212
+
4213
+
/omit-if-no-ref/
4214
+
spi1m2_pins: spi1m2-pins {
4215
+
rockchip,pins =
4216
+
/* spi1_clk_m2 */
4217
+
<3 RK_PC7 10 &pcfg_pull_none>,
4218
+
/* spi1_miso_m2 */
4219
+
<3 RK_PC5 10 &pcfg_pull_none>,
4220
+
/* spi1_mosi_m2 */
4221
+
<3 RK_PC6 10 &pcfg_pull_none>;
4222
+
};
4223
+
4224
+
/omit-if-no-ref/
4225
+
spi1m2_csn0: spi1m2-csn0 {
4226
+
rockchip,pins =
4227
+
/* spi1m2_csn0 */
4228
+
<3 RK_PD0 10 &pcfg_pull_none>;
4229
+
};
4230
+
/omit-if-no-ref/
4231
+
spi1m2_csn1: spi1m2-csn1 {
4232
+
rockchip,pins =
4233
+
/* spi1m2_csn1 */
4234
+
<4 RK_PA0 10 &pcfg_pull_none>;
4235
+
};
4236
+
};
4237
+
4238
+
spi2 {
4239
+
/omit-if-no-ref/
4240
+
spi2m0_pins: spi2m0-pins {
4241
+
rockchip,pins =
4242
+
/* spi2_clk_m0 */
4243
+
<0 RK_PB2 9 &pcfg_pull_none>,
4244
+
/* spi2_miso_m0 */
4245
+
<0 RK_PB1 9 &pcfg_pull_none>,
4246
+
/* spi2_mosi_m0 */
4247
+
<0 RK_PB3 9 &pcfg_pull_none>;
4248
+
};
4249
+
4250
+
/omit-if-no-ref/
4251
+
spi2m0_csn0: spi2m0-csn0 {
4252
+
rockchip,pins =
4253
+
/* spi2m0_csn0 */
4254
+
<0 RK_PB0 9 &pcfg_pull_none>;
4255
+
};
4256
+
/omit-if-no-ref/
4257
+
spi2m0_csn1: spi2m0-csn1 {
4258
+
rockchip,pins =
4259
+
/* spi2m0_csn1 */
4260
+
<0 RK_PA7 9 &pcfg_pull_none>;
4261
+
};
4262
+
4263
+
/omit-if-no-ref/
4264
+
spi2m1_pins: spi2m1-pins {
4265
+
rockchip,pins =
4266
+
/* spi2_clk_m1 */
4267
+
<1 RK_PD5 11 &pcfg_pull_none>,
4268
+
/* spi2_miso_m1 */
4269
+
<1 RK_PC5 11 &pcfg_pull_none>,
4270
+
/* spi2_mosi_m1 */
4271
+
<1 RK_PC4 11 &pcfg_pull_none>;
4272
+
};
4273
+
4274
+
/omit-if-no-ref/
4275
+
spi2m1_csn0: spi2m1-csn0 {
4276
+
rockchip,pins =
4277
+
/* spi2m1_csn0 */
4278
+
<1 RK_PC3 11 &pcfg_pull_none>;
4279
+
};
4280
+
/omit-if-no-ref/
4281
+
spi2m1_csn1: spi2m1-csn1 {
4282
+
rockchip,pins =
4283
+
/* spi2m1_csn1 */
4284
+
<1 RK_PC2 11 &pcfg_pull_none>;
4285
+
};
4286
+
4287
+
/omit-if-no-ref/
4288
+
spi2m2_pins: spi2m2-pins {
4289
+
rockchip,pins =
4290
+
/* spi2_clk_m2 */
4291
+
<3 RK_PA4 10 &pcfg_pull_none>,
4292
+
/* spi2_miso_m2 */
4293
+
<3 RK_PC1 10 &pcfg_pull_none>,
4294
+
/* spi2_mosi_m2 */
4295
+
<3 RK_PB0 10 &pcfg_pull_none>;
4296
+
};
4297
+
4298
+
/omit-if-no-ref/
4299
+
spi2m2_csn0: spi2m2-csn0 {
4300
+
rockchip,pins =
4301
+
/* spi2m2_csn0 */
4302
+
<3 RK_PC4 10 &pcfg_pull_none>;
4303
+
};
4304
+
/omit-if-no-ref/
4305
+
spi2m2_csn1: spi2m2-csn1 {
4306
+
rockchip,pins =
4307
+
/* spi2m2_csn1 */
4308
+
<3 RK_PA5 10 &pcfg_pull_none>;
4309
+
};
4310
+
};
4311
+
4312
+
spi3 {
4313
+
/omit-if-no-ref/
4314
+
spi3m0_pins: spi3m0-pins {
4315
+
rockchip,pins =
4316
+
/* spi3_clk_m0 */
4317
+
<3 RK_PA0 10 &pcfg_pull_none>,
4318
+
/* spi3_miso_m0 */
4319
+
<3 RK_PA2 10 &pcfg_pull_none>,
4320
+
/* spi3_mosi_m0 */
4321
+
<3 RK_PA1 10 &pcfg_pull_none>;
4322
+
};
4323
+
4324
+
/omit-if-no-ref/
4325
+
spi3m0_csn0: spi3m0-csn0 {
4326
+
rockchip,pins =
4327
+
/* spi3m0_csn0 */
4328
+
<3 RK_PA3 10 &pcfg_pull_none>;
4329
+
};
4330
+
/omit-if-no-ref/
4331
+
spi3m0_csn1: spi3m0-csn1 {
4332
+
rockchip,pins =
4333
+
/* spi3m0_csn1 */
4334
+
<2 RK_PD7 10 &pcfg_pull_none>;
4335
+
};
4336
+
4337
+
/omit-if-no-ref/
4338
+
spi3m1_pins: spi3m1-pins {
4339
+
rockchip,pins =
4340
+
/* spi3_clk_m1 */
4341
+
<3 RK_PD4 10 &pcfg_pull_none>,
4342
+
/* spi3_miso_m1 */
4343
+
<3 RK_PD5 10 &pcfg_pull_none>,
4344
+
/* spi3_mosi_m1 */
4345
+
<3 RK_PD6 10 &pcfg_pull_none>;
4346
+
};
4347
+
4348
+
/omit-if-no-ref/
4349
+
spi3m1_csn0: spi3m1-csn0 {
4350
+
rockchip,pins =
4351
+
/* spi3m1_csn0 */
4352
+
<3 RK_PB6 10 &pcfg_pull_none>;
4353
+
};
4354
+
/omit-if-no-ref/
4355
+
spi3m1_csn1: spi3m1-csn1 {
4356
+
rockchip,pins =
4357
+
/* spi3m1_csn1 */
4358
+
<3 RK_PD7 10 &pcfg_pull_none>;
4359
+
};
4360
+
4361
+
/omit-if-no-ref/
4362
+
spi3m2_pins: spi3m2-pins {
4363
+
rockchip,pins =
4364
+
/* spi3_clk_m2 */
4365
+
<4 RK_PA7 9 &pcfg_pull_none>,
4366
+
/* spi3_miso_m2 */
4367
+
<4 RK_PA6 9 &pcfg_pull_none>,
4368
+
/* spi3_mosi_m2 */
4369
+
<4 RK_PA4 9 &pcfg_pull_none>;
4370
+
};
4371
+
4372
+
/omit-if-no-ref/
4373
+
spi3m2_csn0: spi3m2-csn0 {
4374
+
rockchip,pins =
4375
+
/* spi3m2_csn0 */
4376
+
<4 RK_PA3 9 &pcfg_pull_none>;
4377
+
};
4378
+
/omit-if-no-ref/
4379
+
spi3m2_csn1: spi3m2-csn1 {
4380
+
rockchip,pins =
4381
+
/* spi3m2_csn1 */
4382
+
<4 RK_PB3 10 &pcfg_pull_none>;
4383
+
};
4384
+
};
4385
+
4386
+
spi4 {
4387
+
/omit-if-no-ref/
4388
+
spi4m0_pins: spi4m0-pins {
4389
+
rockchip,pins =
4390
+
/* spi4_clk_m0 */
4391
+
<4 RK_PC7 12 &pcfg_pull_none>,
4392
+
/* spi4_miso_m0 */
4393
+
<4 RK_PC6 12 &pcfg_pull_none>,
4394
+
/* spi4_mosi_m0 */
4395
+
<4 RK_PC5 12 &pcfg_pull_none>;
4396
+
};
4397
+
4398
+
/omit-if-no-ref/
4399
+
spi4m0_csn0: spi4m0-csn0 {
4400
+
rockchip,pins =
4401
+
/* spi4m0_csn0 */
4402
+
<4 RK_PC4 12 &pcfg_pull_none>;
4403
+
};
4404
+
/omit-if-no-ref/
4405
+
spi4m0_csn1: spi4m0-csn1 {
4406
+
rockchip,pins =
4407
+
/* spi4m0_csn1 */
4408
+
<4 RK_PC0 12 &pcfg_pull_none>;
4409
+
};
4410
+
4411
+
/omit-if-no-ref/
4412
+
spi4m1_pins: spi4m1-pins {
4413
+
rockchip,pins =
4414
+
/* spi4_clk_m1 */
4415
+
<3 RK_PD1 10 &pcfg_pull_none>,
4416
+
/* spi4_miso_m1 */
4417
+
<3 RK_PC2 10 &pcfg_pull_none>,
4418
+
/* spi4_mosi_m1 */
4419
+
<3 RK_PC3 10 &pcfg_pull_none>;
4420
+
};
4421
+
4422
+
/omit-if-no-ref/
4423
+
spi4m1_csn0: spi4m1-csn0 {
4424
+
rockchip,pins =
4425
+
/* spi4m1_csn0 */
4426
+
<3 RK_PB1 10 &pcfg_pull_none>;
4427
+
};
4428
+
/omit-if-no-ref/
4429
+
spi4m1_csn1: spi4m1-csn1 {
4430
+
rockchip,pins =
4431
+
/* spi4m1_csn1 */
4432
+
<3 RK_PD2 10 &pcfg_pull_none>;
4433
+
};
4434
+
4435
+
/omit-if-no-ref/
4436
+
spi4m2_pins: spi4m2-pins {
4437
+
rockchip,pins =
4438
+
/* spi4_clk_m2 */
4439
+
<4 RK_PB0 9 &pcfg_pull_none>,
4440
+
/* spi4_miso_m2 */
4441
+
<4 RK_PB2 9 &pcfg_pull_none>,
4442
+
/* spi4_mosi_m2 */
4443
+
<4 RK_PB1 9 &pcfg_pull_none>;
4444
+
};
4445
+
4446
+
/omit-if-no-ref/
4447
+
spi4m2_csn0: spi4m2-csn0 {
4448
+
rockchip,pins =
4449
+
/* spi4m2_csn0 */
4450
+
<4 RK_PB3 9 &pcfg_pull_none>;
4451
+
};
4452
+
/omit-if-no-ref/
4453
+
spi4m2_csn1: spi4m2-csn1 {
4454
+
rockchip,pins =
4455
+
/* spi4m2_csn1 */
4456
+
<4 RK_PA5 9 &pcfg_pull_none>;
4457
+
};
4458
+
4459
+
/omit-if-no-ref/
4460
+
spi4m3_pins: spi4m3-pins {
4461
+
rockchip,pins =
4462
+
/* spi4_clk_m3 */
4463
+
<2 RK_PB3 10 &pcfg_pull_none>,
4464
+
/* spi4_miso_m3 */
4465
+
<2 RK_PB5 10 &pcfg_pull_none>,
4466
+
/* spi4_mosi_m3 */
4467
+
<2 RK_PB4 10 &pcfg_pull_none>;
4468
+
};
4469
+
4470
+
/omit-if-no-ref/
4471
+
spi4m3_csn0: spi4m3-csn0 {
4472
+
rockchip,pins =
4473
+
/* spi4m3_csn0 */
4474
+
<2 RK_PB2 10 &pcfg_pull_none>;
4475
+
};
4476
+
/omit-if-no-ref/
4477
+
spi4m3_csn1: spi4m3-csn1 {
4478
+
rockchip,pins =
4479
+
/* spi4m3_csn1 */
4480
+
<2 RK_PA6 10 &pcfg_pull_none>;
4481
+
};
4482
+
};
4483
+
4484
+
test_clk {
4485
+
/omit-if-no-ref/
4486
+
test_clk_pins: test_clk-pins {
4487
+
rockchip,pins =
4488
+
/* test_clk_out */
4489
+
<2 RK_PA5 5 &pcfg_pull_none>;
4490
+
};
4491
+
};
4492
+
4493
+
tsadc {
4494
+
/omit-if-no-ref/
4495
+
tsadcm0_pins: tsadcm0-pins {
4496
+
rockchip,pins =
4497
+
/* tsadc_ctrl_m0 */
4498
+
<0 RK_PA1 9 &pcfg_pull_none>;
4499
+
};
4500
+
4501
+
/omit-if-no-ref/
4502
+
tsadcm1_pins: tsadcm1-pins {
4503
+
rockchip,pins =
4504
+
/* tsadc_ctrl_m1 */
4505
+
<0 RK_PA3 10 &pcfg_pull_none>;
4506
+
};
4507
+
};
4508
+
4509
+
tsadc_ctrl {
4510
+
/omit-if-no-ref/
4511
+
tsadc_ctrl_pins: tsadc_ctrl-pins {
4512
+
rockchip,pins =
4513
+
/* tsadc_ctrl_org */
4514
+
<0 RK_PA1 10 &pcfg_pull_none>;
4515
+
};
4516
+
};
4517
+
4518
+
uart0 {
4519
+
/omit-if-no-ref/
4520
+
uart0m0_xfer: uart0m0-xfer {
4521
+
rockchip,pins =
4522
+
/* uart0_rx_m0 */
4523
+
<0 RK_PD5 9 &pcfg_pull_up>,
4524
+
/* uart0_tx_m0 */
4525
+
<0 RK_PD4 9 &pcfg_pull_up>;
4526
+
};
4527
+
4528
+
/omit-if-no-ref/
4529
+
uart0m1_xfer: uart0m1-xfer {
4530
+
rockchip,pins =
4531
+
/* uart0_rx_m1 */
4532
+
<2 RK_PA0 9 &pcfg_pull_up>,
4533
+
/* uart0_tx_m1 */
4534
+
<2 RK_PA1 9 &pcfg_pull_up>;
4535
+
};
4536
+
};
4537
+
4538
+
uart1 {
4539
+
/omit-if-no-ref/
4540
+
uart1m0_xfer: uart1m0-xfer {
4541
+
rockchip,pins =
4542
+
/* uart1_rx_m0 */
4543
+
<0 RK_PC0 10 &pcfg_pull_up>,
4544
+
/* uart1_tx_m0 */
4545
+
<0 RK_PB7 10 &pcfg_pull_up>;
4546
+
};
4547
+
4548
+
/omit-if-no-ref/
4549
+
uart1m0_ctsn: uart1m0-ctsn {
4550
+
rockchip,pins =
4551
+
/* uart1m0_ctsn */
4552
+
<0 RK_PD2 13 &pcfg_pull_none>;
4553
+
};
4554
+
/omit-if-no-ref/
4555
+
uart1m0_rtsn: uart1m0-rtsn {
4556
+
rockchip,pins =
4557
+
/* uart1m0_rtsn */
4558
+
<0 RK_PD3 13 &pcfg_pull_none>;
4559
+
};
4560
+
4561
+
/omit-if-no-ref/
4562
+
uart1m1_xfer: uart1m1-xfer {
4563
+
rockchip,pins =
4564
+
/* uart1_rx_m1 */
4565
+
<2 RK_PB1 9 &pcfg_pull_up>,
4566
+
/* uart1_tx_m1 */
4567
+
<2 RK_PB0 9 &pcfg_pull_up>;
4568
+
};
4569
+
4570
+
/omit-if-no-ref/
4571
+
uart1m1_ctsn: uart1m1-ctsn {
4572
+
rockchip,pins =
4573
+
/* uart1m1_ctsn */
4574
+
<2 RK_PB2 9 &pcfg_pull_none>;
4575
+
};
4576
+
/omit-if-no-ref/
4577
+
uart1m1_rtsn: uart1m1-rtsn {
4578
+
rockchip,pins =
4579
+
/* uart1m1_rtsn */
4580
+
<2 RK_PB3 9 &pcfg_pull_none>;
4581
+
};
4582
+
4583
+
/omit-if-no-ref/
4584
+
uart1m2_xfer: uart1m2-xfer {
4585
+
rockchip,pins =
4586
+
/* uart1_rx_m2 */
4587
+
<3 RK_PA6 9 &pcfg_pull_up>,
4588
+
/* uart1_tx_m2 */
4589
+
<3 RK_PA7 9 &pcfg_pull_up>;
4590
+
};
4591
+
4592
+
/omit-if-no-ref/
4593
+
uart1m2_ctsn: uart1m2-ctsn {
4594
+
rockchip,pins =
4595
+
/* uart1m2_ctsn */
4596
+
<3 RK_PA4 9 &pcfg_pull_none>;
4597
+
};
4598
+
/omit-if-no-ref/
4599
+
uart1m2_rtsn: uart1m2-rtsn {
4600
+
rockchip,pins =
4601
+
/* uart1m2_rtsn */
4602
+
<3 RK_PA5 9 &pcfg_pull_none>;
4603
+
};
4604
+
};
4605
+
4606
+
uart2 {
4607
+
/omit-if-no-ref/
4608
+
uart2m0_xfer: uart2m0-xfer {
4609
+
rockchip,pins =
4610
+
/* uart2_rx_m0 */
4611
+
<1 RK_PC7 9 &pcfg_pull_up>,
4612
+
/* uart2_tx_m0 */
4613
+
<1 RK_PC6 9 &pcfg_pull_up>;
4614
+
};
4615
+
4616
+
/omit-if-no-ref/
4617
+
uart2m0_ctsn: uart2m0-ctsn {
4618
+
rockchip,pins =
4619
+
/* uart2m0_ctsn */
4620
+
<1 RK_PC5 10 &pcfg_pull_none>;
4621
+
};
4622
+
/omit-if-no-ref/
4623
+
uart2m0_rtsn: uart2m0-rtsn {
4624
+
rockchip,pins =
4625
+
/* uart2m0_rtsn */
4626
+
<1 RK_PC4 10 &pcfg_pull_none>;
4627
+
};
4628
+
4629
+
/omit-if-no-ref/
4630
+
uart2m1_xfer: uart2m1-xfer {
4631
+
rockchip,pins =
4632
+
/* uart2_rx_m1 */
4633
+
<4 RK_PB4 10 &pcfg_pull_up>,
4634
+
/* uart2_tx_m1 */
4635
+
<4 RK_PB5 10 &pcfg_pull_up>;
4636
+
};
4637
+
4638
+
/omit-if-no-ref/
4639
+
uart2m1_ctsn: uart2m1-ctsn {
4640
+
rockchip,pins =
4641
+
/* uart2m1_ctsn */
4642
+
<4 RK_PB1 12 &pcfg_pull_none>;
4643
+
};
4644
+
/omit-if-no-ref/
4645
+
uart2m1_rtsn: uart2m1-rtsn {
4646
+
rockchip,pins =
4647
+
/* uart2m1_rtsn */
4648
+
<4 RK_PB0 12 &pcfg_pull_none>;
4649
+
};
4650
+
4651
+
/omit-if-no-ref/
4652
+
uart2m2_xfer: uart2m2-xfer {
4653
+
rockchip,pins =
4654
+
/* uart2_rx_m2 */
4655
+
<3 RK_PB7 9 &pcfg_pull_up>,
4656
+
/* uart2_tx_m2 */
4657
+
<3 RK_PC0 9 &pcfg_pull_up>;
4658
+
};
4659
+
4660
+
/omit-if-no-ref/
4661
+
uart2m2_ctsn: uart2m2-ctsn {
4662
+
rockchip,pins =
4663
+
/* uart2m2_ctsn */
4664
+
<3 RK_PD3 9 &pcfg_pull_none>;
4665
+
};
4666
+
/omit-if-no-ref/
4667
+
uart2m2_rtsn: uart2m2-rtsn {
4668
+
rockchip,pins =
4669
+
/* uart2m2_rtsn */
4670
+
<3 RK_PD2 9 &pcfg_pull_none>;
4671
+
};
4672
+
};
4673
+
4674
+
uart3 {
4675
+
/omit-if-no-ref/
4676
+
uart3m0_xfer: uart3m0-xfer {
4677
+
rockchip,pins =
4678
+
/* uart3_rx_m0 */
4679
+
<3 RK_PA1 9 &pcfg_pull_up>,
4680
+
/* uart3_tx_m0 */
4681
+
<3 RK_PA0 9 &pcfg_pull_up>;
4682
+
};
4683
+
4684
+
/omit-if-no-ref/
4685
+
uart3m0_ctsn: uart3m0-ctsn {
4686
+
rockchip,pins =
4687
+
/* uart3m0_ctsn */
4688
+
<3 RK_PA2 9 &pcfg_pull_none>;
4689
+
};
4690
+
/omit-if-no-ref/
4691
+
uart3m0_rtsn: uart3m0-rtsn {
4692
+
rockchip,pins =
4693
+
/* uart3m0_rtsn */
4694
+
<3 RK_PA3 9 &pcfg_pull_none>;
4695
+
};
4696
+
4697
+
/omit-if-no-ref/
4698
+
uart3m1_xfer: uart3m1-xfer {
4699
+
rockchip,pins =
4700
+
/* uart3_rx_m1 */
4701
+
<4 RK_PA1 9 &pcfg_pull_up>,
4702
+
/* uart3_tx_m1 */
4703
+
<4 RK_PA0 9 &pcfg_pull_up>;
4704
+
};
4705
+
4706
+
/omit-if-no-ref/
4707
+
uart3m1_ctsn: uart3m1-ctsn {
4708
+
rockchip,pins =
4709
+
/* uart3m1_ctsn */
4710
+
<3 RK_PB7 10 &pcfg_pull_none>;
4711
+
};
4712
+
/omit-if-no-ref/
4713
+
uart3m1_rtsn: uart3m1-rtsn {
4714
+
rockchip,pins =
4715
+
/* uart3m1_rtsn */
4716
+
<3 RK_PC0 10 &pcfg_pull_none>;
4717
+
};
4718
+
4719
+
/omit-if-no-ref/
4720
+
uart3m2_xfer: uart3m2-xfer {
4721
+
rockchip,pins =
4722
+
/* uart3_rx_m2 */
4723
+
<1 RK_PC1 9 &pcfg_pull_up>,
4724
+
/* uart3_tx_m2 */
4725
+
<1 RK_PC0 9 &pcfg_pull_up>;
4726
+
};
4727
+
4728
+
/omit-if-no-ref/
4729
+
uart3m2_ctsn: uart3m2-ctsn {
4730
+
rockchip,pins =
4731
+
/* uart3m2_ctsn */
4732
+
<1 RK_PB6 9 &pcfg_pull_none>;
4733
+
};
4734
+
/omit-if-no-ref/
4735
+
uart3m2_rtsn: uart3m2-rtsn {
4736
+
rockchip,pins =
4737
+
/* uart3m2_rtsn */
4738
+
<1 RK_PB7 9 &pcfg_pull_none>;
4739
+
};
4740
+
};
4741
+
4742
+
uart4 {
4743
+
/omit-if-no-ref/
4744
+
uart4m0_xfer: uart4m0-xfer {
4745
+
rockchip,pins =
4746
+
/* uart4_rx_m0 */
4747
+
<2 RK_PD1 9 &pcfg_pull_up>,
4748
+
/* uart4_tx_m0 */
4749
+
<2 RK_PD0 9 &pcfg_pull_up>;
4750
+
};
4751
+
4752
+
/omit-if-no-ref/
4753
+
uart4m0_ctsn: uart4m0-ctsn {
4754
+
rockchip,pins =
4755
+
/* uart4m0_ctsn */
4756
+
<2 RK_PC6 9 &pcfg_pull_none>;
4757
+
};
4758
+
/omit-if-no-ref/
4759
+
uart4m0_rtsn: uart4m0-rtsn {
4760
+
rockchip,pins =
4761
+
/* uart4m0_rtsn */
4762
+
<2 RK_PC7 9 &pcfg_pull_none>;
4763
+
};
4764
+
4765
+
/omit-if-no-ref/
4766
+
uart4m1_xfer: uart4m1-xfer {
4767
+
rockchip,pins =
4768
+
/* uart4_rx_m1 */
4769
+
<1 RK_PC5 9 &pcfg_pull_up>,
4770
+
/* uart4_tx_m1 */
4771
+
<1 RK_PC4 9 &pcfg_pull_up>;
4772
+
};
4773
+
4774
+
/omit-if-no-ref/
4775
+
uart4m1_ctsn: uart4m1-ctsn {
4776
+
rockchip,pins =
4777
+
/* uart4m1_ctsn */
4778
+
<1 RK_PC3 9 &pcfg_pull_none>;
4779
+
};
4780
+
/omit-if-no-ref/
4781
+
uart4m1_rtsn: uart4m1-rtsn {
4782
+
rockchip,pins =
4783
+
/* uart4m1_rtsn */
4784
+
<1 RK_PC2 9 &pcfg_pull_none>;
4785
+
};
4786
+
4787
+
/omit-if-no-ref/
4788
+
uart4m2_xfer: uart4m2-xfer {
4789
+
rockchip,pins =
4790
+
/* uart4_rx_m2 */
4791
+
<0 RK_PB5 10 &pcfg_pull_up>,
4792
+
/* uart4_tx_m2 */
4793
+
<0 RK_PB4 10 &pcfg_pull_up>;
4794
+
};
4795
+
};
4796
+
4797
+
uart5 {
4798
+
/omit-if-no-ref/
4799
+
uart5m0_xfer: uart5m0-xfer {
4800
+
rockchip,pins =
4801
+
/* uart5_rx_m0 */
4802
+
<3 RK_PD4 9 &pcfg_pull_up>,
4803
+
/* uart5_tx_m0 */
4804
+
<3 RK_PD5 9 &pcfg_pull_up>;
4805
+
};
4806
+
4807
+
/omit-if-no-ref/
4808
+
uart5m0_ctsn: uart5m0-ctsn {
4809
+
rockchip,pins =
4810
+
/* uart5m0_ctsn */
4811
+
<3 RK_PD6 9 &pcfg_pull_none>;
4812
+
};
4813
+
/omit-if-no-ref/
4814
+
uart5m0_rtsn: uart5m0-rtsn {
4815
+
rockchip,pins =
4816
+
/* uart5m0_rtsn */
4817
+
<3 RK_PD7 9 &pcfg_pull_none>;
4818
+
};
4819
+
4820
+
/omit-if-no-ref/
4821
+
uart5m1_xfer: uart5m1-xfer {
4822
+
rockchip,pins =
4823
+
/* uart5_rx_m1 */
4824
+
<4 RK_PB1 10 &pcfg_pull_up>,
4825
+
/* uart5_tx_m1 */
4826
+
<4 RK_PB0 10 &pcfg_pull_up>;
4827
+
};
4828
+
4829
+
/omit-if-no-ref/
4830
+
uart5m1_ctsn: uart5m1-ctsn {
4831
+
rockchip,pins =
4832
+
/* uart5m1_ctsn */
4833
+
<4 RK_PA5 10 &pcfg_pull_none>;
4834
+
};
4835
+
/omit-if-no-ref/
4836
+
uart5m1_rtsn: uart5m1-rtsn {
4837
+
rockchip,pins =
4838
+
/* uart5m1_rtsn */
4839
+
<4 RK_PA3 10 &pcfg_pull_none>;
4840
+
};
4841
+
4842
+
/omit-if-no-ref/
4843
+
uart5m2_xfer: uart5m2-xfer {
4844
+
rockchip,pins =
4845
+
/* uart5_rx_m2 */
4846
+
<2 RK_PA4 9 &pcfg_pull_up>,
4847
+
/* uart5_tx_m2 */
4848
+
<2 RK_PA5 9 &pcfg_pull_up>;
4849
+
};
4850
+
4851
+
/omit-if-no-ref/
4852
+
uart5m2_ctsn: uart5m2-ctsn {
4853
+
rockchip,pins =
4854
+
/* uart5m2_ctsn */
4855
+
<2 RK_PA3 10 &pcfg_pull_none>;
4856
+
};
4857
+
/omit-if-no-ref/
4858
+
uart5m2_rtsn: uart5m2-rtsn {
4859
+
rockchip,pins =
4860
+
/* uart5m2_rtsn */
4861
+
<2 RK_PA2 10 &pcfg_pull_none>;
4862
+
};
4863
+
};
4864
+
4865
+
uart6 {
4866
+
/omit-if-no-ref/
4867
+
uart6m0_xfer: uart6m0-xfer {
4868
+
rockchip,pins =
4869
+
/* uart6_rx_m0 */
4870
+
<4 RK_PA6 10 &pcfg_pull_up>,
4871
+
/* uart6_tx_m0 */
4872
+
<4 RK_PA4 10 &pcfg_pull_up>;
4873
+
};
4874
+
4875
+
/omit-if-no-ref/
4876
+
uart6m0_ctsn: uart6m0-ctsn {
4877
+
rockchip,pins =
4878
+
/* uart6m0_ctsn */
4879
+
<4 RK_PB1 11 &pcfg_pull_none>;
4880
+
};
4881
+
/omit-if-no-ref/
4882
+
uart6m0_rtsn: uart6m0-rtsn {
4883
+
rockchip,pins =
4884
+
/* uart6m0_rtsn */
4885
+
<4 RK_PB0 11 &pcfg_pull_none>;
4886
+
};
4887
+
4888
+
/omit-if-no-ref/
4889
+
uart6m1_xfer: uart6m1-xfer {
4890
+
rockchip,pins =
4891
+
/* uart6_rx_m1 */
4892
+
<2 RK_PD3 9 &pcfg_pull_up>,
4893
+
/* uart6_tx_m1 */
4894
+
<2 RK_PD2 9 &pcfg_pull_up>;
4895
+
};
4896
+
4897
+
/omit-if-no-ref/
4898
+
uart6m1_ctsn: uart6m1-ctsn {
4899
+
rockchip,pins =
4900
+
/* uart6m1_ctsn */
4901
+
<2 RK_PD5 9 &pcfg_pull_none>;
4902
+
};
4903
+
/omit-if-no-ref/
4904
+
uart6m1_rtsn: uart6m1-rtsn {
4905
+
rockchip,pins =
4906
+
/* uart6m1_rtsn */
4907
+
<2 RK_PD4 9 &pcfg_pull_none>;
4908
+
};
4909
+
4910
+
/omit-if-no-ref/
4911
+
uart6m2_xfer: uart6m2-xfer {
4912
+
rockchip,pins =
4913
+
/* uart6_rx_m2 */
4914
+
<1 RK_PB3 9 &pcfg_pull_up>,
4915
+
/* uart6_tx_m2 */
4916
+
<1 RK_PB0 9 &pcfg_pull_up>;
4917
+
};
4918
+
4919
+
/omit-if-no-ref/
4920
+
uart6m2_ctsn: uart6m2-ctsn {
4921
+
rockchip,pins =
4922
+
/* uart6m2_ctsn */
4923
+
<1 RK_PA3 10 &pcfg_pull_none>;
4924
+
};
4925
+
/omit-if-no-ref/
4926
+
uart6m2_rtsn: uart6m2-rtsn {
4927
+
rockchip,pins =
4928
+
/* uart6m2_rtsn */
4929
+
<1 RK_PA2 10 &pcfg_pull_none>;
4930
+
};
4931
+
4932
+
/omit-if-no-ref/
4933
+
uart6m3_xfer: uart6m3-xfer {
4934
+
rockchip,pins =
4935
+
/* uart6_rx_m3 */
4936
+
<4 RK_PC5 13 &pcfg_pull_up>,
4937
+
/* uart6_tx_m3 */
4938
+
<4 RK_PC4 13 &pcfg_pull_up>;
4939
+
};
4940
+
};
4941
+
4942
+
uart7 {
4943
+
/omit-if-no-ref/
4944
+
uart7m0_xfer: uart7m0-xfer {
4945
+
rockchip,pins =
4946
+
/* uart7_rx_m0 */
4947
+
<2 RK_PB7 9 &pcfg_pull_up>,
4948
+
/* uart7_tx_m0 */
4949
+
<2 RK_PB6 9 &pcfg_pull_up>;
4950
+
};
4951
+
4952
+
/omit-if-no-ref/
4953
+
uart7m0_ctsn: uart7m0-ctsn {
4954
+
rockchip,pins =
4955
+
/* uart7m0_ctsn */
4956
+
<2 RK_PB4 9 &pcfg_pull_none>;
4957
+
};
4958
+
/omit-if-no-ref/
4959
+
uart7m0_rtsn: uart7m0-rtsn {
4960
+
rockchip,pins =
4961
+
/* uart7m0_rtsn */
4962
+
<2 RK_PB5 9 &pcfg_pull_none>;
4963
+
};
4964
+
4965
+
/omit-if-no-ref/
4966
+
uart7m1_xfer: uart7m1-xfer {
4967
+
rockchip,pins =
4968
+
/* uart7_rx_m1 */
4969
+
<1 RK_PA3 9 &pcfg_pull_up>,
4970
+
/* uart7_tx_m1 */
4971
+
<1 RK_PA2 9 &pcfg_pull_up>;
4972
+
};
4973
+
4974
+
/omit-if-no-ref/
4975
+
uart7m1_ctsn: uart7m1-ctsn {
4976
+
rockchip,pins =
4977
+
/* uart7m1_ctsn */
4978
+
<1 RK_PA1 9 &pcfg_pull_none>;
4979
+
};
4980
+
/omit-if-no-ref/
4981
+
uart7m1_rtsn: uart7m1-rtsn {
4982
+
rockchip,pins =
4983
+
/* uart7m1_rtsn */
4984
+
<1 RK_PA0 9 &pcfg_pull_none>;
4985
+
};
4986
+
4987
+
/omit-if-no-ref/
4988
+
uart7m2_xfer: uart7m2-xfer {
4989
+
rockchip,pins =
4990
+
/* uart7_rx_m2 */
4991
+
<2 RK_PA0 10 &pcfg_pull_up>,
4992
+
/* uart7_tx_m2 */
4993
+
<2 RK_PA1 10 &pcfg_pull_up>;
4994
+
};
4995
+
};
4996
+
4997
+
uart8 {
4998
+
/omit-if-no-ref/
4999
+
uart8m0_xfer: uart8m0-xfer {
5000
+
rockchip,pins =
5001
+
/* uart8_rx_m0 */
5002
+
<3 RK_PC5 9 &pcfg_pull_up>,
5003
+
/* uart8_tx_m0 */
5004
+
<3 RK_PC6 9 &pcfg_pull_up>;
5005
+
};
5006
+
5007
+
/omit-if-no-ref/
5008
+
uart8m0_ctsn: uart8m0-ctsn {
5009
+
rockchip,pins =
5010
+
/* uart8m0_ctsn */
5011
+
<3 RK_PD0 9 &pcfg_pull_none>;
5012
+
};
5013
+
/omit-if-no-ref/
5014
+
uart8m0_rtsn: uart8m0-rtsn {
5015
+
rockchip,pins =
5016
+
/* uart8m0_rtsn */
5017
+
<3 RK_PC7 9 &pcfg_pull_none>;
5018
+
};
5019
+
5020
+
/omit-if-no-ref/
5021
+
uart8m1_xfer: uart8m1-xfer {
5022
+
rockchip,pins =
5023
+
/* uart8_rx_m1 */
5024
+
<2 RK_PA7 9 &pcfg_pull_up>,
5025
+
/* uart8_tx_m1 */
5026
+
<2 RK_PA6 9 &pcfg_pull_up>;
5027
+
};
5028
+
5029
+
/omit-if-no-ref/
5030
+
uart8m1_ctsn: uart8m1-ctsn {
5031
+
rockchip,pins =
5032
+
/* uart8m1_ctsn */
5033
+
<2 RK_PB7 10 &pcfg_pull_none>;
5034
+
};
5035
+
/omit-if-no-ref/
5036
+
uart8m1_rtsn: uart8m1-rtsn {
5037
+
rockchip,pins =
5038
+
/* uart8m1_rtsn */
5039
+
<2 RK_PB6 10 &pcfg_pull_none>;
5040
+
};
5041
+
5042
+
/omit-if-no-ref/
5043
+
uart8m2_xfer: uart8m2-xfer {
5044
+
rockchip,pins =
5045
+
/* uart8_rx_m2 */
5046
+
<0 RK_PC2 10 &pcfg_pull_up>,
5047
+
/* uart8_tx_m2 */
5048
+
<0 RK_PC1 10 &pcfg_pull_up>;
5049
+
};
5050
+
};
5051
+
5052
+
uart9 {
5053
+
/omit-if-no-ref/
5054
+
uart9m0_xfer: uart9m0-xfer {
5055
+
rockchip,pins =
5056
+
/* uart9_rx_m0 */
5057
+
<2 RK_PC0 9 &pcfg_pull_up>,
5058
+
/* uart9_tx_m0 */
5059
+
<2 RK_PC1 9 &pcfg_pull_up>;
5060
+
};
5061
+
5062
+
/omit-if-no-ref/
5063
+
uart9m0_ctsn: uart9m0-ctsn {
5064
+
rockchip,pins =
5065
+
/* uart9m0_ctsn */
5066
+
<2 RK_PD7 9 &pcfg_pull_none>;
5067
+
};
5068
+
/omit-if-no-ref/
5069
+
uart9m0_rtsn: uart9m0-rtsn {
5070
+
rockchip,pins =
5071
+
/* uart9m0_rtsn */
5072
+
<2 RK_PD6 9 &pcfg_pull_none>;
5073
+
};
5074
+
5075
+
/omit-if-no-ref/
5076
+
uart9m1_xfer: uart9m1-xfer {
5077
+
rockchip,pins =
5078
+
/* uart9_rx_m1 */
5079
+
<3 RK_PB2 9 &pcfg_pull_up>,
5080
+
/* uart9_tx_m1 */
5081
+
<3 RK_PB3 9 &pcfg_pull_up>;
5082
+
};
5083
+
5084
+
/omit-if-no-ref/
5085
+
uart9m1_ctsn: uart9m1-ctsn {
5086
+
rockchip,pins =
5087
+
/* uart9m1_ctsn */
5088
+
<3 RK_PB5 9 &pcfg_pull_none>;
5089
+
};
5090
+
/omit-if-no-ref/
5091
+
uart9m1_rtsn: uart9m1-rtsn {
5092
+
rockchip,pins =
5093
+
/* uart9m1_rtsn */
5094
+
<3 RK_PB4 9 &pcfg_pull_none>;
5095
+
};
5096
+
5097
+
/omit-if-no-ref/
5098
+
uart9m2_xfer: uart9m2-xfer {
5099
+
rockchip,pins =
5100
+
/* uart9_rx_m2 */
5101
+
<4 RK_PC3 13 &pcfg_pull_up>,
5102
+
/* uart9_tx_m2 */
5103
+
<4 RK_PC2 13 &pcfg_pull_up>;
5104
+
};
5105
+
};
5106
+
5107
+
uart10 {
5108
+
/omit-if-no-ref/
5109
+
uart10m0_xfer: uart10m0-xfer {
5110
+
rockchip,pins =
5111
+
/* uart10_rx_m0 */
5112
+
<3 RK_PB0 9 &pcfg_pull_up>,
5113
+
/* uart10_tx_m0 */
5114
+
<3 RK_PB1 9 &pcfg_pull_up>;
5115
+
};
5116
+
5117
+
/omit-if-no-ref/
5118
+
uart10m0_ctsn: uart10m0-ctsn {
5119
+
rockchip,pins =
5120
+
/* uart10m0_ctsn */
5121
+
<3 RK_PA6 10 &pcfg_pull_none>;
5122
+
};
5123
+
/omit-if-no-ref/
5124
+
uart10m0_rtsn: uart10m0-rtsn {
5125
+
rockchip,pins =
5126
+
/* uart10m0_rtsn */
5127
+
<3 RK_PA7 10 &pcfg_pull_none>;
5128
+
};
5129
+
5130
+
/omit-if-no-ref/
5131
+
uart10m1_xfer: uart10m1-xfer {
5132
+
rockchip,pins =
5133
+
/* uart10_rx_m1 */
5134
+
<1 RK_PD1 9 &pcfg_pull_up>,
5135
+
/* uart10_tx_m1 */
5136
+
<1 RK_PD0 9 &pcfg_pull_up>;
5137
+
};
5138
+
5139
+
/omit-if-no-ref/
5140
+
uart10m1_ctsn: uart10m1-ctsn {
5141
+
rockchip,pins =
5142
+
/* uart10m1_ctsn */
5143
+
<1 RK_PD5 9 &pcfg_pull_none>;
5144
+
};
5145
+
/omit-if-no-ref/
5146
+
uart10m1_rtsn: uart10m1-rtsn {
5147
+
rockchip,pins =
5148
+
/* uart10m1_rtsn */
5149
+
<1 RK_PD4 9 &pcfg_pull_none>;
5150
+
};
5151
+
5152
+
/omit-if-no-ref/
5153
+
uart10m2_xfer: uart10m2-xfer {
5154
+
rockchip,pins =
5155
+
/* uart10_rx_m2 */
5156
+
<0 RK_PC5 10 &pcfg_pull_up>,
5157
+
/* uart10_tx_m2 */
5158
+
<0 RK_PC4 10 &pcfg_pull_up>;
5159
+
};
5160
+
};
5161
+
5162
+
uart11 {
5163
+
/omit-if-no-ref/
5164
+
uart11m0_xfer: uart11m0-xfer {
5165
+
rockchip,pins =
5166
+
/* uart11_rx_m0 */
5167
+
<3 RK_PC1 9 &pcfg_pull_up>,
5168
+
/* uart11_tx_m0 */
5169
+
<3 RK_PC4 9 &pcfg_pull_up>;
5170
+
};
5171
+
5172
+
/omit-if-no-ref/
5173
+
uart11m0_ctsn: uart11m0-ctsn {
5174
+
rockchip,pins =
5175
+
/* uart11m0_ctsn */
5176
+
<3 RK_PC3 9 &pcfg_pull_none>;
5177
+
};
5178
+
/omit-if-no-ref/
5179
+
uart11m0_rtsn: uart11m0-rtsn {
5180
+
rockchip,pins =
5181
+
/* uart11m0_rtsn */
5182
+
<3 RK_PC2 9 &pcfg_pull_none>;
5183
+
};
5184
+
5185
+
/omit-if-no-ref/
5186
+
uart11m1_xfer: uart11m1-xfer {
5187
+
rockchip,pins =
5188
+
/* uart11_rx_m1 */
5189
+
<2 RK_PC5 9 &pcfg_pull_up>,
5190
+
/* uart11_tx_m1 */
5191
+
<2 RK_PC4 9 &pcfg_pull_up>;
5192
+
};
5193
+
5194
+
/omit-if-no-ref/
5195
+
uart11m1_ctsn: uart11m1-ctsn {
5196
+
rockchip,pins =
5197
+
/* uart11m1_ctsn */
5198
+
<2 RK_PC2 9 &pcfg_pull_none>;
5199
+
};
5200
+
/omit-if-no-ref/
5201
+
uart11m1_rtsn: uart11m1-rtsn {
5202
+
rockchip,pins =
5203
+
/* uart11m1_rtsn */
5204
+
<2 RK_PC3 9 &pcfg_pull_none>;
5205
+
};
5206
+
5207
+
/omit-if-no-ref/
5208
+
uart11m2_xfer: uart11m2-xfer {
5209
+
rockchip,pins =
5210
+
/* uart11_rx_m2 */
5211
+
<4 RK_PC1 13 &pcfg_pull_up>,
5212
+
/* uart11_tx_m2 */
5213
+
<4 RK_PC0 13 &pcfg_pull_up>;
5214
+
};
5215
+
};
5216
+
5217
+
ufs {
5218
+
/omit-if-no-ref/
5219
+
ufs_refclk: ufs-refclk {
5220
+
rockchip,pins =
5221
+
/* ufs_refclk */
5222
+
<4 RK_PD1 1 &pcfg_pull_none>;
5223
+
};
5224
+
5225
+
/omit-if-no-ref/
5226
+
ufs_rst: ufs-rst {
5227
+
rockchip,pins =
5228
+
/* ufs_rstn */
5229
+
<4 RK_PD0 1 &pcfg_pull_none>;
5230
+
};
5231
+
};
5232
+
5233
+
ufs_testdata0 {
5234
+
/omit-if-no-ref/
5235
+
ufs_testdata0_test: ufs_testdata0-test {
5236
+
rockchip,pins =
5237
+
/* ufs_testdata0_out */
5238
+
<4 RK_PC4 4 &pcfg_pull_none>;
5239
+
};
5240
+
};
5241
+
5242
+
ufs_testdata1 {
5243
+
/omit-if-no-ref/
5244
+
ufs_testdata1_test: ufs_testdata1-test {
5245
+
rockchip,pins =
5246
+
/* ufs_testdata1_out */
5247
+
<4 RK_PC5 4 &pcfg_pull_none>;
5248
+
};
5249
+
};
5250
+
5251
+
ufs_testdata2 {
5252
+
/omit-if-no-ref/
5253
+
ufs_testdata2_test: ufs_testdata2-test {
5254
+
rockchip,pins =
5255
+
/* ufs_testdata2_out */
5256
+
<4 RK_PC6 4 &pcfg_pull_none>;
5257
+
};
5258
+
};
5259
+
5260
+
ufs_testdata3 {
5261
+
/omit-if-no-ref/
5262
+
ufs_testdata3_test: ufs_testdata3-test {
5263
+
rockchip,pins =
5264
+
/* ufs_testdata3_out */
5265
+
<4 RK_PC7 4 &pcfg_pull_none>;
5266
+
};
5267
+
};
5268
+
5269
+
vi_cif {
5270
+
/omit-if-no-ref/
5271
+
vi_cif_pins: vi_cif-pins {
5272
+
rockchip,pins =
5273
+
/* vi_cif_clki */
5274
+
<3 RK_PA3 1 &pcfg_pull_none>,
5275
+
/* vi_cif_clko */
5276
+
<3 RK_PA2 1 &pcfg_pull_none>,
5277
+
/* vi_cif_d0 */
5278
+
<2 RK_PC5 1 &pcfg_pull_none>,
5279
+
/* vi_cif_d1 */
5280
+
<2 RK_PC4 1 &pcfg_pull_none>,
5281
+
/* vi_cif_d2 */
5282
+
<2 RK_PC3 1 &pcfg_pull_none>,
5283
+
/* vi_cif_d3 */
5284
+
<2 RK_PC2 1 &pcfg_pull_none>,
5285
+
/* vi_cif_d4 */
5286
+
<2 RK_PC1 1 &pcfg_pull_none>,
5287
+
/* vi_cif_d5 */
5288
+
<2 RK_PC0 1 &pcfg_pull_none>,
5289
+
/* vi_cif_d6 */
5290
+
<2 RK_PB7 1 &pcfg_pull_none>,
5291
+
/* vi_cif_d7 */
5292
+
<2 RK_PB6 1 &pcfg_pull_none>,
5293
+
/* vi_cif_d8 */
5294
+
<2 RK_PB5 1 &pcfg_pull_none>,
5295
+
/* vi_cif_d9 */
5296
+
<2 RK_PB4 1 &pcfg_pull_none>,
5297
+
/* vi_cif_d10 */
5298
+
<2 RK_PB3 1 &pcfg_pull_none>,
5299
+
/* vi_cif_d11 */
5300
+
<2 RK_PB2 1 &pcfg_pull_none>,
5301
+
/* vi_cif_d12 */
5302
+
<2 RK_PB1 1 &pcfg_pull_none>,
5303
+
/* vi_cif_d13 */
5304
+
<2 RK_PB0 1 &pcfg_pull_none>,
5305
+
/* vi_cif_d14 */
5306
+
<2 RK_PA7 1 &pcfg_pull_none>,
5307
+
/* vi_cif_d15 */
5308
+
<2 RK_PA6 1 &pcfg_pull_none>,
5309
+
/* vi_cif_href */
5310
+
<3 RK_PA0 1 &pcfg_pull_none>,
5311
+
/* vi_cif_vsync */
5312
+
<3 RK_PA1 1 &pcfg_pull_none>;
5313
+
};
5314
+
};
5315
+
5316
+
vo_lcdc {
5317
+
/omit-if-no-ref/
5318
+
vo_lcdc_pins: vo_lcdc-pins {
5319
+
rockchip,pins =
5320
+
/* vo_lcdc_clk */
5321
+
<3 RK_PD7 1 &pcfg_pull_none>,
5322
+
/* vo_lcdc_d0 */
5323
+
<3 RK_PD3 1 &pcfg_pull_none>,
5324
+
/* vo_lcdc_d1 */
5325
+
<3 RK_PD2 1 &pcfg_pull_none>,
5326
+
/* vo_lcdc_d2 */
5327
+
<3 RK_PD1 1 &pcfg_pull_none>,
5328
+
/* vo_lcdc_d3 */
5329
+
<3 RK_PD0 1 &pcfg_pull_none>,
5330
+
/* vo_lcdc_d4 */
5331
+
<3 RK_PC7 1 &pcfg_pull_none>,
5332
+
/* vo_lcdc_d5 */
5333
+
<3 RK_PC6 1 &pcfg_pull_none>,
5334
+
/* vo_lcdc_d6 */
5335
+
<3 RK_PC5 1 &pcfg_pull_none>,
5336
+
/* vo_lcdc_d7 */
5337
+
<3 RK_PC4 1 &pcfg_pull_none>,
5338
+
/* vo_lcdc_d8 */
5339
+
<3 RK_PC3 1 &pcfg_pull_none>,
5340
+
/* vo_lcdc_d9 */
5341
+
<3 RK_PC2 1 &pcfg_pull_none>,
5342
+
/* vo_lcdc_d10 */
5343
+
<3 RK_PC1 1 &pcfg_pull_none>,
5344
+
/* vo_lcdc_d11 */
5345
+
<3 RK_PC0 1 &pcfg_pull_none>,
5346
+
/* vo_lcdc_d12 */
5347
+
<3 RK_PB7 1 &pcfg_pull_none>,
5348
+
/* vo_lcdc_d13 */
5349
+
<3 RK_PB6 1 &pcfg_pull_none>,
5350
+
/* vo_lcdc_d14 */
5351
+
<3 RK_PB5 1 &pcfg_pull_none>,
5352
+
/* vo_lcdc_d15 */
5353
+
<3 RK_PB4 1 &pcfg_pull_none>,
5354
+
/* vo_lcdc_d16 */
5355
+
<3 RK_PB3 1 &pcfg_pull_none>,
5356
+
/* vo_lcdc_d17 */
5357
+
<3 RK_PB2 1 &pcfg_pull_none>,
5358
+
/* vo_lcdc_d18 */
5359
+
<3 RK_PB1 1 &pcfg_pull_none>,
5360
+
/* vo_lcdc_d19 */
5361
+
<3 RK_PB0 1 &pcfg_pull_none>,
5362
+
/* vo_lcdc_d20 */
5363
+
<3 RK_PA7 1 &pcfg_pull_none>,
5364
+
/* vo_lcdc_d21 */
5365
+
<3 RK_PA6 1 &pcfg_pull_none>,
5366
+
/* vo_lcdc_d22 */
5367
+
<3 RK_PA5 1 &pcfg_pull_none>,
5368
+
/* vo_lcdc_d23 */
5369
+
<3 RK_PA4 1 &pcfg_pull_none>,
5370
+
/* vo_lcdc_den */
5371
+
<3 RK_PD4 1 &pcfg_pull_none>,
5372
+
/* vo_lcdc_hsync */
5373
+
<3 RK_PD5 1 &pcfg_pull_none>,
5374
+
/* vo_lcdc_vsync */
5375
+
<3 RK_PD6 1 &pcfg_pull_none>;
5376
+
};
5377
+
};
5378
+
5379
+
vo_post {
5380
+
/omit-if-no-ref/
5381
+
vo_post_pins: vo_post-pins {
5382
+
rockchip,pins =
5383
+
/* vo_post_empty */
5384
+
<4 RK_PA1 1 &pcfg_pull_none>;
5385
+
};
5386
+
};
5387
+
5388
+
vp0_sync {
5389
+
/omit-if-no-ref/
5390
+
vp0_sync_pins: vp0_sync-pins {
5391
+
rockchip,pins =
5392
+
/* vp0_sync_out */
5393
+
<4 RK_PC5 3 &pcfg_pull_none>;
5394
+
};
5395
+
};
5396
+
5397
+
vp1_sync {
5398
+
/omit-if-no-ref/
5399
+
vp1_sync_pins: vp1_sync-pins {
5400
+
rockchip,pins =
5401
+
/* vp1_sync_out */
5402
+
<4 RK_PC6 3 &pcfg_pull_none>;
5403
+
};
5404
+
};
5405
+
5406
+
vp2_sync {
5407
+
/omit-if-no-ref/
5408
+
vp2_sync_pins: vp2_sync-pins {
5409
+
rockchip,pins =
5410
+
/* vp2_sync_out */
5411
+
<4 RK_PC7 3 &pcfg_pull_none>;
5412
+
};
5413
+
};
5414
+
};
5415
+
5416
+
/*
5417
+
* This part is edited handly.
5418
+
*/
5419
+
&pinctrl {
5420
+
pmic {
5421
+
/omit-if-no-ref/
5422
+
pmic_pins: pmic-pins {
5423
+
rockchip,pins =
5424
+
/* pmic_int */
5425
+
<0 RK_PA6 9 &pcfg_pull_up>,
5426
+
/* pmic_sleep */
5427
+
<0 RK_PA4 9 &pcfg_pull_none>;
5428
+
};
5429
+
};
5430
+
5431
+
vo {
5432
+
/omit-if-no-ref/
5433
+
bt1120_pins: bt1120-pins {
5434
+
rockchip,pins =
5435
+
/* vo_lcdc_clk */
5436
+
<3 RK_PD7 1 &pcfg_pull_none>,
5437
+
/* vo_lcdc_d3 */
5438
+
<3 RK_PD0 1 &pcfg_pull_none>,
5439
+
/* vo_lcdc_d4 */
5440
+
<3 RK_PC7 1 &pcfg_pull_none>,
5441
+
/* vo_lcdc_d5 */
5442
+
<3 RK_PC6 1 &pcfg_pull_none>,
5443
+
/* vo_lcdc_d6 */
5444
+
<3 RK_PC5 1 &pcfg_pull_none>,
5445
+
/* vo_lcdc_d7 */
5446
+
<3 RK_PC4 1 &pcfg_pull_none>,
5447
+
/* vo_lcdc_d10 */
5448
+
<3 RK_PC1 1 &pcfg_pull_none>,
5449
+
/* vo_lcdc_d11 */
5450
+
<3 RK_PC0 1 &pcfg_pull_none>,
5451
+
/* vo_lcdc_d12 */
5452
+
<3 RK_PB7 1 &pcfg_pull_none>,
5453
+
/* vo_lcdc_d13 */
5454
+
<3 RK_PB6 1 &pcfg_pull_none>,
5455
+
/* vo_lcdc_d14 */
5456
+
<3 RK_PB5 1 &pcfg_pull_none>,
5457
+
/* vo_lcdc_d15 */
5458
+
<3 RK_PB4 1 &pcfg_pull_none>,
5459
+
/* vo_lcdc_d19 */
5460
+
<3 RK_PB0 1 &pcfg_pull_none>,
5461
+
/* vo_lcdc_d20 */
5462
+
<3 RK_PA7 1 &pcfg_pull_none>,
5463
+
/* vo_lcdc_d21 */
5464
+
<3 RK_PA6 1 &pcfg_pull_none>,
5465
+
/* vo_lcdc_d22 */
5466
+
<3 RK_PA5 1 &pcfg_pull_none>,
5467
+
/* vo_lcdc_d23 */
5468
+
<3 RK_PA4 1 &pcfg_pull_none>;
5469
+
};
5470
+
5471
+
/omit-if-no-ref/
5472
+
bt656_pins: bt656-pins {
5473
+
rockchip,pins =
5474
+
/* vo_lcdc_clk */
5475
+
<3 RK_PD7 1 &pcfg_pull_none>,
5476
+
/* vo_lcdc_d3 */
5477
+
<3 RK_PD0 1 &pcfg_pull_none>,
5478
+
/* vo_lcdc_d4 */
5479
+
<3 RK_PC7 1 &pcfg_pull_none>,
5480
+
/* vo_lcdc_d5 */
5481
+
<3 RK_PC6 1 &pcfg_pull_none>,
5482
+
/* vo_lcdc_d6 */
5483
+
<3 RK_PC5 1 &pcfg_pull_none>,
5484
+
/* vo_lcdc_d7 */
5485
+
<3 RK_PC4 1 &pcfg_pull_none>,
5486
+
/* vo_lcdc_d10 */
5487
+
<3 RK_PC1 1 &pcfg_pull_none>,
5488
+
/* vo_lcdc_d11 */
5489
+
<3 RK_PC0 1 &pcfg_pull_none>,
5490
+
/* vo_lcdc_d12 */
5491
+
<3 RK_PB7 1 &pcfg_pull_none>;
5492
+
};
5493
+
5494
+
/omit-if-no-ref/
5495
+
rgb3x8_pins_m0: rgb3x8-pins-m0 {
5496
+
rockchip,pins =
5497
+
/* vo_lcdc_clk */
5498
+
<3 RK_PD7 1 &pcfg_pull_none>,
5499
+
/* vo_lcdc_d3 */
5500
+
<3 RK_PD0 1 &pcfg_pull_none>,
5501
+
/* vo_lcdc_d4 */
5502
+
<3 RK_PC7 1 &pcfg_pull_none>,
5503
+
/* vo_lcdc_d5 */
5504
+
<3 RK_PC6 1 &pcfg_pull_none>,
5505
+
/* vo_lcdc_d6 */
5506
+
<3 RK_PC5 1 &pcfg_pull_none>,
5507
+
/* vo_lcdc_d7 */
5508
+
<3 RK_PC4 1 &pcfg_pull_none>,
5509
+
/* vo_lcdc_d10 */
5510
+
<3 RK_PC1 1 &pcfg_pull_none>,
5511
+
/* vo_lcdc_d11 */
5512
+
<3 RK_PC0 1 &pcfg_pull_none>,
5513
+
/* vo_lcdc_d12 */
5514
+
<3 RK_PB7 1 &pcfg_pull_none>,
5515
+
/* vo_lcdc_den */
5516
+
<3 RK_PD4 1 &pcfg_pull_none>,
5517
+
/* vo_lcdc_hsync */
5518
+
<3 RK_PD5 1 &pcfg_pull_none>,
5519
+
/* vo_lcdc_vsync */
5520
+
<3 RK_PD6 1 &pcfg_pull_none>;
5521
+
};
5522
+
5523
+
/omit-if-no-ref/
5524
+
rgb3x8_pins_m1: rgb3x8-pins-m1 {
5525
+
rockchip,pins =
5526
+
/* vo_lcdc_clk */
5527
+
<3 RK_PD7 1 &pcfg_pull_none>,
5528
+
/* vo_lcdc_d13 */
5529
+
<3 RK_PB6 1 &pcfg_pull_none>,
5530
+
/* vo_lcdc_d14 */
5531
+
<3 RK_PB5 1 &pcfg_pull_none>,
5532
+
/* vo_lcdc_d15 */
5533
+
<3 RK_PB4 1 &pcfg_pull_none>,
5534
+
/* vo_lcdc_d19 */
5535
+
<3 RK_PB0 1 &pcfg_pull_none>,
5536
+
/* vo_lcdc_d20 */
5537
+
<3 RK_PA7 1 &pcfg_pull_none>,
5538
+
/* vo_lcdc_d21 */
5539
+
<3 RK_PA6 1 &pcfg_pull_none>,
5540
+
/* vo_lcdc_d22 */
5541
+
<3 RK_PA5 1 &pcfg_pull_none>,
5542
+
/* vo_lcdc_d23 */
5543
+
<3 RK_PA4 1 &pcfg_pull_none>,
5544
+
/* vo_lcdc_den */
5545
+
<3 RK_PD4 1 &pcfg_pull_none>,
5546
+
/* vo_lcdc_hsync */
5547
+
<3 RK_PD5 1 &pcfg_pull_none>,
5548
+
/* vo_lcdc_vsync */
5549
+
<3 RK_PD6 1 &pcfg_pull_none>;
5550
+
};
5551
+
5552
+
/omit-if-no-ref/
5553
+
rgb565_pins: rgb565-pins {
5554
+
rockchip,pins =
5555
+
/* vo_lcdc_clk */
5556
+
<3 RK_PD7 1 &pcfg_pull_none>,
5557
+
/* vo_lcdc_d3 */
5558
+
<3 RK_PD0 1 &pcfg_pull_none>,
5559
+
/* vo_lcdc_d4 */
5560
+
<3 RK_PC7 1 &pcfg_pull_none>,
5561
+
/* vo_lcdc_d5 */
5562
+
<3 RK_PC6 1 &pcfg_pull_none>,
5563
+
/* vo_lcdc_d6 */
5564
+
<3 RK_PC5 1 &pcfg_pull_none>,
5565
+
/* vo_lcdc_d7 */
5566
+
<3 RK_PC4 1 &pcfg_pull_none>,
5567
+
/* vo_lcdc_d10 */
5568
+
<3 RK_PC1 1 &pcfg_pull_none>,
5569
+
/* vo_lcdc_d11 */
5570
+
<3 RK_PC0 1 &pcfg_pull_none>,
5571
+
/* vo_lcdc_d12 */
5572
+
<3 RK_PB7 1 &pcfg_pull_none>,
5573
+
/* vo_lcdc_d13 */
5574
+
<3 RK_PB6 1 &pcfg_pull_none>,
5575
+
/* vo_lcdc_d14 */
5576
+
<3 RK_PB5 1 &pcfg_pull_none>,
5577
+
/* vo_lcdc_d15 */
5578
+
<3 RK_PB4 1 &pcfg_pull_none>,
5579
+
/* vo_lcdc_d19 */
5580
+
<3 RK_PB0 1 &pcfg_pull_none>,
5581
+
/* vo_lcdc_d20 */
5582
+
<3 RK_PA7 1 &pcfg_pull_none>,
5583
+
/* vo_lcdc_d21 */
5584
+
<3 RK_PA6 1 &pcfg_pull_none>,
5585
+
/* vo_lcdc_d22 */
5586
+
<3 RK_PA5 1 &pcfg_pull_none>,
5587
+
/* vo_lcdc_d23 */
5588
+
<3 RK_PA4 1 &pcfg_pull_none>,
5589
+
/* vo_lcdc_den */
5590
+
<3 RK_PD4 1 &pcfg_pull_none>,
5591
+
/* vo_lcdc_hsync */
5592
+
<3 RK_PD5 1 &pcfg_pull_none>,
5593
+
/* vo_lcdc_vsync */
5594
+
<3 RK_PD6 1 &pcfg_pull_none>;
5595
+
};
5596
+
5597
+
/omit-if-no-ref/
5598
+
rgb666_pins: rgb666-pins {
5599
+
rockchip,pins =
5600
+
/* vo_lcdc_clk */
5601
+
<3 RK_PD7 1 &pcfg_pull_none>,
5602
+
/* vo_lcdc_d2 */
5603
+
<3 RK_PD1 1 &pcfg_pull_none>,
5604
+
/* vo_lcdc_d3 */
5605
+
<3 RK_PD0 1 &pcfg_pull_none>,
5606
+
/* vo_lcdc_d4 */
5607
+
<3 RK_PC7 1 &pcfg_pull_none>,
5608
+
/* vo_lcdc_d5 */
5609
+
<3 RK_PC6 1 &pcfg_pull_none>,
5610
+
/* vo_lcdc_d6 */
5611
+
<3 RK_PC5 1 &pcfg_pull_none>,
5612
+
/* vo_lcdc_d7 */
5613
+
<3 RK_PC4 1 &pcfg_pull_none>,
5614
+
/* vo_lcdc_d10 */
5615
+
<3 RK_PC1 1 &pcfg_pull_none>,
5616
+
/* vo_lcdc_d11 */
5617
+
<3 RK_PC0 1 &pcfg_pull_none>,
5618
+
/* vo_lcdc_d12 */
5619
+
<3 RK_PB7 1 &pcfg_pull_none>,
5620
+
/* vo_lcdc_d13 */
5621
+
<3 RK_PB6 1 &pcfg_pull_none>,
5622
+
/* vo_lcdc_d14 */
5623
+
<3 RK_PB5 1 &pcfg_pull_none>,
5624
+
/* vo_lcdc_d15 */
5625
+
<3 RK_PB4 1 &pcfg_pull_none>,
5626
+
/* vo_lcdc_d18 */
5627
+
<3 RK_PB1 1 &pcfg_pull_none>,
5628
+
/* vo_lcdc_d19 */
5629
+
<3 RK_PB0 1 &pcfg_pull_none>,
5630
+
/* vo_lcdc_d20 */
5631
+
<3 RK_PA7 1 &pcfg_pull_none>,
5632
+
/* vo_lcdc_d21 */
5633
+
<3 RK_PA6 1 &pcfg_pull_none>,
5634
+
/* vo_lcdc_d22 */
5635
+
<3 RK_PA5 1 &pcfg_pull_none>,
5636
+
/* vo_lcdc_d23 */
5637
+
<3 RK_PA4 1 &pcfg_pull_none>,
5638
+
/* vo_lcdc_den */
5639
+
<3 RK_PD4 1 &pcfg_pull_none>,
5640
+
/* vo_lcdc_hsync */
5641
+
<3 RK_PD5 1 &pcfg_pull_none>,
5642
+
/* vo_lcdc_vsync */
5643
+
<3 RK_PD6 1 &pcfg_pull_none>;
5644
+
};
5645
+
5646
+
/omit-if-no-ref/
5647
+
rgb888_pins: rgb888-pins {
5648
+
rockchip,pins =
5649
+
/* vo_lcdc_clk */
5650
+
<3 RK_PD7 1 &pcfg_pull_none>,
5651
+
/* vo_lcdc_d0 */
5652
+
<3 RK_PD3 1 &pcfg_pull_none>,
5653
+
/* vo_lcdc_d1 */
5654
+
<3 RK_PD2 1 &pcfg_pull_none>,
5655
+
/* vo_lcdc_d2 */
5656
+
<3 RK_PD1 1 &pcfg_pull_none>,
5657
+
/* vo_lcdc_d3 */
5658
+
<3 RK_PD0 1 &pcfg_pull_none>,
5659
+
/* vo_lcdc_d4 */
5660
+
<3 RK_PC7 1 &pcfg_pull_none>,
5661
+
/* vo_lcdc_d5 */
5662
+
<3 RK_PC6 1 &pcfg_pull_none>,
5663
+
/* vo_lcdc_d6 */
5664
+
<3 RK_PC5 1 &pcfg_pull_none>,
5665
+
/* vo_lcdc_d7 */
5666
+
<3 RK_PC4 1 &pcfg_pull_none>,
5667
+
/* vo_lcdc_d8 */
5668
+
<3 RK_PC3 1 &pcfg_pull_none>,
5669
+
/* vo_lcdc_d9 */
5670
+
<3 RK_PC2 1 &pcfg_pull_none>,
5671
+
/* vo_lcdc_d10 */
5672
+
<3 RK_PC1 1 &pcfg_pull_none>,
5673
+
/* vo_lcdc_d11 */
5674
+
<3 RK_PC0 1 &pcfg_pull_none>,
5675
+
/* vo_lcdc_d12 */
5676
+
<3 RK_PB7 1 &pcfg_pull_none>,
5677
+
/* vo_lcdc_d13 */
5678
+
<3 RK_PB6 1 &pcfg_pull_none>,
5679
+
/* vo_lcdc_d14 */
5680
+
<3 RK_PB5 1 &pcfg_pull_none>,
5681
+
/* vo_lcdc_d15 */
5682
+
<3 RK_PB4 1 &pcfg_pull_none>,
5683
+
/* vo_lcdc_d16 */
5684
+
<3 RK_PB3 1 &pcfg_pull_none>,
5685
+
/* vo_lcdc_d17 */
5686
+
<3 RK_PB2 1 &pcfg_pull_none>,
5687
+
/* vo_lcdc_d18 */
5688
+
<3 RK_PB1 1 &pcfg_pull_none>,
5689
+
/* vo_lcdc_d19 */
5690
+
<3 RK_PB0 1 &pcfg_pull_none>,
5691
+
/* vo_lcdc_d20 */
5692
+
<3 RK_PA7 1 &pcfg_pull_none>,
5693
+
/* vo_lcdc_d21 */
5694
+
<3 RK_PA6 1 &pcfg_pull_none>,
5695
+
/* vo_lcdc_d22 */
5696
+
<3 RK_PA5 1 &pcfg_pull_none>,
5697
+
/* vo_lcdc_d23 */
5698
+
<3 RK_PA4 1 &pcfg_pull_none>,
5699
+
/* vo_lcdc_den */
5700
+
<3 RK_PD4 1 &pcfg_pull_none>,
5701
+
/* vo_lcdc_hsync */
5702
+
<3 RK_PD5 1 &pcfg_pull_none>,
5703
+
/* vo_lcdc_vsync */
5704
+
<3 RK_PD6 1 &pcfg_pull_none>;
5705
+
};
5706
+
};
5707
+
5708
+
vo_ebc {
5709
+
/omit-if-no-ref/
5710
+
vo_ebc_pins: vo_ebc-pins {
5711
+
rockchip,pins =
5712
+
/* vo_ebc_gdclk */
5713
+
<3 RK_PD5 2 &pcfg_pull_none>,
5714
+
/* vo_ebc_gdoe */
5715
+
<3 RK_PA6 2 &pcfg_pull_none>,
5716
+
/* vo_ebc_gdsp */
5717
+
<3 RK_PA5 2 &pcfg_pull_none>,
5718
+
/* vo_ebc_sdce0 */
5719
+
<3 RK_PB3 2 &pcfg_pull_none>,
5720
+
/* vo_ebc_sdclk */
5721
+
<3 RK_PD6 2 &pcfg_pull_none>,
5722
+
/* vo_ebc_sddo0 */
5723
+
<3 RK_PD3 2 &pcfg_pull_none>,
5724
+
/* vo_ebc_sddo1 */
5725
+
<3 RK_PD2 2 &pcfg_pull_none>,
5726
+
/* vo_ebc_sddo2 */
5727
+
<3 RK_PD1 2 &pcfg_pull_none>,
5728
+
/* vo_ebc_sddo3 */
5729
+
<3 RK_PD0 2 &pcfg_pull_none>,
5730
+
/* vo_ebc_sddo4 */
5731
+
<3 RK_PC7 2 &pcfg_pull_none>,
5732
+
/* vo_ebc_sddo5 */
5733
+
<3 RK_PC6 2 &pcfg_pull_none>,
5734
+
/* vo_ebc_sddo6 */
5735
+
<3 RK_PC5 2 &pcfg_pull_none>,
5736
+
/* vo_ebc_sddo7 */
5737
+
<3 RK_PC4 2 &pcfg_pull_none>,
5738
+
/* vo_ebc_sddo8 */
5739
+
<3 RK_PC3 2 &pcfg_pull_none>,
5740
+
/* vo_ebc_sddo9 */
5741
+
<3 RK_PC2 2 &pcfg_pull_none>,
5742
+
/* vo_ebc_sddo10 */
5743
+
<3 RK_PC1 2 &pcfg_pull_none>,
5744
+
/* vo_ebc_sddo11 */
5745
+
<3 RK_PC0 2 &pcfg_pull_none>,
5746
+
/* vo_ebc_sddo12 */
5747
+
<3 RK_PB7 2 &pcfg_pull_none>,
5748
+
/* vo_ebc_sddo13 */
5749
+
<3 RK_PB6 2 &pcfg_pull_none>,
5750
+
/* vo_ebc_sddo14 */
5751
+
<3 RK_PB5 2 &pcfg_pull_none>,
5752
+
/* vo_ebc_sddo15 */
5753
+
<3 RK_PB4 2 &pcfg_pull_none>,
5754
+
/* vo_ebc_sdle */
5755
+
<3 RK_PD4 2 &pcfg_pull_none>,
5756
+
/* vo_ebc_sdoe */
5757
+
<3 RK_PD7 2 &pcfg_pull_none>;
5758
+
};
5759
+
5760
+
/omit-if-no-ref/
5761
+
vo_ebc_extern: vo_ebc-extern {
5762
+
rockchip,pins =
5763
+
/* vo_ebc_sdce1 */
5764
+
<3 RK_PB2 2 &pcfg_pull_none>,
5765
+
/* vo_ebc_sdce2 */
5766
+
<3 RK_PB1 2 &pcfg_pull_none>,
5767
+
/* vo_ebc_sdce3 */
5768
+
<3 RK_PB0 2 &pcfg_pull_none>,
5769
+
/* vo_ebc_sdshr */
5770
+
<3 RK_PA4 2 &pcfg_pull_none>,
5771
+
/* vo_ebc_vcom */
5772
+
<3 RK_PA7 2 &pcfg_pull_none>;
5773
+
};
5774
+
};
5775
+
};
+1678
arch/arm64/boot/dts/rockchip/rk3576.dtsi
+1678
arch/arm64/boot/dts/rockchip/rk3576.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4
+
*/
5
+
6
+
#include <dt-bindings/clock/rockchip,rk3576-cru.h>
7
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
8
+
#include <dt-bindings/interrupt-controller/irq.h>
9
+
#include <dt-bindings/phy/phy.h>
10
+
#include <dt-bindings/pinctrl/rockchip.h>
11
+
#include <dt-bindings/power/rockchip,rk3576-power.h>
12
+
#include <dt-bindings/reset/rockchip,rk3576-cru.h>
13
+
#include <dt-bindings/soc/rockchip,boot-mode.h>
14
+
15
+
/ {
16
+
compatible = "rockchip,rk3576";
17
+
18
+
interrupt-parent = <&gic>;
19
+
#address-cells = <2>;
20
+
#size-cells = <2>;
21
+
22
+
aliases {
23
+
i2c0 = &i2c0;
24
+
i2c1 = &i2c1;
25
+
i2c2 = &i2c2;
26
+
i2c3 = &i2c3;
27
+
i2c4 = &i2c4;
28
+
i2c5 = &i2c5;
29
+
i2c6 = &i2c6;
30
+
i2c7 = &i2c7;
31
+
i2c8 = &i2c8;
32
+
i2c9 = &i2c9;
33
+
serial0 = &uart0;
34
+
serial1 = &uart1;
35
+
serial2 = &uart2;
36
+
serial3 = &uart3;
37
+
serial4 = &uart4;
38
+
serial5 = &uart5;
39
+
serial6 = &uart6;
40
+
serial7 = &uart7;
41
+
serial8 = &uart8;
42
+
serial9 = &uart9;
43
+
serial10 = &uart10;
44
+
serial11 = &uart11;
45
+
spi0 = &spi0;
46
+
spi1 = &spi1;
47
+
spi2 = &spi2;
48
+
spi3 = &spi3;
49
+
spi4 = &spi4;
50
+
};
51
+
52
+
xin32k: clock-xin32k {
53
+
compatible = "fixed-clock";
54
+
clock-frequency = <32768>;
55
+
clock-output-names = "xin32k";
56
+
#clock-cells = <0>;
57
+
};
58
+
59
+
xin24m: clock-xin24m {
60
+
compatible = "fixed-clock";
61
+
#clock-cells = <0>;
62
+
clock-frequency = <24000000>;
63
+
clock-output-names = "xin24m";
64
+
};
65
+
66
+
spll: clock-spll {
67
+
compatible = "fixed-clock";
68
+
#clock-cells = <0>;
69
+
clock-frequency = <702000000>;
70
+
clock-output-names = "spll";
71
+
};
72
+
73
+
cpus {
74
+
#address-cells = <1>;
75
+
#size-cells = <0>;
76
+
77
+
cpu-map {
78
+
cluster0 {
79
+
core0 {
80
+
cpu = <&cpu_l0>;
81
+
};
82
+
core1 {
83
+
cpu = <&cpu_l1>;
84
+
};
85
+
core2 {
86
+
cpu = <&cpu_l2>;
87
+
};
88
+
core3 {
89
+
cpu = <&cpu_l3>;
90
+
};
91
+
};
92
+
cluster1 {
93
+
core0 {
94
+
cpu = <&cpu_b0>;
95
+
};
96
+
core1 {
97
+
cpu = <&cpu_b1>;
98
+
};
99
+
core2 {
100
+
cpu = <&cpu_b2>;
101
+
};
102
+
core3 {
103
+
cpu = <&cpu_b3>;
104
+
};
105
+
};
106
+
};
107
+
108
+
cpu_l0: cpu@0 {
109
+
device_type = "cpu";
110
+
compatible = "arm,cortex-a53";
111
+
reg = <0x0>;
112
+
enable-method = "psci";
113
+
capacity-dmips-mhz = <485>;
114
+
clocks = <&scmi_clk ARMCLK_L>;
115
+
operating-points-v2 = <&cluster0_opp_table>;
116
+
#cooling-cells = <2>;
117
+
dynamic-power-coefficient = <120>;
118
+
cpu-idle-states = <&CPU_SLEEP>;
119
+
};
120
+
121
+
cpu_l1: cpu@1 {
122
+
device_type = "cpu";
123
+
compatible = "arm,cortex-a53";
124
+
reg = <0x1>;
125
+
enable-method = "psci";
126
+
capacity-dmips-mhz = <485>;
127
+
clocks = <&scmi_clk ARMCLK_L>;
128
+
operating-points-v2 = <&cluster0_opp_table>;
129
+
cpu-idle-states = <&CPU_SLEEP>;
130
+
};
131
+
132
+
cpu_l2: cpu@2 {
133
+
device_type = "cpu";
134
+
compatible = "arm,cortex-a53";
135
+
reg = <0x2>;
136
+
enable-method = "psci";
137
+
capacity-dmips-mhz = <485>;
138
+
clocks = <&scmi_clk ARMCLK_L>;
139
+
operating-points-v2 = <&cluster0_opp_table>;
140
+
cpu-idle-states = <&CPU_SLEEP>;
141
+
};
142
+
143
+
cpu_l3: cpu@3 {
144
+
device_type = "cpu";
145
+
compatible = "arm,cortex-a53";
146
+
reg = <0x3>;
147
+
enable-method = "psci";
148
+
capacity-dmips-mhz = <485>;
149
+
clocks = <&scmi_clk ARMCLK_L>;
150
+
operating-points-v2 = <&cluster0_opp_table>;
151
+
cpu-idle-states = <&CPU_SLEEP>;
152
+
};
153
+
154
+
cpu_b0: cpu@100 {
155
+
device_type = "cpu";
156
+
compatible = "arm,cortex-a72";
157
+
reg = <0x100>;
158
+
enable-method = "psci";
159
+
capacity-dmips-mhz = <1024>;
160
+
clocks = <&scmi_clk ARMCLK_B>;
161
+
operating-points-v2 = <&cluster1_opp_table>;
162
+
#cooling-cells = <2>;
163
+
dynamic-power-coefficient = <320>;
164
+
cpu-idle-states = <&CPU_SLEEP>;
165
+
};
166
+
167
+
cpu_b1: cpu@101 {
168
+
device_type = "cpu";
169
+
compatible = "arm,cortex-a72";
170
+
reg = <0x101>;
171
+
enable-method = "psci";
172
+
capacity-dmips-mhz = <1024>;
173
+
clocks = <&scmi_clk ARMCLK_B>;
174
+
operating-points-v2 = <&cluster1_opp_table>;
175
+
cpu-idle-states = <&CPU_SLEEP>;
176
+
};
177
+
178
+
cpu_b2: cpu@102 {
179
+
device_type = "cpu";
180
+
compatible = "arm,cortex-a72";
181
+
reg = <0x102>;
182
+
enable-method = "psci";
183
+
capacity-dmips-mhz = <1024>;
184
+
clocks = <&scmi_clk ARMCLK_B>;
185
+
operating-points-v2 = <&cluster1_opp_table>;
186
+
cpu-idle-states = <&CPU_SLEEP>;
187
+
};
188
+
189
+
cpu_b3: cpu@103 {
190
+
device_type = "cpu";
191
+
compatible = "arm,cortex-a72";
192
+
reg = <0x103>;
193
+
enable-method = "psci";
194
+
capacity-dmips-mhz = <1024>;
195
+
clocks = <&scmi_clk ARMCLK_B>;
196
+
operating-points-v2 = <&cluster1_opp_table>;
197
+
cpu-idle-states = <&CPU_SLEEP>;
198
+
};
199
+
200
+
idle-states {
201
+
entry-method = "psci";
202
+
203
+
CPU_SLEEP: cpu-sleep {
204
+
compatible = "arm,idle-state";
205
+
arm,psci-suspend-param = <0x0010000>;
206
+
entry-latency-us = <120>;
207
+
exit-latency-us = <250>;
208
+
min-residency-us = <900>;
209
+
local-timer-stop;
210
+
};
211
+
};
212
+
};
213
+
214
+
cluster0_opp_table: opp-table-cluster0 {
215
+
compatible = "operating-points-v2";
216
+
opp-shared;
217
+
218
+
opp-408000000 {
219
+
opp-hz = /bits/ 64 <408000000>;
220
+
opp-microvolt = <700000 700000 950000>;
221
+
clock-latency-ns = <40000>;
222
+
};
223
+
224
+
opp-600000000 {
225
+
opp-hz = /bits/ 64 <600000000>;
226
+
opp-microvolt = <700000 700000 950000>;
227
+
clock-latency-ns = <40000>;
228
+
};
229
+
230
+
opp-816000000 {
231
+
opp-hz = /bits/ 64 <816000000>;
232
+
opp-microvolt = <700000 700000 950000>;
233
+
clock-latency-ns = <40000>;
234
+
};
235
+
236
+
opp-1008000000 {
237
+
opp-hz = /bits/ 64 <1008000000>;
238
+
opp-microvolt = <700000 700000 950000>;
239
+
clock-latency-ns = <40000>;
240
+
};
241
+
242
+
opp-1200000000 {
243
+
opp-hz = /bits/ 64 <1200000000>;
244
+
opp-microvolt = <700000 700000 950000>;
245
+
clock-latency-ns = <40000>;
246
+
};
247
+
248
+
opp-1416000000 {
249
+
opp-hz = /bits/ 64 <1416000000>;
250
+
opp-microvolt = <725000 725000 950000>;
251
+
clock-latency-ns = <40000>;
252
+
};
253
+
254
+
opp-1608000000 {
255
+
opp-hz = /bits/ 64 <1608000000>;
256
+
opp-microvolt = <750000 750000 950000>;
257
+
clock-latency-ns = <40000>;
258
+
};
259
+
260
+
opp-1800000000 {
261
+
opp-hz = /bits/ 64 <1800000000>;
262
+
opp-microvolt = <825000 825000 950000>;
263
+
clock-latency-ns = <40000>;
264
+
opp-suspend;
265
+
};
266
+
267
+
opp-2016000000 {
268
+
opp-hz = /bits/ 64 <2016000000>;
269
+
opp-microvolt = <900000 900000 950000>;
270
+
clock-latency-ns = <40000>;
271
+
};
272
+
273
+
opp-2208000000 {
274
+
opp-hz = /bits/ 64 <2208000000>;
275
+
opp-microvolt = <950000 950000 950000>;
276
+
clock-latency-ns = <40000>;
277
+
};
278
+
};
279
+
280
+
cluster1_opp_table: opp-table-cluster1 {
281
+
compatible = "operating-points-v2";
282
+
opp-shared;
283
+
284
+
opp-408000000 {
285
+
opp-hz = /bits/ 64 <408000000>;
286
+
opp-microvolt = <700000 700000 950000>;
287
+
clock-latency-ns = <40000>;
288
+
opp-suspend;
289
+
};
290
+
291
+
opp-600000000 {
292
+
opp-hz = /bits/ 64 <600000000>;
293
+
opp-microvolt = <700000 700000 950000>;
294
+
clock-latency-ns = <40000>;
295
+
};
296
+
297
+
opp-816000000 {
298
+
opp-hz = /bits/ 64 <816000000>;
299
+
opp-microvolt = <700000 700000 950000>;
300
+
clock-latency-ns = <40000>;
301
+
};
302
+
303
+
opp-1008000000 {
304
+
opp-hz = /bits/ 64 <1008000000>;
305
+
opp-microvolt = <700000 700000 950000>;
306
+
clock-latency-ns = <40000>;
307
+
};
308
+
309
+
opp-1200000000 {
310
+
opp-hz = /bits/ 64 <1200000000>;
311
+
opp-microvolt = <700000 700000 950000>;
312
+
clock-latency-ns = <40000>;
313
+
};
314
+
315
+
opp-1416000000 {
316
+
opp-hz = /bits/ 64 <1416000000>;
317
+
opp-microvolt = <712500 712500 950000>;
318
+
clock-latency-ns = <40000>;
319
+
};
320
+
321
+
opp-1608000000 {
322
+
opp-hz = /bits/ 64 <1608000000>;
323
+
opp-microvolt = <737500 737500 950000>;
324
+
clock-latency-ns = <40000>;
325
+
};
326
+
327
+
opp-1800000000 {
328
+
opp-hz = /bits/ 64 <1800000000>;
329
+
opp-microvolt = <800000 800000 950000>;
330
+
clock-latency-ns = <40000>;
331
+
};
332
+
333
+
opp-2016000000 {
334
+
opp-hz = /bits/ 64 <2016000000>;
335
+
opp-microvolt = <862500 862500 950000>;
336
+
clock-latency-ns = <40000>;
337
+
};
338
+
339
+
opp-2208000000 {
340
+
opp-hz = /bits/ 64 <2208000000>;
341
+
opp-microvolt = <925000 925000 950000>;
342
+
clock-latency-ns = <40000>;
343
+
};
344
+
345
+
opp-2304000000 {
346
+
opp-hz = /bits/ 64 <2304000000>;
347
+
opp-microvolt = <950000 950000 950000>;
348
+
clock-latency-ns = <40000>;
349
+
};
350
+
};
351
+
352
+
gpu_opp_table: opp-table-gpu {
353
+
compatible = "operating-points-v2";
354
+
355
+
opp-300000000 {
356
+
opp-hz = /bits/ 64 <300000000>;
357
+
opp-microvolt = <700000 700000 850000>;
358
+
};
359
+
360
+
opp-400000000 {
361
+
opp-hz = /bits/ 64 <400000000>;
362
+
opp-microvolt = <700000 700000 850000>;
363
+
};
364
+
365
+
opp-500000000 {
366
+
opp-hz = /bits/ 64 <500000000>;
367
+
opp-microvolt = <700000 700000 850000>;
368
+
};
369
+
370
+
opp-600000000 {
371
+
opp-hz = /bits/ 64 <600000000>;
372
+
opp-microvolt = <700000 700000 850000>;
373
+
};
374
+
375
+
opp-700000000 {
376
+
opp-hz = /bits/ 64 <700000000>;
377
+
opp-microvolt = <725000 725000 850000>;
378
+
};
379
+
380
+
opp-800000000 {
381
+
opp-hz = /bits/ 64 <800000000>;
382
+
opp-microvolt = <775000 775000 850000>;
383
+
};
384
+
385
+
opp-900000000 {
386
+
opp-hz = /bits/ 64 <900000000>;
387
+
opp-microvolt = <825000 825000 850000>;
388
+
};
389
+
390
+
opp-950000000 {
391
+
opp-hz = /bits/ 64 <950000000>;
392
+
opp-microvolt = <850000 850000 850000>;
393
+
};
394
+
};
395
+
396
+
firmware {
397
+
scmi: scmi {
398
+
compatible = "arm,scmi-smc";
399
+
arm,smc-id = <0x82000010>;
400
+
shmem = <&scmi_shmem>;
401
+
#address-cells = <1>;
402
+
#size-cells = <0>;
403
+
404
+
scmi_clk: protocol@14 {
405
+
reg = <0x14>;
406
+
#clock-cells = <1>;
407
+
};
408
+
};
409
+
};
410
+
411
+
pmu_a53: pmu-a53 {
412
+
compatible = "arm,cortex-a53-pmu";
413
+
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
414
+
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
415
+
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
416
+
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
417
+
interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>;
418
+
};
419
+
420
+
pmu_a72: pmu-a72 {
421
+
compatible = "arm,cortex-a72-pmu";
422
+
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
423
+
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
424
+
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
425
+
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
426
+
interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
427
+
};
428
+
429
+
psci {
430
+
compatible = "arm,psci-1.0";
431
+
method = "smc";
432
+
};
433
+
434
+
timer {
435
+
compatible = "arm,armv8-timer";
436
+
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
437
+
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
438
+
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
439
+
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
440
+
};
441
+
442
+
soc {
443
+
compatible = "simple-bus";
444
+
#address-cells = <2>;
445
+
#size-cells = <2>;
446
+
ranges;
447
+
448
+
sys_grf: syscon@2600a000 {
449
+
compatible = "rockchip,rk3576-sys-grf", "syscon";
450
+
reg = <0x0 0x2600a000 0x0 0x2000>;
451
+
};
452
+
453
+
bigcore_grf: syscon@2600c000 {
454
+
compatible = "rockchip,rk3576-bigcore-grf", "syscon";
455
+
reg = <0x0 0x2600c000 0x0 0x2000>;
456
+
};
457
+
458
+
litcore_grf: syscon@2600e000 {
459
+
compatible = "rockchip,rk3576-litcore-grf", "syscon";
460
+
reg = <0x0 0x2600e000 0x0 0x2000>;
461
+
};
462
+
463
+
cci_grf: syscon@26010000 {
464
+
compatible = "rockchip,rk3576-cci-grf", "syscon";
465
+
reg = <0x0 0x26010000 0x0 0x2000>;
466
+
};
467
+
468
+
gpu_grf: syscon@26016000 {
469
+
compatible = "rockchip,rk3576-gpu-grf", "syscon";
470
+
reg = <0x0 0x26016000 0x0 0x2000>;
471
+
};
472
+
473
+
npu_grf: syscon@26018000 {
474
+
compatible = "rockchip,rk3576-npu-grf", "syscon";
475
+
reg = <0x0 0x26018000 0x0 0x2000>;
476
+
};
477
+
478
+
vo0_grf: syscon@2601a000 {
479
+
compatible = "rockchip,rk3576-vo0-grf", "syscon";
480
+
reg = <0x0 0x2601a000 0x0 0x2000>;
481
+
};
482
+
483
+
usb_grf: syscon@2601e000 {
484
+
compatible = "rockchip,rk3576-usb-grf", "syscon";
485
+
reg = <0x0 0x2601e000 0x0 0x1000>;
486
+
};
487
+
488
+
php_grf: syscon@26020000 {
489
+
compatible = "rockchip,rk3576-php-grf", "syscon";
490
+
reg = <0x0 0x26020000 0x0 0x2000>;
491
+
};
492
+
493
+
pmu0_grf: syscon@26024000 {
494
+
compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd";
495
+
reg = <0x0 0x26024000 0x0 0x1000>;
496
+
};
497
+
498
+
pmu1_grf: syscon@26026000 {
499
+
compatible = "rockchip,rk3576-pmu1-grf", "syscon";
500
+
reg = <0x0 0x26026000 0x0 0x1000>;
501
+
};
502
+
503
+
pipe_phy0_grf: syscon@26028000 {
504
+
compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
505
+
reg = <0x0 0x26028000 0x0 0x2000>;
506
+
};
507
+
508
+
pipe_phy1_grf: syscon@2602a000 {
509
+
compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
510
+
reg = <0x0 0x2602a000 0x0 0x2000>;
511
+
};
512
+
513
+
usbdpphy_grf: syscon@2602c000 {
514
+
compatible = "rockchip,rk3576-usbdpphy-grf", "syscon";
515
+
reg = <0x0 0x2602c000 0x0 0x2000>;
516
+
};
517
+
518
+
sdgmac_grf: syscon@26038000 {
519
+
compatible = "rockchip,rk3576-sdgmac-grf", "syscon";
520
+
reg = <0x0 0x26038000 0x0 0x1000>;
521
+
};
522
+
523
+
ioc_grf: syscon@26040000 {
524
+
compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd";
525
+
reg = <0x0 0x26040000 0x0 0xc000>;
526
+
};
527
+
528
+
cru: clock-controller@27200000 {
529
+
compatible = "rockchip,rk3576-cru";
530
+
reg = <0x0 0x27200000 0x0 0x50000>;
531
+
#clock-cells = <1>;
532
+
#reset-cells = <1>;
533
+
534
+
assigned-clocks =
535
+
<&cru CLK_AUDIO_FRAC_1_SRC>,
536
+
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
537
+
<&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>,
538
+
<&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>,
539
+
<&cru CLK_AUDIO_FRAC_0>, <&cru CLK_AUDIO_FRAC_1>,
540
+
<&cru CLK_CPLL_DIV2>, <&cru CLK_CPLL_DIV4>,
541
+
<&cru CLK_CPLL_DIV10>, <&cru FCLK_DDR_CM0_CORE>,
542
+
<&cru ACLK_PHP_ROOT>;
543
+
assigned-clock-parents = <&cru PLL_AUPLL>;
544
+
assigned-clock-rates =
545
+
<0>,
546
+
<1188000000>, <1000000000>,
547
+
<786432000>, <18432000>,
548
+
<96000000>, <128000000>,
549
+
<45158400>, <49152000>,
550
+
<500000000>, <250000000>,
551
+
<100000000>, <500000000>,
552
+
<250000000>;
553
+
};
554
+
555
+
i2c0: i2c@27300000 {
556
+
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
557
+
reg = <0x0 0x27300000 0x0 0x1000>;
558
+
clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
559
+
clock-names = "i2c", "pclk";
560
+
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
561
+
pinctrl-names = "default";
562
+
pinctrl-0 = <&i2c0m0_xfer>;
563
+
#address-cells = <1>;
564
+
#size-cells = <0>;
565
+
status = "disabled";
566
+
};
567
+
568
+
uart1: serial@27310000 {
569
+
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
570
+
reg = <0x0 0x27310000 0x0 0x100>;
571
+
reg-shift = <2>;
572
+
reg-io-width = <4>;
573
+
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
574
+
clock-names = "baudclk", "apb_pclk";
575
+
dmas = <&dmac0 8>, <&dmac0 9>;
576
+
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
577
+
pinctrl-names = "default";
578
+
pinctrl-0 = <&uart1m0_xfer>;
579
+
status = "disabled";
580
+
};
581
+
582
+
pmu: power-management@27380000 {
583
+
compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd";
584
+
reg = <0x0 0x27380000 0x0 0x800>;
585
+
586
+
power: power-controller {
587
+
compatible = "rockchip,rk3576-power-controller";
588
+
#power-domain-cells = <1>;
589
+
#address-cells = <1>;
590
+
#size-cells = <0>;
591
+
592
+
power-domain@RK3576_PD_NPU {
593
+
reg = <RK3576_PD_NPU>;
594
+
#power-domain-cells = <1>;
595
+
#address-cells = <1>;
596
+
#size-cells = <0>;
597
+
598
+
power-domain@RK3576_PD_NPUTOP {
599
+
reg = <RK3576_PD_NPUTOP>;
600
+
clocks = <&cru ACLK_RKNN0>,
601
+
<&cru ACLK_RKNN1>,
602
+
<&cru ACLK_RKNN_CBUF>,
603
+
<&cru CLK_RKNN_DSU0>,
604
+
<&cru HCLK_RKNN_CBUF>,
605
+
<&cru HCLK_RKNN_ROOT>,
606
+
<&cru HCLK_NPU_CM0_ROOT>,
607
+
<&cru PCLK_NPUTOP_ROOT>;
608
+
pm_qos = <&qos_npu_mcu>,
609
+
<&qos_npu_nsp0>,
610
+
<&qos_npu_nsp1>,
611
+
<&qos_npu_m0ro>,
612
+
<&qos_npu_m1ro>;
613
+
#power-domain-cells = <1>;
614
+
#address-cells = <1>;
615
+
#size-cells = <0>;
616
+
617
+
power-domain@RK3576_PD_NPU0 {
618
+
reg = <RK3576_PD_NPU0>;
619
+
clocks = <&cru HCLK_RKNN_ROOT>,
620
+
<&cru ACLK_RKNN0>;
621
+
pm_qos = <&qos_npu_m0>;
622
+
#power-domain-cells = <0>;
623
+
};
624
+
power-domain@RK3576_PD_NPU1 {
625
+
reg = <RK3576_PD_NPU1>;
626
+
clocks = <&cru HCLK_RKNN_ROOT>,
627
+
<&cru ACLK_RKNN1>;
628
+
pm_qos = <&qos_npu_m1>;
629
+
#power-domain-cells = <0>;
630
+
};
631
+
};
632
+
};
633
+
634
+
power-domain@RK3576_PD_GPU {
635
+
reg = <RK3576_PD_GPU>;
636
+
clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>;
637
+
pm_qos = <&qos_gpu>;
638
+
#power-domain-cells = <0>;
639
+
};
640
+
641
+
power-domain@RK3576_PD_NVM {
642
+
reg = <RK3576_PD_NVM>;
643
+
clocks = <&cru ACLK_EMMC>, <&cru HCLK_EMMC>;
644
+
pm_qos = <&qos_emmc>,
645
+
<&qos_fspi0>;
646
+
#power-domain-cells = <1>;
647
+
#address-cells = <1>;
648
+
#size-cells = <0>;
649
+
650
+
power-domain@RK3576_PD_SDGMAC {
651
+
reg = <RK3576_PD_SDGMAC>;
652
+
clocks = <&cru ACLK_HSGPIO>,
653
+
<&cru ACLK_GMAC0>,
654
+
<&cru ACLK_GMAC1>,
655
+
<&cru CCLK_SRC_SDIO>,
656
+
<&cru CCLK_SRC_SDMMC0>,
657
+
<&cru HCLK_HSGPIO>,
658
+
<&cru HCLK_SDIO>,
659
+
<&cru HCLK_SDMMC0>,
660
+
<&cru PCLK_SDGMAC_ROOT>;
661
+
pm_qos = <&qos_fspi1>,
662
+
<&qos_gmac0>,
663
+
<&qos_gmac1>,
664
+
<&qos_sdio>,
665
+
<&qos_sdmmc>,
666
+
<&qos_flexbus>;
667
+
#power-domain-cells = <0>;
668
+
};
669
+
};
670
+
671
+
power-domain@RK3576_PD_PHP {
672
+
reg = <RK3576_PD_PHP>;
673
+
clocks = <&cru ACLK_PHP_ROOT>,
674
+
<&cru PCLK_PHP_ROOT>,
675
+
<&cru ACLK_MMU0>,
676
+
<&cru ACLK_MMU1>;
677
+
pm_qos = <&qos_mmu0>,
678
+
<&qos_mmu1>;
679
+
#power-domain-cells = <1>;
680
+
#address-cells = <1>;
681
+
#size-cells = <0>;
682
+
683
+
power-domain@RK3576_PD_SUBPHP {
684
+
reg = <RK3576_PD_SUBPHP>;
685
+
#power-domain-cells = <0>;
686
+
};
687
+
};
688
+
689
+
power-domain@RK3576_PD_AUDIO {
690
+
reg = <RK3576_PD_AUDIO>;
691
+
#power-domain-cells = <0>;
692
+
};
693
+
694
+
power-domain@RK3576_PD_VEPU1 {
695
+
reg = <RK3576_PD_VEPU1>;
696
+
clocks = <&cru ACLK_VEPU1>,
697
+
<&cru HCLK_VEPU1>;
698
+
pm_qos = <&qos_vepu1>;
699
+
#power-domain-cells = <0>;
700
+
};
701
+
702
+
power-domain@RK3576_PD_VPU {
703
+
reg = <RK3576_PD_VPU>;
704
+
clocks = <&cru ACLK_EBC>,
705
+
<&cru HCLK_EBC>,
706
+
<&cru ACLK_JPEG>,
707
+
<&cru HCLK_JPEG>,
708
+
<&cru ACLK_RGA2E_0>,
709
+
<&cru HCLK_RGA2E_0>,
710
+
<&cru ACLK_RGA2E_1>,
711
+
<&cru HCLK_RGA2E_1>,
712
+
<&cru ACLK_VDPP>,
713
+
<&cru HCLK_VDPP>;
714
+
pm_qos = <&qos_ebc>,
715
+
<&qos_jpeg>,
716
+
<&qos_rga0>,
717
+
<&qos_rga1>,
718
+
<&qos_vdpp>;
719
+
#power-domain-cells = <0>;
720
+
};
721
+
722
+
power-domain@RK3576_PD_VDEC {
723
+
reg = <RK3576_PD_VDEC>;
724
+
clocks = <&cru ACLK_RKVDEC_ROOT>,
725
+
<&cru HCLK_RKVDEC>;
726
+
pm_qos = <&qos_rkvdec>;
727
+
#power-domain-cells = <0>;
728
+
};
729
+
730
+
power-domain@RK3576_PD_VI {
731
+
reg = <RK3576_PD_VI>;
732
+
clocks = <&cru ACLK_VICAP>,
733
+
<&cru HCLK_VICAP>,
734
+
<&cru DCLK_VICAP>,
735
+
<&cru ACLK_VI_ROOT>,
736
+
<&cru HCLK_VI_ROOT>,
737
+
<&cru PCLK_VI_ROOT>,
738
+
<&cru CLK_ISP_CORE>,
739
+
<&cru ACLK_ISP>,
740
+
<&cru HCLK_ISP>,
741
+
<&cru CLK_CORE_VPSS>,
742
+
<&cru ACLK_VPSS>,
743
+
<&cru HCLK_VPSS>;
744
+
pm_qos = <&qos_isp_mro>,
745
+
<&qos_isp_mwo>,
746
+
<&qos_vicap_m0>,
747
+
<&qos_vpss_mro>,
748
+
<&qos_vpss_mwo>;
749
+
#power-domain-cells = <1>;
750
+
#address-cells = <1>;
751
+
#size-cells = <0>;
752
+
753
+
power-domain@RK3576_PD_VEPU0 {
754
+
reg = <RK3576_PD_VEPU0>;
755
+
clocks = <&cru ACLK_VEPU0>,
756
+
<&cru HCLK_VEPU0>;
757
+
pm_qos = <&qos_vepu0>;
758
+
#power-domain-cells = <0>;
759
+
};
760
+
};
761
+
762
+
power-domain@RK3576_PD_VOP {
763
+
reg = <RK3576_PD_VOP>;
764
+
clocks = <&cru ACLK_VOP>,
765
+
<&cru HCLK_VOP>,
766
+
<&cru HCLK_VOP_ROOT>,
767
+
<&cru PCLK_VOP_ROOT>;
768
+
pm_qos = <&qos_vop_m0>,
769
+
<&qos_vop_m1ro>;
770
+
#power-domain-cells = <1>;
771
+
#address-cells = <1>;
772
+
#size-cells = <0>;
773
+
774
+
power-domain@RK3576_PD_USB {
775
+
reg = <RK3576_PD_USB>;
776
+
clocks = <&cru PCLK_PHP_ROOT>,
777
+
<&cru ACLK_USB_ROOT>,
778
+
<&cru ACLK_MMU2>,
779
+
<&cru ACLK_SLV_MMU2>,
780
+
<&cru ACLK_UFS_SYS>;
781
+
pm_qos = <&qos_mmu2>,
782
+
<&qos_ufshc>;
783
+
#power-domain-cells = <0>;
784
+
};
785
+
786
+
power-domain@RK3576_PD_VO0 {
787
+
reg = <RK3576_PD_VO0>;
788
+
clocks = <&cru ACLK_HDCP0>,
789
+
<&cru HCLK_HDCP0>,
790
+
<&cru ACLK_VO0_ROOT>,
791
+
<&cru PCLK_VO0_ROOT>,
792
+
<&cru HCLK_VOP_ROOT>;
793
+
pm_qos = <&qos_hdcp0>;
794
+
#power-domain-cells = <0>;
795
+
};
796
+
797
+
power-domain@RK3576_PD_VO1 {
798
+
reg = <RK3576_PD_VO1>;
799
+
clocks = <&cru ACLK_HDCP1>,
800
+
<&cru HCLK_HDCP1>,
801
+
<&cru ACLK_VO1_ROOT>,
802
+
<&cru PCLK_VO1_ROOT>,
803
+
<&cru HCLK_VOP_ROOT>;
804
+
pm_qos = <&qos_hdcp1>;
805
+
#power-domain-cells = <0>;
806
+
};
807
+
};
808
+
};
809
+
};
810
+
811
+
gpu: gpu@27800000 {
812
+
compatible = "rockchip,rk3576-mali", "arm,mali-bifrost";
813
+
reg = <0x0 0x27800000 0x0 0x200000>;
814
+
assigned-clocks = <&scmi_clk CLK_GPU>;
815
+
assigned-clock-rates = <198000000>;
816
+
clocks = <&cru CLK_GPU>;
817
+
clock-names = "core";
818
+
dynamic-power-coefficient = <1625>;
819
+
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
820
+
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
821
+
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
822
+
interrupt-names = "job", "mmu", "gpu";
823
+
operating-points-v2 = <&gpu_opp_table>;
824
+
power-domains = <&power RK3576_PD_GPU>;
825
+
#cooling-cells = <2>;
826
+
status = "disabled";
827
+
};
828
+
829
+
qos_hdcp1: qos@27f02000 {
830
+
compatible = "rockchip,rk3576-qos", "syscon";
831
+
reg = <0x0 0x27f02000 0x0 0x20>;
832
+
};
833
+
834
+
qos_fspi1: qos@27f04000 {
835
+
compatible = "rockchip,rk3576-qos", "syscon";
836
+
reg = <0x0 0x27f04000 0x0 0x20>;
837
+
};
838
+
839
+
qos_gmac0: qos@27f04080 {
840
+
compatible = "rockchip,rk3576-qos", "syscon";
841
+
reg = <0x0 0x27f04080 0x0 0x20>;
842
+
};
843
+
844
+
qos_gmac1: qos@27f04100 {
845
+
compatible = "rockchip,rk3576-qos", "syscon";
846
+
reg = <0x0 0x27f04100 0x0 0x20>;
847
+
};
848
+
849
+
qos_sdio: qos@27f04180 {
850
+
compatible = "rockchip,rk3576-qos", "syscon";
851
+
reg = <0x0 0x27f04180 0x0 0x20>;
852
+
};
853
+
854
+
qos_sdmmc: qos@27f04200 {
855
+
compatible = "rockchip,rk3576-qos", "syscon";
856
+
reg = <0x0 0x27f04200 0x0 0x20>;
857
+
};
858
+
859
+
qos_flexbus: qos@27f04280 {
860
+
compatible = "rockchip,rk3576-qos", "syscon";
861
+
reg = <0x0 0x27f04280 0x0 0x20>;
862
+
};
863
+
864
+
qos_gpu: qos@27f05000 {
865
+
compatible = "rockchip,rk3576-qos", "syscon";
866
+
reg = <0x0 0x27f05000 0x0 0x20>;
867
+
};
868
+
869
+
qos_vepu1: qos@27f06000 {
870
+
compatible = "rockchip,rk3576-qos", "syscon";
871
+
reg = <0x0 0x27f06000 0x0 0x20>;
872
+
};
873
+
874
+
qos_npu_mcu: qos@27f08000 {
875
+
compatible = "rockchip,rk3576-qos", "syscon";
876
+
reg = <0x0 0x27f08000 0x0 0x20>;
877
+
};
878
+
879
+
qos_npu_nsp0: qos@27f08080 {
880
+
compatible = "rockchip,rk3576-qos", "syscon";
881
+
reg = <0x0 0x27f08080 0x0 0x20>;
882
+
};
883
+
884
+
qos_npu_nsp1: qos@27f08100 {
885
+
compatible = "rockchip,rk3576-qos", "syscon";
886
+
reg = <0x0 0x27f08100 0x0 0x20>;
887
+
};
888
+
889
+
qos_emmc: qos@27f09000 {
890
+
compatible = "rockchip,rk3576-qos", "syscon";
891
+
reg = <0x0 0x27f09000 0x0 0x20>;
892
+
};
893
+
894
+
qos_fspi0: qos@27f09080 {
895
+
compatible = "rockchip,rk3576-qos", "syscon";
896
+
reg = <0x0 0x27f09080 0x0 0x20>;
897
+
};
898
+
899
+
qos_mmu0: qos@27f0a000 {
900
+
compatible = "rockchip,rk3576-qos", "syscon";
901
+
reg = <0x0 0x27f0a000 0x0 0x20>;
902
+
};
903
+
904
+
qos_mmu1: qos@27f0a080 {
905
+
compatible = "rockchip,rk3576-qos", "syscon";
906
+
reg = <0x0 0x27f0a080 0x0 0x20>;
907
+
};
908
+
909
+
qos_rkvdec: qos@27f0c000 {
910
+
compatible = "rockchip,rk3576-qos", "syscon";
911
+
reg = <0x0 0x27f0c000 0x0 0x20>;
912
+
};
913
+
914
+
qos_crypto: qos@27f0d000 {
915
+
compatible = "rockchip,rk3576-qos", "syscon";
916
+
reg = <0x0 0x27f0d000 0x0 0x20>;
917
+
};
918
+
919
+
qos_mmu2: qos@27f0e000 {
920
+
compatible = "rockchip,rk3576-qos", "syscon";
921
+
reg = <0x0 0x27f0e000 0x0 0x20>;
922
+
};
923
+
924
+
qos_ufshc: qos@27f0e080 {
925
+
compatible = "rockchip,rk3576-qos", "syscon";
926
+
reg = <0x0 0x27f0e080 0x0 0x20>;
927
+
};
928
+
929
+
qos_vepu0: qos@27f0f000 {
930
+
compatible = "rockchip,rk3576-qos", "syscon";
931
+
reg = <0x0 0x27f0f000 0x0 0x20>;
932
+
};
933
+
934
+
qos_isp_mro: qos@27f10000 {
935
+
compatible = "rockchip,rk3576-qos", "syscon";
936
+
reg = <0x0 0x27f10000 0x0 0x20>;
937
+
};
938
+
939
+
qos_isp_mwo: qos@27f10080 {
940
+
compatible = "rockchip,rk3576-qos", "syscon";
941
+
reg = <0x0 0x27f10080 0x0 0x20>;
942
+
};
943
+
944
+
qos_vicap_m0: qos@27f10100 {
945
+
compatible = "rockchip,rk3576-qos", "syscon";
946
+
reg = <0x0 0x27f10100 0x0 0x20>;
947
+
};
948
+
949
+
qos_vpss_mro: qos@27f10180 {
950
+
compatible = "rockchip,rk3576-qos", "syscon";
951
+
reg = <0x0 0x27f10180 0x0 0x20>;
952
+
};
953
+
954
+
qos_vpss_mwo: qos@27f10200 {
955
+
compatible = "rockchip,rk3576-qos", "syscon";
956
+
reg = <0x0 0x27f10200 0x0 0x20>;
957
+
};
958
+
959
+
qos_hdcp0: qos@27f11000 {
960
+
compatible = "rockchip,rk3576-qos", "syscon";
961
+
reg = <0x0 0x27f11000 0x0 0x20>;
962
+
};
963
+
964
+
qos_vop_m0: qos@27f12800 {
965
+
compatible = "rockchip,rk3576-qos", "syscon";
966
+
reg = <0x0 0x27f12800 0x0 0x20>;
967
+
};
968
+
969
+
qos_vop_m1ro: qos@27f12880 {
970
+
compatible = "rockchip,rk3576-qos", "syscon";
971
+
reg = <0x0 0x27f12880 0x0 0x20>;
972
+
};
973
+
974
+
qos_ebc: qos@27f13000 {
975
+
compatible = "rockchip,rk3576-qos", "syscon";
976
+
reg = <0x0 0x27f13000 0x0 0x20>;
977
+
};
978
+
979
+
qos_rga0: qos@27f13080 {
980
+
compatible = "rockchip,rk3576-qos", "syscon";
981
+
reg = <0x0 0x27f13080 0x0 0x20>;
982
+
};
983
+
984
+
qos_rga1: qos@27f13100 {
985
+
compatible = "rockchip,rk3576-qos", "syscon";
986
+
reg = <0x0 0x27f13100 0x0 0x20>;
987
+
};
988
+
989
+
qos_jpeg: qos@27f13180 {
990
+
compatible = "rockchip,rk3576-qos", "syscon";
991
+
reg = <0x0 0x27f13180 0x0 0x20>;
992
+
};
993
+
994
+
qos_vdpp: qos@27f13200 {
995
+
compatible = "rockchip,rk3576-qos", "syscon";
996
+
reg = <0x0 0x27f13200 0x0 0x20>;
997
+
};
998
+
999
+
qos_npu_m0: qos@27f20000 {
1000
+
compatible = "rockchip,rk3576-qos", "syscon";
1001
+
reg = <0x0 0x27f20000 0x0 0x20>;
1002
+
};
1003
+
1004
+
qos_npu_m1: qos@27f21000 {
1005
+
compatible = "rockchip,rk3576-qos", "syscon";
1006
+
reg = <0x0 0x27f21000 0x0 0x20>;
1007
+
};
1008
+
1009
+
qos_npu_m0ro: qos@27f22080 {
1010
+
compatible = "rockchip,rk3576-qos", "syscon";
1011
+
reg = <0x0 0x27f22080 0x0 0x20>;
1012
+
};
1013
+
1014
+
qos_npu_m1ro: qos@27f22100 {
1015
+
compatible = "rockchip,rk3576-qos", "syscon";
1016
+
reg = <0x0 0x27f22100 0x0 0x20>;
1017
+
};
1018
+
1019
+
gmac0: ethernet@2a220000 {
1020
+
compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
1021
+
reg = <0x0 0x2a220000 0x0 0x10000>;
1022
+
clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>,
1023
+
<&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
1024
+
<&cru CLK_GMAC0_PTP_REF>;
1025
+
clock-names = "stmmaceth", "clk_mac_ref",
1026
+
"pclk_mac", "aclk_mac",
1027
+
"ptp_ref";
1028
+
interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1029
+
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1030
+
interrupt-names = "macirq", "eth_wake_irq";
1031
+
power-domains = <&power RK3576_PD_SDGMAC>;
1032
+
resets = <&cru SRST_A_GMAC0>;
1033
+
reset-names = "stmmaceth";
1034
+
rockchip,grf = <&sdgmac_grf>;
1035
+
rockchip,php-grf = <&ioc_grf>;
1036
+
snps,axi-config = <&gmac0_stmmac_axi_setup>;
1037
+
snps,mixed-burst;
1038
+
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
1039
+
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
1040
+
snps,tso;
1041
+
status = "disabled";
1042
+
1043
+
mdio0: mdio {
1044
+
compatible = "snps,dwmac-mdio";
1045
+
#address-cells = <0x1>;
1046
+
#size-cells = <0x0>;
1047
+
};
1048
+
1049
+
gmac0_stmmac_axi_setup: stmmac-axi-config {
1050
+
snps,blen = <0 0 0 0 16 8 4>;
1051
+
snps,rd_osr_lmt = <8>;
1052
+
snps,wr_osr_lmt = <4>;
1053
+
};
1054
+
1055
+
gmac0_mtl_rx_setup: rx-queues-config {
1056
+
snps,rx-queues-to-use = <1>;
1057
+
queue0 {};
1058
+
};
1059
+
1060
+
gmac0_mtl_tx_setup: tx-queues-config {
1061
+
snps,tx-queues-to-use = <1>;
1062
+
queue0 {};
1063
+
};
1064
+
};
1065
+
1066
+
gmac1: ethernet@2a230000 {
1067
+
compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
1068
+
reg = <0x0 0x2a230000 0x0 0x10000>;
1069
+
clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>,
1070
+
<&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
1071
+
<&cru CLK_GMAC1_PTP_REF>;
1072
+
clock-names = "stmmaceth", "clk_mac_ref",
1073
+
"pclk_mac", "aclk_mac",
1074
+
"ptp_ref";
1075
+
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
1076
+
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
1077
+
interrupt-names = "macirq", "eth_wake_irq";
1078
+
power-domains = <&power RK3576_PD_SDGMAC>;
1079
+
resets = <&cru SRST_A_GMAC1>;
1080
+
reset-names = "stmmaceth";
1081
+
rockchip,grf = <&sdgmac_grf>;
1082
+
rockchip,php-grf = <&ioc_grf>;
1083
+
snps,axi-config = <&gmac1_stmmac_axi_setup>;
1084
+
snps,mixed-burst;
1085
+
snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1086
+
snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1087
+
snps,tso;
1088
+
status = "disabled";
1089
+
1090
+
mdio1: mdio {
1091
+
compatible = "snps,dwmac-mdio";
1092
+
#address-cells = <0x1>;
1093
+
#size-cells = <0x0>;
1094
+
};
1095
+
1096
+
gmac1_stmmac_axi_setup: stmmac-axi-config {
1097
+
snps,blen = <0 0 0 0 16 8 4>;
1098
+
snps,rd_osr_lmt = <8>;
1099
+
snps,wr_osr_lmt = <4>;
1100
+
};
1101
+
1102
+
gmac1_mtl_rx_setup: rx-queues-config {
1103
+
snps,rx-queues-to-use = <1>;
1104
+
queue0 {};
1105
+
};
1106
+
1107
+
gmac1_mtl_tx_setup: tx-queues-config {
1108
+
snps,tx-queues-to-use = <1>;
1109
+
queue0 {};
1110
+
};
1111
+
};
1112
+
1113
+
sdmmc: mmc@2a310000 {
1114
+
compatible = "rockchip,rk3576-dw-mshc";
1115
+
reg = <0x0 0x2a310000 0x0 0x4000>;
1116
+
clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
1117
+
clock-names = "biu", "ciu";
1118
+
fifo-depth = <0x100>;
1119
+
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
1120
+
max-frequency = <200000000>;
1121
+
pinctrl-names = "default";
1122
+
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>;
1123
+
power-domains = <&power RK3576_PD_SDGMAC>;
1124
+
resets = <&cru SRST_H_SDMMC0>;
1125
+
reset-names = "reset";
1126
+
status = "disabled";
1127
+
};
1128
+
1129
+
sdhci: mmc@2a330000 {
1130
+
compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc";
1131
+
reg = <0x0 0x2a330000 0x0 0x10000>;
1132
+
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
1133
+
assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1134
+
clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
1135
+
<&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1136
+
<&cru TCLK_EMMC>;
1137
+
clock-names = "core", "bus", "axi", "block", "timer";
1138
+
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
1139
+
max-frequency = <200000000>;
1140
+
pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1141
+
<&emmc_cmd>, <&emmc_strb>;
1142
+
pinctrl-names = "default";
1143
+
power-domains = <&power RK3576_PD_NVM>;
1144
+
resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1145
+
<&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1146
+
<&cru SRST_T_EMMC>;
1147
+
reset-names = "core", "bus", "axi", "block", "timer";
1148
+
supports-cqe;
1149
+
status = "disabled";
1150
+
};
1151
+
1152
+
gic: interrupt-controller@2a701000 {
1153
+
compatible = "arm,gic-400";
1154
+
reg = <0x0 0x2a701000 0 0x10000>,
1155
+
<0x0 0x2a702000 0 0x10000>,
1156
+
<0x0 0x2a704000 0 0x10000>,
1157
+
<0x0 0x2a706000 0 0x10000>;
1158
+
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1159
+
interrupt-controller;
1160
+
#interrupt-cells = <3>;
1161
+
#address-cells = <2>;
1162
+
#size-cells = <2>;
1163
+
};
1164
+
1165
+
dmac0: dma-controller@2ab90000 {
1166
+
compatible = "arm,pl330", "arm,primecell";
1167
+
reg = <0x0 0x2ab90000 0x0 0x4000>;
1168
+
arm,pl330-periph-burst;
1169
+
clocks = <&cru ACLK_DMAC0>;
1170
+
clock-names = "apb_pclk";
1171
+
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1172
+
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1173
+
#dma-cells = <1>;
1174
+
};
1175
+
1176
+
dmac1: dma-controller@2abb0000 {
1177
+
compatible = "arm,pl330", "arm,primecell";
1178
+
reg = <0x0 0x2abb0000 0x0 0x4000>;
1179
+
arm,pl330-periph-burst;
1180
+
clocks = <&cru ACLK_DMAC1>;
1181
+
clock-names = "apb_pclk";
1182
+
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1183
+
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1184
+
#dma-cells = <1>;
1185
+
};
1186
+
1187
+
dmac2: dma-controller@2abd0000 {
1188
+
compatible = "arm,pl330", "arm,primecell";
1189
+
reg = <0x0 0x2abd0000 0x0 0x4000>;
1190
+
arm,pl330-periph-burst;
1191
+
clocks = <&cru ACLK_DMAC2>;
1192
+
clock-names = "apb_pclk";
1193
+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1194
+
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1195
+
#dma-cells = <1>;
1196
+
};
1197
+
1198
+
i2c1: i2c@2ac40000 {
1199
+
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1200
+
reg = <0x0 0x2ac40000 0x0 0x1000>;
1201
+
clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1202
+
clock-names = "i2c", "pclk";
1203
+
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1204
+
pinctrl-names = "default";
1205
+
pinctrl-0 = <&i2c1m0_xfer>;
1206
+
#address-cells = <1>;
1207
+
#size-cells = <0>;
1208
+
status = "disabled";
1209
+
};
1210
+
1211
+
i2c2: i2c@2ac50000 {
1212
+
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1213
+
reg = <0x0 0x2ac50000 0x0 0x1000>;
1214
+
clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1215
+
clock-names = "i2c", "pclk";
1216
+
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1217
+
pinctrl-names = "default";
1218
+
pinctrl-0 = <&i2c2m0_xfer>;
1219
+
#address-cells = <1>;
1220
+
#size-cells = <0>;
1221
+
status = "disabled";
1222
+
};
1223
+
1224
+
i2c3: i2c@2ac60000 {
1225
+
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1226
+
reg = <0x0 0x2ac60000 0x0 0x1000>;
1227
+
clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1228
+
clock-names = "i2c", "pclk";
1229
+
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1230
+
pinctrl-names = "default";
1231
+
pinctrl-0 = <&i2c3m0_xfer>;
1232
+
#address-cells = <1>;
1233
+
#size-cells = <0>;
1234
+
status = "disabled";
1235
+
};
1236
+
1237
+
i2c4: i2c@2ac70000 {
1238
+
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1239
+
reg = <0x0 0x2ac70000 0x0 0x1000>;
1240
+
clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1241
+
clock-names = "i2c", "pclk";
1242
+
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1243
+
pinctrl-names = "default";
1244
+
pinctrl-0 = <&i2c4m0_xfer>;
1245
+
#address-cells = <1>;
1246
+
#size-cells = <0>;
1247
+
status = "disabled";
1248
+
};
1249
+
1250
+
i2c5: i2c@2ac80000 {
1251
+
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1252
+
reg = <0x0 0x2ac80000 0x0 0x1000>;
1253
+
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1254
+
clock-names = "i2c", "pclk";
1255
+
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1256
+
pinctrl-names = "default";
1257
+
pinctrl-0 = <&i2c5m0_xfer>;
1258
+
#address-cells = <1>;
1259
+
#size-cells = <0>;
1260
+
status = "disabled";
1261
+
};
1262
+
1263
+
1264
+
i2c6: i2c@2ac90000 {
1265
+
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1266
+
reg = <0x0 0x2ac90000 0x0 0x1000>;
1267
+
clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
1268
+
clock-names = "i2c", "pclk";
1269
+
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1270
+
pinctrl-names = "default";
1271
+
pinctrl-0 = <&i2c6m0_xfer>;
1272
+
#address-cells = <1>;
1273
+
#size-cells = <0>;
1274
+
status = "disabled";
1275
+
};
1276
+
1277
+
i2c7: i2c@2aca0000 {
1278
+
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1279
+
reg = <0x0 0x2aca0000 0x0 0x1000>;
1280
+
clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
1281
+
clock-names = "i2c", "pclk";
1282
+
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1283
+
pinctrl-names = "default";
1284
+
pinctrl-0 = <&i2c7m0_xfer>;
1285
+
#address-cells = <1>;
1286
+
#size-cells = <0>;
1287
+
status = "disabled";
1288
+
};
1289
+
1290
+
i2c8: i2c@2acb0000 {
1291
+
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1292
+
reg = <0x0 0x2acb0000 0x0 0x1000>;
1293
+
clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
1294
+
clock-names = "i2c", "pclk";
1295
+
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1296
+
pinctrl-names = "default";
1297
+
pinctrl-0 = <&i2c8m0_xfer>;
1298
+
#address-cells = <1>;
1299
+
#size-cells = <0>;
1300
+
status = "disabled";
1301
+
};
1302
+
1303
+
timer0: timer@2acc0000 {
1304
+
compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer";
1305
+
reg = <0x0 0x2acc0000 0x0 0x20>;
1306
+
clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>;
1307
+
clock-names = "pclk", "timer";
1308
+
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1309
+
};
1310
+
1311
+
wdt: watchdog@2ace0000 {
1312
+
compatible = "rockchip,rk3576-wdt", "snps,dw-wdt";
1313
+
reg = <0x0 0x2ace0000 0x0 0x100>;
1314
+
clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
1315
+
clock-names = "tclk", "pclk";
1316
+
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1317
+
status = "disabled";
1318
+
};
1319
+
1320
+
spi0: spi@2acf0000 {
1321
+
compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1322
+
reg = <0x0 0x2acf0000 0x0 0x1000>;
1323
+
clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1324
+
clock-names = "spiclk", "apb_pclk";
1325
+
dmas = <&dmac0 14>, <&dmac0 15>;
1326
+
dma-names = "tx", "rx";
1327
+
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1328
+
num-cs = <2>;
1329
+
pinctrl-names = "default";
1330
+
pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
1331
+
#address-cells = <1>;
1332
+
#size-cells = <0>;
1333
+
status = "disabled";
1334
+
};
1335
+
1336
+
spi1: spi@2ad00000 {
1337
+
compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1338
+
reg = <0x0 0x2ad00000 0x0 0x1000>;
1339
+
clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1340
+
clock-names = "spiclk", "apb_pclk";
1341
+
dmas = <&dmac0 16>, <&dmac0 17>;
1342
+
dma-names = "tx", "rx";
1343
+
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1344
+
num-cs = <2>;
1345
+
pinctrl-names = "default";
1346
+
pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
1347
+
#address-cells = <1>;
1348
+
#size-cells = <0>;
1349
+
status = "disabled";
1350
+
};
1351
+
1352
+
spi2: spi@2ad10000 {
1353
+
compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1354
+
reg = <0x0 0x2ad10000 0x0 0x1000>;
1355
+
clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1356
+
clock-names = "spiclk", "apb_pclk";
1357
+
dmas = <&dmac1 15>, <&dmac1 16>;
1358
+
dma-names = "tx", "rx";
1359
+
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1360
+
num-cs = <2>;
1361
+
pinctrl-names = "default";
1362
+
pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
1363
+
#address-cells = <1>;
1364
+
#size-cells = <0>;
1365
+
status = "disabled";
1366
+
};
1367
+
1368
+
spi3: spi@2ad20000 {
1369
+
compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1370
+
reg = <0x0 0x2ad20000 0x0 0x1000>;
1371
+
clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1372
+
clock-names = "spiclk", "apb_pclk";
1373
+
dmas = <&dmac1 17>, <&dmac1 18>;
1374
+
dma-names = "tx", "rx";
1375
+
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1376
+
num-cs = <2>;
1377
+
pinctrl-names = "default";
1378
+
pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>;
1379
+
#address-cells = <1>;
1380
+
#size-cells = <0>;
1381
+
status = "disabled";
1382
+
};
1383
+
1384
+
spi4: spi@2ad30000 {
1385
+
compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1386
+
reg = <0x0 0x2ad30000 0x0 0x1000>;
1387
+
clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
1388
+
clock-names = "spiclk", "apb_pclk";
1389
+
dmas = <&dmac2 12>, <&dmac2 13>;
1390
+
dma-names = "tx", "rx";
1391
+
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1392
+
num-cs = <2>;
1393
+
pinctrl-names = "default";
1394
+
pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>;
1395
+
#address-cells = <1>;
1396
+
#size-cells = <0>;
1397
+
status = "disabled";
1398
+
};
1399
+
1400
+
uart0: serial@2ad40000 {
1401
+
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1402
+
reg = <0x0 0x2ad40000 0x0 0x100>;
1403
+
reg-shift = <2>;
1404
+
reg-io-width = <4>;
1405
+
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
1406
+
clock-names = "baudclk", "apb_pclk";
1407
+
dmas = <&dmac0 6>, <&dmac0 7>;
1408
+
dma-names = "tx", "rx";
1409
+
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1410
+
pinctrl-0 = <&uart0m0_xfer>;
1411
+
pinctrl-names = "default";
1412
+
status = "disabled";
1413
+
};
1414
+
1415
+
uart2: serial@2ad50000 {
1416
+
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1417
+
reg = <0x0 0x2ad50000 0x0 0x100>;
1418
+
reg-shift = <2>;
1419
+
reg-io-width = <4>;
1420
+
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1421
+
clock-names = "baudclk", "apb_pclk";
1422
+
dmas = <&dmac0 10>, <&dmac0 11>;
1423
+
dma-names = "tx", "rx";
1424
+
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1425
+
pinctrl-names = "default";
1426
+
pinctrl-0 = <&uart2m0_xfer>;
1427
+
status = "disabled";
1428
+
};
1429
+
1430
+
uart3: serial@2ad60000 {
1431
+
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1432
+
reg = <0x0 0x2ad60000 0x0 0x100>;
1433
+
reg-shift = <2>;
1434
+
reg-io-width = <4>;
1435
+
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1436
+
clock-names = "baudclk", "apb_pclk";
1437
+
dmas = <&dmac0 12>, <&dmac0 13>;
1438
+
dma-names = "tx", "rx";
1439
+
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1440
+
pinctrl-0 = <&uart3m0_xfer>;
1441
+
pinctrl-names = "default";
1442
+
status = "disabled";
1443
+
};
1444
+
1445
+
uart4: serial@2ad70000 {
1446
+
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1447
+
reg = <0x0 0x2ad70000 0x0 0x100>;
1448
+
reg-shift = <2>;
1449
+
reg-io-width = <4>;
1450
+
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1451
+
clock-names = "baudclk", "apb_pclk";
1452
+
dmas = <&dmac1 9>, <&dmac1 10>;
1453
+
dma-names = "tx", "rx";
1454
+
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1455
+
pinctrl-0 = <&uart4m0_xfer>;
1456
+
pinctrl-names = "default";
1457
+
status = "disabled";
1458
+
};
1459
+
1460
+
uart5: serial@2ad80000 {
1461
+
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1462
+
reg = <0x0 0x2ad80000 0x0 0x100>;
1463
+
reg-shift = <2>;
1464
+
reg-io-width = <4>;
1465
+
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1466
+
clock-names = "baudclk", "apb_pclk";
1467
+
dmas = <&dmac1 11>, <&dmac1 12>;
1468
+
dma-names = "tx", "rx";
1469
+
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1470
+
pinctrl-0 = <&uart5m0_xfer>;
1471
+
pinctrl-names = "default";
1472
+
status = "disabled";
1473
+
};
1474
+
1475
+
uart6: serial@2ad90000 {
1476
+
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1477
+
reg = <0x0 0x2ad90000 0x0 0x100>;
1478
+
reg-shift = <2>;
1479
+
reg-io-width = <4>;
1480
+
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1481
+
clock-names = "baudclk", "apb_pclk";
1482
+
dmas = <&dmac1 13>, <&dmac1 14>;
1483
+
dma-names = "tx", "rx";
1484
+
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1485
+
pinctrl-0 = <&uart6m0_xfer>;
1486
+
pinctrl-names = "default";
1487
+
status = "disabled";
1488
+
};
1489
+
1490
+
uart7: serial@2ada0000 {
1491
+
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1492
+
reg = <0x0 0x2ada0000 0x0 0x100>;
1493
+
reg-shift = <2>;
1494
+
reg-io-width = <4>;
1495
+
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1496
+
clock-names = "baudclk", "apb_pclk";
1497
+
dmas = <&dmac2 6>, <&dmac2 7>;
1498
+
dma-names = "tx", "rx";
1499
+
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1500
+
pinctrl-0 = <&uart7m0_xfer>;
1501
+
pinctrl-names = "default";
1502
+
status = "disabled";
1503
+
};
1504
+
1505
+
uart8: serial@2adb0000 {
1506
+
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1507
+
reg = <0x0 0x2adb0000 0x0 0x100>;
1508
+
reg-shift = <2>;
1509
+
reg-io-width = <4>;
1510
+
clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1511
+
clock-names = "baudclk", "apb_pclk";
1512
+
dmas = <&dmac2 8>, <&dmac2 9>;
1513
+
dma-names = "tx", "rx";
1514
+
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1515
+
pinctrl-0 = <&uart8m0_xfer>;
1516
+
pinctrl-names = "default";
1517
+
status = "disabled";
1518
+
};
1519
+
1520
+
uart9: serial@2adc0000 {
1521
+
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1522
+
reg = <0x0 0x2adc0000 0x0 0x100>;
1523
+
reg-shift = <2>;
1524
+
reg-io-width = <4>;
1525
+
clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1526
+
clock-names = "baudclk", "apb_pclk";
1527
+
dmas = <&dmac2 10>, <&dmac2 11>;
1528
+
dma-names = "tx", "rx";
1529
+
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1530
+
pinctrl-0 = <&uart9m0_xfer>;
1531
+
pinctrl-names = "default";
1532
+
status = "disabled";
1533
+
};
1534
+
1535
+
saradc: adc@2ae00000 {
1536
+
compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc";
1537
+
reg = <0x0 0x2ae00000 0x0 0x10000>;
1538
+
clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1539
+
clock-names = "saradc", "apb_pclk";
1540
+
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1541
+
resets = <&cru SRST_P_SARADC>;
1542
+
reset-names = "saradc-apb";
1543
+
#io-channel-cells = <1>;
1544
+
status = "disabled";
1545
+
};
1546
+
1547
+
i2c9: i2c@2ae80000 {
1548
+
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1549
+
reg = <0x0 0x2ae80000 0x0 0x1000>;
1550
+
clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>;
1551
+
clock-names = "i2c", "pclk";
1552
+
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1553
+
pinctrl-names = "default";
1554
+
pinctrl-0 = <&i2c9m0_xfer>;
1555
+
resets = <&cru SRST_I2C9>, <&cru SRST_P_I2C9>;
1556
+
reset-names = "i2c", "apb";
1557
+
#address-cells = <1>;
1558
+
#size-cells = <0>;
1559
+
status = "disabled";
1560
+
};
1561
+
1562
+
uart10: serial@2afc0000 {
1563
+
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1564
+
reg = <0x0 0x2afc0000 0x0 0x100>;
1565
+
reg-shift = <2>;
1566
+
reg-io-width = <4>;
1567
+
clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>;
1568
+
clock-names = "baudclk", "apb_pclk";
1569
+
dmas = <&dmac2 21>, <&dmac2 22>;
1570
+
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1571
+
pinctrl-names = "default";
1572
+
pinctrl-0 = <&uart10m0_xfer>;
1573
+
status = "disabled";
1574
+
};
1575
+
1576
+
uart11: serial@2afd0000 {
1577
+
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1578
+
reg = <0x0 0x2afd0000 0x0 0x100>;
1579
+
reg-shift = <2>;
1580
+
reg-io-width = <4>;
1581
+
clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>;
1582
+
clock-names = "baudclk", "apb_pclk";
1583
+
dmas = <&dmac2 23>, <&dmac2 24>;
1584
+
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1585
+
pinctrl-names = "default";
1586
+
pinctrl-0 = <&uart11m0_xfer>;
1587
+
status = "disabled";
1588
+
};
1589
+
1590
+
sram: sram@3ff88000 {
1591
+
compatible = "mmio-sram";
1592
+
reg = <0x0 0x3ff88000 0x0 0x78000>;
1593
+
ranges = <0x0 0x0 0x3ff88000 0x78000>;
1594
+
#address-cells = <1>;
1595
+
#size-cells = <1>;
1596
+
1597
+
/* start address and size should be 4k align */
1598
+
rkvdec_sram: rkvdec-sram@0 {
1599
+
reg = <0x0 0x78000>;
1600
+
};
1601
+
};
1602
+
1603
+
scmi_shmem: scmi-shmem@4010f000 {
1604
+
compatible = "arm,scmi-shmem";
1605
+
reg = <0x0 0x4010f000 0x0 0x100>;
1606
+
};
1607
+
1608
+
pinctrl: pinctrl {
1609
+
compatible = "rockchip,rk3576-pinctrl";
1610
+
rockchip,grf = <&ioc_grf>;
1611
+
#address-cells = <2>;
1612
+
#size-cells = <2>;
1613
+
ranges;
1614
+
1615
+
gpio0: gpio@27320000 {
1616
+
compatible = "rockchip,gpio-bank";
1617
+
reg = <0x0 0x27320000 0x0 0x200>;
1618
+
clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
1619
+
gpio-controller;
1620
+
gpio-ranges = <&pinctrl 0 0 32>;
1621
+
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1622
+
interrupt-controller;
1623
+
#gpio-cells = <2>;
1624
+
#interrupt-cells = <2>;
1625
+
};
1626
+
1627
+
gpio1: gpio@2ae10000 {
1628
+
compatible = "rockchip,gpio-bank";
1629
+
reg = <0x0 0x2ae10000 0x0 0x200>;
1630
+
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1631
+
gpio-controller;
1632
+
gpio-ranges = <&pinctrl 0 32 32>;
1633
+
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1634
+
interrupt-controller;
1635
+
#gpio-cells = <2>;
1636
+
#interrupt-cells = <2>;
1637
+
};
1638
+
1639
+
gpio2: gpio@2ae20000 {
1640
+
compatible = "rockchip,gpio-bank";
1641
+
reg = <0x0 0x2ae20000 0x0 0x200>;
1642
+
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1643
+
gpio-controller;
1644
+
gpio-ranges = <&pinctrl 0 64 32>;
1645
+
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
1646
+
interrupt-controller;
1647
+
#gpio-cells = <2>;
1648
+
#interrupt-cells = <2>;
1649
+
};
1650
+
1651
+
gpio3: gpio@2ae30000 {
1652
+
compatible = "rockchip,gpio-bank";
1653
+
reg = <0x0 0x2ae30000 0x0 0x200>;
1654
+
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1655
+
gpio-controller;
1656
+
gpio-ranges = <&pinctrl 0 96 32>;
1657
+
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1658
+
interrupt-controller;
1659
+
#gpio-cells = <2>;
1660
+
#interrupt-cells = <2>;
1661
+
};
1662
+
1663
+
gpio4: gpio@2ae40000 {
1664
+
compatible = "rockchip,gpio-bank";
1665
+
reg = <0x0 0x2ae40000 0x0 0x200>;
1666
+
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
1667
+
gpio-controller;
1668
+
gpio-ranges = <&pinctrl 0 128 32>;
1669
+
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1670
+
interrupt-controller;
1671
+
#gpio-cells = <2>;
1672
+
#interrupt-cells = <2>;
1673
+
};
1674
+
};
1675
+
};
1676
+
};
1677
+
1678
+
#include "rk3576-pinctrl.dtsi"
+455
arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi
+455
arch/arm64/boot/dts/rockchip/rk3588-armsom-lm7.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
3
+
/dts-v1/;
4
+
5
+
#include <dt-bindings/gpio/gpio.h>
6
+
#include <dt-bindings/leds/common.h>
7
+
#include "rk3588.dtsi"
8
+
9
+
/ {
10
+
compatible = "armsom,lm7", "rockchip,rk3588";
11
+
12
+
aliases {
13
+
mmc0 = &sdhci;
14
+
};
15
+
16
+
chosen {
17
+
stdout-path = "serial2:1500000n8";
18
+
};
19
+
20
+
vcc5v0_sys: vcc5v0-sys-regulator {
21
+
compatible = "regulator-fixed";
22
+
regulator-name = "vcc5v0_sys";
23
+
regulator-always-on;
24
+
regulator-boot-on;
25
+
regulator-min-microvolt = <5000000>;
26
+
regulator-max-microvolt = <5000000>;
27
+
};
28
+
29
+
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
30
+
compatible = "regulator-fixed";
31
+
regulator-name = "vcc_1v1_nldo_s3";
32
+
regulator-always-on;
33
+
regulator-boot-on;
34
+
regulator-min-microvolt = <1100000>;
35
+
regulator-max-microvolt = <1100000>;
36
+
vin-supply = <&vcc5v0_sys>;
37
+
};
38
+
};
39
+
40
+
&cpu_b0 {
41
+
cpu-supply = <&vdd_cpu_big0_s0>;
42
+
};
43
+
44
+
&cpu_b1 {
45
+
cpu-supply = <&vdd_cpu_big0_s0>;
46
+
};
47
+
48
+
&cpu_b2 {
49
+
cpu-supply = <&vdd_cpu_big1_s0>;
50
+
};
51
+
52
+
&cpu_b3 {
53
+
cpu-supply = <&vdd_cpu_big1_s0>;
54
+
};
55
+
56
+
&cpu_l0 {
57
+
cpu-supply = <&vdd_cpu_lit_s0>;
58
+
};
59
+
60
+
&cpu_l1 {
61
+
cpu-supply = <&vdd_cpu_lit_s0>;
62
+
};
63
+
64
+
&cpu_l2 {
65
+
cpu-supply = <&vdd_cpu_lit_s0>;
66
+
};
67
+
68
+
&cpu_l3 {
69
+
cpu-supply = <&vdd_cpu_lit_s0>;
70
+
};
71
+
72
+
&gpu {
73
+
mali-supply = <&vdd_gpu_s0>;
74
+
status = "okay";
75
+
};
76
+
77
+
&i2c0 {
78
+
pinctrl-names = "default";
79
+
pinctrl-0 = <&i2c0m2_xfer>;
80
+
status = "okay";
81
+
82
+
vdd_cpu_big0_s0: regulator@42 {
83
+
compatible = "rockchip,rk8602";
84
+
reg = <0x42>;
85
+
fcs,suspend-voltage-selector = <1>;
86
+
regulator-name = "vdd_cpu_big0_s0";
87
+
regulator-always-on;
88
+
regulator-boot-on;
89
+
regulator-min-microvolt = <550000>;
90
+
regulator-max-microvolt = <1050000>;
91
+
regulator-ramp-delay = <2300>;
92
+
vin-supply = <&vcc5v0_sys>;
93
+
94
+
regulator-state-mem {
95
+
regulator-off-in-suspend;
96
+
};
97
+
};
98
+
99
+
vdd_cpu_big1_s0: regulator@43 {
100
+
compatible = "rockchip,rk8603", "rockchip,rk8602";
101
+
reg = <0x43>;
102
+
fcs,suspend-voltage-selector = <1>;
103
+
regulator-name = "vdd_cpu_big1_s0";
104
+
regulator-always-on;
105
+
regulator-boot-on;
106
+
regulator-min-microvolt = <550000>;
107
+
regulator-max-microvolt = <1050000>;
108
+
regulator-ramp-delay = <2300>;
109
+
vin-supply = <&vcc5v0_sys>;
110
+
111
+
regulator-state-mem {
112
+
regulator-off-in-suspend;
113
+
};
114
+
};
115
+
};
116
+
117
+
&saradc {
118
+
vref-supply = <&avcc_1v8_s0>;
119
+
status = "okay";
120
+
};
121
+
122
+
&sdhci {
123
+
bus-width = <8>;
124
+
mmc-hs400-1_8v;
125
+
mmc-hs400-enhanced-strobe;
126
+
no-sdio;
127
+
no-sd;
128
+
non-removable;
129
+
status = "okay";
130
+
};
131
+
132
+
&spi2 {
133
+
assigned-clocks = <&cru CLK_SPI2>;
134
+
assigned-clock-rates = <200000000>;
135
+
num-cs = <1>;
136
+
pinctrl-names = "default";
137
+
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
138
+
status = "okay";
139
+
140
+
pmic@0 {
141
+
compatible = "rockchip,rk806";
142
+
reg = <0x0>;
143
+
interrupt-parent = <&gpio0>;
144
+
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
145
+
gpio-controller;
146
+
#gpio-cells = <2>;
147
+
pinctrl-names = "default";
148
+
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
149
+
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
150
+
spi-max-frequency = <1000000>;
151
+
system-power-controller;
152
+
153
+
vcc1-supply = <&vcc5v0_sys>;
154
+
vcc2-supply = <&vcc5v0_sys>;
155
+
vcc3-supply = <&vcc5v0_sys>;
156
+
vcc4-supply = <&vcc5v0_sys>;
157
+
vcc5-supply = <&vcc5v0_sys>;
158
+
vcc6-supply = <&vcc5v0_sys>;
159
+
vcc7-supply = <&vcc5v0_sys>;
160
+
vcc8-supply = <&vcc5v0_sys>;
161
+
vcc9-supply = <&vcc5v0_sys>;
162
+
vcc10-supply = <&vcc5v0_sys>;
163
+
vcc11-supply = <&vcc_2v0_pldo_s3>;
164
+
vcc12-supply = <&vcc5v0_sys>;
165
+
vcc13-supply = <&vcc_1v1_nldo_s3>;
166
+
vcc14-supply = <&vcc_1v1_nldo_s3>;
167
+
vcca-supply = <&vcc5v0_sys>;
168
+
169
+
rk806_dvs1_null: dvs1-null-pins {
170
+
pins = "gpio_pwrctrl1";
171
+
function = "pin_fun0";
172
+
};
173
+
174
+
rk806_dvs2_null: dvs2-null-pins {
175
+
pins = "gpio_pwrctrl2";
176
+
function = "pin_fun0";
177
+
};
178
+
179
+
rk806_dvs3_null: dvs3-null-pins {
180
+
pins = "gpio_pwrctrl3";
181
+
function = "pin_fun0";
182
+
};
183
+
184
+
regulators {
185
+
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
186
+
regulator-name = "vdd_gpu_s0";
187
+
regulator-boot-on;
188
+
regulator-min-microvolt = <550000>;
189
+
regulator-max-microvolt = <950000>;
190
+
regulator-ramp-delay = <12500>;
191
+
regulator-enable-ramp-delay = <400>;
192
+
193
+
regulator-state-mem {
194
+
regulator-off-in-suspend;
195
+
};
196
+
};
197
+
198
+
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
199
+
regulator-name = "vdd_cpu_lit_s0";
200
+
regulator-always-on;
201
+
regulator-boot-on;
202
+
regulator-min-microvolt = <550000>;
203
+
regulator-max-microvolt = <950000>;
204
+
regulator-ramp-delay = <12500>;
205
+
206
+
regulator-state-mem {
207
+
regulator-off-in-suspend;
208
+
};
209
+
};
210
+
211
+
vdd_log_s0: dcdc-reg3 {
212
+
regulator-name = "vdd_log_s0";
213
+
regulator-always-on;
214
+
regulator-boot-on;
215
+
regulator-min-microvolt = <675000>;
216
+
regulator-max-microvolt = <750000>;
217
+
regulator-ramp-delay = <12500>;
218
+
219
+
regulator-state-mem {
220
+
regulator-off-in-suspend;
221
+
regulator-suspend-microvolt = <750000>;
222
+
};
223
+
};
224
+
225
+
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
226
+
regulator-name = "vdd_vdenc_s0";
227
+
regulator-always-on;
228
+
regulator-boot-on;
229
+
regulator-min-microvolt = <550000>;
230
+
regulator-max-microvolt = <950000>;
231
+
regulator-ramp-delay = <12500>;
232
+
233
+
regulator-state-mem {
234
+
regulator-off-in-suspend;
235
+
};
236
+
};
237
+
238
+
vdd_ddr_s0: dcdc-reg5 {
239
+
regulator-name = "vdd_ddr_s0";
240
+
regulator-always-on;
241
+
regulator-boot-on;
242
+
regulator-min-microvolt = <675000>;
243
+
regulator-max-microvolt = <900000>;
244
+
regulator-ramp-delay = <12500>;
245
+
246
+
regulator-state-mem {
247
+
regulator-off-in-suspend;
248
+
regulator-suspend-microvolt = <850000>;
249
+
};
250
+
};
251
+
252
+
vdd2_ddr_s3: dcdc-reg6 {
253
+
regulator-name = "vdd2_ddr_s3";
254
+
regulator-always-on;
255
+
regulator-boot-on;
256
+
257
+
regulator-state-mem {
258
+
regulator-on-in-suspend;
259
+
};
260
+
};
261
+
262
+
vcc_2v0_pldo_s3: dcdc-reg7 {
263
+
regulator-name = "vdd_2v0_pldo_s3";
264
+
regulator-always-on;
265
+
regulator-boot-on;
266
+
regulator-min-microvolt = <2000000>;
267
+
regulator-max-microvolt = <2000000>;
268
+
regulator-ramp-delay = <12500>;
269
+
270
+
regulator-state-mem {
271
+
regulator-on-in-suspend;
272
+
regulator-suspend-microvolt = <2000000>;
273
+
};
274
+
};
275
+
276
+
vcc_3v3_s3: dcdc-reg8 {
277
+
regulator-name = "vcc_3v3_s3";
278
+
regulator-always-on;
279
+
regulator-boot-on;
280
+
regulator-min-microvolt = <3300000>;
281
+
regulator-max-microvolt = <3300000>;
282
+
283
+
regulator-state-mem {
284
+
regulator-on-in-suspend;
285
+
regulator-suspend-microvolt = <3300000>;
286
+
};
287
+
};
288
+
289
+
vddq_ddr_s0: dcdc-reg9 {
290
+
regulator-name = "vddq_ddr_s0";
291
+
regulator-always-on;
292
+
regulator-boot-on;
293
+
294
+
regulator-state-mem {
295
+
regulator-off-in-suspend;
296
+
};
297
+
};
298
+
299
+
vcc_1v8_s3: dcdc-reg10 {
300
+
regulator-name = "vcc_1v8_s3";
301
+
regulator-always-on;
302
+
regulator-boot-on;
303
+
regulator-min-microvolt = <1800000>;
304
+
regulator-max-microvolt = <1800000>;
305
+
306
+
regulator-state-mem {
307
+
regulator-on-in-suspend;
308
+
regulator-suspend-microvolt = <1800000>;
309
+
};
310
+
};
311
+
312
+
avcc_1v8_s0: pldo-reg1 {
313
+
regulator-name = "avcc_1v8_s0";
314
+
regulator-always-on;
315
+
regulator-boot-on;
316
+
regulator-min-microvolt = <1800000>;
317
+
regulator-max-microvolt = <1800000>;
318
+
319
+
regulator-state-mem {
320
+
regulator-off-in-suspend;
321
+
};
322
+
};
323
+
324
+
vcc_1v8_s0: pldo-reg2 {
325
+
regulator-name = "vcc_1v8_s0";
326
+
regulator-always-on;
327
+
regulator-boot-on;
328
+
regulator-min-microvolt = <1800000>;
329
+
regulator-max-microvolt = <1800000>;
330
+
331
+
regulator-state-mem {
332
+
regulator-off-in-suspend;
333
+
regulator-suspend-microvolt = <1800000>;
334
+
};
335
+
};
336
+
337
+
avdd_1v2_s0: pldo-reg3 {
338
+
regulator-name = "avdd_1v2_s0";
339
+
regulator-always-on;
340
+
regulator-boot-on;
341
+
regulator-min-microvolt = <1200000>;
342
+
regulator-max-microvolt = <1200000>;
343
+
344
+
regulator-state-mem {
345
+
regulator-off-in-suspend;
346
+
};
347
+
};
348
+
349
+
vcc_3v3_s0: pldo-reg4 {
350
+
regulator-name = "vcc_3v3_s0";
351
+
regulator-always-on;
352
+
regulator-boot-on;
353
+
regulator-min-microvolt = <3300000>;
354
+
regulator-max-microvolt = <3300000>;
355
+
regulator-ramp-delay = <12500>;
356
+
357
+
regulator-state-mem {
358
+
regulator-off-in-suspend;
359
+
};
360
+
};
361
+
362
+
vccio_sd_s0: pldo-reg5 {
363
+
regulator-name = "vccio_sd_s0";
364
+
regulator-always-on;
365
+
regulator-boot-on;
366
+
regulator-min-microvolt = <1800000>;
367
+
regulator-max-microvolt = <3300000>;
368
+
regulator-ramp-delay = <12500>;
369
+
370
+
regulator-state-mem {
371
+
regulator-off-in-suspend;
372
+
};
373
+
};
374
+
375
+
pldo6_s3: pldo-reg6 {
376
+
regulator-name = "pldo6_s3";
377
+
regulator-always-on;
378
+
regulator-boot-on;
379
+
regulator-min-microvolt = <1800000>;
380
+
regulator-max-microvolt = <1800000>;
381
+
382
+
regulator-state-mem {
383
+
regulator-on-in-suspend;
384
+
regulator-suspend-microvolt = <1800000>;
385
+
};
386
+
};
387
+
388
+
vdd_0v75_s3: nldo-reg1 {
389
+
regulator-name = "vdd_0v75_s3";
390
+
regulator-always-on;
391
+
regulator-boot-on;
392
+
regulator-min-microvolt = <750000>;
393
+
regulator-max-microvolt = <750000>;
394
+
395
+
regulator-state-mem {
396
+
regulator-on-in-suspend;
397
+
regulator-suspend-microvolt = <750000>;
398
+
};
399
+
};
400
+
401
+
vdd_ddr_pll_s0: nldo-reg2 {
402
+
regulator-name = "vdd_ddr_pll_s0";
403
+
regulator-always-on;
404
+
regulator-boot-on;
405
+
regulator-min-microvolt = <850000>;
406
+
regulator-max-microvolt = <850000>;
407
+
408
+
regulator-state-mem {
409
+
regulator-off-in-suspend;
410
+
regulator-suspend-microvolt = <850000>;
411
+
};
412
+
};
413
+
414
+
avdd_0v75_s0: nldo-reg3 {
415
+
regulator-name = "avdd_0v75_s0";
416
+
regulator-always-on;
417
+
regulator-boot-on;
418
+
regulator-min-microvolt = <750000>;
419
+
regulator-max-microvolt = <750000>;
420
+
421
+
regulator-state-mem {
422
+
regulator-off-in-suspend;
423
+
};
424
+
};
425
+
426
+
vdd_0v85_s0: nldo-reg4 {
427
+
regulator-name = "vdd_0v85_s0";
428
+
regulator-always-on;
429
+
regulator-boot-on;
430
+
regulator-min-microvolt = <850000>;
431
+
regulator-max-microvolt = <850000>;
432
+
433
+
regulator-state-mem {
434
+
regulator-off-in-suspend;
435
+
};
436
+
};
437
+
438
+
vdd_0v75_s0: nldo-reg5 {
439
+
regulator-name = "vdd_0v75_s0";
440
+
regulator-always-on;
441
+
regulator-boot-on;
442
+
regulator-min-microvolt = <750000>;
443
+
regulator-max-microvolt = <750000>;
444
+
445
+
regulator-state-mem {
446
+
regulator-off-in-suspend;
447
+
};
448
+
};
449
+
};
450
+
};
451
+
};
452
+
453
+
&tsadc {
454
+
status = "okay";
455
+
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
···
23
23
compatible = "audio-graph-card";
24
24
dais = <&i2s0_8ch_p0>;
25
25
label = "rk3588-es8316";
26
-
hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
26
+
hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
27
27
pinctrl-names = "default";
28
28
pinctrl-0 = <&hp_detect>;
29
29
routing = "MIC2", "Mic Jack",
+408
arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts
+408
arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
3
+
/dts-v1/;
4
+
5
+
#include <dt-bindings/gpio/gpio.h>
6
+
#include <dt-bindings/leds/common.h>
7
+
#include "rk3588-armsom-lm7.dtsi"
8
+
9
+
/ {
10
+
model = "ArmSoM W3";
11
+
compatible = "armsom,w3", "armsom,lm7", "rockchip,rk3588";
12
+
13
+
aliases {
14
+
mmc1 = &sdmmc;
15
+
mmc2 = &sdio;
16
+
};
17
+
18
+
analog-sound {
19
+
compatible = "audio-graph-card";
20
+
label = "rk3588-es8316";
21
+
22
+
widgets = "Microphone", "Mic Jack",
23
+
"Headphone", "Headphones";
24
+
25
+
routing = "MIC2", "Mic Jack",
26
+
"Headphones", "HPOL",
27
+
"Headphones", "HPOR";
28
+
29
+
dais = <&i2s0_8ch_p0>;
30
+
hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
31
+
pinctrl-names = "default";
32
+
pinctrl-0 = <&hp_detect>;
33
+
};
34
+
35
+
leds {
36
+
compatible = "gpio-leds";
37
+
pinctrl-names = "default";
38
+
pinctrl-0 = <&led_rgb_b>;
39
+
40
+
led-rgb-b {
41
+
function = LED_FUNCTION_STATUS;
42
+
color = <LED_COLOR_ID_BLUE>;
43
+
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
44
+
linux,default-trigger = "heartbeat";
45
+
};
46
+
47
+
led-rgb-r {
48
+
function = LED_FUNCTION_STATUS;
49
+
color = <LED_COLOR_ID_RED>;
50
+
gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
51
+
linux,default-trigger = "none";
52
+
};
53
+
};
54
+
55
+
fan: pwm-fan {
56
+
compatible = "pwm-fan";
57
+
cooling-levels = <0 120 150 180 210 240 255>;
58
+
fan-supply = <&vcc5v0_sys>;
59
+
pwms = <&pwm1 0 50000 0>;
60
+
#cooling-cells = <2>;
61
+
};
62
+
63
+
rfkill {
64
+
compatible = "rfkill-gpio";
65
+
label = "rfkill-pcie-wlan";
66
+
radio-type = "wlan";
67
+
shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
68
+
};
69
+
70
+
rfkill-bt {
71
+
compatible = "rfkill-gpio";
72
+
label = "rfkill-m2-bt";
73
+
radio-type = "bluetooth";
74
+
shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
75
+
};
76
+
77
+
vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
78
+
compatible = "regulator-fixed";
79
+
enable-active-high;
80
+
gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
81
+
pinctrl-names = "default";
82
+
pinctrl-0 = <&pcie2_0_vcc3v3_en>;
83
+
regulator-name = "vcc3v3_pcie2x1l0";
84
+
regulator-always-on;
85
+
regulator-boot-on;
86
+
regulator-min-microvolt = <3300000>;
87
+
regulator-max-microvolt = <3300000>;
88
+
startup-delay-us = <50000>;
89
+
vin-supply = <&vcc5v0_sys>;
90
+
};
91
+
92
+
vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
93
+
compatible = "regulator-fixed";
94
+
regulator-name = "vcc3v3_pcie2x1l2";
95
+
regulator-min-microvolt = <3300000>;
96
+
regulator-max-microvolt = <3300000>;
97
+
startup-delay-us = <5000>;
98
+
vin-supply = <&vcc_3v3_s3>;
99
+
};
100
+
101
+
vcc3v3_pcie30: vcc3v3-pcie30-regulator {
102
+
compatible = "regulator-fixed";
103
+
enable-active-high;
104
+
gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
105
+
pinctrl-names = "default";
106
+
pinctrl-0 = <&pcie3_vcc3v3_en>;
107
+
regulator-name = "vcc3v3_pcie30";
108
+
regulator-min-microvolt = <3300000>;
109
+
regulator-max-microvolt = <3300000>;
110
+
startup-delay-us = <5000>;
111
+
vin-supply = <&vcc5v0_sys>;
112
+
};
113
+
114
+
vcc5v0_host: vcc5v0-host-regulator {
115
+
compatible = "regulator-fixed";
116
+
regulator-name = "vcc5v0_host";
117
+
regulator-boot-on;
118
+
regulator-always-on;
119
+
regulator-min-microvolt = <5000000>;
120
+
regulator-max-microvolt = <5000000>;
121
+
enable-active-high;
122
+
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
123
+
pinctrl-names = "default";
124
+
pinctrl-0 = <&vcc5v0_host_en>;
125
+
vin-supply = <&vcc5v0_sys>;
126
+
};
127
+
};
128
+
129
+
&combphy0_ps {
130
+
status = "okay";
131
+
};
132
+
133
+
&combphy1_ps {
134
+
status = "okay";
135
+
};
136
+
137
+
&combphy2_psu {
138
+
status = "okay";
139
+
};
140
+
141
+
&i2c6 {
142
+
status = "okay";
143
+
144
+
hym8563: rtc@51 {
145
+
compatible = "haoyu,hym8563";
146
+
reg = <0x51>;
147
+
#clock-cells = <0>;
148
+
clock-output-names = "hym8563";
149
+
pinctrl-names = "default";
150
+
pinctrl-0 = <&hym8563_int>;
151
+
interrupt-parent = <&gpio0>;
152
+
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
153
+
wakeup-source;
154
+
};
155
+
};
156
+
157
+
&i2c7 {
158
+
status = "okay";
159
+
160
+
es8316: audio-codec@11 {
161
+
compatible = "everest,es8316";
162
+
reg = <0x11>;
163
+
clocks = <&cru I2S0_8CH_MCLKOUT>;
164
+
clock-names = "mclk";
165
+
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
166
+
assigned-clock-rates = <12288000>;
167
+
#sound-dai-cells = <0>;
168
+
169
+
port {
170
+
es8316_p0_0: endpoint {
171
+
remote-endpoint = <&i2s0_8ch_p0_0>;
172
+
};
173
+
};
174
+
};
175
+
};
176
+
177
+
&i2s0_8ch {
178
+
pinctrl-names = "default";
179
+
pinctrl-0 = <&i2s0_lrck
180
+
&i2s0_mclk
181
+
&i2s0_sclk
182
+
&i2s0_sdi0
183
+
&i2s0_sdo0>;
184
+
status = "okay";
185
+
186
+
i2s0_8ch_p0: port {
187
+
i2s0_8ch_p0_0: endpoint {
188
+
dai-format = "i2s";
189
+
mclk-fs = <256>;
190
+
remote-endpoint = <&es8316_p0_0>;
191
+
};
192
+
};
193
+
};
194
+
195
+
&package_thermal {
196
+
polling-delay = <1000>;
197
+
198
+
trips {
199
+
package_fan0: package-fan0 {
200
+
temperature = <55000>;
201
+
hysteresis = <2000>;
202
+
type = "active";
203
+
};
204
+
205
+
package_fan1: package-fan1 {
206
+
temperature = <65000>;
207
+
hysteresis = <2000>;
208
+
type = "active";
209
+
};
210
+
};
211
+
212
+
cooling-maps {
213
+
map0 {
214
+
trip = <&package_fan0>;
215
+
cooling-device = <&fan THERMAL_NO_LIMIT 1>;
216
+
};
217
+
218
+
map1 {
219
+
trip = <&package_fan1>;
220
+
cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
221
+
};
222
+
};
223
+
};
224
+
225
+
&pcie2x1l0 {
226
+
pinctrl-names = "default";
227
+
pinctrl-0 = <&pcie2_0_rst>;
228
+
reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
229
+
vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
230
+
status = "okay";
231
+
};
232
+
233
+
&pcie2x1l2 {
234
+
pinctrl-names = "default";
235
+
pinctrl-0 = <&pcie2_2_rst>;
236
+
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
237
+
vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
238
+
status = "okay";
239
+
};
240
+
241
+
&pcie30phy {
242
+
status = "okay";
243
+
};
244
+
245
+
&pcie3x4 {
246
+
pinctrl-names = "default";
247
+
pinctrl-0 = <&pcie3_rst>;
248
+
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
249
+
vpcie3v3-supply = <&vcc3v3_pcie30>;
250
+
status = "okay";
251
+
};
252
+
253
+
&pinctrl {
254
+
hym8563 {
255
+
hym8563_int: hym8563-int {
256
+
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
257
+
};
258
+
};
259
+
260
+
leds {
261
+
led_rgb_b: led-rgb-b {
262
+
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
263
+
};
264
+
};
265
+
266
+
sound {
267
+
hp_detect: hp-detect {
268
+
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
269
+
};
270
+
};
271
+
272
+
pcie2 {
273
+
pcie2_0_rst: pcie2-0-rst {
274
+
rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
275
+
};
276
+
277
+
pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
278
+
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
279
+
};
280
+
281
+
pcie2_2_rst: pcie2-2-rst {
282
+
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
283
+
};
284
+
};
285
+
286
+
pcie3 {
287
+
pcie3_rst: pcie3-rst {
288
+
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
289
+
};
290
+
291
+
pcie3_vcc3v3_en: pcie3-vcc3v3-en {
292
+
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
293
+
};
294
+
};
295
+
296
+
usb {
297
+
vcc5v0_host_en: vcc5v0-host-en {
298
+
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
299
+
};
300
+
};
301
+
};
302
+
303
+
&pwm1 {
304
+
status = "okay";
305
+
};
306
+
307
+
&sdmmc {
308
+
bus-width = <4>;
309
+
cap-mmc-highspeed;
310
+
cap-sd-highspeed;
311
+
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
312
+
disable-wp;
313
+
max-frequency = <200000000>;
314
+
no-sdio;
315
+
no-mmc;
316
+
sd-uhs-sdr104;
317
+
vmmc-supply = <&vcc_3v3_s3>;
318
+
vqmmc-supply = <&vccio_sd_s0>;
319
+
status = "okay";
320
+
};
321
+
322
+
&sdio {
323
+
bus-width = <4>;
324
+
cap-sdio-irq;
325
+
disable-wp;
326
+
keep-power-in-suspend;
327
+
max-frequency = <200000000>;
328
+
no-sd;
329
+
no-mmc;
330
+
non-removable;
331
+
pinctrl-names = "default";
332
+
pinctrl-0 = <&sdiom0_pins>;
333
+
sd-uhs-sdr12;
334
+
sd-uhs-sdr25;
335
+
sd-uhs-sdr50;
336
+
sd-uhs-sdr104;
337
+
vmmc-supply = <&vcc3v3_pcie2x1l0>;
338
+
vqmmc-supply = <&vcc_1v8_s3>;
339
+
wakeup-source;
340
+
status = "okay";
341
+
};
342
+
343
+
&uart2 {
344
+
pinctrl-0 = <&uart2m0_xfer>;
345
+
status = "okay";
346
+
};
347
+
348
+
&uart6 {
349
+
pinctrl-names = "default";
350
+
pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>;
351
+
status = "okay";
352
+
};
353
+
354
+
&u2phy1 {
355
+
status = "okay";
356
+
};
357
+
358
+
&u2phy1_otg {
359
+
status = "okay";
360
+
};
361
+
362
+
&u2phy2 {
363
+
status = "okay";
364
+
};
365
+
366
+
&u2phy2_host {
367
+
/* connected to USB hub, which is powered by vcc5v0_sys */
368
+
phy-supply = <&vcc5v0_sys>;
369
+
status = "okay";
370
+
};
371
+
372
+
&u2phy3 {
373
+
status = "okay";
374
+
};
375
+
376
+
&u2phy3_host {
377
+
phy-supply = <&vcc5v0_host>;
378
+
status = "okay";
379
+
};
380
+
381
+
&usbdp_phy1 {
382
+
status = "okay";
383
+
};
384
+
385
+
&usb_host0_ehci {
386
+
status = "okay";
387
+
};
388
+
389
+
&usb_host0_ohci {
390
+
status = "okay";
391
+
};
392
+
393
+
&usb_host1_ehci {
394
+
status = "okay";
395
+
};
396
+
397
+
&usb_host1_ohci {
398
+
status = "okay";
399
+
};
400
+
401
+
&usb_host1_xhci {
402
+
dr_mode = "host";
403
+
status = "okay";
404
+
};
405
+
406
+
&usb_host2_xhci {
407
+
status = "okay";
408
+
};
+223
-48
arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
+223
-48
arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
···
1612
1612
1613
1613
pcie20x1 {
1614
1614
/omit-if-no-ref/
1615
-
pcie20x1m0_pins: pcie20x1m0-pins {
1615
+
pcie20x1m0_clkreqn: pcie20x1m0-clkreqn {
1616
1616
rockchip,pins =
1617
1617
/* pcie20x1_2_clkreqn_m0 */
1618
-
<3 RK_PC7 4 &pcfg_pull_none>,
1618
+
<3 RK_PC7 4 &pcfg_pull_none>;
1619
+
};
1620
+
1621
+
/omit-if-no-ref/
1622
+
pcie20x1m0_perstn: pcie20x1m0-perstn {
1623
+
rockchip,pins =
1619
1624
/* pcie20x1_2_perstn_m0 */
1620
-
<3 RK_PD1 4 &pcfg_pull_none>,
1625
+
<3 RK_PD1 4 &pcfg_pull_none>;
1626
+
};
1627
+
1628
+
/omit-if-no-ref/
1629
+
pcie20x1m0_waken: pcie20x1m0-waken {
1630
+
rockchip,pins =
1621
1631
/* pcie20x1_2_waken_m0 */
1622
1632
<3 RK_PD0 4 &pcfg_pull_none>;
1623
1633
};
1624
1634
1625
1635
/omit-if-no-ref/
1626
-
pcie20x1m1_pins: pcie20x1m1-pins {
1636
+
pcie20x1m1_clkreqn: pcie20x1m1-clkreqn {
1627
1637
rockchip,pins =
1628
1638
/* pcie20x1_2_clkreqn_m1 */
1629
-
<4 RK_PB7 4 &pcfg_pull_none>,
1639
+
<4 RK_PB7 4 &pcfg_pull_none>;
1640
+
};
1641
+
1642
+
/omit-if-no-ref/
1643
+
pcie20x1m1_perstn: pcie20x1m1-perstn {
1644
+
rockchip,pins =
1630
1645
/* pcie20x1_2_perstn_m1 */
1631
-
<4 RK_PC1 4 &pcfg_pull_none>,
1646
+
<4 RK_PC1 4 &pcfg_pull_none>;
1647
+
};
1648
+
1649
+
/omit-if-no-ref/
1650
+
pcie20x1m1_waken: pcie20x1m1-waken {
1651
+
rockchip,pins =
1632
1652
/* pcie20x1_2_waken_m1 */
1633
1653
<4 RK_PC0 4 &pcfg_pull_none>;
1634
1654
};
···
1674
1654
1675
1655
pcie30x1 {
1676
1656
/omit-if-no-ref/
1677
-
pcie30x1m0_pins: pcie30x1m0-pins {
1657
+
pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn {
1678
1658
rockchip,pins =
1679
1659
/* pcie30x1_0_clkreqn_m0 */
1680
-
<0 RK_PC0 12 &pcfg_pull_none>,
1660
+
<0 RK_PC0 12 &pcfg_pull_none>;
1661
+
};
1662
+
1663
+
/omit-if-no-ref/
1664
+
pcie30x1m0_0_perstn: pcie30x1m0-0-perstn {
1665
+
rockchip,pins =
1681
1666
/* pcie30x1_0_perstn_m0 */
1682
-
<0 RK_PC5 12 &pcfg_pull_none>,
1667
+
<0 RK_PC5 12 &pcfg_pull_none>;
1668
+
};
1669
+
1670
+
/omit-if-no-ref/
1671
+
pcie30x1m0_0_waken: pcie30x1m0-0-waken {
1672
+
rockchip,pins =
1683
1673
/* pcie30x1_0_waken_m0 */
1684
-
<0 RK_PC4 12 &pcfg_pull_none>,
1674
+
<0 RK_PC4 12 &pcfg_pull_none>;
1675
+
};
1676
+
1677
+
/omit-if-no-ref/
1678
+
pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn {
1679
+
rockchip,pins =
1685
1680
/* pcie30x1_1_clkreqn_m0 */
1686
-
<0 RK_PB5 12 &pcfg_pull_none>,
1681
+
<0 RK_PB5 12 &pcfg_pull_none>;
1682
+
};
1683
+
1684
+
/omit-if-no-ref/
1685
+
pcie30x1m0_1_perstn: pcie30x1m0-1-perstn {
1686
+
rockchip,pins =
1687
1687
/* pcie30x1_1_perstn_m0 */
1688
-
<0 RK_PB7 12 &pcfg_pull_none>,
1688
+
<0 RK_PB7 12 &pcfg_pull_none>;
1689
+
};
1690
+
1691
+
/omit-if-no-ref/
1692
+
pcie30x1m0_1_waken: pcie30x1m0-1-waken {
1693
+
rockchip,pins =
1689
1694
/* pcie30x1_1_waken_m0 */
1690
1695
<0 RK_PB6 12 &pcfg_pull_none>;
1691
1696
};
1692
1697
1693
1698
/omit-if-no-ref/
1694
-
pcie30x1m1_pins: pcie30x1m1-pins {
1699
+
pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn {
1695
1700
rockchip,pins =
1696
1701
/* pcie30x1_0_clkreqn_m1 */
1697
-
<4 RK_PA3 4 &pcfg_pull_none>,
1702
+
<4 RK_PA3 4 &pcfg_pull_none>;
1703
+
};
1704
+
1705
+
/omit-if-no-ref/
1706
+
pcie30x1m1_0_perstn: pcie30x1m1-0-perstn {
1707
+
rockchip,pins =
1698
1708
/* pcie30x1_0_perstn_m1 */
1699
-
<4 RK_PA5 4 &pcfg_pull_none>,
1709
+
<4 RK_PA5 4 &pcfg_pull_none>;
1710
+
};
1711
+
1712
+
/omit-if-no-ref/
1713
+
pcie30x1m1_0_waken: pcie30x1m1-0-waken {
1714
+
rockchip,pins =
1700
1715
/* pcie30x1_0_waken_m1 */
1701
-
<4 RK_PA4 4 &pcfg_pull_none>,
1716
+
<4 RK_PA4 4 &pcfg_pull_none>;
1717
+
};
1718
+
1719
+
/omit-if-no-ref/
1720
+
pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn {
1721
+
rockchip,pins =
1702
1722
/* pcie30x1_1_clkreqn_m1 */
1703
-
<4 RK_PA0 4 &pcfg_pull_none>,
1723
+
<4 RK_PA0 4 &pcfg_pull_none>;
1724
+
};
1725
+
1726
+
/omit-if-no-ref/
1727
+
pcie30x1m1_1_perstn: pcie30x1m1-1-perstn {
1728
+
rockchip,pins =
1704
1729
/* pcie30x1_1_perstn_m1 */
1705
-
<4 RK_PA2 4 &pcfg_pull_none>,
1730
+
<4 RK_PA2 4 &pcfg_pull_none>;
1731
+
};
1732
+
1733
+
/omit-if-no-ref/
1734
+
pcie30x1m1_1_waken: pcie30x1m1-1-waken {
1735
+
rockchip,pins =
1706
1736
/* pcie30x1_1_waken_m1 */
1707
1737
<4 RK_PA1 4 &pcfg_pull_none>;
1708
1738
};
1709
1739
1710
1740
/omit-if-no-ref/
1711
-
pcie30x1m2_pins: pcie30x1m2-pins {
1741
+
pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn {
1712
1742
rockchip,pins =
1713
1743
/* pcie30x1_0_clkreqn_m2 */
1714
-
<1 RK_PB5 4 &pcfg_pull_none>,
1744
+
<1 RK_PB5 4 &pcfg_pull_none>;
1745
+
};
1746
+
1747
+
/omit-if-no-ref/
1748
+
pcie30x1m2_0_perstn: pcie30x1m2-0-perstn {
1749
+
rockchip,pins =
1715
1750
/* pcie30x1_0_perstn_m2 */
1716
-
<1 RK_PB4 4 &pcfg_pull_none>,
1751
+
<1 RK_PB4 4 &pcfg_pull_none>;
1752
+
};
1753
+
1754
+
/omit-if-no-ref/
1755
+
pcie30x1m2_0_waken: pcie30x1m2-0-waken {
1756
+
rockchip,pins =
1717
1757
/* pcie30x1_0_waken_m2 */
1718
-
<1 RK_PB3 4 &pcfg_pull_none>,
1758
+
<1 RK_PB3 4 &pcfg_pull_none>;
1759
+
};
1760
+
1761
+
/omit-if-no-ref/
1762
+
pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn {
1763
+
rockchip,pins =
1719
1764
/* pcie30x1_1_clkreqn_m2 */
1720
-
<1 RK_PA0 4 &pcfg_pull_none>,
1765
+
<1 RK_PA0 4 &pcfg_pull_none>;
1766
+
};
1767
+
1768
+
/omit-if-no-ref/
1769
+
pcie30x1m2_1_perstn: pcie30x1m2-1-perstn {
1770
+
rockchip,pins =
1721
1771
/* pcie30x1_1_perstn_m2 */
1722
-
<1 RK_PA7 4 &pcfg_pull_none>,
1772
+
<1 RK_PA7 4 &pcfg_pull_none>;
1773
+
};
1774
+
1775
+
/omit-if-no-ref/
1776
+
pcie30x1m2_1_waken: pcie30x1m2-1-waken {
1777
+
rockchip,pins =
1723
1778
/* pcie30x1_1_waken_m2 */
1724
1779
<1 RK_PA1 4 &pcfg_pull_none>;
1725
1780
};
···
1816
1721
1817
1722
pcie30x2 {
1818
1723
/omit-if-no-ref/
1819
-
pcie30x2m0_pins: pcie30x2m0-pins {
1724
+
pcie30x2m0_clkreqn: pcie30x2m0-clkreqn {
1820
1725
rockchip,pins =
1821
1726
/* pcie30x2_clkreqn_m0 */
1822
-
<0 RK_PD1 12 &pcfg_pull_none>,
1727
+
<0 RK_PD1 12 &pcfg_pull_none>;
1728
+
};
1729
+
1730
+
/omit-if-no-ref/
1731
+
pcie30x2m0_perstn: pcie30x2m0-perstn {
1732
+
rockchip,pins =
1823
1733
/* pcie30x2_perstn_m0 */
1824
-
<0 RK_PD4 12 &pcfg_pull_none>,
1734
+
<0 RK_PD4 12 &pcfg_pull_none>;
1735
+
};
1736
+
1737
+
/omit-if-no-ref/
1738
+
pcie30x2m0_waken: pcie30x2m0-waken {
1739
+
rockchip,pins =
1825
1740
/* pcie30x2_waken_m0 */
1826
1741
<0 RK_PD2 12 &pcfg_pull_none>;
1827
1742
};
1828
1743
1829
1744
/omit-if-no-ref/
1830
-
pcie30x2m1_pins: pcie30x2m1-pins {
1745
+
pcie30x2m1_clkreqn: pcie30x2m1-clkreqn {
1831
1746
rockchip,pins =
1832
1747
/* pcie30x2_clkreqn_m1 */
1833
-
<4 RK_PA6 4 &pcfg_pull_none>,
1748
+
<4 RK_PA6 4 &pcfg_pull_none>;
1749
+
};
1750
+
1751
+
/omit-if-no-ref/
1752
+
pcie30x2m1_perstn: pcie30x2m1-perstn {
1753
+
rockchip,pins =
1834
1754
/* pcie30x2_perstn_m1 */
1835
-
<4 RK_PB0 4 &pcfg_pull_none>,
1755
+
<4 RK_PB0 4 &pcfg_pull_none>;
1756
+
};
1757
+
1758
+
/omit-if-no-ref/
1759
+
pcie30x2m1_waken: pcie30x2m1-waken {
1760
+
rockchip,pins =
1836
1761
/* pcie30x2_waken_m1 */
1837
1762
<4 RK_PA7 4 &pcfg_pull_none>;
1838
1763
};
1839
1764
1840
1765
/omit-if-no-ref/
1841
-
pcie30x2m2_pins: pcie30x2m2-pins {
1766
+
pcie30x2m2_clkreqn: pcie30x2m2-clkreqn {
1842
1767
rockchip,pins =
1843
1768
/* pcie30x2_clkreqn_m2 */
1844
-
<3 RK_PD2 4 &pcfg_pull_none>,
1769
+
<3 RK_PD2 4 &pcfg_pull_none>;
1770
+
};
1771
+
1772
+
/omit-if-no-ref/
1773
+
pcie30x2m2_perstn: pcie30x2m2-perstn {
1774
+
rockchip,pins =
1845
1775
/* pcie30x2_perstn_m2 */
1846
-
<3 RK_PD4 4 &pcfg_pull_none>,
1776
+
<3 RK_PD4 4 &pcfg_pull_none>;
1777
+
};
1778
+
1779
+
/omit-if-no-ref/
1780
+
pcie30x2m2_waken: pcie30x2m2-waken {
1781
+
rockchip,pins =
1847
1782
/* pcie30x2_waken_m2 */
1848
1783
<3 RK_PD3 4 &pcfg_pull_none>;
1849
1784
};
1850
1785
1851
1786
/omit-if-no-ref/
1852
-
pcie30x2m3_pins: pcie30x2m3-pins {
1787
+
pcie30x2m3_clkreqn: pcie30x2m3-clkreqn {
1853
1788
rockchip,pins =
1854
1789
/* pcie30x2_clkreqn_m3 */
1855
-
<1 RK_PD7 4 &pcfg_pull_none>,
1790
+
<1 RK_PD7 4 &pcfg_pull_none>;
1791
+
};
1792
+
1793
+
/omit-if-no-ref/
1794
+
pcie30x2m3_perstn: pcie30x2m3-perstn {
1795
+
rockchip,pins =
1856
1796
/* pcie30x2_perstn_m3 */
1857
-
<1 RK_PB7 4 &pcfg_pull_none>,
1797
+
<1 RK_PB7 4 &pcfg_pull_none>;
1798
+
};
1799
+
1800
+
/omit-if-no-ref/
1801
+
pcie30x2m3_waken: pcie30x2m3-waken {
1802
+
rockchip,pins =
1858
1803
/* pcie30x2_waken_m3 */
1859
1804
<1 RK_PB6 4 &pcfg_pull_none>;
1860
1805
};
···
1909
1774
1910
1775
pcie30x4 {
1911
1776
/omit-if-no-ref/
1912
-
pcie30x4m0_pins: pcie30x4m0-pins {
1777
+
pcie30x4m0_clkreqn: pcie30x4m0-clkreqn {
1913
1778
rockchip,pins =
1914
1779
/* pcie30x4_clkreqn_m0 */
1915
-
<0 RK_PC6 12 &pcfg_pull_none>,
1780
+
<0 RK_PC6 12 &pcfg_pull_none>;
1781
+
};
1782
+
1783
+
/omit-if-no-ref/
1784
+
pcie30x4m0_perstn: pcie30x4m0-perstn {
1785
+
rockchip,pins =
1916
1786
/* pcie30x4_perstn_m0 */
1917
-
<0 RK_PD0 12 &pcfg_pull_none>,
1787
+
<0 RK_PD0 12 &pcfg_pull_none>;
1788
+
};
1789
+
1790
+
/omit-if-no-ref/
1791
+
pcie30x4m0_waken: pcie30x4m0-waken {
1792
+
rockchip,pins =
1918
1793
/* pcie30x4_waken_m0 */
1919
1794
<0 RK_PC7 12 &pcfg_pull_none>;
1920
1795
};
1921
1796
1922
1797
/omit-if-no-ref/
1923
-
pcie30x4m1_pins: pcie30x4m1-pins {
1798
+
pcie30x4m1_clkreqn: pcie30x4m1-clkreqn {
1924
1799
rockchip,pins =
1925
1800
/* pcie30x4_clkreqn_m1 */
1926
-
<4 RK_PB4 4 &pcfg_pull_none>,
1801
+
<4 RK_PB4 4 &pcfg_pull_none>;
1802
+
};
1803
+
1804
+
/omit-if-no-ref/
1805
+
pcie30x4m1_perstn: pcie30x4m1-perstn {
1806
+
rockchip,pins =
1927
1807
/* pcie30x4_perstn_m1 */
1928
-
<4 RK_PB6 4 &pcfg_pull_none>,
1808
+
<4 RK_PB6 4 &pcfg_pull_none>;
1809
+
};
1810
+
1811
+
/omit-if-no-ref/
1812
+
pcie30x4m1_waken: pcie30x4m1-waken {
1813
+
rockchip,pins =
1929
1814
/* pcie30x4_waken_m1 */
1930
1815
<4 RK_PB5 4 &pcfg_pull_none>;
1931
1816
};
1932
1817
1933
1818
/omit-if-no-ref/
1934
-
pcie30x4m2_pins: pcie30x4m2-pins {
1819
+
pcie30x4m2_clkreqn: pcie30x4m2-clkreqn {
1935
1820
rockchip,pins =
1936
1821
/* pcie30x4_clkreqn_m2 */
1937
-
<3 RK_PC4 4 &pcfg_pull_none>,
1822
+
<3 RK_PC4 4 &pcfg_pull_none>;
1823
+
};
1824
+
1825
+
/omit-if-no-ref/
1826
+
pcie30x4m2_perstn: pcie30x4m2-perstn {
1827
+
rockchip,pins =
1938
1828
/* pcie30x4_perstn_m2 */
1939
-
<3 RK_PC6 4 &pcfg_pull_none>,
1829
+
<3 RK_PC6 4 &pcfg_pull_none>;
1830
+
};
1831
+
1832
+
/omit-if-no-ref/
1833
+
pcie30x4m2_waken: pcie30x4m2-waken {
1834
+
rockchip,pins =
1940
1835
/* pcie30x4_waken_m2 */
1941
1836
<3 RK_PC5 4 &pcfg_pull_none>;
1942
1837
};
1943
1838
1944
1839
/omit-if-no-ref/
1945
-
pcie30x4m3_pins: pcie30x4m3-pins {
1840
+
pcie30x4m3_clkreqn: pcie30x4m3-clkreqn {
1946
1841
rockchip,pins =
1947
1842
/* pcie30x4_clkreqn_m3 */
1948
-
<1 RK_PB0 4 &pcfg_pull_none>,
1843
+
<1 RK_PB0 4 &pcfg_pull_none>;
1844
+
};
1845
+
1846
+
/omit-if-no-ref/
1847
+
pcie30x4m3_perstn: pcie30x4m3-perstn {
1848
+
rockchip,pins =
1949
1849
/* pcie30x4_perstn_m3 */
1950
-
<1 RK_PB2 4 &pcfg_pull_none>,
1850
+
<1 RK_PB2 4 &pcfg_pull_none>;
1851
+
};
1852
+
1853
+
/omit-if-no-ref/
1854
+
pcie30x4m3_waken: pcie30x4m3-waken {
1855
+
rockchip,pins =
1951
1856
/* pcie30x4_waken_m3 */
1952
1857
<1 RK_PB1 4 &pcfg_pull_none>;
1953
1858
};
+41
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+41
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
···
1366
1366
status = "disabled";
1367
1367
};
1368
1368
1369
+
hdmi0: hdmi@fde80000 {
1370
+
compatible = "rockchip,rk3588-dw-hdmi-qp";
1371
+
reg = <0x0 0xfde80000 0x0 0x20000>;
1372
+
clocks = <&cru PCLK_HDMITX0>,
1373
+
<&cru CLK_HDMITX0_EARC>,
1374
+
<&cru CLK_HDMITX0_REF>,
1375
+
<&cru MCLK_I2S5_8CH_TX>,
1376
+
<&cru CLK_HDMIHDP0>,
1377
+
<&cru HCLK_VO1>;
1378
+
clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
1379
+
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
1380
+
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
1381
+
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
1382
+
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
1383
+
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
1384
+
interrupt-names = "avp", "cec", "earc", "main", "hpd";
1385
+
phys = <&hdptxphy_hdmi0>;
1386
+
pinctrl-names = "default";
1387
+
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
1388
+
&hdmim0_tx0_scl &hdmim0_tx0_sda>;
1389
+
power-domains = <&power RK3588_PD_VO1>;
1390
+
resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
1391
+
reset-names = "ref", "hdp";
1392
+
rockchip,grf = <&sys_grf>;
1393
+
rockchip,vo-grf = <&vo1_grf>;
1394
+
status = "disabled";
1395
+
1396
+
ports {
1397
+
#address-cells = <1>;
1398
+
#size-cells = <0>;
1399
+
1400
+
hdmi0_in: port@0 {
1401
+
reg = <0>;
1402
+
};
1403
+
1404
+
hdmi0_out: port@1 {
1405
+
reg = <1>;
1406
+
};
1407
+
};
1408
+
};
1409
+
1369
1410
qos_gpu_m0: qos@fdf35000 {
1370
1411
compatible = "rockchip,rk3588-qos", "syscon";
1371
1412
reg = <0x0 0xfdf35000 0x0 0x20>;
+48
-1
arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+48
-1
arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
···
9
9
#include <dt-bindings/gpio/gpio.h>
10
10
#include <dt-bindings/input/input.h>
11
11
#include <dt-bindings/pinctrl/rockchip.h>
12
+
#include <dt-bindings/soc/rockchip,vop2.h>
12
13
#include <dt-bindings/usb/pd.h>
13
14
#include "rk3588.dtsi"
14
15
···
67
66
simple-audio-card,bitclock-master = <&masterdai>;
68
67
simple-audio-card,format = "i2s";
69
68
simple-audio-card,frame-master = <&masterdai>;
70
-
simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
69
+
simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
71
70
simple-audio-card,mclk-fs = <256>;
72
71
simple-audio-card,pin-switches = "Headphones", "Speaker";
73
72
simple-audio-card,routing =
···
119
118
compatible = "pwm-backlight";
120
119
power-supply = <&vcc12v_dcin>;
121
120
pwms = <&pwm2 0 25000 0>;
121
+
};
122
+
123
+
hdmi0-con {
124
+
compatible = "hdmi-connector";
125
+
type = "a";
126
+
127
+
port {
128
+
hdmi0_con_in: endpoint {
129
+
remote-endpoint = <&hdmi0_out_con>;
130
+
};
131
+
};
122
132
};
123
133
124
134
pcie20_avdd0v85: pcie20-avdd0v85-regulator {
···
309
297
&gpu {
310
298
mali-supply = <&vdd_gpu_s0>;
311
299
sram-supply = <&vdd_gpu_mem_s0>;
300
+
status = "okay";
301
+
};
302
+
303
+
&hdmi0 {
304
+
status = "okay";
305
+
};
306
+
307
+
&hdmi0_in {
308
+
hdmi0_in_vp0: endpoint {
309
+
remote-endpoint = <&vp0_out_hdmi0>;
310
+
};
311
+
};
312
+
313
+
&hdmi0_out {
314
+
hdmi0_out_con: endpoint {
315
+
remote-endpoint = <&hdmi0_con_in>;
316
+
};
317
+
};
318
+
319
+
&hdptxphy_hdmi0 {
312
320
status = "okay";
313
321
};
314
322
···
1287
1255
&usb_host1_xhci {
1288
1256
dr_mode = "host";
1289
1257
status = "okay";
1258
+
};
1259
+
1260
+
&vop_mmu {
1261
+
status = "okay";
1262
+
};
1263
+
1264
+
&vop {
1265
+
status = "okay";
1266
+
};
1267
+
1268
+
&vp0 {
1269
+
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
1270
+
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
1271
+
remote-endpoint = <&hdmi0_in_vp0>;
1272
+
};
1290
1273
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts
···
38
38
pinctrl-0 = <&headphone_detect>;
39
39
40
40
simple-audio-card,format = "i2s";
41
-
simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
41
+
simple-audio-card,hp-det-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
42
42
simple-audio-card,mclk-fs = <256>;
43
43
simple-audio-card,name = "realtek,rt5616-codec";
44
44
+69
-6
arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
+69
-6
arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
···
8
8
#include <dt-bindings/input/input.h>
9
9
#include <dt-bindings/leds/common.h>
10
10
#include <dt-bindings/pinctrl/rockchip.h>
11
+
#include <dt-bindings/soc/rockchip,vop2.h>
11
12
#include <dt-bindings/usb/pd.h>
12
13
#include "rk3588.dtsi"
13
14
···
33
32
34
33
aliases {
35
34
ethernet0 = &gmac0;
35
+
i2c10 = &i2c10;
36
36
mmc0 = &sdhci;
37
37
mmc1 = &sdmmc;
38
38
rtc0 = &rtc_twi;
···
58
56
pinctrl-0 = <&emmc_reset>;
59
57
pinctrl-names = "default";
60
58
reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
59
+
};
60
+
61
+
hdmi-con {
62
+
compatible = "hdmi-connector";
63
+
type = "a";
64
+
65
+
port {
66
+
hdmi_con_in: endpoint {
67
+
remote-endpoint = <&hdmi0_out_con>;
68
+
};
69
+
};
61
70
};
62
71
63
72
leds {
···
284
271
status = "okay";
285
272
};
286
273
274
+
&hdmi0 {
275
+
/* No CEC on Jaguar */
276
+
pinctrl-names = "default";
277
+
pinctrl-0 = <&hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>;
278
+
status = "okay";
279
+
};
280
+
281
+
&hdmi0_in {
282
+
hdmi0_in_vp0: endpoint {
283
+
remote-endpoint = <&vp0_out_hdmi0>;
284
+
};
285
+
};
286
+
287
+
&hdmi0_out {
288
+
hdmi0_out_con: endpoint {
289
+
remote-endpoint = <&hdmi_con_in>;
290
+
};
291
+
};
292
+
293
+
&hdptxphy_hdmi0 {
294
+
status = "okay";
295
+
};
296
+
287
297
&i2c0 {
288
298
pinctrl-0 = <&i2c0m2_xfer>;
289
299
status = "okay";
290
300
291
301
fan@18 {
292
-
compatible = "ti,amc6821";
302
+
compatible = "tsd,mule", "ti,amc6821";
293
303
reg = <0x18>;
304
+
305
+
i2c-mux {
306
+
compatible = "tsd,mule-i2c-mux";
307
+
#address-cells = <1>;
308
+
#size-cells = <0>;
309
+
310
+
i2c10: i2c@0 {
311
+
reg = <0x0>;
312
+
#address-cells = <1>;
313
+
#size-cells = <0>;
314
+
315
+
rtc_twi: rtc@6f {
316
+
compatible = "isil,isl1208";
317
+
reg = <0x6f>;
318
+
};
319
+
};
320
+
};
294
321
};
295
322
296
323
vdd_npu_s0: regulator@42 {
···
365
312
regulator-state-mem {
366
313
regulator-off-in-suspend;
367
314
};
368
-
};
369
-
370
-
rtc_twi: rtc@6f {
371
-
compatible = "isil,isl1208";
372
-
reg = <0x6f>;
373
315
};
374
316
};
375
317
···
911
863
/* host1 on M.2 E-key */
912
864
&usb_host1_ohci {
913
865
status = "okay";
866
+
};
867
+
868
+
&vop {
869
+
status = "okay";
870
+
};
871
+
872
+
&vop_mmu {
873
+
status = "okay";
874
+
};
875
+
876
+
&vp0 {
877
+
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
878
+
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
879
+
remote-endpoint = <&hdmi0_in_vp0>;
880
+
};
914
881
};
+48
-1
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
+48
-1
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
···
10
10
#include <dt-bindings/gpio/gpio.h>
11
11
#include <dt-bindings/input/input.h>
12
12
#include <dt-bindings/pinctrl/rockchip.h>
13
+
#include <dt-bindings/soc/rockchip,vop2.h>
13
14
#include <dt-bindings/usb/pd.h>
14
15
#include "rk3588.dtsi"
15
16
···
39
38
40
39
chosen {
41
40
stdout-path = "serial2:1500000n8";
41
+
};
42
+
43
+
hdmi0-con {
44
+
compatible = "hdmi-connector";
45
+
type = "a";
46
+
47
+
port {
48
+
hdmi0_con_in: endpoint {
49
+
remote-endpoint = <&hdmi0_out_con>;
50
+
};
51
+
};
42
52
};
43
53
44
54
ir-receiver {
···
87
75
simple-audio-card,format = "i2s";
88
76
simple-audio-card,mclk-fs = <256>;
89
77
90
-
simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
78
+
simple-audio-card,hp-det-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
91
79
92
80
simple-audio-card,widgets =
93
81
"Headphone", "Headphones",
···
327
315
328
316
&gpu {
329
317
mali-supply = <&vdd_gpu_s0>;
318
+
status = "okay";
319
+
};
320
+
321
+
&hdmi0 {
322
+
status = "okay";
323
+
};
324
+
325
+
&hdmi0_in {
326
+
hdmi0_in_vp0: endpoint {
327
+
remote-endpoint = <&vp0_out_hdmi0>;
328
+
};
329
+
};
330
+
331
+
&hdmi0_out {
332
+
hdmi0_out_con: endpoint {
333
+
remote-endpoint = <&hdmi0_con_in>;
334
+
};
335
+
};
336
+
337
+
&hdptxphy_hdmi0 {
330
338
status = "okay";
331
339
};
332
340
···
1070
1038
1071
1039
&usb_host1_ohci {
1072
1040
status = "okay";
1041
+
};
1042
+
1043
+
&vop_mmu {
1044
+
status = "okay";
1045
+
};
1046
+
1047
+
&vop {
1048
+
status = "okay";
1049
+
};
1050
+
1051
+
&vp0 {
1052
+
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
1053
+
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
1054
+
remote-endpoint = <&hdmi0_in_vp0>;
1055
+
};
1073
1056
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
···
75
75
simple-audio-card,bitclock-master = <&masterdai>;
76
76
simple-audio-card,format = "i2s";
77
77
simple-audio-card,frame-master = <&masterdai>;
78
-
simple-audio-card,hp-det-gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
78
+
simple-audio-card,hp-det-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
79
79
simple-audio-card,mclk-fs = <256>;
80
80
simple-audio-card,pin-switches = "Headphones", "Speaker";
81
81
simple-audio-card,widgets =
+78
-1
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
+78
-1
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
···
9
9
#include <dt-bindings/leds/common.h>
10
10
#include <dt-bindings/input/input.h>
11
11
#include <dt-bindings/pinctrl/rockchip.h>
12
+
#include <dt-bindings/soc/rockchip,vop2.h>
12
13
#include <dt-bindings/usb/pd.h>
13
14
#include "rk3588.dtsi"
14
15
···
86
85
};
87
86
};
88
87
88
+
hdmi0-con {
89
+
compatible = "hdmi-connector";
90
+
type = "a";
91
+
92
+
port {
93
+
hdmi0_con_in: endpoint {
94
+
remote-endpoint = <&hdmi0_out_con>;
95
+
};
96
+
};
97
+
};
98
+
89
99
fan: pwm-fan {
90
100
compatible = "pwm-fan";
91
101
cooling-levels = <0 70 75 80 100>;
···
132
120
simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>;
133
121
simple-audio-card,format = "i2s";
134
122
simple-audio-card,mclk-fs = <256>;
135
-
simple-audio-card,hp-det-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>;
123
+
simple-audio-card,hp-det-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>;
136
124
simple-audio-card,bitclock-master = <&daicpu>;
137
125
simple-audio-card,frame-master = <&daicpu>;
138
126
/*TODO: SARADC_IN3 is used as MIC detection / key input */
···
275
263
cpu-supply = <&vdd_cpu_lit_s0>;
276
264
};
277
265
266
+
&hdmi0 {
267
+
status = "okay";
268
+
};
269
+
270
+
&hdmi0_in {
271
+
hdmi0_in_vp0: endpoint {
272
+
remote-endpoint = <&vp0_out_hdmi0>;
273
+
};
274
+
};
275
+
276
+
&hdmi0_out {
277
+
hdmi0_out_con: endpoint {
278
+
remote-endpoint = <&hdmi0_con_in>;
279
+
};
280
+
};
281
+
282
+
&hdptxphy_hdmi0 {
283
+
status = "okay";
284
+
};
285
+
278
286
&i2c0 {
279
287
pinctrl-names = "default";
280
288
pinctrl-0 = <&i2c0m2_xfer>;
···
388
356
&i2s2m0_sdi
389
357
&i2s2m0_sdo>;
390
358
status = "okay";
359
+
};
360
+
361
+
&package_thermal {
362
+
polling-delay = <1000>;
363
+
364
+
cooling-maps {
365
+
map0 {
366
+
trip = <&package_fan0>;
367
+
cooling-device = <&fan THERMAL_NO_LIMIT 1>;
368
+
};
369
+
370
+
map1 {
371
+
trip = <&package_fan1>;
372
+
cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
373
+
};
374
+
};
375
+
376
+
trips {
377
+
package_fan0: package-fan0 {
378
+
temperature = <55000>;
379
+
hysteresis = <2000>;
380
+
type = "active";
381
+
};
382
+
383
+
package_fan1: package-fan1 {
384
+
temperature = <65000>;
385
+
hysteresis = <2000>;
386
+
type = "active";
387
+
};
388
+
};
391
389
};
392
390
393
391
/* phy1 - M.KEY socket */
···
914
852
915
853
&usb_host1_ohci {
916
854
status = "okay";
855
+
};
856
+
857
+
&vop_mmu {
858
+
status = "okay";
859
+
};
860
+
861
+
&vop {
862
+
status = "okay";
863
+
};
864
+
865
+
&vp0 {
866
+
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
867
+
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
868
+
remote-endpoint = <&hdmi0_in_vp0>;
869
+
};
917
870
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
···
104
104
simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>;
105
105
simple-audio-card,format = "i2s";
106
106
simple-audio-card,mclk-fs = <256>;
107
-
simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
107
+
simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
108
108
simple-audio-card,bitclock-master = <&daicpu>;
109
109
simple-audio-card,frame-master = <&daicpu>;
110
110
/* SARADC_IN3 is used as MIC detection / key input */
+37
-3
arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+37
-3
arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
···
46
46
compatible = "audio-graph-card";
47
47
label = "rk3588-es8316";
48
48
dais = <&i2s0_8ch_p0>;
49
-
hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
49
+
hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
50
50
pinctrl-names = "default";
51
51
pinctrl-0 = <&hp_detect>;
52
52
routing = "MIC2", "Mic Jack",
···
70
70
gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
71
71
linux,default-trigger = "disk-activity";
72
72
};
73
+
};
74
+
75
+
/* Unnamed gated oscillator: 100MHz,3.3V,3225 */
76
+
pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
77
+
compatible = "gated-fixed-clock";
78
+
#clock-cells = <0>;
79
+
clock-frequency = <100000000>;
80
+
clock-output-names = "pcie30_refclk";
81
+
vdd-supply = <&vcc3v3_pi6c_05>;
73
82
};
74
83
75
84
fan0: pwm-fan {
···
155
146
vin-supply = <&vcc_3v3_s3>;
156
147
};
157
148
158
-
vcc3v3_mkey: regulator-vcc3v3-mkey {
149
+
/* The PCIE30x4_PWREN_H controls two regulators */
150
+
vcc3v3_mkey: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
159
151
compatible = "regulator-fixed";
160
152
enable-active-high;
161
153
gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
162
154
pinctrl-names = "default";
163
155
pinctrl-0 = <&pcie30x4_pwren_h>;
164
-
regulator-name = "vcc3v3_mkey";
156
+
regulator-name = "vcc3v3_pi6c_05";
165
157
regulator-min-microvolt = <3300000>;
166
158
regulator-max-microvolt = <3300000>;
167
159
startup-delay-us = <5000>;
···
523
513
524
514
/* ASMedia ASM1164 Sata controller */
525
515
&pcie3x2 {
516
+
/*
517
+
* The board has a "pcie_refclk" oscillator that needs enabling,
518
+
* so add it to the list of clocks.
519
+
*/
520
+
clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
521
+
<&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
522
+
<&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>,
523
+
<&pcie30_port1_refclk>;
524
+
clock-names = "aclk_mst", "aclk_slv",
525
+
"aclk_dbi", "pclk",
526
+
"aux", "pipe",
527
+
"ref";
526
528
pinctrl-names = "default";
527
529
pinctrl-0 = <&pcie30x2_perstn_m1_l>;
528
530
reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
···
544
522
545
523
/* M.2 M.key */
546
524
&pcie3x4 {
525
+
/*
526
+
* The board has a "pcie_refclk" oscillator that needs enabling,
527
+
* so add it to the list of clocks.
528
+
*/
529
+
clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
530
+
<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
531
+
<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
532
+
<&pcie30_port0_refclk>;
533
+
clock-names = "aclk_mst", "aclk_slv",
534
+
"aclk_dbi", "pclk",
535
+
"aux", "pipe",
536
+
"ref";
547
537
num-lanes = <2>;
548
538
pinctrl-names = "default";
549
539
pinctrl-0 = <&pcie30x4_perstn_m1_l>;
+48
-1
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+48
-1
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
···
4
4
5
5
#include <dt-bindings/gpio/gpio.h>
6
6
#include <dt-bindings/leds/common.h>
7
+
#include <dt-bindings/soc/rockchip,vop2.h>
7
8
#include "rk3588.dtsi"
8
9
9
10
/ {
···
33
32
"Headphones", "HPOR";
34
33
35
34
dais = <&i2s0_8ch_p0>;
36
-
hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
35
+
hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
37
36
pinctrl-names = "default";
38
37
pinctrl-0 = <&hp_detect>;
38
+
};
39
+
40
+
hdmi0-con {
41
+
compatible = "hdmi-connector";
42
+
type = "a";
43
+
44
+
port {
45
+
hdmi0_con_in: endpoint {
46
+
remote-endpoint = <&hdmi0_out_con>;
47
+
};
48
+
};
39
49
};
40
50
41
51
leds {
···
201
189
202
190
&gpu {
203
191
mali-supply = <&vdd_gpu_s0>;
192
+
status = "okay";
193
+
};
194
+
195
+
&hdmi0 {
196
+
status = "okay";
197
+
};
198
+
199
+
&hdmi0_in {
200
+
hdmi0_in_vp0: endpoint {
201
+
remote-endpoint = <&vp0_out_hdmi0>;
202
+
};
203
+
};
204
+
205
+
&hdmi0_out {
206
+
hdmi0_out_con: endpoint {
207
+
remote-endpoint = <&hdmi0_con_in>;
208
+
};
209
+
};
210
+
211
+
&hdptxphy_hdmi0 {
204
212
status = "okay";
205
213
};
206
214
···
889
857
890
858
&usb_host2_xhci {
891
859
status = "okay";
860
+
};
861
+
862
+
&vop_mmu {
863
+
status = "okay";
864
+
};
865
+
866
+
&vop {
867
+
status = "okay";
868
+
};
869
+
870
+
&vp0 {
871
+
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
872
+
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
873
+
remote-endpoint = <&hdmi0_in_vp0>;
874
+
};
892
875
};
+53
arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts
+53
arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts
···
5
5
6
6
/dts-v1/;
7
7
#include <dt-bindings/input/input.h>
8
+
#include <dt-bindings/soc/rockchip,vop2.h>
8
9
#include "rk3588-tiger.dtsi"
9
10
10
11
/ {
···
59
58
linux,code = <SW_LID>;
60
59
linux,input-type = <EV_SW>;
61
60
gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
61
+
};
62
+
};
63
+
64
+
hdmi-con {
65
+
compatible = "hdmi-connector";
66
+
type = "a";
67
+
68
+
port {
69
+
hdmi_con_in: endpoint {
70
+
remote-endpoint = <&hdmi0_out_con>;
71
+
};
62
72
};
63
73
};
64
74
···
164
152
};
165
153
166
154
&gmac0 {
155
+
status = "okay";
156
+
};
157
+
158
+
&hdmi0 {
159
+
/*
160
+
* While HDMI-CEC is present on the Q7 connector, it is not
161
+
* connected on Haikou itself.
162
+
*/
163
+
pinctrl-names = "default";
164
+
pinctrl-0 = <&hdmim0_tx0_hpd &hdmim1_tx0_scl &hdmim1_tx0_sda>;
165
+
status = "okay";
166
+
};
167
+
168
+
&hdmi0_in {
169
+
hdmi0_in_vp0: endpoint {
170
+
remote-endpoint = <&vp0_out_hdmi0>;
171
+
};
172
+
};
173
+
174
+
&hdmi0_out {
175
+
hdmi0_out_con: endpoint {
176
+
remote-endpoint = <&hdmi_con_in>;
177
+
};
178
+
};
179
+
180
+
&hdptxphy_hdmi0 {
167
181
status = "okay";
168
182
};
169
183
···
358
320
/* host2 on Q7_USB_P2, upper usb3 port */
359
321
&usb_host2_xhci {
360
322
status = "okay";
323
+
};
324
+
325
+
&vop {
326
+
status = "okay";
327
+
};
328
+
329
+
&vop_mmu {
330
+
status = "okay";
331
+
};
332
+
333
+
&vp0 {
334
+
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
335
+
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
336
+
remote-endpoint = <&hdmi0_in_vp0>;
337
+
};
361
338
};
+24
-5
arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
+24
-5
arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
···
12
12
compatible = "tsd,rk3588-tiger", "rockchip,rk3588";
13
13
14
14
aliases {
15
+
i2c10 = &i2c10;
15
16
mmc0 = &sdhci;
16
17
rtc0 = &rtc_twi;
17
18
};
···
153
152
status = "okay";
154
153
};
155
154
155
+
&hdmi0 {
156
+
pinctrl-names = "default";
157
+
pinctrl-0 = <&hdmim1_tx0_cec &hdmim0_tx0_hpd &hdmim1_tx0_scl
158
+
&hdmim1_tx0_sda>;
159
+
};
160
+
156
161
&i2c1 {
157
162
pinctrl-0 = <&i2c1m0_xfer>;
158
163
};
···
231
224
status = "okay";
232
225
233
226
fan@18 {
234
-
compatible = "ti,amc6821";
227
+
compatible = "tsd,mule", "ti,amc6821";
235
228
reg = <0x18>;
236
-
};
237
229
238
-
rtc_twi: rtc@6f {
239
-
compatible = "isil,isl1208";
240
-
reg = <0x6f>;
230
+
i2c-mux {
231
+
compatible = "tsd,mule-i2c-mux";
232
+
#address-cells = <1>;
233
+
#size-cells = <0>;
234
+
235
+
i2c10: i2c@0 {
236
+
reg = <0x0>;
237
+
#address-cells = <1>;
238
+
#size-cells = <0>;
239
+
240
+
rtc_twi: rtc@6f {
241
+
compatible = "isil,isl1208";
242
+
reg = <0x6f>;
243
+
};
244
+
};
245
+
};
241
246
};
242
247
};
243
248
+136
-2
arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
+136
-2
arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
···
116
116
status = "okay";
117
117
};
118
118
119
+
&gpu {
120
+
mali-supply = <&vdd_gpu_s0>;
121
+
status = "okay";
122
+
};
123
+
119
124
&i2c0 {
120
125
pinctrl-names = "default";
121
126
pinctrl-0 = <&i2c0m2_xfer>;
···
213
208
};
214
209
};
215
210
211
+
&package_thermal {
212
+
trips {
213
+
package_active1: trip-active1 {
214
+
temperature = <45000>;
215
+
hysteresis = <5000>;
216
+
type = "active";
217
+
};
218
+
package_active2: trip-active2 {
219
+
temperature = <50000>;
220
+
hysteresis = <5000>;
221
+
type = "active";
222
+
};
223
+
package_active3: trip-active3 {
224
+
temperature = <60000>;
225
+
hysteresis = <5000>;
226
+
type = "active";
227
+
};
228
+
package_active4: trip-active4 {
229
+
temperature = <70000>;
230
+
hysteresis = <5000>;
231
+
type = "active";
232
+
};
233
+
package_active5: trip-active5 {
234
+
temperature = <80000>;
235
+
hysteresis = <5000>;
236
+
type = "active";
237
+
};
238
+
};
239
+
240
+
cooling-maps {
241
+
map1 {
242
+
trip = <&package_active1>;
243
+
cooling-device = <&fan 1 1>;
244
+
};
245
+
map2 {
246
+
trip = <&package_active2>;
247
+
cooling-device = <&fan 2 2>;
248
+
};
249
+
map3 {
250
+
trip = <&package_active3>;
251
+
cooling-device = <&fan 3 3>;
252
+
};
253
+
map4 {
254
+
trip = <&package_active4>;
255
+
cooling-device = <&fan 4 4>;
256
+
};
257
+
map5 {
258
+
trip = <&package_active5>;
259
+
cooling-device = <&fan 5 5>;
260
+
};
261
+
};
262
+
};
263
+
216
264
&pcie2x1l1 {
217
265
linux,pci-domain = <1>;
218
266
pinctrl-names = "default";
219
-
pinctrl-0 = <&pcie2_reset>;
267
+
pinctrl-0 = <&pcie2_reset>, <&pcie30x1m1_0_clkreqn>, <&pcie30x1m1_0_waken>;
220
268
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
221
269
status = "okay";
222
270
};
···
281
223
&pcie3x4 {
282
224
linux,pci-domain = <0>;
283
225
pinctrl-names = "default";
284
-
pinctrl-0 = <&pcie3_reset>;
226
+
pinctrl-0 = <&pcie3_reset>, <&pcie30x4m1_clkreqn>, <&pcie30x4m1_waken>;
285
227
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
286
228
vpcie3v3-supply = <&vcc3v3_pcie30>;
287
229
status = "okay";
···
391
333
392
334
regulators {
393
335
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
336
+
/*
337
+
* RK3588's GPU power domain cannot be enabled
338
+
* without this regulator active, but it
339
+
* doesn't have to be on when the GPU PD is
340
+
* disabled. Because the PD binding does not
341
+
* currently allow us to express this
342
+
* relationship, we have no choice but to do
343
+
* this instead:
344
+
*/
345
+
regulator-always-on;
346
+
394
347
regulator-boot-on;
395
348
regulator-min-microvolt = <550000>;
396
349
regulator-max-microvolt = <950000>;
···
680
611
681
612
&uart9 {
682
613
pinctrl-0 = <&uart9m0_xfer>;
614
+
status = "okay";
615
+
};
616
+
617
+
/* USB 0: USB 2.0 only, OTG-capable */
618
+
&u2phy0 {
619
+
status = "okay";
620
+
};
621
+
622
+
&u2phy0_otg {
623
+
status = "okay";
624
+
};
625
+
626
+
&usbdp_phy0 {
627
+
/*
628
+
* TODO: On the RK1, USBDP0 drives the DisplayPort pins and is not
629
+
* involved in this USB2-only bus. The bus controller (below) needs to
630
+
* know that it doesn't have a USB3 port so it can ignore any
631
+
* USB3-related signals. This is handled in hardware by updating the
632
+
* GRFs corresponding to that bus controller. Alas, Linux currently
633
+
* puts the code to do that in the USBDP driver, so USBDP0 must be
634
+
* enabled for now.
635
+
*/
636
+
rockchip,dp-lane-mux = <0 1 2 3>; /* "No USB lanes" */
637
+
status = "okay";
638
+
};
639
+
640
+
&usb_host0_xhci {
641
+
extcon = <&u2phy0>;
642
+
maximum-speed = "high-speed";
643
+
status = "okay";
644
+
};
645
+
646
+
/* USB 1: USB 3.0, host only */
647
+
&u2phy1 {
648
+
status = "okay";
649
+
};
650
+
651
+
&u2phy1_otg {
652
+
status = "okay";
653
+
};
654
+
655
+
&usbdp_phy1 {
656
+
status = "okay";
657
+
};
658
+
659
+
&usb_host1_xhci {
660
+
dr_mode = "host";
661
+
extcon = <&u2phy1>;
662
+
status = "okay";
663
+
};
664
+
665
+
/* USB 2: USB 2.0, host only */
666
+
&u2phy2 {
667
+
status = "okay";
668
+
};
669
+
670
+
&u2phy2_host {
671
+
status = "okay";
672
+
};
673
+
674
+
&usb_host0_ehci {
675
+
status = "okay";
676
+
};
677
+
678
+
&usb_host0_ohci {
683
679
status = "okay";
684
680
};
+1170
arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts
+1170
arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
/*
3
+
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4
+
*
5
+
*/
6
+
7
+
/dts-v1/;
8
+
9
+
#include <dt-bindings/gpio/gpio.h>
10
+
#include <dt-bindings/input/input.h>
11
+
#include <dt-bindings/pinctrl/rockchip.h>
12
+
#include <dt-bindings/usb/pd.h>
13
+
#include "rk3588s.dtsi"
14
+
15
+
/ {
16
+
model = "Rockchip RK3588S EVB1 V10 Board";
17
+
compatible = "rockchip,rk3588s-evb1-v10", "rockchip,rk3588s";
18
+
19
+
aliases {
20
+
mmc0 = &sdhci;
21
+
mmc1 = &sdmmc;
22
+
};
23
+
24
+
chosen {
25
+
stdout-path = "serial2:1500000n8";
26
+
};
27
+
28
+
adc-keys {
29
+
compatible = "adc-keys";
30
+
io-channels = <&saradc 1>;
31
+
io-channel-names = "buttons";
32
+
keyup-threshold-microvolt = <1800000>;
33
+
poll-interval = <100>;
34
+
35
+
button-escape {
36
+
label = "Escape";
37
+
linux,code = <KEY_ESC>;
38
+
press-threshold-microvolt = <1235000>;
39
+
};
40
+
41
+
button-menu {
42
+
label = "Menu";
43
+
linux,code = <KEY_MENU>;
44
+
press-threshold-microvolt = <890000>;
45
+
};
46
+
47
+
button-vol-up {
48
+
label = "Volume Up";
49
+
linux,code = <KEY_VOLUMEUP>;
50
+
press-threshold-microvolt = <17000>;
51
+
};
52
+
53
+
button-vol-down {
54
+
label = "Volume Down";
55
+
linux,code = <KEY_VOLUMEDOWN>;
56
+
press-threshold-microvolt = <417000>;
57
+
};
58
+
};
59
+
60
+
amp_headphone: amplifier-headphone {
61
+
compatible = "simple-audio-amplifier";
62
+
enable-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
63
+
pinctrl-names = "default";
64
+
pinctrl-0 = <&headphone_amplifier_en>;
65
+
sound-name-prefix = "Headphones Amplifier";
66
+
};
67
+
68
+
amp_speaker: amplifier-speaker {
69
+
compatible = "simple-audio-amplifier";
70
+
enable-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
71
+
pinctrl-names = "default";
72
+
pinctrl-0 = <&speaker_amplifier_en>;
73
+
sound-name-prefix = "Speaker Amplifier";
74
+
};
75
+
76
+
analog-sound {
77
+
compatible = "simple-audio-card";
78
+
pinctrl-names = "default";
79
+
pinctrl-0 = <&hp_detect>;
80
+
simple-audio-card,name = "RK3588 EVB1 Audio";
81
+
simple-audio-card,aux-devs = <&_headphone>, <&_speaker>;
82
+
simple-audio-card,bitclock-master = <&masterdai>;
83
+
simple-audio-card,format = "i2s";
84
+
simple-audio-card,frame-master = <&masterdai>;
85
+
simple-audio-card,hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
86
+
simple-audio-card,mclk-fs = <256>;
87
+
simple-audio-card,pin-switches = "Headphones", "Speaker";
88
+
simple-audio-card,routing =
89
+
"Speaker Amplifier INL", "LOUT2",
90
+
"Speaker Amplifier INR", "ROUT2",
91
+
"Speaker", "Speaker Amplifier OUTL",
92
+
"Speaker", "Speaker Amplifier OUTR",
93
+
"Headphones Amplifier INL", "LOUT1",
94
+
"Headphones Amplifier INR", "ROUT1",
95
+
"Headphones", "Headphones Amplifier OUTL",
96
+
"Headphones", "Headphones Amplifier OUTR",
97
+
"LINPUT1", "Onboard Microphone",
98
+
"RINPUT1", "Onboard Microphone",
99
+
"LINPUT2", "Microphone Jack",
100
+
"RINPUT2", "Microphone Jack";
101
+
simple-audio-card,widgets =
102
+
"Microphone", "Microphone Jack",
103
+
"Microphone", "Onboard Microphone",
104
+
"Headphone", "Headphones",
105
+
"Speaker", "Speaker";
106
+
107
+
simple-audio-card,cpu {
108
+
sound-dai = <&i2s0_8ch>;
109
+
};
110
+
111
+
masterdai: simple-audio-card,codec {
112
+
sound-dai = <&es8388>;
113
+
system-clock-frequency = <12288000>;
114
+
};
115
+
};
116
+
117
+
backlight: backlight {
118
+
compatible = "pwm-backlight";
119
+
power-supply = <&vcc3v3_lcd_edp>;
120
+
pwms = <&pwm12 0 25000 0>;
121
+
};
122
+
123
+
combophy_avdd0v85: regulator-combophy-avdd0v85 {
124
+
compatible = "regulator-fixed";
125
+
regulator-name = "combophy_avdd0v85";
126
+
regulator-always-on;
127
+
regulator-boot-on;
128
+
regulator-min-microvolt = <850000>;
129
+
regulator-max-microvolt = <850000>;
130
+
vin-supply = <&vdd_0v85_s0>;
131
+
};
132
+
133
+
combophy_avdd1v8: regulator-combophy-avdd1v8 {
134
+
compatible = "regulator-fixed";
135
+
regulator-name = "combophy_avdd1v8";
136
+
regulator-always-on;
137
+
regulator-boot-on;
138
+
regulator-min-microvolt = <1800000>;
139
+
regulator-max-microvolt = <1800000>;
140
+
vin-supply = <&avcc_1v8_s0>;
141
+
};
142
+
143
+
vbus5v0_typec: regulator-vbus5v0-typec {
144
+
compatible = "regulator-fixed";
145
+
enable-active-high;
146
+
gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
147
+
pinctrl-names = "default";
148
+
pinctrl-0 = <&typec5v_pwren>;
149
+
regulator-name = "vbus5v0_typec";
150
+
regulator-min-microvolt = <5000000>;
151
+
regulator-max-microvolt = <5000000>;
152
+
vin-supply = <&vcc5v0_usb>;
153
+
};
154
+
155
+
vcc12v_dcin: regulator-vcc12v-dcin {
156
+
compatible = "regulator-fixed";
157
+
regulator-name = "vcc12v_dcin";
158
+
regulator-always-on;
159
+
regulator-boot-on;
160
+
regulator-min-microvolt = <12000000>;
161
+
regulator-max-microvolt = <12000000>;
162
+
};
163
+
164
+
vcc3v3_lcd_edp: regulator-vcc3v3-lcd-edp {
165
+
compatible = "regulator-fixed";
166
+
enable-active-high;
167
+
gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;
168
+
pinctrl-names = "default";
169
+
pinctrl-0 = <&vcc3v3_lcd_edp_en>;
170
+
regulator-name = "vcc3v3_lcd_edp";
171
+
regulator-boot-on;
172
+
vin-supply = <&vcc_3v3_s3>;
173
+
};
174
+
175
+
vcc3v3_pcie20: regulator-vcc3v3-pcie20 {
176
+
compatible = "regulator-fixed";
177
+
enable-active-high;
178
+
gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
179
+
pinctrl-names = "default";
180
+
pinctrl-0 = <&vcc3v3_pcie20_en>;
181
+
regulator-name = "vcc3v3_pcie20";
182
+
regulator-min-microvolt = <3300000>;
183
+
regulator-max-microvolt = <3300000>;
184
+
startup-delay-us = <5000>;
185
+
vin-supply = <&vcc12v_dcin>;
186
+
};
187
+
188
+
vcc5v0_host: regulator-vcc5v0-host {
189
+
compatible = "regulator-fixed";
190
+
enable-active-high;
191
+
gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
192
+
pinctrl-names = "default";
193
+
pinctrl-0 = <&vcc5v0_host_en>;
194
+
regulator-name = "vcc5v0_host";
195
+
regulator-always-on;
196
+
regulator-boot-on;
197
+
regulator-min-microvolt = <5000000>;
198
+
regulator-max-microvolt = <5000000>;
199
+
vin-supply = <&vcc5v0_usb>;
200
+
};
201
+
202
+
vcc5v0_sys: regulator-vcc5v0-sys {
203
+
compatible = "regulator-fixed";
204
+
regulator-name = "vcc5v0_sys";
205
+
regulator-always-on;
206
+
regulator-boot-on;
207
+
regulator-min-microvolt = <5000000>;
208
+
regulator-max-microvolt = <5000000>;
209
+
vin-supply = <&vcc12v_dcin>;
210
+
};
211
+
212
+
vcc5v0_usb: regulator-vcc5v0-usb {
213
+
compatible = "regulator-fixed";
214
+
regulator-name = "vcc5v0_usb";
215
+
regulator-always-on;
216
+
regulator-boot-on;
217
+
regulator-min-microvolt = <5000000>;
218
+
regulator-max-microvolt = <5000000>;
219
+
vin-supply = <&vcc5v0_usbdcin>;
220
+
};
221
+
222
+
vcc5v0_usbdcin: regulator-vcc5v0-usbdcin {
223
+
compatible = "regulator-fixed";
224
+
regulator-name = "vcc5v0_usbdcin";
225
+
regulator-always-on;
226
+
regulator-boot-on;
227
+
regulator-min-microvolt = <5000000>;
228
+
regulator-max-microvolt = <5000000>;
229
+
vin-supply = <&vcc12v_dcin>;
230
+
};
231
+
};
232
+
233
+
&combphy0_ps {
234
+
status = "okay";
235
+
};
236
+
237
+
&combphy2_psu {
238
+
status = "okay";
239
+
};
240
+
241
+
&i2c3 {
242
+
status = "okay";
243
+
244
+
es8388: audio-codec@11 {
245
+
compatible = "everest,es8388";
246
+
reg = <0x11>;
247
+
clocks = <&cru I2S0_8CH_MCLKOUT>;
248
+
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
249
+
assigned-clock-rates = <12288000>;
250
+
AVDD-supply = <&avcc_1v8_s0>;
251
+
DVDD-supply = <&avcc_1v8_s0>;
252
+
HPVDD-supply = <&vcc_3v3_s0>;
253
+
PVDD-supply = <&vcc_3v3_s0>;
254
+
#sound-dai-cells = <0>;
255
+
};
256
+
};
257
+
258
+
&i2c8 {
259
+
pinctrl-names = "default";
260
+
pinctrl-0 = <&i2c8m2_xfer>;
261
+
status = "okay";
262
+
263
+
usbc0: usb-typec@22 {
264
+
compatible = "fcs,fusb302";
265
+
reg = <0x22>;
266
+
interrupt-parent = <&gpio0>;
267
+
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
268
+
pinctrl-names = "default";
269
+
pinctrl-0 = <&usbc0_int>;
270
+
vbus-supply = <&vbus5v0_typec>;
271
+
272
+
usb_con: connector {
273
+
compatible = "usb-c-connector";
274
+
label = "USB-C";
275
+
data-role = "dual";
276
+
op-sink-microwatt = <1000000>;
277
+
power-role = "dual";
278
+
sink-pdos =
279
+
<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
280
+
source-pdos =
281
+
<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
282
+
try-power-role = "source";
283
+
284
+
ports {
285
+
#address-cells = <1>;
286
+
#size-cells = <0>;
287
+
288
+
port@0 {
289
+
reg = <0>;
290
+
291
+
usbc0_orien_sw: endpoint {
292
+
remote-endpoint = <&usbdp_phy0_orientation_switch>;
293
+
};
294
+
};
295
+
296
+
port@1 {
297
+
reg = <1>;
298
+
299
+
usbc0_role_sw: endpoint {
300
+
remote-endpoint = <&dwc3_0_role_switch>;
301
+
};
302
+
};
303
+
304
+
port@2 {
305
+
reg = <2>;
306
+
307
+
dp_altmode_mux: endpoint {
308
+
remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
309
+
};
310
+
};
311
+
};
312
+
};
313
+
};
314
+
315
+
hym8563: rtc@51 {
316
+
compatible = "haoyu,hym8563";
317
+
reg = <0x51>;
318
+
#clock-cells = <0>;
319
+
clock-output-names = "hym8563";
320
+
pinctrl-names = "default";
321
+
pinctrl-0 = <&hym8563_int>;
322
+
interrupt-parent = <&gpio0>;
323
+
interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
324
+
wakeup-source;
325
+
};
326
+
};
327
+
328
+
&pcie2x1l1 {
329
+
pinctrl-names = "default";
330
+
pinctrl-0 = <&pcie2_1_rst>;
331
+
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
332
+
vpcie3v3-supply = <&vcc3v3_pcie20>;
333
+
status = "okay";
334
+
};
335
+
336
+
&pcie2x1l2 {
337
+
pinctrl-names = "default";
338
+
pinctrl-0 = <&pcie2_2_rst>;
339
+
reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
340
+
status = "okay";
341
+
};
342
+
343
+
&pinctrl {
344
+
audio {
345
+
hp_detect: headphone-detect {
346
+
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
347
+
};
348
+
349
+
headphone_amplifier_en: headphone-amplifier-en {
350
+
rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
351
+
};
352
+
353
+
speaker_amplifier_en: speaker-amplifier-en {
354
+
rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
355
+
};
356
+
};
357
+
358
+
hym8563 {
359
+
hym8563_int: hym8563-int {
360
+
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
361
+
};
362
+
};
363
+
364
+
lcd-edp {
365
+
vcc3v3_lcd_edp_en: vcc3v3-lcd-edp-en {
366
+
rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
367
+
};
368
+
};
369
+
370
+
pcie2 {
371
+
pcie2_1_rst: pcie2-1-rst {
372
+
rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
373
+
};
374
+
375
+
pcie2_2_rst: pcie2-2-rst {
376
+
rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
377
+
};
378
+
379
+
vcc3v3_pcie20_en: vcc3v3-pcie20-en {
380
+
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
381
+
};
382
+
};
383
+
384
+
usb {
385
+
vcc5v0_host_en: vcc5v0-host-en {
386
+
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
387
+
};
388
+
};
389
+
390
+
usb-typec {
391
+
typec5v_pwren: typec5v-pwren {
392
+
rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
393
+
};
394
+
395
+
usbc0_int: usbc0-int {
396
+
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
397
+
};
398
+
};
399
+
};
400
+
401
+
&pwm12 {
402
+
status = "okay";
403
+
};
404
+
405
+
&saradc {
406
+
vref-supply = <&vcc_1v8_s0>;
407
+
status = "okay";
408
+
};
409
+
410
+
&sdhci {
411
+
bus-width = <8>;
412
+
mmc-hs400-1_8v;
413
+
mmc-hs400-enhanced-strobe;
414
+
no-sdio;
415
+
no-sd;
416
+
non-removable;
417
+
status = "okay";
418
+
};
419
+
420
+
&sdmmc {
421
+
bus-width = <4>;
422
+
cap-mmc-highspeed;
423
+
cap-sd-highspeed;
424
+
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
425
+
disable-wp;
426
+
max-frequency = <150000000>;
427
+
no-mmc;
428
+
no-sdio;
429
+
sd-uhs-sdr104;
430
+
vmmc-supply = <&vcc_3v3_sd_s0>;
431
+
vqmmc-supply = <&vccio_sd_s0>;
432
+
status = "okay";
433
+
};
434
+
435
+
&spi2 {
436
+
assigned-clocks = <&cru CLK_SPI2>;
437
+
assigned-clock-rates = <200000000>;
438
+
num-cs = <2>;
439
+
status = "okay";
440
+
441
+
pmic@0 {
442
+
compatible = "rockchip,rk806";
443
+
reg = <0x0>;
444
+
#gpio-cells = <2>;
445
+
gpio-controller;
446
+
interrupt-parent = <&gpio0>;
447
+
interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
448
+
pinctrl-names = "default";
449
+
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
450
+
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
451
+
spi-max-frequency = <1000000>;
452
+
system-power-controller;
453
+
454
+
vcc1-supply = <&vcc5v0_sys>;
455
+
vcc2-supply = <&vcc5v0_sys>;
456
+
vcc3-supply = <&vcc5v0_sys>;
457
+
vcc4-supply = <&vcc5v0_sys>;
458
+
vcc5-supply = <&vcc5v0_sys>;
459
+
vcc6-supply = <&vcc5v0_sys>;
460
+
vcc7-supply = <&vcc5v0_sys>;
461
+
vcc8-supply = <&vcc5v0_sys>;
462
+
vcc9-supply = <&vcc5v0_sys>;
463
+
vcc10-supply = <&vcc5v0_sys>;
464
+
vcc11-supply = <&vcc_2v0_pldo_s3>;
465
+
vcc12-supply = <&vcc5v0_sys>;
466
+
vcc13-supply = <&vcc5v0_sys>;
467
+
vcc14-supply = <&vcc_1v1_nldo_s3>;
468
+
vcca-supply = <&vcc5v0_sys>;
469
+
470
+
rk806_dvs1_null: dvs1-null-pins {
471
+
pins = "gpio_pwrctrl1";
472
+
function = "pin_fun0";
473
+
};
474
+
475
+
rk806_dvs2_null: dvs2-null-pins {
476
+
pins = "gpio_pwrctrl2";
477
+
function = "pin_fun0";
478
+
};
479
+
480
+
rk806_dvs3_null: dvs3-null-pins {
481
+
pins = "gpio_pwrctrl3";
482
+
function = "pin_fun0";
483
+
};
484
+
485
+
regulators {
486
+
vdd_gpu_s0: dcdc-reg1 {
487
+
regulator-name = "vdd_gpu_s0";
488
+
regulator-boot-on;
489
+
regulator-min-microvolt = <550000>;
490
+
regulator-max-microvolt = <950000>;
491
+
regulator-ramp-delay = <12500>;
492
+
regulator-enable-ramp-delay = <400>;
493
+
494
+
regulator-state-mem {
495
+
regulator-off-in-suspend;
496
+
};
497
+
};
498
+
499
+
vdd_npu_s0: dcdc-reg2 {
500
+
regulator-name = "vdd_npu_s0";
501
+
regulator-always-on;
502
+
regulator-boot-on;
503
+
regulator-min-microvolt = <550000>;
504
+
regulator-max-microvolt = <950000>;
505
+
regulator-ramp-delay = <12500>;
506
+
507
+
regulator-state-mem {
508
+
regulator-off-in-suspend;
509
+
};
510
+
};
511
+
512
+
vdd_log_s0: dcdc-reg3 {
513
+
regulator-name = "vdd_log_s0";
514
+
regulator-always-on;
515
+
regulator-boot-on;
516
+
regulator-min-microvolt = <675000>;
517
+
regulator-max-microvolt = <800000>;
518
+
regulator-ramp-delay = <12500>;
519
+
520
+
regulator-state-mem {
521
+
regulator-off-in-suspend;
522
+
regulator-suspend-microvolt = <750000>;
523
+
};
524
+
};
525
+
526
+
vdd_vdenc_s0: dcdc-reg4 {
527
+
regulator-name = "vdd_vdenc_s0";
528
+
regulator-always-on;
529
+
regulator-boot-on;
530
+
regulator-min-microvolt = <550000>;
531
+
regulator-max-microvolt = <950000>;
532
+
regulator-ramp-delay = <12500>;
533
+
534
+
regulator-state-mem {
535
+
regulator-off-in-suspend;
536
+
};
537
+
};
538
+
539
+
vdd_gpu_mem_s0: dcdc-reg5 {
540
+
regulator-name = "vdd_gpu_mem_s0";
541
+
regulator-boot-on;
542
+
regulator-min-microvolt = <675000>;
543
+
regulator-max-microvolt = <950000>;
544
+
regulator-ramp-delay = <12500>;
545
+
regulator-enable-ramp-delay = <400>;
546
+
547
+
regulator-state-mem {
548
+
regulator-off-in-suspend;
549
+
};
550
+
};
551
+
552
+
vdd_npu_mem_s0: dcdc-reg6 {
553
+
regulator-name = "vdd_npu_mem_s0";
554
+
regulator-always-on;
555
+
regulator-boot-on;
556
+
regulator-min-microvolt = <675000>;
557
+
regulator-max-microvolt = <950000>;
558
+
regulator-ramp-delay = <12500>;
559
+
560
+
regulator-state-mem {
561
+
regulator-off-in-suspend;
562
+
};
563
+
};
564
+
565
+
vcc_2v0_pldo_s3: dcdc-reg7 {
566
+
regulator-name = "vdd_2v0_pldo_s3";
567
+
regulator-always-on;
568
+
regulator-boot-on;
569
+
regulator-min-microvolt = <2000000>;
570
+
regulator-max-microvolt = <2000000>;
571
+
regulator-ramp-delay = <12500>;
572
+
573
+
regulator-state-mem {
574
+
regulator-on-in-suspend;
575
+
regulator-suspend-microvolt = <2000000>;
576
+
};
577
+
};
578
+
579
+
vdd_vdenc_mem_s0: dcdc-reg8 {
580
+
regulator-name = "vdd_vdenc_mem_s0";
581
+
regulator-always-on;
582
+
regulator-boot-on;
583
+
regulator-min-microvolt = <675000>;
584
+
regulator-max-microvolt = <950000>;
585
+
regulator-ramp-delay = <12500>;
586
+
587
+
regulator-state-mem {
588
+
regulator-off-in-suspend;
589
+
};
590
+
};
591
+
592
+
vdd2_ddr_s3: dcdc-reg9 {
593
+
regulator-name = "vdd2_ddr_s3";
594
+
regulator-always-on;
595
+
regulator-boot-on;
596
+
597
+
regulator-state-mem {
598
+
regulator-on-in-suspend;
599
+
};
600
+
};
601
+
602
+
vcc_1v1_nldo_s3: dcdc-reg10 {
603
+
regulator-name = "vcc_1v1_nldo_s3";
604
+
regulator-always-on;
605
+
regulator-boot-on;
606
+
regulator-min-microvolt = <1100000>;
607
+
regulator-max-microvolt = <1100000>;
608
+
regulator-ramp-delay = <12500>;
609
+
610
+
regulator-state-mem {
611
+
regulator-on-in-suspend;
612
+
regulator-suspend-microvolt = <1100000>;
613
+
};
614
+
};
615
+
616
+
avcc_1v8_s0: pldo-reg1 {
617
+
regulator-name = "avcc_1v8_s0";
618
+
regulator-always-on;
619
+
regulator-boot-on;
620
+
regulator-min-microvolt = <1800000>;
621
+
regulator-max-microvolt = <1800000>;
622
+
regulator-ramp-delay = <12500>;
623
+
624
+
regulator-state-mem {
625
+
regulator-off-in-suspend;
626
+
};
627
+
};
628
+
629
+
vdd1_1v8_ddr_s3: pldo-reg2 {
630
+
regulator-name = "vdd1_1v8_ddr_s3";
631
+
regulator-always-on;
632
+
regulator-boot-on;
633
+
regulator-min-microvolt = <1800000>;
634
+
regulator-max-microvolt = <1800000>;
635
+
regulator-ramp-delay = <12500>;
636
+
637
+
regulator-state-mem {
638
+
regulator-on-in-suspend;
639
+
regulator-suspend-microvolt = <1800000>;
640
+
};
641
+
};
642
+
643
+
vcc_1v8_s3: pldo-reg3 {
644
+
regulator-name = "vcc_1v8_s3";
645
+
regulator-always-on;
646
+
regulator-boot-on;
647
+
regulator-min-microvolt = <1800000>;
648
+
regulator-max-microvolt = <1800000>;
649
+
regulator-ramp-delay = <12500>;
650
+
651
+
regulator-state-mem {
652
+
regulator-on-in-suspend;
653
+
regulator-suspend-microvolt = <1800000>;
654
+
};
655
+
};
656
+
657
+
vcc_3v3_s0: pldo-reg4 {
658
+
regulator-name = "vcc_3v3_s0";
659
+
regulator-always-on;
660
+
regulator-boot-on;
661
+
regulator-min-microvolt = <3300000>;
662
+
regulator-max-microvolt = <3300000>;
663
+
regulator-ramp-delay = <12500>;
664
+
665
+
regulator-state-mem {
666
+
regulator-off-in-suspend;
667
+
};
668
+
};
669
+
670
+
vccio_sd_s0: pldo-reg5 {
671
+
regulator-name = "vccio_sd_s0";
672
+
regulator-always-on;
673
+
regulator-boot-on;
674
+
regulator-min-microvolt = <1800000>;
675
+
regulator-max-microvolt = <3300000>;
676
+
regulator-ramp-delay = <12500>;
677
+
678
+
regulator-state-mem {
679
+
regulator-off-in-suspend;
680
+
};
681
+
};
682
+
683
+
master_pldo6_s3: pldo-reg6 {
684
+
regulator-name = "master_pldo6_s3";
685
+
regulator-always-on;
686
+
regulator-boot-on;
687
+
regulator-min-microvolt = <1800000>;
688
+
regulator-max-microvolt = <1800000>;
689
+
690
+
regulator-state-mem {
691
+
regulator-on-in-suspend;
692
+
regulator-suspend-microvolt = <1800000>;
693
+
};
694
+
};
695
+
696
+
vdd_0v75_s3: nldo-reg1 {
697
+
regulator-name = "vdd_0v75_s3";
698
+
regulator-always-on;
699
+
regulator-boot-on;
700
+
regulator-min-microvolt = <750000>;
701
+
regulator-max-microvolt = <750000>;
702
+
regulator-ramp-delay = <12500>;
703
+
704
+
regulator-state-mem {
705
+
regulator-on-in-suspend;
706
+
regulator-suspend-microvolt = <750000>;
707
+
};
708
+
};
709
+
710
+
vdd2l_0v9_ddr_s3: nldo-reg2 {
711
+
regulator-name = "vdd2l_0v9_ddr_s3";
712
+
regulator-always-on;
713
+
regulator-boot-on;
714
+
regulator-min-microvolt = <900000>;
715
+
regulator-max-microvolt = <900000>;
716
+
717
+
regulator-state-mem {
718
+
regulator-on-in-suspend;
719
+
regulator-suspend-microvolt = <900000>;
720
+
};
721
+
};
722
+
723
+
master_nldo3: nldo-reg3 {
724
+
regulator-name = "master_nldo3";
725
+
726
+
regulator-state-mem {
727
+
regulator-off-in-suspend;
728
+
};
729
+
};
730
+
731
+
avdd_0v75_s0: nldo-reg4 {
732
+
regulator-name = "avdd_0v75_s0";
733
+
regulator-always-on;
734
+
regulator-boot-on;
735
+
regulator-min-microvolt = <750000>;
736
+
regulator-max-microvolt = <750000>;
737
+
738
+
regulator-state-mem {
739
+
regulator-off-in-suspend;
740
+
};
741
+
};
742
+
743
+
vdd_0v85_s0: nldo-reg5 {
744
+
regulator-name = "vdd_0v85_s0";
745
+
regulator-always-on;
746
+
regulator-boot-on;
747
+
regulator-min-microvolt = <850000>;
748
+
regulator-max-microvolt = <850000>;
749
+
750
+
regulator-state-mem {
751
+
regulator-off-in-suspend;
752
+
};
753
+
};
754
+
};
755
+
};
756
+
757
+
pmic@1 {
758
+
compatible = "rockchip,rk806";
759
+
reg = <0x01>;
760
+
#gpio-cells = <2>;
761
+
gpio-controller;
762
+
interrupt-parent = <&gpio0>;
763
+
interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
764
+
pinctrl-names = "default";
765
+
pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>,
766
+
<&rk806_slave_dvs3_null>;
767
+
spi-max-frequency = <1000000>;
768
+
769
+
vcc1-supply = <&vcc5v0_sys>;
770
+
vcc2-supply = <&vcc5v0_sys>;
771
+
vcc3-supply = <&vcc5v0_sys>;
772
+
vcc4-supply = <&vcc5v0_sys>;
773
+
vcc5-supply = <&vcc5v0_sys>;
774
+
vcc6-supply = <&vcc5v0_sys>;
775
+
vcc7-supply = <&vcc5v0_sys>;
776
+
vcc8-supply = <&vcc5v0_sys>;
777
+
vcc9-supply = <&vcc5v0_sys>;
778
+
vcc10-supply = <&vcc5v0_sys>;
779
+
vcc11-supply = <&vcc_2v0_pldo_s3>;
780
+
vcc12-supply = <&vcc5v0_sys>;
781
+
vcc13-supply = <&vcc_1v1_nldo_s3>;
782
+
vcc14-supply = <&vcc_2v0_pldo_s3>;
783
+
vcca-supply = <&vcc5v0_sys>;
784
+
785
+
rk806_slave_dvs1_null: dvs1-null-pins {
786
+
pins = "gpio_pwrctrl1";
787
+
function = "pin_fun0";
788
+
};
789
+
790
+
rk806_slave_dvs2_null: dvs2-null-pins {
791
+
pins = "gpio_pwrctrl2";
792
+
function = "pin_fun0";
793
+
};
794
+
795
+
rk806_slave_dvs3_null: dvs3-null-pins {
796
+
pins = "gpio_pwrctrl3";
797
+
function = "pin_fun0";
798
+
};
799
+
800
+
regulators {
801
+
vdd_cpu_big1_s0: dcdc-reg1 {
802
+
regulator-name = "vdd_cpu_big1_s0";
803
+
regulator-always-on;
804
+
regulator-boot-on;
805
+
regulator-coupled-with = <&vdd_cpu_big1_mem_s0>;
806
+
regulator-coupled-max-spread = <10000>;
807
+
regulator-min-microvolt = <550000>;
808
+
regulator-max-microvolt = <1050000>;
809
+
regulator-ramp-delay = <12500>;
810
+
811
+
regulator-state-mem {
812
+
regulator-off-in-suspend;
813
+
};
814
+
};
815
+
816
+
vdd_cpu_big0_s0: dcdc-reg2 {
817
+
regulator-name = "vdd_cpu_big0_s0";
818
+
regulator-always-on;
819
+
regulator-boot-on;
820
+
regulator-coupled-with = <&vdd_cpu_big0_mem_s0>;
821
+
regulator-coupled-max-spread = <10000>;
822
+
regulator-min-microvolt = <550000>;
823
+
regulator-max-microvolt = <1050000>;
824
+
regulator-ramp-delay = <12500>;
825
+
826
+
regulator-state-mem {
827
+
regulator-off-in-suspend;
828
+
};
829
+
};
830
+
831
+
vdd_cpu_lit_s0: dcdc-reg3 {
832
+
regulator-name = "vdd_cpu_lit_s0";
833
+
regulator-always-on;
834
+
regulator-boot-on;
835
+
regulator-coupled-with = <&vdd_cpu_lit_mem_s0>;
836
+
regulator-coupled-max-spread = <10000>;
837
+
regulator-min-microvolt = <550000>;
838
+
regulator-max-microvolt = <950000>;
839
+
regulator-ramp-delay = <12500>;
840
+
841
+
regulator-state-mem {
842
+
regulator-off-in-suspend;
843
+
};
844
+
};
845
+
846
+
vcc_3v3_s3: dcdc-reg4 {
847
+
regulator-name = "vcc_3v3_s3";
848
+
regulator-always-on;
849
+
regulator-boot-on;
850
+
regulator-min-microvolt = <3300000>;
851
+
regulator-max-microvolt = <3300000>;
852
+
regulator-ramp-delay = <12500>;
853
+
854
+
regulator-state-mem {
855
+
regulator-on-in-suspend;
856
+
regulator-suspend-microvolt = <3300000>;
857
+
};
858
+
};
859
+
860
+
vdd_cpu_big1_mem_s0: dcdc-reg5 {
861
+
regulator-name = "vdd_cpu_big1_mem_s0";
862
+
regulator-always-on;
863
+
regulator-boot-on;
864
+
regulator-coupled-with = <&vdd_cpu_big1_s0>;
865
+
regulator-coupled-max-spread = <10000>;
866
+
regulator-min-microvolt = <675000>;
867
+
regulator-max-microvolt = <1050000>;
868
+
regulator-ramp-delay = <12500>;
869
+
870
+
regulator-state-mem {
871
+
regulator-off-in-suspend;
872
+
};
873
+
};
874
+
875
+
876
+
vdd_cpu_big0_mem_s0: dcdc-reg6 {
877
+
regulator-name = "vdd_cpu_big0_mem_s0";
878
+
regulator-always-on;
879
+
regulator-boot-on;
880
+
regulator-coupled-with = <&vdd_cpu_big0_s0>;
881
+
regulator-coupled-max-spread = <10000>;
882
+
regulator-min-microvolt = <675000>;
883
+
regulator-max-microvolt = <1050000>;
884
+
regulator-ramp-delay = <12500>;
885
+
886
+
regulator-state-mem {
887
+
regulator-off-in-suspend;
888
+
};
889
+
};
890
+
891
+
vcc_1v8_s0: dcdc-reg7 {
892
+
regulator-name = "vcc_1v8_s0";
893
+
regulator-always-on;
894
+
regulator-boot-on;
895
+
regulator-min-microvolt = <1800000>;
896
+
regulator-max-microvolt = <1800000>;
897
+
regulator-ramp-delay = <12500>;
898
+
899
+
regulator-state-mem {
900
+
regulator-off-in-suspend;
901
+
};
902
+
};
903
+
904
+
vdd_cpu_lit_mem_s0: dcdc-reg8 {
905
+
regulator-name = "vdd_cpu_lit_mem_s0";
906
+
regulator-always-on;
907
+
regulator-boot-on;
908
+
regulator-coupled-with = <&vdd_cpu_lit_s0>;
909
+
regulator-coupled-max-spread = <10000>;
910
+
regulator-min-microvolt = <675000>;
911
+
regulator-max-microvolt = <950000>;
912
+
regulator-ramp-delay = <12500>;
913
+
914
+
regulator-state-mem {
915
+
regulator-off-in-suspend;
916
+
};
917
+
};
918
+
919
+
vddq_ddr_s0: dcdc-reg9 {
920
+
regulator-name = "vddq_ddr_s0";
921
+
regulator-always-on;
922
+
regulator-boot-on;
923
+
924
+
regulator-state-mem {
925
+
regulator-off-in-suspend;
926
+
};
927
+
};
928
+
929
+
vdd_ddr_s0: dcdc-reg10 {
930
+
regulator-name = "vdd_ddr_s0";
931
+
regulator-always-on;
932
+
regulator-boot-on;
933
+
regulator-min-microvolt = <675000>;
934
+
regulator-max-microvolt = <900000>;
935
+
regulator-ramp-delay = <12500>;
936
+
937
+
regulator-state-mem {
938
+
regulator-off-in-suspend;
939
+
};
940
+
};
941
+
942
+
vcc_1v8_cam_s0: pldo-reg1 {
943
+
regulator-name = "vcc_1v8_cam_s0";
944
+
regulator-always-on;
945
+
regulator-boot-on;
946
+
regulator-min-microvolt = <1800000>;
947
+
regulator-max-microvolt = <1800000>;
948
+
regulator-ramp-delay = <12500>;
949
+
950
+
regulator-state-mem {
951
+
regulator-off-in-suspend;
952
+
};
953
+
};
954
+
955
+
avdd1v8_ddr_pll_s0: pldo-reg2 {
956
+
regulator-name = "avdd1v8_ddr_pll_s0";
957
+
regulator-always-on;
958
+
regulator-boot-on;
959
+
regulator-min-microvolt = <1800000>;
960
+
regulator-max-microvolt = <1800000>;
961
+
regulator-ramp-delay = <12500>;
962
+
963
+
regulator-state-mem {
964
+
regulator-off-in-suspend;
965
+
};
966
+
};
967
+
968
+
vdd_1v8_pll_s0: pldo-reg3 {
969
+
regulator-name = "vdd_1v8_pll_s0";
970
+
regulator-always-on;
971
+
regulator-boot-on;
972
+
regulator-min-microvolt = <1800000>;
973
+
regulator-max-microvolt = <1800000>;
974
+
regulator-ramp-delay = <12500>;
975
+
976
+
regulator-state-mem {
977
+
regulator-off-in-suspend;
978
+
};
979
+
};
980
+
981
+
vcc_3v3_sd_s0: pldo-reg4 {
982
+
regulator-name = "vcc_3v3_sd_s0";
983
+
regulator-always-on;
984
+
regulator-boot-on;
985
+
regulator-min-microvolt = <3300000>;
986
+
regulator-max-microvolt = <3300000>;
987
+
regulator-ramp-delay = <12500>;
988
+
989
+
regulator-state-mem {
990
+
regulator-off-in-suspend;
991
+
};
992
+
};
993
+
994
+
vcc_2v8_cam_s0: pldo-reg5 {
995
+
regulator-name = "vcc_2v8_cam_s0";
996
+
regulator-always-on;
997
+
regulator-boot-on;
998
+
regulator-min-microvolt = <2800000>;
999
+
regulator-max-microvolt = <2800000>;
1000
+
regulator-ramp-delay = <12500>;
1001
+
1002
+
regulator-state-mem {
1003
+
regulator-off-in-suspend;
1004
+
};
1005
+
};
1006
+
1007
+
pldo6_s3: pldo-reg6 {
1008
+
regulator-name = "pldo6_s3";
1009
+
regulator-always-on;
1010
+
regulator-boot-on;
1011
+
regulator-min-microvolt = <1800000>;
1012
+
regulator-max-microvolt = <1800000>;
1013
+
1014
+
regulator-state-mem {
1015
+
regulator-on-in-suspend;
1016
+
regulator-suspend-microvolt = <1800000>;
1017
+
};
1018
+
};
1019
+
1020
+
vdd_0v75_pll_s0: nldo-reg1 {
1021
+
regulator-name = "vdd_0v75_pll_s0";
1022
+
regulator-always-on;
1023
+
regulator-boot-on;
1024
+
regulator-min-microvolt = <750000>;
1025
+
regulator-max-microvolt = <750000>;
1026
+
regulator-ramp-delay = <12500>;
1027
+
1028
+
regulator-state-mem {
1029
+
regulator-off-in-suspend;
1030
+
};
1031
+
};
1032
+
1033
+
vdd_ddr_pll_s0: nldo-reg2 {
1034
+
regulator-name = "vdd_ddr_pll_s0";
1035
+
regulator-always-on;
1036
+
regulator-boot-on;
1037
+
regulator-min-microvolt = <850000>;
1038
+
regulator-max-microvolt = <850000>;
1039
+
1040
+
regulator-state-mem {
1041
+
regulator-off-in-suspend;
1042
+
};
1043
+
};
1044
+
1045
+
slave_nldo3: nldo-reg3 {
1046
+
regulator-name = "slave_nldo3";
1047
+
1048
+
regulator-state-mem {
1049
+
regulator-off-in-suspend;
1050
+
};
1051
+
};
1052
+
1053
+
avdd_1v2_cam_s0: nldo-reg4 {
1054
+
regulator-always-on;
1055
+
regulator-boot-on;
1056
+
regulator-min-microvolt = <1200000>;
1057
+
regulator-max-microvolt = <1200000>;
1058
+
regulator-ramp-delay = <12500>;
1059
+
regulator-name = "avdd_1v2_cam_s0";
1060
+
1061
+
regulator-state-mem {
1062
+
regulator-off-in-suspend;
1063
+
};
1064
+
};
1065
+
1066
+
avdd_1v2_s0: nldo-reg5 {
1067
+
regulator-always-on;
1068
+
regulator-boot-on;
1069
+
regulator-min-microvolt = <1200000>;
1070
+
regulator-max-microvolt = <1200000>;
1071
+
regulator-ramp-delay = <12500>;
1072
+
regulator-name = "avdd_1v2_s0";
1073
+
1074
+
regulator-state-mem {
1075
+
regulator-off-in-suspend;
1076
+
};
1077
+
};
1078
+
};
1079
+
};
1080
+
};
1081
+
1082
+
&tsadc {
1083
+
status = "okay";
1084
+
};
1085
+
1086
+
&u2phy0 {
1087
+
status = "okay";
1088
+
};
1089
+
1090
+
&u2phy2 {
1091
+
status = "okay";
1092
+
};
1093
+
1094
+
&u2phy3 {
1095
+
status = "okay";
1096
+
};
1097
+
1098
+
&u2phy0_otg {
1099
+
status = "okay";
1100
+
};
1101
+
1102
+
&u2phy2_host {
1103
+
phy-supply = <&vcc5v0_host>;
1104
+
status = "okay";
1105
+
};
1106
+
1107
+
&u2phy3_host {
1108
+
phy-supply = <&vcc5v0_host>;
1109
+
status = "okay";
1110
+
};
1111
+
1112
+
&uart2 {
1113
+
pinctrl-names = "default";
1114
+
pinctrl-0 = <&uart2m0_xfer>;
1115
+
status = "okay";
1116
+
};
1117
+
1118
+
&usb_host0_ehci {
1119
+
status = "okay";
1120
+
};
1121
+
1122
+
&usb_host0_ohci {
1123
+
status = "okay";
1124
+
};
1125
+
1126
+
&usb_host0_xhci {
1127
+
usb-role-switch;
1128
+
status = "okay";
1129
+
1130
+
port {
1131
+
#address-cells = <1>;
1132
+
#size-cells = <0>;
1133
+
1134
+
dwc3_0_role_switch: endpoint@0 {
1135
+
reg = <0>;
1136
+
remote-endpoint = <&usbc0_role_sw>;
1137
+
};
1138
+
};
1139
+
};
1140
+
1141
+
&usb_host1_ehci {
1142
+
status = "okay";
1143
+
};
1144
+
1145
+
&usb_host1_ohci {
1146
+
status = "okay";
1147
+
};
1148
+
1149
+
&usbdp_phy0 {
1150
+
mode-switch;
1151
+
orientation-switch;
1152
+
sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
1153
+
sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>;
1154
+
status = "okay";
1155
+
1156
+
port {
1157
+
#address-cells = <1>;
1158
+
#size-cells = <0>;
1159
+
1160
+
usbdp_phy0_orientation_switch: endpoint@0 {
1161
+
reg = <0>;
1162
+
remote-endpoint = <&usbc0_orien_sw>;
1163
+
};
1164
+
1165
+
usbdp_phy0_dp_altmode_mux: endpoint@1 {
1166
+
reg = <1>;
1167
+
remote-endpoint = <&dp_altmode_mux>;
1168
+
};
1169
+
};
1170
+
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts
···
122
122
simple-audio-card,bitclock-master = <&masterdai>;
123
123
simple-audio-card,format = "i2s";
124
124
simple-audio-card,frame-master = <&masterdai>;
125
-
simple-audio-card,hp-det-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
125
+
simple-audio-card,hp-det-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
126
126
simple-audio-card,mclk-fs = <256>;
127
127
simple-audio-card,name = "rockchip,es8388-codec";
128
128
simple-audio-card,pin-switches = "Headphones", "Speaker";
+16
arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+16
arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
···
283
283
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
284
284
vpcie3v3-supply = <&vcc3v3_pcie_wl>;
285
285
status = "okay";
286
+
287
+
pcie@0,0 {
288
+
reg = <0x400000 0 0 0 0>;
289
+
#address-cells = <3>;
290
+
#size-cells = <2>;
291
+
ranges;
292
+
device_type = "pci";
293
+
bus-range = <0x40 0x4f>;
294
+
295
+
wifi: wifi@0,0 {
296
+
compatible = "pci14e4,449d";
297
+
reg = <0x410000 0 0 0 0>;
298
+
clocks = <&hym8563>;
299
+
clock-names = "lpo";
300
+
};
301
+
};
286
302
};
287
303
288
304
&pwm11 {
+760
arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
+760
arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
3
+
/dts-v1/;
4
+
5
+
#include <dt-bindings/pinctrl/rockchip.h>
6
+
#include <dt-bindings/gpio/gpio.h>
7
+
#include <dt-bindings/input/input.h>
8
+
#include "rk3588s.dtsi"
9
+
10
+
/ {
11
+
aliases {
12
+
ethernet0 = &gmac1;
13
+
mmc0 = &sdmmc;
14
+
mmc1 = &sdhci;
15
+
};
16
+
17
+
chosen {
18
+
stdout-path = "serial2:1500000n8";
19
+
};
20
+
21
+
adc-keys {
22
+
compatible = "adc-keys";
23
+
io-channels = <&saradc 0>;
24
+
io-channel-names = "buttons";
25
+
keyup-threshold-microvolt = <1800000>;
26
+
poll-interval = <100>;
27
+
28
+
button-maskrom {
29
+
label = "Maskrom";
30
+
linux,code = <KEY_VENDOR>;
31
+
press-threshold-microvolt = <1800>;
32
+
};
33
+
};
34
+
35
+
gpio-keys {
36
+
compatible = "gpio-keys";
37
+
pinctrl-names = "default";
38
+
pinctrl-0 = <&key1_pin>;
39
+
40
+
button-user {
41
+
label = "User";
42
+
linux,code = <BTN_1>;
43
+
gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>;
44
+
debounce-interval = <50>;
45
+
};
46
+
};
47
+
48
+
leds {
49
+
compatible = "gpio-leds";
50
+
51
+
sys_led: led-0 {
52
+
label = "sys_led";
53
+
gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
54
+
linux,default-trigger = "heartbeat";
55
+
pinctrl-names = "default";
56
+
pinctrl-0 = <&sys_led_pin>;
57
+
};
58
+
59
+
wan_led: led-1 {
60
+
label = "wan_led";
61
+
gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
62
+
pinctrl-names = "default";
63
+
pinctrl-0 = <&wan_led_pin>;
64
+
};
65
+
66
+
lan1_led: led-2 {
67
+
label = "lan1_led";
68
+
gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
69
+
pinctrl-names = "default";
70
+
pinctrl-0 = <&lan1_led_pin>;
71
+
};
72
+
73
+
lan2_led: led-3 {
74
+
gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
75
+
pinctrl-names = "default";
76
+
pinctrl-0 = <&lan2_led_pin>;
77
+
};
78
+
};
79
+
80
+
vcc5v0_sys: vcc5v0-sys-regulator {
81
+
compatible = "regulator-fixed";
82
+
regulator-name = "vcc5v0_sys";
83
+
regulator-always-on;
84
+
regulator-boot-on;
85
+
regulator-min-microvolt = <5000000>;
86
+
regulator-max-microvolt = <5000000>;
87
+
};
88
+
89
+
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
90
+
compatible = "regulator-fixed";
91
+
regulator-name = "vcc_1v1_nldo_s3";
92
+
regulator-always-on;
93
+
regulator-boot-on;
94
+
regulator-min-microvolt = <1100000>;
95
+
regulator-max-microvolt = <1100000>;
96
+
vin-supply = <&vcc5v0_sys>;
97
+
};
98
+
99
+
vcc_3v3_s0: vcc-3v3-s0-regulator {
100
+
compatible = "regulator-fixed";
101
+
regulator-always-on;
102
+
regulator-boot-on;
103
+
regulator-min-microvolt = <3300000>;
104
+
regulator-max-microvolt = <3300000>;
105
+
regulator-name = "vcc_3v3_s0";
106
+
vin-supply = <&vcc_3v3_s3>;
107
+
};
108
+
109
+
vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
110
+
compatible = "regulator-fixed";
111
+
enable-active-high;
112
+
gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
113
+
pinctrl-names = "default";
114
+
pinctrl-0 = <&sd_s0_pwr>;
115
+
regulator-name = "vcc_3v3_sd_s0";
116
+
regulator-boot-on;
117
+
regulator-max-microvolt = <3000000>;
118
+
regulator-min-microvolt = <3000000>;
119
+
vin-supply = <&vcc_3v3_s3>;
120
+
};
121
+
122
+
vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
123
+
compatible = "regulator-fixed";
124
+
regulator-name = "vcc_3v3_pcie20";
125
+
regulator-always-on;
126
+
regulator-boot-on;
127
+
regulator-min-microvolt = <3300000>;
128
+
regulator-max-microvolt = <3300000>;
129
+
vin-supply = <&vcc_3v3_s3>;
130
+
};
131
+
132
+
vcc5v0_usb: vcc5v0-usb-regulator {
133
+
compatible = "regulator-fixed";
134
+
regulator-name = "vcc5v0_usb";
135
+
regulator-always-on;
136
+
regulator-boot-on;
137
+
regulator-min-microvolt = <5000000>;
138
+
regulator-max-microvolt = <5000000>;
139
+
vin-supply = <&vcc5v0_sys>;
140
+
};
141
+
142
+
vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator {
143
+
compatible = "regulator-fixed";
144
+
enable-active-high;
145
+
gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
146
+
pinctrl-names = "default";
147
+
pinctrl-0 = <&typec5v_pwren>;
148
+
regulator-name = "vcc5v0_usb_otg0";
149
+
regulator-min-microvolt = <5000000>;
150
+
regulator-max-microvolt = <5000000>;
151
+
vin-supply = <&vcc5v0_usb>;
152
+
};
153
+
154
+
vcc5v0_host_20: vcc5v0-host-20-regulator {
155
+
compatible = "regulator-fixed";
156
+
enable-active-high;
157
+
gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
158
+
pinctrl-names = "default";
159
+
pinctrl-0 = <&vcc5v0_host20_en>;
160
+
regulator-name = "vcc5v0_host_20";
161
+
regulator-min-microvolt = <5000000>;
162
+
regulator-max-microvolt = <5000000>;
163
+
vin-supply = <&vcc5v0_usb>;
164
+
};
165
+
};
166
+
167
+
&combphy0_ps {
168
+
status = "okay";
169
+
};
170
+
171
+
&combphy2_psu {
172
+
status = "okay";
173
+
};
174
+
175
+
&cpu_b0 {
176
+
cpu-supply = <&vdd_cpu_big0_s0>;
177
+
};
178
+
179
+
&cpu_b1 {
180
+
cpu-supply = <&vdd_cpu_big0_s0>;
181
+
};
182
+
183
+
&cpu_b2 {
184
+
cpu-supply = <&vdd_cpu_big1_s0>;
185
+
};
186
+
187
+
&cpu_b3 {
188
+
cpu-supply = <&vdd_cpu_big1_s0>;
189
+
};
190
+
191
+
&cpu_l0 {
192
+
cpu-supply = <&vdd_cpu_lit_s0>;
193
+
};
194
+
195
+
&cpu_l1 {
196
+
cpu-supply = <&vdd_cpu_lit_s0>;
197
+
};
198
+
199
+
&cpu_l2 {
200
+
cpu-supply = <&vdd_cpu_lit_s0>;
201
+
};
202
+
203
+
&cpu_l3 {
204
+
cpu-supply = <&vdd_cpu_lit_s0>;
205
+
};
206
+
207
+
&gmac1 {
208
+
clock_in_out = "output";
209
+
phy-handle = <&rgmii_phy1>;
210
+
phy-mode = "rgmii-rxid";
211
+
pinctrl-0 = <&gmac1_miim
212
+
&gmac1_tx_bus2
213
+
&gmac1_rx_bus2
214
+
&gmac1_rgmii_clk
215
+
&gmac1_rgmii_bus>;
216
+
pinctrl-names = "default";
217
+
tx_delay = <0x42>;
218
+
status = "okay";
219
+
};
220
+
221
+
&i2c0 {
222
+
pinctrl-names = "default";
223
+
pinctrl-0 = <&i2c0m2_xfer>;
224
+
status = "okay";
225
+
226
+
vdd_cpu_big0_s0: regulator@42 {
227
+
compatible = "rockchip,rk8602";
228
+
reg = <0x42>;
229
+
fcs,suspend-voltage-selector = <1>;
230
+
regulator-name = "vdd_cpu_big0_s0";
231
+
regulator-always-on;
232
+
regulator-boot-on;
233
+
regulator-min-microvolt = <550000>;
234
+
regulator-max-microvolt = <1050000>;
235
+
regulator-ramp-delay = <2300>;
236
+
vin-supply = <&vcc5v0_sys>;
237
+
238
+
regulator-state-mem {
239
+
regulator-off-in-suspend;
240
+
};
241
+
};
242
+
243
+
vdd_cpu_big1_s0: regulator@43 {
244
+
compatible = "rockchip,rk8603", "rockchip,rk8602";
245
+
reg = <0x43>;
246
+
fcs,suspend-voltage-selector = <1>;
247
+
regulator-name = "vdd_cpu_big1_s0";
248
+
regulator-always-on;
249
+
regulator-boot-on;
250
+
regulator-min-microvolt = <550000>;
251
+
regulator-max-microvolt = <1050000>;
252
+
regulator-ramp-delay = <2300>;
253
+
vin-supply = <&vcc5v0_sys>;
254
+
255
+
regulator-state-mem {
256
+
regulator-off-in-suspend;
257
+
};
258
+
};
259
+
};
260
+
261
+
&i2c2 {
262
+
status = "okay";
263
+
264
+
vdd_npu_s0: regulator@42 {
265
+
compatible = "rockchip,rk8602";
266
+
reg = <0x42>;
267
+
fcs,suspend-voltage-selector = <1>;
268
+
regulator-name = "vdd_npu_s0";
269
+
regulator-min-microvolt = <550000>;
270
+
regulator-max-microvolt = <950000>;
271
+
regulator-ramp-delay = <2300>;
272
+
regulator-boot-on;
273
+
regulator-always-on;
274
+
vin-supply = <&vcc5v0_sys>;
275
+
276
+
regulator-state-mem {
277
+
regulator-off-in-suspend;
278
+
};
279
+
};
280
+
};
281
+
282
+
&i2c6 {
283
+
clock-frequency = <200000>;
284
+
pinctrl-names = "default";
285
+
pinctrl-0 = <&i2c6m0_xfer>;
286
+
status = "okay";
287
+
288
+
hym8563: rtc@51 {
289
+
compatible = "haoyu,hym8563";
290
+
reg = <0x51>;
291
+
#clock-cells = <0>;
292
+
clock-output-names = "hym8563";
293
+
pinctrl-names = "default";
294
+
pinctrl-0 = <&rtc_int>;
295
+
interrupt-parent = <&gpio0>;
296
+
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
297
+
wakeup-source;
298
+
};
299
+
};
300
+
301
+
&mdio1 {
302
+
rgmii_phy1: ethernet-phy@1 {
303
+
compatible = "ethernet-phy-id001c.c916";
304
+
reg = <0x1>;
305
+
pinctrl-names = "default";
306
+
pinctrl-0 = <&rtl8211f_rst>;
307
+
reset-assert-us = <20000>;
308
+
reset-deassert-us = <100000>;
309
+
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
310
+
};
311
+
};
312
+
313
+
&pcie2x1l1 {
314
+
reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
315
+
vpcie3v3-supply = <&vcc_3v3_pcie20>;
316
+
status = "okay";
317
+
};
318
+
319
+
&pcie2x1l2 {
320
+
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
321
+
vpcie3v3-supply = <&vcc_3v3_pcie20>;
322
+
status = "okay";
323
+
};
324
+
325
+
&pinctrl {
326
+
gpio-key {
327
+
key1_pin: key1-pin {
328
+
rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
329
+
};
330
+
};
331
+
332
+
gpio-leds {
333
+
sys_led_pin: sys-led-pin {
334
+
rockchip,pins =
335
+
<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
336
+
};
337
+
338
+
wan_led_pin: wan-led-pin {
339
+
rockchip,pins =
340
+
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
341
+
};
342
+
343
+
lan1_led_pin: lan1-led-pin {
344
+
rockchip,pins =
345
+
<1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
346
+
};
347
+
348
+
lan2_led_pin: lan2-led-pin {
349
+
rockchip,pins =
350
+
<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
351
+
};
352
+
};
353
+
354
+
hym8563 {
355
+
rtc_int: rtc-int {
356
+
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
357
+
};
358
+
};
359
+
360
+
sdmmc {
361
+
sd_s0_pwr: sd-s0-pwr {
362
+
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
363
+
};
364
+
};
365
+
366
+
usb {
367
+
typec5v_pwren: typec5v-pwren {
368
+
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
369
+
};
370
+
371
+
vcc5v0_host20_en: vcc5v0-host20-en {
372
+
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
373
+
};
374
+
};
375
+
376
+
rtl8211f {
377
+
rtl8211f_rst: rtl8211f-rst {
378
+
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
379
+
};
380
+
};
381
+
};
382
+
383
+
&saradc {
384
+
vref-supply = <&avcc_1v8_s0>;
385
+
status = "okay";
386
+
};
387
+
388
+
&sdhci {
389
+
bus-width = <8>;
390
+
no-sdio;
391
+
no-sd;
392
+
non-removable;
393
+
mmc-hs200-1_8v;
394
+
status = "okay";
395
+
};
396
+
397
+
&sdmmc {
398
+
bus-width = <4>;
399
+
cap-sd-highspeed;
400
+
disable-wp;
401
+
max-frequency = <150000000>;
402
+
no-mmc;
403
+
no-sdio;
404
+
sd-uhs-sdr104;
405
+
vmmc-supply = <&vcc_3v3_sd_s0>;
406
+
vqmmc-supply = <&vccio_sd_s0>;
407
+
status = "okay";
408
+
};
409
+
410
+
&spi2 {
411
+
status = "okay";
412
+
assigned-clocks = <&cru CLK_SPI2>;
413
+
assigned-clock-rates = <200000000>;
414
+
pinctrl-names = "default";
415
+
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
416
+
num-cs = <1>;
417
+
418
+
pmic@0 {
419
+
compatible = "rockchip,rk806";
420
+
spi-max-frequency = <1000000>;
421
+
reg = <0x0>;
422
+
423
+
interrupt-parent = <&gpio0>;
424
+
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
425
+
426
+
pinctrl-names = "default";
427
+
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
428
+
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
429
+
430
+
system-power-controller;
431
+
432
+
vcc1-supply = <&vcc5v0_sys>;
433
+
vcc2-supply = <&vcc5v0_sys>;
434
+
vcc3-supply = <&vcc5v0_sys>;
435
+
vcc4-supply = <&vcc5v0_sys>;
436
+
vcc5-supply = <&vcc5v0_sys>;
437
+
vcc6-supply = <&vcc5v0_sys>;
438
+
vcc7-supply = <&vcc5v0_sys>;
439
+
vcc8-supply = <&vcc5v0_sys>;
440
+
vcc9-supply = <&vcc5v0_sys>;
441
+
vcc10-supply = <&vcc5v0_sys>;
442
+
vcc11-supply = <&vcc_2v0_pldo_s3>;
443
+
vcc12-supply = <&vcc5v0_sys>;
444
+
vcc13-supply = <&vcc_1v1_nldo_s3>;
445
+
vcc14-supply = <&vcc_1v1_nldo_s3>;
446
+
vcca-supply = <&vcc5v0_sys>;
447
+
448
+
gpio-controller;
449
+
#gpio-cells = <2>;
450
+
451
+
rk806_dvs1_null: dvs1-null-pins {
452
+
pins = "gpio_pwrctrl1";
453
+
function = "pin_fun0";
454
+
};
455
+
456
+
rk806_dvs2_null: dvs2-null-pins {
457
+
pins = "gpio_pwrctrl2";
458
+
function = "pin_fun0";
459
+
};
460
+
461
+
rk806_dvs3_null: dvs3-null-pins {
462
+
pins = "gpio_pwrctrl3";
463
+
function = "pin_fun0";
464
+
};
465
+
466
+
regulators {
467
+
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
468
+
regulator-boot-on;
469
+
regulator-min-microvolt = <550000>;
470
+
regulator-max-microvolt = <950000>;
471
+
regulator-ramp-delay = <12500>;
472
+
regulator-name = "vdd_gpu_s0";
473
+
regulator-enable-ramp-delay = <400>;
474
+
475
+
regulator-state-mem {
476
+
regulator-off-in-suspend;
477
+
};
478
+
};
479
+
480
+
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
481
+
regulator-always-on;
482
+
regulator-boot-on;
483
+
regulator-min-microvolt = <550000>;
484
+
regulator-max-microvolt = <950000>;
485
+
regulator-ramp-delay = <12500>;
486
+
regulator-name = "vdd_cpu_lit_s0";
487
+
488
+
regulator-state-mem {
489
+
regulator-off-in-suspend;
490
+
};
491
+
};
492
+
493
+
vdd_log_s0: dcdc-reg3 {
494
+
regulator-always-on;
495
+
regulator-boot-on;
496
+
regulator-min-microvolt = <675000>;
497
+
regulator-max-microvolt = <750000>;
498
+
regulator-ramp-delay = <12500>;
499
+
regulator-name = "vdd_log_s0";
500
+
501
+
regulator-state-mem {
502
+
regulator-off-in-suspend;
503
+
regulator-suspend-microvolt = <750000>;
504
+
};
505
+
};
506
+
507
+
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
508
+
regulator-always-on;
509
+
regulator-boot-on;
510
+
regulator-min-microvolt = <550000>;
511
+
regulator-max-microvolt = <950000>;
512
+
regulator-ramp-delay = <12500>;
513
+
regulator-name = "vdd_vdenc_s0";
514
+
515
+
regulator-state-mem {
516
+
regulator-off-in-suspend;
517
+
};
518
+
};
519
+
520
+
vdd_ddr_s0: dcdc-reg5 {
521
+
regulator-always-on;
522
+
regulator-boot-on;
523
+
regulator-min-microvolt = <675000>;
524
+
regulator-max-microvolt = <900000>;
525
+
regulator-ramp-delay = <12500>;
526
+
regulator-name = "vdd_ddr_s0";
527
+
528
+
regulator-state-mem {
529
+
regulator-off-in-suspend;
530
+
regulator-suspend-microvolt = <850000>;
531
+
};
532
+
};
533
+
534
+
vdd2_ddr_s3: dcdc-reg6 {
535
+
regulator-always-on;
536
+
regulator-boot-on;
537
+
regulator-name = "vdd2_ddr_s3";
538
+
539
+
regulator-state-mem {
540
+
regulator-on-in-suspend;
541
+
};
542
+
};
543
+
544
+
vcc_2v0_pldo_s3: dcdc-reg7 {
545
+
regulator-always-on;
546
+
regulator-boot-on;
547
+
regulator-min-microvolt = <2000000>;
548
+
regulator-max-microvolt = <2000000>;
549
+
regulator-ramp-delay = <12500>;
550
+
regulator-name = "vdd_2v0_pldo_s3";
551
+
552
+
regulator-state-mem {
553
+
regulator-on-in-suspend;
554
+
regulator-suspend-microvolt = <2000000>;
555
+
};
556
+
};
557
+
558
+
vcc_3v3_s3: dcdc-reg8 {
559
+
regulator-always-on;
560
+
regulator-boot-on;
561
+
regulator-min-microvolt = <3300000>;
562
+
regulator-max-microvolt = <3300000>;
563
+
regulator-name = "vcc_3v3_s3";
564
+
565
+
regulator-state-mem {
566
+
regulator-on-in-suspend;
567
+
regulator-suspend-microvolt = <3300000>;
568
+
};
569
+
};
570
+
571
+
vddq_ddr_s0: dcdc-reg9 {
572
+
regulator-always-on;
573
+
regulator-boot-on;
574
+
regulator-name = "vddq_ddr_s0";
575
+
576
+
regulator-state-mem {
577
+
regulator-off-in-suspend;
578
+
};
579
+
};
580
+
581
+
vcc_1v8_s3: dcdc-reg10 {
582
+
regulator-always-on;
583
+
regulator-boot-on;
584
+
regulator-min-microvolt = <1800000>;
585
+
regulator-max-microvolt = <1800000>;
586
+
regulator-name = "vcc_1v8_s3";
587
+
588
+
regulator-state-mem {
589
+
regulator-on-in-suspend;
590
+
regulator-suspend-microvolt = <1800000>;
591
+
};
592
+
};
593
+
594
+
avcc_1v8_s0: pldo-reg1 {
595
+
regulator-always-on;
596
+
regulator-boot-on;
597
+
regulator-min-microvolt = <1800000>;
598
+
regulator-max-microvolt = <1800000>;
599
+
regulator-name = "avcc_1v8_s0";
600
+
601
+
regulator-state-mem {
602
+
regulator-off-in-suspend;
603
+
regulator-suspend-microvolt = <1800000>;
604
+
};
605
+
};
606
+
607
+
vcc_1v8_s0: pldo-reg2 {
608
+
regulator-always-on;
609
+
regulator-boot-on;
610
+
regulator-min-microvolt = <1800000>;
611
+
regulator-max-microvolt = <1800000>;
612
+
regulator-name = "vcc_1v8_s0";
613
+
614
+
regulator-state-mem {
615
+
regulator-off-in-suspend;
616
+
regulator-suspend-microvolt = <1800000>;
617
+
};
618
+
};
619
+
620
+
avdd_1v2_s0: pldo-reg3 {
621
+
regulator-always-on;
622
+
regulator-boot-on;
623
+
regulator-min-microvolt = <1200000>;
624
+
regulator-max-microvolt = <1200000>;
625
+
regulator-name = "avdd_1v2_s0";
626
+
627
+
regulator-state-mem {
628
+
regulator-off-in-suspend;
629
+
};
630
+
};
631
+
632
+
avcc_3v3_s0: pldo-reg4 {
633
+
regulator-always-on;
634
+
regulator-boot-on;
635
+
regulator-min-microvolt = <3300000>;
636
+
regulator-max-microvolt = <3300000>;
637
+
regulator-ramp-delay = <12500>;
638
+
regulator-name = "avcc_3v3_s0";
639
+
640
+
regulator-state-mem {
641
+
regulator-off-in-suspend;
642
+
};
643
+
};
644
+
645
+
vccio_sd_s0: pldo-reg5 {
646
+
regulator-always-on;
647
+
regulator-boot-on;
648
+
regulator-min-microvolt = <1800000>;
649
+
regulator-max-microvolt = <3300000>;
650
+
regulator-ramp-delay = <12500>;
651
+
regulator-name = "vccio_sd_s0";
652
+
653
+
regulator-state-mem {
654
+
regulator-off-in-suspend;
655
+
};
656
+
};
657
+
658
+
pldo6_s3: pldo-reg6 {
659
+
regulator-always-on;
660
+
regulator-boot-on;
661
+
regulator-min-microvolt = <1800000>;
662
+
regulator-max-microvolt = <1800000>;
663
+
regulator-name = "pldo6_s3";
664
+
665
+
regulator-state-mem {
666
+
regulator-on-in-suspend;
667
+
regulator-suspend-microvolt = <1800000>;
668
+
};
669
+
};
670
+
671
+
vdd_0v75_s3: nldo-reg1 {
672
+
regulator-always-on;
673
+
regulator-boot-on;
674
+
regulator-min-microvolt = <750000>;
675
+
regulator-max-microvolt = <750000>;
676
+
regulator-name = "vdd_0v75_s3";
677
+
678
+
regulator-state-mem {
679
+
regulator-on-in-suspend;
680
+
regulator-suspend-microvolt = <750000>;
681
+
};
682
+
};
683
+
684
+
avdd_ddr_pll_s0: nldo-reg2 {
685
+
regulator-always-on;
686
+
regulator-boot-on;
687
+
regulator-min-microvolt = <850000>;
688
+
regulator-max-microvolt = <850000>;
689
+
regulator-name = "avdd_ddr_pll_s0";
690
+
691
+
regulator-state-mem {
692
+
regulator-off-in-suspend;
693
+
regulator-suspend-microvolt = <850000>;
694
+
};
695
+
};
696
+
697
+
avdd_0v75_s0: nldo-reg3 {
698
+
regulator-always-on;
699
+
regulator-boot-on;
700
+
regulator-min-microvolt = <750000>;
701
+
regulator-max-microvolt = <750000>;
702
+
regulator-name = "avdd_0v75_s0";
703
+
704
+
regulator-state-mem {
705
+
regulator-off-in-suspend;
706
+
};
707
+
};
708
+
709
+
avdd_0v85_s0: nldo-reg4 {
710
+
regulator-always-on;
711
+
regulator-boot-on;
712
+
regulator-min-microvolt = <850000>;
713
+
regulator-max-microvolt = <850000>;
714
+
regulator-name = "avdd_0v85_s0";
715
+
716
+
regulator-state-mem {
717
+
regulator-off-in-suspend;
718
+
};
719
+
};
720
+
721
+
vdd_0v75_s0: nldo-reg5 {
722
+
regulator-always-on;
723
+
regulator-boot-on;
724
+
regulator-min-microvolt = <750000>;
725
+
regulator-max-microvolt = <750000>;
726
+
regulator-name = "vdd_0v75_s0";
727
+
728
+
regulator-state-mem {
729
+
regulator-off-in-suspend;
730
+
};
731
+
};
732
+
};
733
+
};
734
+
};
735
+
736
+
&tsadc {
737
+
status = "okay";
738
+
};
739
+
740
+
&u2phy2 {
741
+
status = "okay";
742
+
};
743
+
744
+
&u2phy2_host {
745
+
phy-supply = <&vcc5v0_host_20>;
746
+
status = "okay";
747
+
};
748
+
749
+
&uart2 {
750
+
pinctrl-0 = <&uart2m0_xfer>;
751
+
status = "okay";
752
+
};
753
+
754
+
&usb_host0_ehci {
755
+
status = "okay";
756
+
};
757
+
758
+
&usb_host0_ohci {
759
+
status = "okay";
760
+
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
+3
-753
arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
+3
-753
arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
···
2
2
3
3
/dts-v1/;
4
4
5
-
#include <dt-bindings/pinctrl/rockchip.h>
6
-
#include <dt-bindings/gpio/gpio.h>
7
-
#include <dt-bindings/input/input.h>
8
-
#include "rk3588s.dtsi"
5
+
#include "rk3588s-nanopi-r6.dtsi"
9
6
10
7
/ {
11
8
model = "FriendlyElec NanoPi R6S";
12
9
compatible = "friendlyarm,nanopi-r6s", "rockchip,rk3588s";
13
-
14
-
aliases {
15
-
ethernet0 = &gmac1;
16
-
mmc0 = &sdmmc;
17
-
mmc1 = &sdhci;
18
-
};
19
-
20
-
chosen {
21
-
stdout-path = "serial2:1500000n8";
22
-
};
23
-
24
-
adc-keys {
25
-
compatible = "adc-keys";
26
-
io-channels = <&saradc 0>;
27
-
io-channel-names = "buttons";
28
-
keyup-threshold-microvolt = <1800000>;
29
-
poll-interval = <100>;
30
-
31
-
button-maskrom {
32
-
label = "Maskrom";
33
-
linux,code = <KEY_VENDOR>;
34
-
press-threshold-microvolt = <1800>;
35
-
};
36
-
};
37
-
38
-
gpio-keys {
39
-
compatible = "gpio-keys";
40
-
pinctrl-names = "default";
41
-
pinctrl-0 = <&key1_pin>;
42
-
43
-
button-user {
44
-
label = "User";
45
-
linux,code = <BTN_1>;
46
-
gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>;
47
-
debounce-interval = <50>;
48
-
};
49
-
};
50
-
51
-
leds {
52
-
compatible = "gpio-leds";
53
-
54
-
sys_led: led-0 {
55
-
label = "sys_led";
56
-
gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
57
-
linux,default-trigger = "heartbeat";
58
-
pinctrl-names = "default";
59
-
pinctrl-0 = <&sys_led_pin>;
60
-
};
61
-
62
-
wan_led: led-1 {
63
-
label = "wan_led";
64
-
gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
65
-
pinctrl-names = "default";
66
-
pinctrl-0 = <&wan_led_pin>;
67
-
};
68
-
69
-
lan1_led: led-2 {
70
-
label = "lan1_led";
71
-
gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
72
-
pinctrl-names = "default";
73
-
pinctrl-0 = <&lan1_led_pin>;
74
-
};
75
-
76
-
lan2_led: led-3 {
77
-
label = "lan2_led";
78
-
gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
79
-
pinctrl-names = "default";
80
-
pinctrl-0 = <&lan2_led_pin>;
81
-
};
82
-
};
83
-
84
-
vcc5v0_sys: vcc5v0-sys-regulator {
85
-
compatible = "regulator-fixed";
86
-
regulator-name = "vcc5v0_sys";
87
-
regulator-always-on;
88
-
regulator-boot-on;
89
-
regulator-min-microvolt = <5000000>;
90
-
regulator-max-microvolt = <5000000>;
91
-
};
92
-
93
-
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
94
-
compatible = "regulator-fixed";
95
-
regulator-name = "vcc_1v1_nldo_s3";
96
-
regulator-always-on;
97
-
regulator-boot-on;
98
-
regulator-min-microvolt = <1100000>;
99
-
regulator-max-microvolt = <1100000>;
100
-
vin-supply = <&vcc5v0_sys>;
101
-
};
102
-
103
-
vcc_3v3_s0: vcc-3v3-s0-regulator {
104
-
compatible = "regulator-fixed";
105
-
regulator-always-on;
106
-
regulator-boot-on;
107
-
regulator-min-microvolt = <3300000>;
108
-
regulator-max-microvolt = <3300000>;
109
-
regulator-name = "vcc_3v3_s0";
110
-
vin-supply = <&vcc_3v3_s3>;
111
-
};
112
-
113
-
vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
114
-
compatible = "regulator-fixed";
115
-
enable-active-high;
116
-
gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
117
-
pinctrl-names = "default";
118
-
pinctrl-0 = <&sd_s0_pwr>;
119
-
regulator-name = "vcc_3v3_sd_s0";
120
-
regulator-boot-on;
121
-
regulator-max-microvolt = <3000000>;
122
-
regulator-min-microvolt = <3000000>;
123
-
vin-supply = <&vcc_3v3_s3>;
124
-
};
125
-
126
-
vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
127
-
compatible = "regulator-fixed";
128
-
regulator-name = "vcc_3v3_pcie20";
129
-
regulator-always-on;
130
-
regulator-boot-on;
131
-
regulator-min-microvolt = <3300000>;
132
-
regulator-max-microvolt = <3300000>;
133
-
vin-supply = <&vcc_3v3_s3>;
134
-
};
135
-
136
-
vcc5v0_usb: vcc5v0-usb-regulator {
137
-
compatible = "regulator-fixed";
138
-
regulator-name = "vcc5v0_usb";
139
-
regulator-always-on;
140
-
regulator-boot-on;
141
-
regulator-min-microvolt = <5000000>;
142
-
regulator-max-microvolt = <5000000>;
143
-
vin-supply = <&vcc5v0_sys>;
144
-
};
145
-
146
-
vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator {
147
-
compatible = "regulator-fixed";
148
-
enable-active-high;
149
-
gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
150
-
pinctrl-names = "default";
151
-
pinctrl-0 = <&typec5v_pwren>;
152
-
regulator-name = "vcc5v0_usb_otg0";
153
-
regulator-min-microvolt = <5000000>;
154
-
regulator-max-microvolt = <5000000>;
155
-
vin-supply = <&vcc5v0_usb>;
156
-
};
157
-
158
-
vcc5v0_host_20: vcc5v0-host-20-regulator {
159
-
compatible = "regulator-fixed";
160
-
enable-active-high;
161
-
gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
162
-
pinctrl-names = "default";
163
-
pinctrl-0 = <&vcc5v0_host20_en>;
164
-
regulator-name = "vcc5v0_host_20";
165
-
regulator-min-microvolt = <5000000>;
166
-
regulator-max-microvolt = <5000000>;
167
-
vin-supply = <&vcc5v0_usb>;
168
-
};
169
10
};
170
11
171
-
&combphy0_ps {
172
-
status = "okay";
173
-
};
174
-
175
-
&combphy2_psu {
176
-
status = "okay";
177
-
};
178
-
179
-
&cpu_b0 {
180
-
cpu-supply = <&vdd_cpu_big0_s0>;
181
-
};
182
-
183
-
&cpu_b1 {
184
-
cpu-supply = <&vdd_cpu_big0_s0>;
185
-
};
186
-
187
-
&cpu_b2 {
188
-
cpu-supply = <&vdd_cpu_big1_s0>;
189
-
};
190
-
191
-
&cpu_b3 {
192
-
cpu-supply = <&vdd_cpu_big1_s0>;
193
-
};
194
-
195
-
&cpu_l0 {
196
-
cpu-supply = <&vdd_cpu_lit_s0>;
197
-
};
198
-
199
-
&cpu_l1 {
200
-
cpu-supply = <&vdd_cpu_lit_s0>;
201
-
};
202
-
203
-
&cpu_l2 {
204
-
cpu-supply = <&vdd_cpu_lit_s0>;
205
-
};
206
-
207
-
&cpu_l3 {
208
-
cpu-supply = <&vdd_cpu_lit_s0>;
209
-
};
210
-
211
-
&gmac1 {
212
-
clock_in_out = "output";
213
-
phy-handle = <&rgmii_phy1>;
214
-
phy-mode = "rgmii-rxid";
215
-
pinctrl-0 = <&gmac1_miim
216
-
&gmac1_tx_bus2
217
-
&gmac1_rx_bus2
218
-
&gmac1_rgmii_clk
219
-
&gmac1_rgmii_bus>;
220
-
pinctrl-names = "default";
221
-
tx_delay = <0x42>;
222
-
status = "okay";
223
-
};
224
-
225
-
&i2c0 {
226
-
pinctrl-names = "default";
227
-
pinctrl-0 = <&i2c0m2_xfer>;
228
-
status = "okay";
229
-
230
-
vdd_cpu_big0_s0: regulator@42 {
231
-
compatible = "rockchip,rk8602";
232
-
reg = <0x42>;
233
-
fcs,suspend-voltage-selector = <1>;
234
-
regulator-name = "vdd_cpu_big0_s0";
235
-
regulator-always-on;
236
-
regulator-boot-on;
237
-
regulator-min-microvolt = <550000>;
238
-
regulator-max-microvolt = <1050000>;
239
-
regulator-ramp-delay = <2300>;
240
-
vin-supply = <&vcc5v0_sys>;
241
-
242
-
regulator-state-mem {
243
-
regulator-off-in-suspend;
244
-
};
245
-
};
246
-
247
-
vdd_cpu_big1_s0: regulator@43 {
248
-
compatible = "rockchip,rk8603", "rockchip,rk8602";
249
-
reg = <0x43>;
250
-
fcs,suspend-voltage-selector = <1>;
251
-
regulator-name = "vdd_cpu_big1_s0";
252
-
regulator-always-on;
253
-
regulator-boot-on;
254
-
regulator-min-microvolt = <550000>;
255
-
regulator-max-microvolt = <1050000>;
256
-
regulator-ramp-delay = <2300>;
257
-
vin-supply = <&vcc5v0_sys>;
258
-
259
-
regulator-state-mem {
260
-
regulator-off-in-suspend;
261
-
};
262
-
};
263
-
};
264
-
265
-
&i2c2 {
266
-
status = "okay";
267
-
268
-
vdd_npu_s0: regulator@42 {
269
-
compatible = "rockchip,rk8602";
270
-
reg = <0x42>;
271
-
fcs,suspend-voltage-selector = <1>;
272
-
regulator-name = "vdd_npu_s0";
273
-
regulator-min-microvolt = <550000>;
274
-
regulator-max-microvolt = <950000>;
275
-
regulator-ramp-delay = <2300>;
276
-
regulator-boot-on;
277
-
regulator-always-on;
278
-
vin-supply = <&vcc5v0_sys>;
279
-
280
-
regulator-state-mem {
281
-
regulator-off-in-suspend;
282
-
};
283
-
};
284
-
};
285
-
286
-
&i2c6 {
287
-
clock-frequency = <200000>;
288
-
pinctrl-names = "default";
289
-
pinctrl-0 = <&i2c6m0_xfer>;
290
-
status = "okay";
291
-
292
-
hym8563: rtc@51 {
293
-
compatible = "haoyu,hym8563";
294
-
reg = <0x51>;
295
-
#clock-cells = <0>;
296
-
clock-output-names = "hym8563";
297
-
pinctrl-names = "default";
298
-
pinctrl-0 = <&rtc_int>;
299
-
interrupt-parent = <&gpio0>;
300
-
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
301
-
wakeup-source;
302
-
};
303
-
};
304
-
305
-
&mdio1 {
306
-
rgmii_phy1: ethernet-phy@1 {
307
-
compatible = "ethernet-phy-id001c.c916";
308
-
reg = <0x1>;
309
-
pinctrl-names = "default";
310
-
pinctrl-0 = <&rtl8211f_rst>;
311
-
reset-assert-us = <20000>;
312
-
reset-deassert-us = <100000>;
313
-
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
314
-
};
315
-
};
316
-
317
-
&pcie2x1l1 {
318
-
reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
319
-
vpcie3v3-supply = <&vcc_3v3_pcie20>;
320
-
status = "okay";
321
-
};
322
-
323
-
&pcie2x1l2 {
324
-
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
325
-
vpcie3v3-supply = <&vcc_3v3_pcie20>;
326
-
status = "okay";
327
-
};
328
-
329
-
&pinctrl {
330
-
gpio-key {
331
-
key1_pin: key1-pin {
332
-
rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
333
-
};
334
-
};
335
-
336
-
gpio-leds {
337
-
sys_led_pin: sys-led-pin {
338
-
rockchip,pins =
339
-
<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
340
-
};
341
-
342
-
wan_led_pin: wan-led-pin {
343
-
rockchip,pins =
344
-
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
345
-
};
346
-
347
-
lan1_led_pin: lan1-led-pin {
348
-
rockchip,pins =
349
-
<1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
350
-
};
351
-
352
-
lan2_led_pin: lan2-led-pin {
353
-
rockchip,pins =
354
-
<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
355
-
};
356
-
};
357
-
358
-
hym8563 {
359
-
rtc_int: rtc-int {
360
-
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
361
-
};
362
-
};
363
-
364
-
sdmmc {
365
-
sd_s0_pwr: sd-s0-pwr {
366
-
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
367
-
};
368
-
};
369
-
370
-
usb {
371
-
typec5v_pwren: typec5v-pwren {
372
-
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
373
-
};
374
-
375
-
vcc5v0_host20_en: vcc5v0-host20-en {
376
-
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
377
-
};
378
-
};
379
-
380
-
rtl8211f {
381
-
rtl8211f_rst: rtl8211f-rst {
382
-
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
383
-
};
384
-
};
385
-
};
386
-
387
-
&saradc {
388
-
vref-supply = <&avcc_1v8_s0>;
389
-
status = "okay";
390
-
};
391
-
392
-
&sdhci {
393
-
bus-width = <8>;
394
-
no-sdio;
395
-
no-sd;
396
-
non-removable;
397
-
mmc-hs200-1_8v;
398
-
status = "okay";
399
-
};
400
-
401
-
&sdmmc {
402
-
bus-width = <4>;
403
-
cap-sd-highspeed;
404
-
disable-wp;
405
-
max-frequency = <150000000>;
406
-
no-mmc;
407
-
no-sdio;
408
-
sd-uhs-sdr104;
409
-
vmmc-supply = <&vcc_3v3_sd_s0>;
410
-
vqmmc-supply = <&vccio_sd_s0>;
411
-
status = "okay";
412
-
};
413
-
414
-
&spi2 {
415
-
status = "okay";
416
-
assigned-clocks = <&cru CLK_SPI2>;
417
-
assigned-clock-rates = <200000000>;
418
-
pinctrl-names = "default";
419
-
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
420
-
num-cs = <1>;
421
-
422
-
pmic@0 {
423
-
compatible = "rockchip,rk806";
424
-
spi-max-frequency = <1000000>;
425
-
reg = <0x0>;
426
-
427
-
interrupt-parent = <&gpio0>;
428
-
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
429
-
430
-
pinctrl-names = "default";
431
-
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
432
-
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
433
-
434
-
system-power-controller;
435
-
436
-
vcc1-supply = <&vcc5v0_sys>;
437
-
vcc2-supply = <&vcc5v0_sys>;
438
-
vcc3-supply = <&vcc5v0_sys>;
439
-
vcc4-supply = <&vcc5v0_sys>;
440
-
vcc5-supply = <&vcc5v0_sys>;
441
-
vcc6-supply = <&vcc5v0_sys>;
442
-
vcc7-supply = <&vcc5v0_sys>;
443
-
vcc8-supply = <&vcc5v0_sys>;
444
-
vcc9-supply = <&vcc5v0_sys>;
445
-
vcc10-supply = <&vcc5v0_sys>;
446
-
vcc11-supply = <&vcc_2v0_pldo_s3>;
447
-
vcc12-supply = <&vcc5v0_sys>;
448
-
vcc13-supply = <&vcc_1v1_nldo_s3>;
449
-
vcc14-supply = <&vcc_1v1_nldo_s3>;
450
-
vcca-supply = <&vcc5v0_sys>;
451
-
452
-
gpio-controller;
453
-
#gpio-cells = <2>;
454
-
455
-
rk806_dvs1_null: dvs1-null-pins {
456
-
pins = "gpio_pwrctrl1";
457
-
function = "pin_fun0";
458
-
};
459
-
460
-
rk806_dvs2_null: dvs2-null-pins {
461
-
pins = "gpio_pwrctrl2";
462
-
function = "pin_fun0";
463
-
};
464
-
465
-
rk806_dvs3_null: dvs3-null-pins {
466
-
pins = "gpio_pwrctrl3";
467
-
function = "pin_fun0";
468
-
};
469
-
470
-
regulators {
471
-
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
472
-
regulator-boot-on;
473
-
regulator-min-microvolt = <550000>;
474
-
regulator-max-microvolt = <950000>;
475
-
regulator-ramp-delay = <12500>;
476
-
regulator-name = "vdd_gpu_s0";
477
-
regulator-enable-ramp-delay = <400>;
478
-
479
-
regulator-state-mem {
480
-
regulator-off-in-suspend;
481
-
};
482
-
};
483
-
484
-
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
485
-
regulator-always-on;
486
-
regulator-boot-on;
487
-
regulator-min-microvolt = <550000>;
488
-
regulator-max-microvolt = <950000>;
489
-
regulator-ramp-delay = <12500>;
490
-
regulator-name = "vdd_cpu_lit_s0";
491
-
492
-
regulator-state-mem {
493
-
regulator-off-in-suspend;
494
-
};
495
-
};
496
-
497
-
vdd_log_s0: dcdc-reg3 {
498
-
regulator-always-on;
499
-
regulator-boot-on;
500
-
regulator-min-microvolt = <675000>;
501
-
regulator-max-microvolt = <750000>;
502
-
regulator-ramp-delay = <12500>;
503
-
regulator-name = "vdd_log_s0";
504
-
505
-
regulator-state-mem {
506
-
regulator-off-in-suspend;
507
-
regulator-suspend-microvolt = <750000>;
508
-
};
509
-
};
510
-
511
-
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
512
-
regulator-always-on;
513
-
regulator-boot-on;
514
-
regulator-min-microvolt = <550000>;
515
-
regulator-max-microvolt = <950000>;
516
-
regulator-ramp-delay = <12500>;
517
-
regulator-name = "vdd_vdenc_s0";
518
-
519
-
regulator-state-mem {
520
-
regulator-off-in-suspend;
521
-
};
522
-
};
523
-
524
-
vdd_ddr_s0: dcdc-reg5 {
525
-
regulator-always-on;
526
-
regulator-boot-on;
527
-
regulator-min-microvolt = <675000>;
528
-
regulator-max-microvolt = <900000>;
529
-
regulator-ramp-delay = <12500>;
530
-
regulator-name = "vdd_ddr_s0";
531
-
532
-
regulator-state-mem {
533
-
regulator-off-in-suspend;
534
-
regulator-suspend-microvolt = <850000>;
535
-
};
536
-
};
537
-
538
-
vdd2_ddr_s3: dcdc-reg6 {
539
-
regulator-always-on;
540
-
regulator-boot-on;
541
-
regulator-name = "vdd2_ddr_s3";
542
-
543
-
regulator-state-mem {
544
-
regulator-on-in-suspend;
545
-
};
546
-
};
547
-
548
-
vcc_2v0_pldo_s3: dcdc-reg7 {
549
-
regulator-always-on;
550
-
regulator-boot-on;
551
-
regulator-min-microvolt = <2000000>;
552
-
regulator-max-microvolt = <2000000>;
553
-
regulator-ramp-delay = <12500>;
554
-
regulator-name = "vdd_2v0_pldo_s3";
555
-
556
-
regulator-state-mem {
557
-
regulator-on-in-suspend;
558
-
regulator-suspend-microvolt = <2000000>;
559
-
};
560
-
};
561
-
562
-
vcc_3v3_s3: dcdc-reg8 {
563
-
regulator-always-on;
564
-
regulator-boot-on;
565
-
regulator-min-microvolt = <3300000>;
566
-
regulator-max-microvolt = <3300000>;
567
-
regulator-name = "vcc_3v3_s3";
568
-
569
-
regulator-state-mem {
570
-
regulator-on-in-suspend;
571
-
regulator-suspend-microvolt = <3300000>;
572
-
};
573
-
};
574
-
575
-
vddq_ddr_s0: dcdc-reg9 {
576
-
regulator-always-on;
577
-
regulator-boot-on;
578
-
regulator-name = "vddq_ddr_s0";
579
-
580
-
regulator-state-mem {
581
-
regulator-off-in-suspend;
582
-
};
583
-
};
584
-
585
-
vcc_1v8_s3: dcdc-reg10 {
586
-
regulator-always-on;
587
-
regulator-boot-on;
588
-
regulator-min-microvolt = <1800000>;
589
-
regulator-max-microvolt = <1800000>;
590
-
regulator-name = "vcc_1v8_s3";
591
-
592
-
regulator-state-mem {
593
-
regulator-on-in-suspend;
594
-
regulator-suspend-microvolt = <1800000>;
595
-
};
596
-
};
597
-
598
-
avcc_1v8_s0: pldo-reg1 {
599
-
regulator-always-on;
600
-
regulator-boot-on;
601
-
regulator-min-microvolt = <1800000>;
602
-
regulator-max-microvolt = <1800000>;
603
-
regulator-name = "avcc_1v8_s0";
604
-
605
-
regulator-state-mem {
606
-
regulator-off-in-suspend;
607
-
regulator-suspend-microvolt = <1800000>;
608
-
};
609
-
};
610
-
611
-
vcc_1v8_s0: pldo-reg2 {
612
-
regulator-always-on;
613
-
regulator-boot-on;
614
-
regulator-min-microvolt = <1800000>;
615
-
regulator-max-microvolt = <1800000>;
616
-
regulator-name = "vcc_1v8_s0";
617
-
618
-
regulator-state-mem {
619
-
regulator-off-in-suspend;
620
-
regulator-suspend-microvolt = <1800000>;
621
-
};
622
-
};
623
-
624
-
avdd_1v2_s0: pldo-reg3 {
625
-
regulator-always-on;
626
-
regulator-boot-on;
627
-
regulator-min-microvolt = <1200000>;
628
-
regulator-max-microvolt = <1200000>;
629
-
regulator-name = "avdd_1v2_s0";
630
-
631
-
regulator-state-mem {
632
-
regulator-off-in-suspend;
633
-
};
634
-
};
635
-
636
-
avcc_3v3_s0: pldo-reg4 {
637
-
regulator-always-on;
638
-
regulator-boot-on;
639
-
regulator-min-microvolt = <3300000>;
640
-
regulator-max-microvolt = <3300000>;
641
-
regulator-ramp-delay = <12500>;
642
-
regulator-name = "avcc_3v3_s0";
643
-
644
-
regulator-state-mem {
645
-
regulator-off-in-suspend;
646
-
};
647
-
};
648
-
649
-
vccio_sd_s0: pldo-reg5 {
650
-
regulator-always-on;
651
-
regulator-boot-on;
652
-
regulator-min-microvolt = <1800000>;
653
-
regulator-max-microvolt = <3300000>;
654
-
regulator-ramp-delay = <12500>;
655
-
regulator-name = "vccio_sd_s0";
656
-
657
-
regulator-state-mem {
658
-
regulator-off-in-suspend;
659
-
};
660
-
};
661
-
662
-
pldo6_s3: pldo-reg6 {
663
-
regulator-always-on;
664
-
regulator-boot-on;
665
-
regulator-min-microvolt = <1800000>;
666
-
regulator-max-microvolt = <1800000>;
667
-
regulator-name = "pldo6_s3";
668
-
669
-
regulator-state-mem {
670
-
regulator-on-in-suspend;
671
-
regulator-suspend-microvolt = <1800000>;
672
-
};
673
-
};
674
-
675
-
vdd_0v75_s3: nldo-reg1 {
676
-
regulator-always-on;
677
-
regulator-boot-on;
678
-
regulator-min-microvolt = <750000>;
679
-
regulator-max-microvolt = <750000>;
680
-
regulator-name = "vdd_0v75_s3";
681
-
682
-
regulator-state-mem {
683
-
regulator-on-in-suspend;
684
-
regulator-suspend-microvolt = <750000>;
685
-
};
686
-
};
687
-
688
-
avdd_ddr_pll_s0: nldo-reg2 {
689
-
regulator-always-on;
690
-
regulator-boot-on;
691
-
regulator-min-microvolt = <850000>;
692
-
regulator-max-microvolt = <850000>;
693
-
regulator-name = "avdd_ddr_pll_s0";
694
-
695
-
regulator-state-mem {
696
-
regulator-off-in-suspend;
697
-
regulator-suspend-microvolt = <850000>;
698
-
};
699
-
};
700
-
701
-
avdd_0v75_s0: nldo-reg3 {
702
-
regulator-always-on;
703
-
regulator-boot-on;
704
-
regulator-min-microvolt = <750000>;
705
-
regulator-max-microvolt = <750000>;
706
-
regulator-name = "avdd_0v75_s0";
707
-
708
-
regulator-state-mem {
709
-
regulator-off-in-suspend;
710
-
};
711
-
};
712
-
713
-
avdd_0v85_s0: nldo-reg4 {
714
-
regulator-always-on;
715
-
regulator-boot-on;
716
-
regulator-min-microvolt = <850000>;
717
-
regulator-max-microvolt = <850000>;
718
-
regulator-name = "avdd_0v85_s0";
719
-
720
-
regulator-state-mem {
721
-
regulator-off-in-suspend;
722
-
};
723
-
};
724
-
725
-
vdd_0v75_s0: nldo-reg5 {
726
-
regulator-always-on;
727
-
regulator-boot-on;
728
-
regulator-min-microvolt = <750000>;
729
-
regulator-max-microvolt = <750000>;
730
-
regulator-name = "vdd_0v75_s0";
731
-
732
-
regulator-state-mem {
733
-
regulator-off-in-suspend;
734
-
};
735
-
};
736
-
};
737
-
};
738
-
};
739
-
740
-
&tsadc {
741
-
status = "okay";
742
-
};
743
-
744
-
&u2phy2 {
745
-
status = "okay";
746
-
};
747
-
748
-
&u2phy2_host {
749
-
phy-supply = <&vcc5v0_host_20>;
750
-
status = "okay";
751
-
};
752
-
753
-
&uart2 {
754
-
pinctrl-0 = <&uart2m0_xfer>;
755
-
status = "okay";
756
-
};
757
-
758
-
&usb_host0_ehci {
759
-
status = "okay";
760
-
};
761
-
762
-
&usb_host0_ohci {
763
-
status = "okay";
12
+
&lan2_led {
13
+
label = "lan2_led";
764
14
};
+1
-735
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
+1
-735
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
···
2
2
3
3
/dts-v1/;
4
4
5
-
#include <dt-bindings/gpio/gpio.h>
6
-
#include <dt-bindings/leds/common.h>
7
-
#include <dt-bindings/input/input.h>
8
-
#include <dt-bindings/pinctrl/rockchip.h>
9
-
#include <dt-bindings/usb/pd.h>
10
-
#include "rk3588s.dtsi"
5
+
#include "rk3588s-orangepi-5.dtsi"
11
6
12
7
/ {
13
8
model = "Xunlong Orange Pi 5";
14
9
compatible = "xunlong,orangepi-5", "rockchip,rk3588s";
15
-
16
-
aliases {
17
-
ethernet0 = &gmac1;
18
-
mmc0 = &sdmmc;
19
-
};
20
-
21
-
chosen {
22
-
stdout-path = "serial2:1500000n8";
23
-
};
24
-
25
-
adc-keys {
26
-
compatible = "adc-keys";
27
-
io-channels = <&saradc 1>;
28
-
io-channel-names = "buttons";
29
-
keyup-threshold-microvolt = <1800000>;
30
-
poll-interval = <100>;
31
-
32
-
button-recovery {
33
-
label = "Recovery";
34
-
linux,code = <KEY_VENDOR>;
35
-
press-threshold-microvolt = <1800>;
36
-
};
37
-
};
38
-
39
-
leds {
40
-
compatible = "gpio-leds";
41
-
pinctrl-names = "default";
42
-
pinctrl-0 = <&leds_gpio>;
43
-
44
-
led-1 {
45
-
gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
46
-
label = "status_led";
47
-
linux,default-trigger = "heartbeat";
48
-
};
49
-
};
50
-
51
-
vbus_typec: vbus-typec-regulator {
52
-
compatible = "regulator-fixed";
53
-
enable-active-high;
54
-
gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
55
-
pinctrl-names = "default";
56
-
pinctrl-0 = <&typec5v_pwren>;
57
-
regulator-name = "vbus_typec";
58
-
regulator-min-microvolt = <5000000>;
59
-
regulator-max-microvolt = <5000000>;
60
-
vin-supply = <&vcc5v0_sys>;
61
-
};
62
-
63
-
vcc5v0_sys: vcc5v0-sys-regulator {
64
-
compatible = "regulator-fixed";
65
-
regulator-name = "vcc5v0_sys";
66
-
regulator-always-on;
67
-
regulator-boot-on;
68
-
regulator-min-microvolt = <5000000>;
69
-
regulator-max-microvolt = <5000000>;
70
-
};
71
-
72
-
vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
73
-
compatible = "regulator-fixed";
74
-
enable-active-low;
75
-
gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
76
-
regulator-name = "vcc_3v3_sd_s0";
77
-
regulator-boot-on;
78
-
regulator-min-microvolt = <3300000>;
79
-
regulator-max-microvolt = <3300000>;
80
-
vin-supply = <&vcc_3v3_s3>;
81
-
};
82
10
83
11
vcc3v3_pcie20: vcc3v3-pcie20-regulator {
84
12
compatible = "regulator-fixed";
···
21
93
};
22
94
};
23
95
24
-
&combphy0_ps {
25
-
status = "okay";
26
-
};
27
-
28
-
&combphy2_psu {
29
-
status = "okay";
30
-
};
31
-
32
-
&cpu_b0 {
33
-
cpu-supply = <&vdd_cpu_big0_s0>;
34
-
};
35
-
36
-
&cpu_b1 {
37
-
cpu-supply = <&vdd_cpu_big0_s0>;
38
-
};
39
-
40
-
&cpu_b2 {
41
-
cpu-supply = <&vdd_cpu_big1_s0>;
42
-
};
43
-
44
-
&cpu_b3 {
45
-
cpu-supply = <&vdd_cpu_big1_s0>;
46
-
};
47
-
48
-
&cpu_l0 {
49
-
cpu-supply = <&vdd_cpu_lit_s0>;
50
-
};
51
-
52
-
&cpu_l1 {
53
-
cpu-supply = <&vdd_cpu_lit_s0>;
54
-
};
55
-
56
-
&cpu_l2 {
57
-
cpu-supply = <&vdd_cpu_lit_s0>;
58
-
};
59
-
60
-
&cpu_l3 {
61
-
cpu-supply = <&vdd_cpu_lit_s0>;
62
-
};
63
-
64
-
&gmac1 {
65
-
clock_in_out = "output";
66
-
phy-handle = <&rgmii_phy1>;
67
-
phy-mode = "rgmii-rxid";
68
-
pinctrl-0 = <&gmac1_miim
69
-
&gmac1_tx_bus2
70
-
&gmac1_rx_bus2
71
-
&gmac1_rgmii_clk
72
-
&gmac1_rgmii_bus>;
73
-
pinctrl-names = "default";
74
-
tx_delay = <0x42>;
75
-
status = "okay";
76
-
};
77
-
78
-
&gpu {
79
-
mali-supply = <&vdd_gpu_s0>;
80
-
status = "okay";
81
-
};
82
-
83
-
&i2c0 {
84
-
pinctrl-names = "default";
85
-
pinctrl-0 = <&i2c0m2_xfer>;
86
-
status = "okay";
87
-
88
-
vdd_cpu_big0_s0: regulator@42 {
89
-
compatible = "rockchip,rk8602";
90
-
reg = <0x42>;
91
-
fcs,suspend-voltage-selector = <1>;
92
-
regulator-name = "vdd_cpu_big0_s0";
93
-
regulator-always-on;
94
-
regulator-boot-on;
95
-
regulator-min-microvolt = <550000>;
96
-
regulator-max-microvolt = <1050000>;
97
-
regulator-ramp-delay = <2300>;
98
-
vin-supply = <&vcc5v0_sys>;
99
-
100
-
regulator-state-mem {
101
-
regulator-off-in-suspend;
102
-
};
103
-
};
104
-
105
-
vdd_cpu_big1_s0: regulator@43 {
106
-
compatible = "rockchip,rk8603", "rockchip,rk8602";
107
-
reg = <0x43>;
108
-
fcs,suspend-voltage-selector = <1>;
109
-
regulator-name = "vdd_cpu_big1_s0";
110
-
regulator-always-on;
111
-
regulator-boot-on;
112
-
regulator-min-microvolt = <550000>;
113
-
regulator-max-microvolt = <1050000>;
114
-
regulator-ramp-delay = <2300>;
115
-
vin-supply = <&vcc5v0_sys>;
116
-
117
-
regulator-state-mem {
118
-
regulator-off-in-suspend;
119
-
};
120
-
};
121
-
};
122
-
123
-
&i2c2 {
124
-
status = "okay";
125
-
126
-
vdd_npu_s0: regulator@42 {
127
-
compatible = "rockchip,rk8602";
128
-
reg = <0x42>;
129
-
fcs,suspend-voltage-selector = <1>;
130
-
regulator-name = "vdd_npu_s0";
131
-
regulator-always-on;
132
-
regulator-boot-on;
133
-
regulator-min-microvolt = <550000>;
134
-
regulator-max-microvolt = <950000>;
135
-
regulator-ramp-delay = <2300>;
136
-
vin-supply = <&vcc5v0_sys>;
137
-
138
-
regulator-state-mem {
139
-
regulator-off-in-suspend;
140
-
};
141
-
};
142
-
};
143
-
144
-
&i2c6 {
145
-
pinctrl-names = "default";
146
-
pinctrl-0 = <&i2c6m3_xfer>;
147
-
status = "okay";
148
-
149
-
usbc0: usb-typec@22 {
150
-
compatible = "fcs,fusb302";
151
-
reg = <0x22>;
152
-
interrupt-parent = <&gpio0>;
153
-
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
154
-
pinctrl-names = "default";
155
-
pinctrl-0 = <&usbc0_int>;
156
-
vbus-supply = <&vbus_typec>;
157
-
status = "okay";
158
-
159
-
usb_con: connector {
160
-
compatible = "usb-c-connector";
161
-
label = "USB-C";
162
-
data-role = "dual";
163
-
op-sink-microwatt = <1000000>;
164
-
power-role = "dual";
165
-
sink-pdos =
166
-
<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
167
-
source-pdos =
168
-
<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
169
-
try-power-role = "source";
170
-
171
-
ports {
172
-
#address-cells = <1>;
173
-
#size-cells = <0>;
174
-
175
-
port@0 {
176
-
reg = <0>;
177
-
usbc0_hs: endpoint {
178
-
remote-endpoint = <&usb_host0_xhci_drd_sw>;
179
-
};
180
-
};
181
-
182
-
port@1 {
183
-
reg = <1>;
184
-
usbc0_ss: endpoint {
185
-
remote-endpoint = <&usbdp_phy0_typec_ss>;
186
-
};
187
-
};
188
-
189
-
port@2 {
190
-
reg = <2>;
191
-
usbc0_sbu: endpoint {
192
-
remote-endpoint = <&usbdp_phy0_typec_sbu>;
193
-
};
194
-
};
195
-
};
196
-
};
197
-
};
198
-
199
-
hym8563: rtc@51 {
200
-
compatible = "haoyu,hym8563";
201
-
reg = <0x51>;
202
-
#clock-cells = <0>;
203
-
clock-output-names = "hym8563";
204
-
pinctrl-names = "default";
205
-
pinctrl-0 = <&hym8563_int>;
206
-
interrupt-parent = <&gpio0>;
207
-
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
208
-
wakeup-source;
209
-
};
210
-
};
211
-
212
-
&mdio1 {
213
-
rgmii_phy1: ethernet-phy@1 {
214
-
compatible = "ethernet-phy-ieee802.3-c22";
215
-
reg = <0x1>;
216
-
reset-assert-us = <20000>;
217
-
reset-deassert-us = <100000>;
218
-
reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
219
-
};
220
-
};
221
-
222
96
&pcie2x1l2 {
223
97
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
224
98
vpcie3v3-supply = <&vcc3v3_pcie20>;
225
99
status = "okay";
226
100
};
227
101
228
-
&pinctrl {
229
-
gpio-func {
230
-
leds_gpio: leds-gpio {
231
-
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
232
-
};
233
-
};
234
-
235
-
hym8563 {
236
-
hym8563_int: hym8563-int {
237
-
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
238
-
};
239
-
};
240
-
241
-
usb-typec {
242
-
usbc0_int: usbc0-int {
243
-
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
244
-
};
245
-
246
-
typec5v_pwren: typec5v-pwren {
247
-
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
248
-
};
249
-
};
250
-
};
251
-
252
-
&saradc {
253
-
vref-supply = <&avcc_1v8_s0>;
254
-
status = "okay";
255
-
};
256
-
257
-
&sdmmc {
258
-
bus-width = <4>;
259
-
cap-sd-highspeed;
260
-
disable-wp;
261
-
max-frequency = <150000000>;
262
-
no-mmc;
263
-
no-sdio;
264
-
sd-uhs-sdr104;
265
-
vmmc-supply = <&vcc_3v3_sd_s0>;
266
-
vqmmc-supply = <&vccio_sd_s0>;
267
-
status = "okay";
268
-
};
269
-
270
102
&sfc {
271
-
pinctrl-names = "default";
272
-
pinctrl-0 = <&fspim0_pins>;
273
-
status = "okay";
274
-
275
-
flash@0 {
276
-
compatible = "jedec,spi-nor";
277
-
reg = <0x0>;
278
-
spi-max-frequency = <100000000>;
279
-
spi-rx-bus-width = <4>;
280
-
spi-tx-bus-width = <1>;
281
-
};
282
-
};
283
-
284
-
&spi2 {
285
-
status = "okay";
286
-
assigned-clocks = <&cru CLK_SPI2>;
287
-
assigned-clock-rates = <200000000>;
288
-
num-cs = <1>;
289
-
pinctrl-names = "default";
290
-
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
291
-
292
-
pmic@0 {
293
-
compatible = "rockchip,rk806";
294
-
reg = <0x0>;
295
-
interrupt-parent = <&gpio0>;
296
-
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
297
-
pinctrl-names = "default";
298
-
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
299
-
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
300
-
spi-max-frequency = <1000000>;
301
-
system-power-controller;
302
-
303
-
vcc1-supply = <&vcc5v0_sys>;
304
-
vcc2-supply = <&vcc5v0_sys>;
305
-
vcc3-supply = <&vcc5v0_sys>;
306
-
vcc4-supply = <&vcc5v0_sys>;
307
-
vcc5-supply = <&vcc5v0_sys>;
308
-
vcc6-supply = <&vcc5v0_sys>;
309
-
vcc7-supply = <&vcc5v0_sys>;
310
-
vcc8-supply = <&vcc5v0_sys>;
311
-
vcc9-supply = <&vcc5v0_sys>;
312
-
vcc10-supply = <&vcc5v0_sys>;
313
-
vcc11-supply = <&vcc_2v0_pldo_s3>;
314
-
vcc12-supply = <&vcc5v0_sys>;
315
-
vcc13-supply = <&vcc_1v1_nldo_s3>;
316
-
vcc14-supply = <&vcc_1v1_nldo_s3>;
317
-
vcca-supply = <&vcc5v0_sys>;
318
-
319
-
gpio-controller;
320
-
#gpio-cells = <2>;
321
-
322
-
rk806_dvs1_null: dvs1-null-pins {
323
-
pins = "gpio_pwrctrl1";
324
-
function = "pin_fun0";
325
-
};
326
-
327
-
rk806_dvs2_null: dvs2-null-pins {
328
-
pins = "gpio_pwrctrl2";
329
-
function = "pin_fun0";
330
-
};
331
-
332
-
rk806_dvs3_null: dvs3-null-pins {
333
-
pins = "gpio_pwrctrl3";
334
-
function = "pin_fun0";
335
-
};
336
-
337
-
regulators {
338
-
vdd_gpu_s0: dcdc-reg1 {
339
-
regulator-name = "vdd_gpu_s0";
340
-
regulator-boot-on;
341
-
regulator-min-microvolt = <550000>;
342
-
regulator-max-microvolt = <950000>;
343
-
regulator-ramp-delay = <12500>;
344
-
regulator-enable-ramp-delay = <400>;
345
-
346
-
regulator-state-mem {
347
-
regulator-off-in-suspend;
348
-
};
349
-
};
350
-
351
-
vdd_cpu_lit_s0: dcdc-reg2 {
352
-
regulator-name = "vdd_cpu_lit_s0";
353
-
regulator-always-on;
354
-
regulator-boot-on;
355
-
regulator-min-microvolt = <550000>;
356
-
regulator-max-microvolt = <950000>;
357
-
regulator-ramp-delay = <12500>;
358
-
359
-
regulator-state-mem {
360
-
regulator-off-in-suspend;
361
-
};
362
-
};
363
-
364
-
vdd_log_s0: dcdc-reg3 {
365
-
regulator-name = "vdd_log_s0";
366
-
regulator-always-on;
367
-
regulator-boot-on;
368
-
regulator-min-microvolt = <675000>;
369
-
regulator-max-microvolt = <750000>;
370
-
regulator-ramp-delay = <12500>;
371
-
372
-
regulator-state-mem {
373
-
regulator-off-in-suspend;
374
-
regulator-suspend-microvolt = <750000>;
375
-
};
376
-
};
377
-
378
-
vdd_vdenc_s0: dcdc-reg4 {
379
-
regulator-name = "vdd_vdenc_s0";
380
-
regulator-always-on;
381
-
regulator-boot-on;
382
-
regulator-min-microvolt = <550000>;
383
-
regulator-max-microvolt = <950000>;
384
-
regulator-ramp-delay = <12500>;
385
-
386
-
regulator-state-mem {
387
-
regulator-off-in-suspend;
388
-
};
389
-
};
390
-
391
-
vdd_ddr_s0: dcdc-reg5 {
392
-
regulator-name = "vdd_ddr_s0";
393
-
regulator-always-on;
394
-
regulator-boot-on;
395
-
regulator-min-microvolt = <675000>;
396
-
regulator-max-microvolt = <900000>;
397
-
regulator-ramp-delay = <12500>;
398
-
399
-
regulator-state-mem {
400
-
regulator-off-in-suspend;
401
-
regulator-suspend-microvolt = <850000>;
402
-
};
403
-
};
404
-
405
-
vcc_1v1_nldo_s3: vdd2_ddr_s3: dcdc-reg6 {
406
-
regulator-name = "vdd2_ddr_s3";
407
-
regulator-always-on;
408
-
regulator-boot-on;
409
-
regulator-max-microvolt = <1100000>;
410
-
regulator-min-microvolt = <1100000>;
411
-
412
-
regulator-state-mem {
413
-
regulator-on-in-suspend;
414
-
};
415
-
};
416
-
417
-
vcc_2v0_pldo_s3: dcdc-reg7 {
418
-
regulator-name = "vdd_2v0_pldo_s3";
419
-
regulator-always-on;
420
-
regulator-boot-on;
421
-
regulator-min-microvolt = <2000000>;
422
-
regulator-max-microvolt = <2000000>;
423
-
regulator-ramp-delay = <12500>;
424
-
425
-
regulator-state-mem {
426
-
regulator-on-in-suspend;
427
-
regulator-suspend-microvolt = <2000000>;
428
-
};
429
-
};
430
-
431
-
vcc_3v3_s3: dcdc-reg8 {
432
-
regulator-name = "vcc_3v3_s3";
433
-
regulator-always-on;
434
-
regulator-boot-on;
435
-
regulator-min-microvolt = <3300000>;
436
-
regulator-max-microvolt = <3300000>;
437
-
438
-
regulator-state-mem {
439
-
regulator-on-in-suspend;
440
-
regulator-suspend-microvolt = <3300000>;
441
-
};
442
-
};
443
-
444
-
vddq_ddr_s0: dcdc-reg9 {
445
-
regulator-name = "vddq_ddr_s0";
446
-
regulator-always-on;
447
-
regulator-boot-on;
448
-
449
-
regulator-state-mem {
450
-
regulator-off-in-suspend;
451
-
};
452
-
};
453
-
454
-
vcc_1v8_s3: dcdc-reg10 {
455
-
regulator-name = "vcc_1v8_s3";
456
-
regulator-always-on;
457
-
regulator-boot-on;
458
-
regulator-min-microvolt = <1800000>;
459
-
regulator-max-microvolt = <1800000>;
460
-
461
-
regulator-state-mem {
462
-
regulator-on-in-suspend;
463
-
regulator-suspend-microvolt = <1800000>;
464
-
};
465
-
};
466
-
467
-
avcc_1v8_s0: pldo-reg1 {
468
-
regulator-name = "avcc_1v8_s0";
469
-
regulator-always-on;
470
-
regulator-boot-on;
471
-
regulator-min-microvolt = <1800000>;
472
-
regulator-max-microvolt = <1800000>;
473
-
474
-
regulator-state-mem {
475
-
regulator-off-in-suspend;
476
-
};
477
-
};
478
-
479
-
vcc_1v8_s0: pldo-reg2 {
480
-
regulator-name = "vcc_1v8_s0";
481
-
regulator-always-on;
482
-
regulator-boot-on;
483
-
regulator-min-microvolt = <1800000>;
484
-
regulator-max-microvolt = <1800000>;
485
-
486
-
regulator-state-mem {
487
-
regulator-off-in-suspend;
488
-
regulator-suspend-microvolt = <1800000>;
489
-
};
490
-
};
491
-
492
-
avdd_1v2_s0: pldo-reg3 {
493
-
regulator-name = "avdd_1v2_s0";
494
-
regulator-always-on;
495
-
regulator-boot-on;
496
-
regulator-min-microvolt = <1200000>;
497
-
regulator-max-microvolt = <1200000>;
498
-
499
-
regulator-state-mem {
500
-
regulator-off-in-suspend;
501
-
};
502
-
};
503
-
504
-
vcc_3v3_s0: pldo-reg4 {
505
-
regulator-name = "vcc_3v3_s0";
506
-
regulator-always-on;
507
-
regulator-boot-on;
508
-
regulator-min-microvolt = <3300000>;
509
-
regulator-max-microvolt = <3300000>;
510
-
regulator-ramp-delay = <12500>;
511
-
512
-
regulator-state-mem {
513
-
regulator-off-in-suspend;
514
-
};
515
-
};
516
-
517
-
vccio_sd_s0: pldo-reg5 {
518
-
regulator-name = "vccio_sd_s0";
519
-
regulator-always-on;
520
-
regulator-boot-on;
521
-
regulator-min-microvolt = <1800000>;
522
-
regulator-max-microvolt = <3300000>;
523
-
regulator-ramp-delay = <12500>;
524
-
525
-
regulator-state-mem {
526
-
regulator-off-in-suspend;
527
-
};
528
-
};
529
-
530
-
pldo6_s3: pldo-reg6 {
531
-
regulator-name = "pldo6_s3";
532
-
regulator-always-on;
533
-
regulator-boot-on;
534
-
regulator-min-microvolt = <1800000>;
535
-
regulator-max-microvolt = <1800000>;
536
-
537
-
regulator-state-mem {
538
-
regulator-on-in-suspend;
539
-
regulator-suspend-microvolt = <1800000>;
540
-
};
541
-
};
542
-
543
-
vdd_0v75_s3: nldo-reg1 {
544
-
regulator-name = "vdd_0v75_s3";
545
-
regulator-always-on;
546
-
regulator-boot-on;
547
-
regulator-min-microvolt = <750000>;
548
-
regulator-max-microvolt = <750000>;
549
-
550
-
regulator-state-mem {
551
-
regulator-on-in-suspend;
552
-
regulator-suspend-microvolt = <750000>;
553
-
};
554
-
};
555
-
556
-
vdd_ddr_pll_s0: nldo-reg2 {
557
-
regulator-name = "vdd_ddr_pll_s0";
558
-
regulator-always-on;
559
-
regulator-boot-on;
560
-
regulator-min-microvolt = <850000>;
561
-
regulator-max-microvolt = <850000>;
562
-
563
-
regulator-state-mem {
564
-
regulator-off-in-suspend;
565
-
regulator-suspend-microvolt = <850000>;
566
-
};
567
-
};
568
-
569
-
avdd_0v75_s0: nldo-reg3 {
570
-
regulator-name = "avdd_0v75_s0";
571
-
regulator-always-on;
572
-
regulator-boot-on;
573
-
regulator-min-microvolt = <750000>;
574
-
regulator-max-microvolt = <750000>;
575
-
576
-
regulator-state-mem {
577
-
regulator-off-in-suspend;
578
-
};
579
-
};
580
-
581
-
vdd_0v85_s0: nldo-reg4 {
582
-
regulator-name = "vdd_0v85_s0";
583
-
regulator-always-on;
584
-
regulator-boot-on;
585
-
regulator-min-microvolt = <850000>;
586
-
regulator-max-microvolt = <850000>;
587
-
588
-
regulator-state-mem {
589
-
regulator-off-in-suspend;
590
-
};
591
-
};
592
-
593
-
vdd_0v75_s0: nldo-reg5 {
594
-
regulator-name = "vdd_0v75_s0";
595
-
regulator-always-on;
596
-
regulator-boot-on;
597
-
regulator-min-microvolt = <750000>;
598
-
regulator-max-microvolt = <750000>;
599
-
600
-
regulator-state-mem {
601
-
regulator-off-in-suspend;
602
-
};
603
-
};
604
-
};
605
-
};
606
-
};
607
-
608
-
&tsadc {
609
-
status = "okay";
610
-
};
611
-
612
-
&u2phy0 {
613
-
status = "okay";
614
-
};
615
-
616
-
&u2phy0_otg {
617
-
status = "okay";
618
-
};
619
-
620
-
&u2phy2 {
621
-
status = "okay";
622
-
};
623
-
624
-
&u2phy2_host {
625
-
status = "okay";
626
-
};
627
-
628
-
&u2phy3 {
629
-
status = "okay";
630
-
};
631
-
632
-
&u2phy3_host {
633
-
status = "okay";
634
-
};
635
-
636
-
&uart2 {
637
-
pinctrl-0 = <&uart2m0_xfer>;
638
-
status = "okay";
639
-
};
640
-
641
-
&usbdp_phy0 {
642
-
mode-switch;
643
-
orientation-switch;
644
-
sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
645
-
sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
646
-
status = "okay";
647
-
648
-
port {
649
-
#address-cells = <1>;
650
-
#size-cells = <0>;
651
-
652
-
usbdp_phy0_typec_ss: endpoint@0 {
653
-
reg = <0>;
654
-
remote-endpoint = <&usbc0_ss>;
655
-
};
656
-
657
-
usbdp_phy0_typec_sbu: endpoint@1 {
658
-
reg = <1>;
659
-
remote-endpoint = <&usbc0_sbu>;
660
-
};
661
-
};
662
-
};
663
-
664
-
&usb_host0_ehci {
665
-
status = "okay";
666
-
};
667
-
668
-
&usb_host0_ohci {
669
-
status = "okay";
670
-
};
671
-
672
-
&usb_host0_xhci {
673
-
dr_mode = "otg";
674
-
usb-role-switch;
675
-
status = "okay";
676
-
677
-
port {
678
-
usb_host0_xhci_drd_sw: endpoint {
679
-
remote-endpoint = <&usbc0_hs>;
680
-
};
681
-
};
682
-
};
683
-
684
-
&usb_host1_ehci {
685
-
status = "okay";
686
-
};
687
-
688
-
&usb_host1_ohci {
689
-
status = "okay";
690
-
};
691
-
692
-
&usb_host2_xhci {
693
103
status = "okay";
694
104
};
+866
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi
+866
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
3
+
/dts-v1/;
4
+
5
+
#include <dt-bindings/gpio/gpio.h>
6
+
#include <dt-bindings/leds/common.h>
7
+
#include <dt-bindings/input/input.h>
8
+
#include <dt-bindings/pinctrl/rockchip.h>
9
+
#include <dt-bindings/soc/rockchip,vop2.h>
10
+
#include <dt-bindings/usb/pd.h>
11
+
#include "rk3588s.dtsi"
12
+
13
+
/ {
14
+
aliases {
15
+
ethernet0 = &gmac1;
16
+
mmc0 = &sdmmc;
17
+
};
18
+
19
+
chosen {
20
+
stdout-path = "serial2:1500000n8";
21
+
};
22
+
23
+
adc-keys {
24
+
compatible = "adc-keys";
25
+
io-channels = <&saradc 1>;
26
+
io-channel-names = "buttons";
27
+
keyup-threshold-microvolt = <1800000>;
28
+
poll-interval = <100>;
29
+
30
+
button-recovery {
31
+
label = "Recovery";
32
+
linux,code = <KEY_VENDOR>;
33
+
press-threshold-microvolt = <1800>;
34
+
};
35
+
};
36
+
37
+
analog-sound {
38
+
compatible = "simple-audio-card";
39
+
pinctrl-names = "default";
40
+
pinctrl-0 = <&hp_detect>;
41
+
simple-audio-card,name = "rockchip,es8388";
42
+
simple-audio-card,bitclock-master = <&masterdai>;
43
+
simple-audio-card,format = "i2s";
44
+
simple-audio-card,frame-master = <&masterdai>;
45
+
simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
46
+
simple-audio-card,mclk-fs = <256>;
47
+
simple-audio-card,pin-switches = "Headphones";
48
+
simple-audio-card,routing =
49
+
"Headphones", "LOUT1",
50
+
"Headphones", "ROUT1",
51
+
"LINPUT1", "Microphone Jack",
52
+
"RINPUT1", "Microphone Jack",
53
+
"LINPUT2", "Onboard Microphone",
54
+
"RINPUT2", "Onboard Microphone";
55
+
simple-audio-card,widgets =
56
+
"Microphone", "Microphone Jack",
57
+
"Microphone", "Onboard Microphone",
58
+
"Headphone", "Headphones";
59
+
60
+
simple-audio-card,cpu {
61
+
sound-dai = <&i2s1_8ch>;
62
+
};
63
+
64
+
masterdai: simple-audio-card,codec {
65
+
sound-dai = <&es8388>;
66
+
system-clock-frequency = <12288000>;
67
+
};
68
+
};
69
+
70
+
hdmi0-con {
71
+
compatible = "hdmi-connector";
72
+
type = "a";
73
+
74
+
port {
75
+
hdmi0_con_in: endpoint {
76
+
remote-endpoint = <&hdmi0_out_con>;
77
+
};
78
+
};
79
+
};
80
+
81
+
pwm-leds {
82
+
compatible = "pwm-leds";
83
+
84
+
led {
85
+
color = <LED_COLOR_ID_GREEN>;
86
+
function = LED_FUNCTION_STATUS;
87
+
linux,default-trigger = "heartbeat";
88
+
max-brightness = <255>;
89
+
pwms = <&pwm0 0 25000 0>;
90
+
};
91
+
};
92
+
93
+
vbus_typec: vbus-typec-regulator {
94
+
compatible = "regulator-fixed";
95
+
enable-active-high;
96
+
gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
97
+
pinctrl-names = "default";
98
+
pinctrl-0 = <&typec5v_pwren>;
99
+
regulator-name = "vbus_typec";
100
+
regulator-min-microvolt = <5000000>;
101
+
regulator-max-microvolt = <5000000>;
102
+
vin-supply = <&vcc5v0_sys>;
103
+
};
104
+
105
+
vcc5v0_sys: vcc5v0-sys-regulator {
106
+
compatible = "regulator-fixed";
107
+
regulator-name = "vcc5v0_sys";
108
+
regulator-always-on;
109
+
regulator-boot-on;
110
+
regulator-min-microvolt = <5000000>;
111
+
regulator-max-microvolt = <5000000>;
112
+
};
113
+
114
+
vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
115
+
compatible = "regulator-fixed";
116
+
gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
117
+
regulator-name = "vcc_3v3_sd_s0";
118
+
regulator-boot-on;
119
+
regulator-min-microvolt = <3300000>;
120
+
regulator-max-microvolt = <3300000>;
121
+
vin-supply = <&vcc_3v3_s3>;
122
+
};
123
+
};
124
+
125
+
&combphy0_ps {
126
+
status = "okay";
127
+
};
128
+
129
+
&combphy2_psu {
130
+
status = "okay";
131
+
};
132
+
133
+
&cpu_b0 {
134
+
cpu-supply = <&vdd_cpu_big0_s0>;
135
+
};
136
+
137
+
&cpu_b1 {
138
+
cpu-supply = <&vdd_cpu_big0_s0>;
139
+
};
140
+
141
+
&cpu_b2 {
142
+
cpu-supply = <&vdd_cpu_big1_s0>;
143
+
};
144
+
145
+
&cpu_b3 {
146
+
cpu-supply = <&vdd_cpu_big1_s0>;
147
+
};
148
+
149
+
&cpu_l0 {
150
+
cpu-supply = <&vdd_cpu_lit_s0>;
151
+
};
152
+
153
+
&cpu_l1 {
154
+
cpu-supply = <&vdd_cpu_lit_s0>;
155
+
};
156
+
157
+
&cpu_l2 {
158
+
cpu-supply = <&vdd_cpu_lit_s0>;
159
+
};
160
+
161
+
&cpu_l3 {
162
+
cpu-supply = <&vdd_cpu_lit_s0>;
163
+
};
164
+
165
+
&gmac1 {
166
+
clock_in_out = "output";
167
+
phy-handle = <&rgmii_phy1>;
168
+
phy-mode = "rgmii-rxid";
169
+
pinctrl-0 = <&gmac1_miim
170
+
&gmac1_tx_bus2
171
+
&gmac1_rx_bus2
172
+
&gmac1_rgmii_clk
173
+
&gmac1_rgmii_bus>;
174
+
pinctrl-names = "default";
175
+
tx_delay = <0x42>;
176
+
status = "okay";
177
+
};
178
+
179
+
&gpu {
180
+
mali-supply = <&vdd_gpu_s0>;
181
+
status = "okay";
182
+
};
183
+
184
+
&hdmi0 {
185
+
status = "okay";
186
+
};
187
+
188
+
&hdmi0_in {
189
+
hdmi0_in_vp0: endpoint {
190
+
remote-endpoint = <&vp0_out_hdmi0>;
191
+
};
192
+
};
193
+
194
+
&hdmi0_out {
195
+
hdmi0_out_con: endpoint {
196
+
remote-endpoint = <&hdmi0_con_in>;
197
+
};
198
+
};
199
+
200
+
&hdptxphy_hdmi0 {
201
+
status = "okay";
202
+
};
203
+
204
+
&i2c0 {
205
+
pinctrl-names = "default";
206
+
pinctrl-0 = <&i2c0m2_xfer>;
207
+
status = "okay";
208
+
209
+
vdd_cpu_big0_s0: regulator@42 {
210
+
compatible = "rockchip,rk8602";
211
+
reg = <0x42>;
212
+
fcs,suspend-voltage-selector = <1>;
213
+
regulator-name = "vdd_cpu_big0_s0";
214
+
regulator-always-on;
215
+
regulator-boot-on;
216
+
regulator-min-microvolt = <550000>;
217
+
regulator-max-microvolt = <1050000>;
218
+
regulator-ramp-delay = <2300>;
219
+
vin-supply = <&vcc5v0_sys>;
220
+
221
+
regulator-state-mem {
222
+
regulator-off-in-suspend;
223
+
};
224
+
};
225
+
226
+
vdd_cpu_big1_s0: regulator@43 {
227
+
compatible = "rockchip,rk8603", "rockchip,rk8602";
228
+
reg = <0x43>;
229
+
fcs,suspend-voltage-selector = <1>;
230
+
regulator-name = "vdd_cpu_big1_s0";
231
+
regulator-always-on;
232
+
regulator-boot-on;
233
+
regulator-min-microvolt = <550000>;
234
+
regulator-max-microvolt = <1050000>;
235
+
regulator-ramp-delay = <2300>;
236
+
vin-supply = <&vcc5v0_sys>;
237
+
238
+
regulator-state-mem {
239
+
regulator-off-in-suspend;
240
+
};
241
+
};
242
+
};
243
+
244
+
&i2c2 {
245
+
status = "okay";
246
+
247
+
vdd_npu_s0: regulator@42 {
248
+
compatible = "rockchip,rk8602";
249
+
reg = <0x42>;
250
+
fcs,suspend-voltage-selector = <1>;
251
+
regulator-name = "vdd_npu_s0";
252
+
regulator-always-on;
253
+
regulator-boot-on;
254
+
regulator-min-microvolt = <550000>;
255
+
regulator-max-microvolt = <950000>;
256
+
regulator-ramp-delay = <2300>;
257
+
vin-supply = <&vcc5v0_sys>;
258
+
259
+
regulator-state-mem {
260
+
regulator-off-in-suspend;
261
+
};
262
+
};
263
+
};
264
+
265
+
&i2c6 {
266
+
pinctrl-names = "default";
267
+
pinctrl-0 = <&i2c6m3_xfer>;
268
+
status = "okay";
269
+
270
+
es8388: audio-codec@10 {
271
+
compatible = "everest,es8388";
272
+
reg = <0x10>;
273
+
clocks = <&cru I2S1_8CH_MCLKOUT>;
274
+
AVDD-supply = <&vcc_3v3_s0>;
275
+
DVDD-supply = <&vcc_1v8_s0>;
276
+
HPVDD-supply = <&vcc_3v3_s0>;
277
+
PVDD-supply = <&vcc_3v3_s0>;
278
+
assigned-clocks = <&cru I2S1_8CH_MCLKOUT>;
279
+
assigned-clock-rates = <12288000>;
280
+
#sound-dai-cells = <0>;
281
+
};
282
+
283
+
usbc0: usb-typec@22 {
284
+
compatible = "fcs,fusb302";
285
+
reg = <0x22>;
286
+
interrupt-parent = <&gpio0>;
287
+
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
288
+
pinctrl-names = "default";
289
+
pinctrl-0 = <&usbc0_int>;
290
+
vbus-supply = <&vbus_typec>;
291
+
status = "okay";
292
+
293
+
usb_con: connector {
294
+
compatible = "usb-c-connector";
295
+
label = "USB-C";
296
+
data-role = "dual";
297
+
op-sink-microwatt = <1000000>;
298
+
power-role = "dual";
299
+
sink-pdos =
300
+
<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
301
+
source-pdos =
302
+
<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
303
+
try-power-role = "source";
304
+
305
+
ports {
306
+
#address-cells = <1>;
307
+
#size-cells = <0>;
308
+
309
+
port@0 {
310
+
reg = <0>;
311
+
usbc0_hs: endpoint {
312
+
remote-endpoint = <&usb_host0_xhci_drd_sw>;
313
+
};
314
+
};
315
+
316
+
port@1 {
317
+
reg = <1>;
318
+
usbc0_ss: endpoint {
319
+
remote-endpoint = <&usbdp_phy0_typec_ss>;
320
+
};
321
+
};
322
+
323
+
port@2 {
324
+
reg = <2>;
325
+
usbc0_sbu: endpoint {
326
+
remote-endpoint = <&usbdp_phy0_typec_sbu>;
327
+
};
328
+
};
329
+
};
330
+
};
331
+
};
332
+
333
+
hym8563: rtc@51 {
334
+
compatible = "haoyu,hym8563";
335
+
reg = <0x51>;
336
+
#clock-cells = <0>;
337
+
clock-output-names = "hym8563";
338
+
pinctrl-names = "default";
339
+
pinctrl-0 = <&hym8563_int>;
340
+
interrupt-parent = <&gpio0>;
341
+
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
342
+
wakeup-source;
343
+
};
344
+
};
345
+
346
+
&i2s1_8ch {
347
+
rockchip,i2s-tx-route = <3 2 1 0>;
348
+
rockchip,i2s-rx-route = <1 3 2 0>;
349
+
pinctrl-names = "default";
350
+
pinctrl-0 = <&i2s1m0_sclk
351
+
&i2s1m0_mclk
352
+
&i2s1m0_lrck
353
+
&i2s1m0_sdi1
354
+
&i2s1m0_sdo3>;
355
+
status = "okay";
356
+
};
357
+
358
+
&mdio1 {
359
+
rgmii_phy1: ethernet-phy@1 {
360
+
compatible = "ethernet-phy-ieee802.3-c22";
361
+
reg = <0x1>;
362
+
reset-assert-us = <20000>;
363
+
reset-deassert-us = <100000>;
364
+
reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
365
+
};
366
+
};
367
+
368
+
&pinctrl {
369
+
hym8563 {
370
+
hym8563_int: hym8563-int {
371
+
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
372
+
};
373
+
};
374
+
375
+
sound {
376
+
hp_detect: hp-detect {
377
+
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
378
+
};
379
+
};
380
+
381
+
usb-typec {
382
+
usbc0_int: usbc0-int {
383
+
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
384
+
};
385
+
386
+
typec5v_pwren: typec5v-pwren {
387
+
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
388
+
};
389
+
};
390
+
};
391
+
392
+
&pwm0 {
393
+
pinctrl-0 = <&pwm0m2_pins>;
394
+
pinctrl-names = "default";
395
+
status = "okay";
396
+
};
397
+
398
+
&saradc {
399
+
vref-supply = <&avcc_1v8_s0>;
400
+
status = "okay";
401
+
};
402
+
403
+
&sdhci {
404
+
bus-width = <8>;
405
+
no-sdio;
406
+
no-sd;
407
+
non-removable;
408
+
max-frequency = <200000000>;
409
+
mmc-hs400-1_8v;
410
+
mmc-hs400-enhanced-strobe;
411
+
status = "disabled";
412
+
};
413
+
414
+
&sdmmc {
415
+
bus-width = <4>;
416
+
cap-sd-highspeed;
417
+
disable-wp;
418
+
max-frequency = <150000000>;
419
+
no-mmc;
420
+
no-sdio;
421
+
sd-uhs-sdr104;
422
+
vmmc-supply = <&vcc_3v3_sd_s0>;
423
+
vqmmc-supply = <&vccio_sd_s0>;
424
+
status = "okay";
425
+
};
426
+
427
+
&sfc {
428
+
pinctrl-names = "default";
429
+
pinctrl-0 = <&fspim0_pins>;
430
+
status = "disabled";
431
+
432
+
flash@0 {
433
+
compatible = "jedec,spi-nor";
434
+
reg = <0x0>;
435
+
spi-max-frequency = <100000000>;
436
+
spi-rx-bus-width = <4>;
437
+
spi-tx-bus-width = <1>;
438
+
};
439
+
};
440
+
441
+
&spi2 {
442
+
status = "okay";
443
+
assigned-clocks = <&cru CLK_SPI2>;
444
+
assigned-clock-rates = <200000000>;
445
+
num-cs = <1>;
446
+
pinctrl-names = "default";
447
+
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
448
+
449
+
pmic@0 {
450
+
compatible = "rockchip,rk806";
451
+
reg = <0x0>;
452
+
interrupt-parent = <&gpio0>;
453
+
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
454
+
pinctrl-names = "default";
455
+
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
456
+
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
457
+
spi-max-frequency = <1000000>;
458
+
system-power-controller;
459
+
460
+
vcc1-supply = <&vcc5v0_sys>;
461
+
vcc2-supply = <&vcc5v0_sys>;
462
+
vcc3-supply = <&vcc5v0_sys>;
463
+
vcc4-supply = <&vcc5v0_sys>;
464
+
vcc5-supply = <&vcc5v0_sys>;
465
+
vcc6-supply = <&vcc5v0_sys>;
466
+
vcc7-supply = <&vcc5v0_sys>;
467
+
vcc8-supply = <&vcc5v0_sys>;
468
+
vcc9-supply = <&vcc5v0_sys>;
469
+
vcc10-supply = <&vcc5v0_sys>;
470
+
vcc11-supply = <&vcc_2v0_pldo_s3>;
471
+
vcc12-supply = <&vcc5v0_sys>;
472
+
vcc13-supply = <&vcc_1v1_nldo_s3>;
473
+
vcc14-supply = <&vcc_1v1_nldo_s3>;
474
+
vcca-supply = <&vcc5v0_sys>;
475
+
476
+
gpio-controller;
477
+
#gpio-cells = <2>;
478
+
479
+
rk806_dvs1_null: dvs1-null-pins {
480
+
pins = "gpio_pwrctrl1";
481
+
function = "pin_fun0";
482
+
};
483
+
484
+
rk806_dvs2_null: dvs2-null-pins {
485
+
pins = "gpio_pwrctrl2";
486
+
function = "pin_fun0";
487
+
};
488
+
489
+
rk806_dvs3_null: dvs3-null-pins {
490
+
pins = "gpio_pwrctrl3";
491
+
function = "pin_fun0";
492
+
};
493
+
494
+
regulators {
495
+
vdd_gpu_s0: dcdc-reg1 {
496
+
regulator-name = "vdd_gpu_s0";
497
+
regulator-boot-on;
498
+
regulator-min-microvolt = <550000>;
499
+
regulator-max-microvolt = <950000>;
500
+
regulator-ramp-delay = <12500>;
501
+
regulator-enable-ramp-delay = <400>;
502
+
503
+
regulator-state-mem {
504
+
regulator-off-in-suspend;
505
+
};
506
+
};
507
+
508
+
vdd_cpu_lit_s0: dcdc-reg2 {
509
+
regulator-name = "vdd_cpu_lit_s0";
510
+
regulator-always-on;
511
+
regulator-boot-on;
512
+
regulator-min-microvolt = <550000>;
513
+
regulator-max-microvolt = <950000>;
514
+
regulator-ramp-delay = <12500>;
515
+
516
+
regulator-state-mem {
517
+
regulator-off-in-suspend;
518
+
};
519
+
};
520
+
521
+
vdd_log_s0: dcdc-reg3 {
522
+
regulator-name = "vdd_log_s0";
523
+
regulator-always-on;
524
+
regulator-boot-on;
525
+
regulator-min-microvolt = <675000>;
526
+
regulator-max-microvolt = <750000>;
527
+
regulator-ramp-delay = <12500>;
528
+
529
+
regulator-state-mem {
530
+
regulator-off-in-suspend;
531
+
regulator-suspend-microvolt = <750000>;
532
+
};
533
+
};
534
+
535
+
vdd_vdenc_s0: dcdc-reg4 {
536
+
regulator-name = "vdd_vdenc_s0";
537
+
regulator-always-on;
538
+
regulator-boot-on;
539
+
regulator-min-microvolt = <550000>;
540
+
regulator-max-microvolt = <950000>;
541
+
regulator-ramp-delay = <12500>;
542
+
543
+
regulator-state-mem {
544
+
regulator-off-in-suspend;
545
+
};
546
+
};
547
+
548
+
vdd_ddr_s0: dcdc-reg5 {
549
+
regulator-name = "vdd_ddr_s0";
550
+
regulator-always-on;
551
+
regulator-boot-on;
552
+
regulator-min-microvolt = <675000>;
553
+
regulator-max-microvolt = <900000>;
554
+
regulator-ramp-delay = <12500>;
555
+
556
+
regulator-state-mem {
557
+
regulator-off-in-suspend;
558
+
regulator-suspend-microvolt = <850000>;
559
+
};
560
+
};
561
+
562
+
vcc_1v1_nldo_s3: vdd2_ddr_s3: dcdc-reg6 {
563
+
regulator-name = "vdd2_ddr_s3";
564
+
regulator-always-on;
565
+
regulator-boot-on;
566
+
regulator-max-microvolt = <1100000>;
567
+
regulator-min-microvolt = <1100000>;
568
+
569
+
regulator-state-mem {
570
+
regulator-on-in-suspend;
571
+
};
572
+
};
573
+
574
+
vcc_2v0_pldo_s3: dcdc-reg7 {
575
+
regulator-name = "vdd_2v0_pldo_s3";
576
+
regulator-always-on;
577
+
regulator-boot-on;
578
+
regulator-min-microvolt = <2000000>;
579
+
regulator-max-microvolt = <2000000>;
580
+
regulator-ramp-delay = <12500>;
581
+
582
+
regulator-state-mem {
583
+
regulator-on-in-suspend;
584
+
regulator-suspend-microvolt = <2000000>;
585
+
};
586
+
};
587
+
588
+
vcc_3v3_s3: dcdc-reg8 {
589
+
regulator-name = "vcc_3v3_s3";
590
+
regulator-always-on;
591
+
regulator-boot-on;
592
+
regulator-min-microvolt = <3300000>;
593
+
regulator-max-microvolt = <3300000>;
594
+
595
+
regulator-state-mem {
596
+
regulator-on-in-suspend;
597
+
regulator-suspend-microvolt = <3300000>;
598
+
};
599
+
};
600
+
601
+
vddq_ddr_s0: dcdc-reg9 {
602
+
regulator-name = "vddq_ddr_s0";
603
+
regulator-always-on;
604
+
regulator-boot-on;
605
+
606
+
regulator-state-mem {
607
+
regulator-off-in-suspend;
608
+
};
609
+
};
610
+
611
+
vcc_1v8_s3: dcdc-reg10 {
612
+
regulator-name = "vcc_1v8_s3";
613
+
regulator-always-on;
614
+
regulator-boot-on;
615
+
regulator-min-microvolt = <1800000>;
616
+
regulator-max-microvolt = <1800000>;
617
+
618
+
regulator-state-mem {
619
+
regulator-on-in-suspend;
620
+
regulator-suspend-microvolt = <1800000>;
621
+
};
622
+
};
623
+
624
+
avcc_1v8_s0: pldo-reg1 {
625
+
regulator-name = "avcc_1v8_s0";
626
+
regulator-always-on;
627
+
regulator-boot-on;
628
+
regulator-min-microvolt = <1800000>;
629
+
regulator-max-microvolt = <1800000>;
630
+
631
+
regulator-state-mem {
632
+
regulator-off-in-suspend;
633
+
};
634
+
};
635
+
636
+
vcc_1v8_s0: pldo-reg2 {
637
+
regulator-name = "vcc_1v8_s0";
638
+
regulator-always-on;
639
+
regulator-boot-on;
640
+
regulator-min-microvolt = <1800000>;
641
+
regulator-max-microvolt = <1800000>;
642
+
643
+
regulator-state-mem {
644
+
regulator-off-in-suspend;
645
+
regulator-suspend-microvolt = <1800000>;
646
+
};
647
+
};
648
+
649
+
avdd_1v2_s0: pldo-reg3 {
650
+
regulator-name = "avdd_1v2_s0";
651
+
regulator-always-on;
652
+
regulator-boot-on;
653
+
regulator-min-microvolt = <1200000>;
654
+
regulator-max-microvolt = <1200000>;
655
+
656
+
regulator-state-mem {
657
+
regulator-off-in-suspend;
658
+
};
659
+
};
660
+
661
+
vcc_3v3_s0: pldo-reg4 {
662
+
regulator-name = "vcc_3v3_s0";
663
+
regulator-always-on;
664
+
regulator-boot-on;
665
+
regulator-min-microvolt = <3300000>;
666
+
regulator-max-microvolt = <3300000>;
667
+
regulator-ramp-delay = <12500>;
668
+
669
+
regulator-state-mem {
670
+
regulator-off-in-suspend;
671
+
};
672
+
};
673
+
674
+
vccio_sd_s0: pldo-reg5 {
675
+
regulator-name = "vccio_sd_s0";
676
+
regulator-always-on;
677
+
regulator-boot-on;
678
+
regulator-min-microvolt = <1800000>;
679
+
regulator-max-microvolt = <3300000>;
680
+
regulator-ramp-delay = <12500>;
681
+
682
+
regulator-state-mem {
683
+
regulator-off-in-suspend;
684
+
};
685
+
};
686
+
687
+
pldo6_s3: pldo-reg6 {
688
+
regulator-name = "pldo6_s3";
689
+
regulator-always-on;
690
+
regulator-boot-on;
691
+
regulator-min-microvolt = <1800000>;
692
+
regulator-max-microvolt = <1800000>;
693
+
694
+
regulator-state-mem {
695
+
regulator-on-in-suspend;
696
+
regulator-suspend-microvolt = <1800000>;
697
+
};
698
+
};
699
+
700
+
vdd_0v75_s3: nldo-reg1 {
701
+
regulator-name = "vdd_0v75_s3";
702
+
regulator-always-on;
703
+
regulator-boot-on;
704
+
regulator-min-microvolt = <750000>;
705
+
regulator-max-microvolt = <750000>;
706
+
707
+
regulator-state-mem {
708
+
regulator-on-in-suspend;
709
+
regulator-suspend-microvolt = <750000>;
710
+
};
711
+
};
712
+
713
+
vdd_ddr_pll_s0: nldo-reg2 {
714
+
regulator-name = "vdd_ddr_pll_s0";
715
+
regulator-always-on;
716
+
regulator-boot-on;
717
+
regulator-min-microvolt = <850000>;
718
+
regulator-max-microvolt = <850000>;
719
+
720
+
regulator-state-mem {
721
+
regulator-off-in-suspend;
722
+
regulator-suspend-microvolt = <850000>;
723
+
};
724
+
};
725
+
726
+
avdd_0v75_s0: nldo-reg3 {
727
+
regulator-name = "avdd_0v75_s0";
728
+
regulator-always-on;
729
+
regulator-boot-on;
730
+
regulator-min-microvolt = <750000>;
731
+
regulator-max-microvolt = <750000>;
732
+
733
+
regulator-state-mem {
734
+
regulator-off-in-suspend;
735
+
};
736
+
};
737
+
738
+
vdd_0v85_s0: nldo-reg4 {
739
+
regulator-name = "vdd_0v85_s0";
740
+
regulator-always-on;
741
+
regulator-boot-on;
742
+
regulator-min-microvolt = <850000>;
743
+
regulator-max-microvolt = <850000>;
744
+
745
+
regulator-state-mem {
746
+
regulator-off-in-suspend;
747
+
};
748
+
};
749
+
750
+
vdd_0v75_s0: nldo-reg5 {
751
+
regulator-name = "vdd_0v75_s0";
752
+
regulator-always-on;
753
+
regulator-boot-on;
754
+
regulator-min-microvolt = <750000>;
755
+
regulator-max-microvolt = <750000>;
756
+
757
+
regulator-state-mem {
758
+
regulator-off-in-suspend;
759
+
};
760
+
};
761
+
};
762
+
};
763
+
};
764
+
765
+
&tsadc {
766
+
status = "okay";
767
+
};
768
+
769
+
&u2phy0 {
770
+
status = "okay";
771
+
};
772
+
773
+
&u2phy0_otg {
774
+
status = "okay";
775
+
};
776
+
777
+
&u2phy2 {
778
+
status = "okay";
779
+
};
780
+
781
+
&u2phy2_host {
782
+
status = "okay";
783
+
};
784
+
785
+
&u2phy3 {
786
+
status = "okay";
787
+
};
788
+
789
+
&u2phy3_host {
790
+
status = "okay";
791
+
};
792
+
793
+
&uart2 {
794
+
pinctrl-0 = <&uart2m0_xfer>;
795
+
status = "okay";
796
+
};
797
+
798
+
&usbdp_phy0 {
799
+
mode-switch;
800
+
orientation-switch;
801
+
sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
802
+
sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
803
+
status = "okay";
804
+
805
+
port {
806
+
#address-cells = <1>;
807
+
#size-cells = <0>;
808
+
809
+
usbdp_phy0_typec_ss: endpoint@0 {
810
+
reg = <0>;
811
+
remote-endpoint = <&usbc0_ss>;
812
+
};
813
+
814
+
usbdp_phy0_typec_sbu: endpoint@1 {
815
+
reg = <1>;
816
+
remote-endpoint = <&usbc0_sbu>;
817
+
};
818
+
};
819
+
};
820
+
821
+
&usb_host0_ehci {
822
+
status = "okay";
823
+
};
824
+
825
+
&usb_host0_ohci {
826
+
status = "okay";
827
+
};
828
+
829
+
&usb_host0_xhci {
830
+
dr_mode = "otg";
831
+
usb-role-switch;
832
+
status = "okay";
833
+
834
+
port {
835
+
usb_host0_xhci_drd_sw: endpoint {
836
+
remote-endpoint = <&usbc0_hs>;
837
+
};
838
+
};
839
+
};
840
+
841
+
&usb_host1_ehci {
842
+
status = "okay";
843
+
};
844
+
845
+
&usb_host1_ohci {
846
+
status = "okay";
847
+
};
848
+
849
+
&usb_host2_xhci {
850
+
status = "okay";
851
+
};
852
+
853
+
&vop_mmu {
854
+
status = "okay";
855
+
};
856
+
857
+
&vop {
858
+
status = "okay";
859
+
};
860
+
861
+
&vp0 {
862
+
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
863
+
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
864
+
remote-endpoint = <&hdmi0_in_vp0>;
865
+
};
866
+
};
+19
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts
+19
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+
3
+
/dts-v1/;
4
+
5
+
#include "rk3588s-orangepi-5.dtsi"
6
+
7
+
/ {
8
+
model = "Xunlong Orange Pi 5B";
9
+
compatible = "xunlong,orangepi-5b", "rockchip,rk3588s";
10
+
11
+
aliases {
12
+
mmc0 = &sdhci;
13
+
mmc1 = &sdmmc;
14
+
};
15
+
};
16
+
17
+
&sdhci {
18
+
status = "okay";
19
+
};
+62
-1
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+62
-1
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
···
5
5
#include <dt-bindings/gpio/gpio.h>
6
6
#include <dt-bindings/leds/common.h>
7
7
#include <dt-bindings/pinctrl/rockchip.h>
8
+
#include <dt-bindings/soc/rockchip,vop2.h>
8
9
#include "rk3588s.dtsi"
9
10
10
11
/ {
···
34
33
35
34
chosen {
36
35
stdout-path = "serial2:1500000n8";
36
+
};
37
+
38
+
hdmi0-con {
39
+
compatible = "hdmi-connector";
40
+
type = "d";
41
+
42
+
port {
43
+
hdmi0_con_in: endpoint {
44
+
remote-endpoint = <&hdmi0_out_con>;
45
+
};
46
+
};
37
47
};
38
48
39
49
leds {
···
178
166
cpu-supply = <&vdd_cpu_lit_s0>;
179
167
};
180
168
169
+
&gpu {
170
+
mali-supply = <&vdd_gpu_s0>;
171
+
status = "okay";
172
+
};
173
+
181
174
&i2c0 {
182
175
pinctrl-names = "default";
183
176
pinctrl-0 = <&i2c0m2_xfer>;
···
313
296
status = "okay";
314
297
};
315
298
299
+
&hdmi0 {
300
+
pinctrl-names = "default";
301
+
pinctrl-0 = <&hdmim0_tx0_cec
302
+
&hdmim1_tx0_hpd
303
+
&hdmim0_tx0_scl
304
+
&hdmim0_tx0_sda>;
305
+
status = "okay";
306
+
};
307
+
308
+
&hdmi0_in {
309
+
hdmi0_in_vp0: endpoint {
310
+
remote-endpoint = <&vp0_out_hdmi0>;
311
+
};
312
+
};
313
+
314
+
&hdmi0_out {
315
+
hdmi0_out_con: endpoint {
316
+
remote-endpoint = <&hdmi0_con_in>;
317
+
};
318
+
};
319
+
320
+
&hdptxphy_hdmi0 {
321
+
status = "okay";
322
+
};
323
+
316
324
&mdio1 {
317
325
rgmii_phy1: ethernet-phy@1 {
318
326
/* RTL8211F */
···
352
310
};
353
311
354
312
&pcie2x1l2 {
355
-
pinctrl-0 = <&pcie20x1m0_pins>;
313
+
pinctrl-0 = <&pcie2_reset>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>;
356
314
pinctrl-names = "default";
357
315
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
358
316
vpcie3v3-supply = <&vcc3v3_wf>;
···
369
327
pcie {
370
328
pow_en: pow-en {
371
329
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
330
+
};
331
+
332
+
pcie2_reset: pcie2-reset {
333
+
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
372
334
};
373
335
};
374
336
···
829
783
830
784
&usb_host2_xhci {
831
785
status = "okay";
786
+
};
787
+
788
+
&vop_mmu {
789
+
status = "okay";
790
+
};
791
+
792
+
&vop {
793
+
status = "okay";
794
+
};
795
+
796
+
&vp0 {
797
+
vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
798
+
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
799
+
remote-endpoint = <&hdmi0_in_vp0>;
800
+
};
832
801
};