Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
platform/x86/intel/pmc: Remove unnecessary declarations in header
Remove unnecessary declarations in header file. Variable that are
used by only one .c file are removed from header file and changed
to be static in their corresponding .c file.
Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
Link: https://lore.kernel.org/r/20250214214416.10150-3-xi.pardee@linux.intel.com
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
authored by
Xi Pardee
and committed by
Ilpo Järvinen
9eeeb2a7
d31feed7
+122
-248
+17
-17
drivers/platform/x86/intel/pmc/adl.c
+17
-17
drivers/platform/x86/intel/pmc/adl.c
···
11
11
#include "core.h"
12
12
13
13
/* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */
14
-
const struct pmc_bit_map adl_pfear_map[] = {
14
+
static const struct pmc_bit_map adl_pfear_map[] = {
15
15
{"SPI/eSPI", BIT(2)},
16
16
{"XHCI", BIT(3)},
17
17
{"SPA", BIT(4)},
···
54
54
{}
55
55
};
56
56
57
-
const struct pmc_bit_map *ext_adl_pfear_map[] = {
57
+
static const struct pmc_bit_map *ext_adl_pfear_map[] = {
58
58
/*
59
59
* Check intel_pmc_core_ids[] users of cnp_reg_map for
60
60
* a list of core SoCs using this.
···
63
63
NULL
64
64
};
65
65
66
-
const struct pmc_bit_map adl_ltr_show_map[] = {
66
+
static const struct pmc_bit_map adl_ltr_show_map[] = {
67
67
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
68
68
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
69
69
{"SATA", CNP_PMC_LTR_SATA},
···
100
100
{}
101
101
};
102
102
103
-
const struct pmc_bit_map adl_clocksource_status_map[] = {
103
+
static const struct pmc_bit_map adl_clocksource_status_map[] = {
104
104
{"CLKPART1_OFF_STS", BIT(0)},
105
105
{"CLKPART2_OFF_STS", BIT(1)},
106
106
{"CLKPART3_OFF_STS", BIT(2)},
···
128
128
{}
129
129
};
130
130
131
-
const struct pmc_bit_map adl_power_gating_status_0_map[] = {
131
+
static const struct pmc_bit_map adl_power_gating_status_0_map[] = {
132
132
{"PMC_PGD0_PG_STS", BIT(0)},
133
133
{"DMI_PGD0_PG_STS", BIT(1)},
134
134
{"ESPISPI_PGD0_PG_STS", BIT(2)},
···
158
158
{}
159
159
};
160
160
161
-
const struct pmc_bit_map adl_power_gating_status_1_map[] = {
161
+
static const struct pmc_bit_map adl_power_gating_status_1_map[] = {
162
162
{"USBR0_PGD0_PG_STS", BIT(0)},
163
163
{"SMT1_PGD0_PG_STS", BIT(2)},
164
164
{"CSMERTC_PGD0_PG_STS", BIT(6)},
···
170
170
{}
171
171
};
172
172
173
-
const struct pmc_bit_map adl_power_gating_status_2_map[] = {
173
+
static const struct pmc_bit_map adl_power_gating_status_2_map[] = {
174
174
{"THC0_PGD0_PG_STS", BIT(7)},
175
175
{"THC1_PGD0_PG_STS", BIT(8)},
176
176
{"SPF_PGD0_PG_STS", BIT(14)},
177
177
{}
178
178
};
179
179
180
-
const struct pmc_bit_map adl_d3_status_0_map[] = {
180
+
static const struct pmc_bit_map adl_d3_status_0_map[] = {
181
181
{"ISH_D3_STS", BIT(2)},
182
182
{"LPSS_D3_STS", BIT(3)},
183
183
{"XDCI_D3_STS", BIT(4)},
···
193
193
{}
194
194
};
195
195
196
-
const struct pmc_bit_map adl_d3_status_1_map[] = {
196
+
static const struct pmc_bit_map adl_d3_status_1_map[] = {
197
197
{"GBE_D3_STS", BIT(19)},
198
198
{"CNVI_D3_STS", BIT(27)},
199
199
{}
200
200
};
201
201
202
-
const struct pmc_bit_map adl_d3_status_2_map[] = {
202
+
static const struct pmc_bit_map adl_d3_status_2_map[] = {
203
203
{"CSMERTC_D3_STS", BIT(1)},
204
204
{"CSE_D3_STS", BIT(4)},
205
205
{"KVMCC_D3_STS", BIT(5)},
···
210
210
{}
211
211
};
212
212
213
-
const struct pmc_bit_map adl_d3_status_3_map[] = {
213
+
static const struct pmc_bit_map adl_d3_status_3_map[] = {
214
214
{"THC0_D3_STS", BIT(14)},
215
215
{"THC1_D3_STS", BIT(15)},
216
216
{}
217
217
};
218
218
219
-
const struct pmc_bit_map adl_vnn_req_status_0_map[] = {
219
+
static const struct pmc_bit_map adl_vnn_req_status_0_map[] = {
220
220
{"ISH_VNN_REQ_STS", BIT(2)},
221
221
{"ESPISPI_VNN_REQ_STS", BIT(18)},
222
222
{"DSP_VNN_REQ_STS", BIT(19)},
223
223
{}
224
224
};
225
225
226
-
const struct pmc_bit_map adl_vnn_req_status_1_map[] = {
226
+
static const struct pmc_bit_map adl_vnn_req_status_1_map[] = {
227
227
{"NPK_VNN_REQ_STS", BIT(4)},
228
228
{"EXI_VNN_REQ_STS", BIT(9)},
229
229
{"GBE_VNN_REQ_STS", BIT(19)},
···
232
232
{}
233
233
};
234
234
235
-
const struct pmc_bit_map adl_vnn_req_status_2_map[] = {
235
+
static const struct pmc_bit_map adl_vnn_req_status_2_map[] = {
236
236
{"CSMERTC_VNN_REQ_STS", BIT(1)},
237
237
{"CSE_VNN_REQ_STS", BIT(4)},
238
238
{"SMT1_VNN_REQ_STS", BIT(8)},
···
245
245
{}
246
246
};
247
247
248
-
const struct pmc_bit_map adl_vnn_req_status_3_map[] = {
248
+
static const struct pmc_bit_map adl_vnn_req_status_3_map[] = {
249
249
{"GPIOCOM5_VNN_REQ_STS", BIT(11)},
250
250
{}
251
251
};
252
252
253
-
const struct pmc_bit_map adl_vnn_misc_status_map[] = {
253
+
static const struct pmc_bit_map adl_vnn_misc_status_map[] = {
254
254
{"CPU_C10_REQ_STS", BIT(0)},
255
255
{"PCIe_LPM_En_REQ_STS", BIT(3)},
256
256
{"ITH_REQ_STS", BIT(5)},
···
265
265
{}
266
266
};
267
267
268
-
const struct pmc_bit_map *adl_lpm_maps[] = {
268
+
static const struct pmc_bit_map *adl_lpm_maps[] = {
269
269
adl_clocksource_status_map,
270
270
adl_power_gating_status_0_map,
271
271
adl_power_gating_status_1_map,
+29
-29
drivers/platform/x86/intel/pmc/arl.c
+29
-29
drivers/platform/x86/intel/pmc/arl.c
···
20
20
21
21
static const u8 ARL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
22
22
23
-
const struct pmc_bit_map arl_socs_ltr_show_map[] = {
23
+
static const struct pmc_bit_map arl_socs_ltr_show_map[] = {
24
24
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
25
25
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
26
26
{"SATA", CNP_PMC_LTR_SATA},
···
60
60
{}
61
61
};
62
62
63
-
const struct pmc_bit_map arl_socs_clocksource_status_map[] = {
63
+
static const struct pmc_bit_map arl_socs_clocksource_status_map[] = {
64
64
{"AON2_OFF_STS", BIT(0)},
65
65
{"AON3_OFF_STS", BIT(1)},
66
66
{"AON4_OFF_STS", BIT(2)},
···
88
88
{}
89
89
};
90
90
91
-
const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = {
91
+
static const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = {
92
92
{"PMC_PGD0_PG_STS", BIT(0)},
93
93
{"DMI_PGD0_PG_STS", BIT(1)},
94
94
{"ESPISPI_PGD0_PG_STS", BIT(2)},
···
124
124
{}
125
125
};
126
126
127
-
const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = {
127
+
static const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = {
128
128
{"USBR0_PGD0_PG_STS", BIT(0)},
129
129
{"SUSRAM_PGD0_PG_STS", BIT(1)},
130
130
{"SMT1_PGD0_PG_STS", BIT(2)},
···
160
160
{}
161
161
};
162
162
163
-
const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = {
163
+
static const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = {
164
164
{"PSF8_PGD0_PG_STS", BIT(0)},
165
165
{"FIA_PGD0_PG_STS", BIT(1)},
166
166
{"SOC_D2D_PGD3_PG_STS", BIT(2)},
···
188
188
{}
189
189
};
190
190
191
-
const struct pmc_bit_map arl_socs_d3_status_2_map[] = {
191
+
static const struct pmc_bit_map arl_socs_d3_status_2_map[] = {
192
192
{"CSMERTC_D3_STS", BIT(1)},
193
193
{"SUSRAM_D3_STS", BIT(2)},
194
194
{"CSE_D3_STS", BIT(4)},
···
207
207
{}
208
208
};
209
209
210
-
const struct pmc_bit_map arl_socs_d3_status_3_map[] = {
210
+
static const struct pmc_bit_map arl_socs_d3_status_3_map[] = {
211
211
{"GBETSN_D3_STS", BIT(13)},
212
212
{"THC0_D3_STS", BIT(14)},
213
213
{"THC1_D3_STS", BIT(15)},
···
215
215
{}
216
216
};
217
217
218
-
const struct pmc_bit_map arl_socs_vnn_req_status_3_map[] = {
218
+
static const struct pmc_bit_map arl_socs_vnn_req_status_3_map[] = {
219
219
{"DTS0_VNN_REQ_STS", BIT(7)},
220
220
{"GPIOCOM5_VNN_REQ_STS", BIT(11)},
221
221
{}
222
222
};
223
223
224
-
const struct pmc_bit_map *arl_socs_lpm_maps[] = {
224
+
static const struct pmc_bit_map *arl_socs_lpm_maps[] = {
225
225
arl_socs_clocksource_status_map,
226
226
arl_socs_power_gating_status_0_map,
227
227
arl_socs_power_gating_status_1_map,
···
239
239
NULL
240
240
};
241
241
242
-
const struct pmc_bit_map arl_socs_pfear_map[] = {
242
+
static const struct pmc_bit_map arl_socs_pfear_map[] = {
243
243
{"RSVD64", BIT(0)},
244
244
{"RSVD65", BIT(1)},
245
245
{"RSVD66", BIT(2)},
···
250
250
{}
251
251
};
252
252
253
-
const struct pmc_bit_map *ext_arl_socs_pfear_map[] = {
253
+
static const struct pmc_bit_map *ext_arl_socs_pfear_map[] = {
254
254
mtl_socm_pfear_map,
255
255
arl_socs_pfear_map,
256
256
NULL
257
257
};
258
258
259
-
const struct pmc_reg_map arl_socs_reg_map = {
259
+
static const struct pmc_reg_map arl_socs_reg_map = {
260
260
.pfear_sts = ext_arl_socs_pfear_map,
261
261
.ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES,
262
262
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
···
284
284
.pson_residency_counter_step = TGL_PSON_RES_COUNTER_STEP,
285
285
};
286
286
287
-
const struct pmc_bit_map arl_pchs_ltr_show_map[] = {
287
+
static const struct pmc_bit_map arl_pchs_ltr_show_map[] = {
288
288
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
289
289
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
290
290
{"SATA", CNP_PMC_LTR_SATA},
···
324
324
{}
325
325
};
326
326
327
-
const struct pmc_bit_map arl_pchs_clocksource_status_map[] = {
327
+
static const struct pmc_bit_map arl_pchs_clocksource_status_map[] = {
328
328
{"AON2_OFF_STS", BIT(0)},
329
329
{"AON3_OFF_STS", BIT(1)},
330
330
{"AON4_OFF_STS", BIT(2)},
···
359
359
{}
360
360
};
361
361
362
-
const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = {
362
+
static const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = {
363
363
{"PMC_PGD0_PG_STS", BIT(0)},
364
364
{"DMI_PGD0_PG_STS", BIT(1)},
365
365
{"ESPISPI_PGD0_PG_STS", BIT(2)},
···
395
395
{}
396
396
};
397
397
398
-
const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = {
398
+
static const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = {
399
399
{"USBR0_PGD0_PG_STS", BIT(0)},
400
400
{"SUSRAM_PGD0_PG_STS", BIT(1)},
401
401
{"SMT1_PGD0_PG_STS", BIT(2)},
···
431
431
{}
432
432
};
433
433
434
-
const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = {
434
+
static const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = {
435
435
{"U3FPW2_PGD0_PG_STS", BIT(0)},
436
436
{"FIA_PGD0_PG_STS", BIT(1)},
437
437
{"FIACPCB_X_PGD0_PG_STS", BIT(2)},
···
458
458
{}
459
459
};
460
460
461
-
const struct pmc_bit_map arl_pchs_d3_status_0_map[] = {
461
+
static const struct pmc_bit_map arl_pchs_d3_status_0_map[] = {
462
462
{"SPF_D3_STS", BIT(0)},
463
463
{"LPSS_D3_STS", BIT(3)},
464
464
{"XDCI_D3_STS", BIT(4)},
···
475
475
{}
476
476
};
477
477
478
-
const struct pmc_bit_map arl_pchs_d3_status_1_map[] = {
478
+
static const struct pmc_bit_map arl_pchs_d3_status_1_map[] = {
479
479
{"GBETSN1_D3_STS", BIT(14)},
480
480
{"GBE_D3_STS", BIT(19)},
481
481
{"ITSS_D3_STS", BIT(23)},
···
484
484
{}
485
485
};
486
486
487
-
const struct pmc_bit_map arl_pchs_d3_status_2_map[] = {
487
+
static const struct pmc_bit_map arl_pchs_d3_status_2_map[] = {
488
488
{"CSMERTC_D3_STS", BIT(1)},
489
489
{"SUSRAM_D3_STS", BIT(2)},
490
490
{"CSE_D3_STS", BIT(4)},
···
505
505
{}
506
506
};
507
507
508
-
const struct pmc_bit_map arl_pchs_d3_status_3_map[] = {
508
+
static const struct pmc_bit_map arl_pchs_d3_status_3_map[] = {
509
509
{"ESE_D3_STS", BIT(3)},
510
510
{"GBETSN_D3_STS", BIT(13)},
511
511
{"THC0_D3_STS", BIT(14)},
···
514
514
{}
515
515
};
516
516
517
-
const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[] = {
517
+
static const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[] = {
518
518
{"FIA_VNN_REQ_STS", BIT(17)},
519
519
{"ESPISPI_VNN_REQ_STS", BIT(18)},
520
520
{}
521
521
};
522
522
523
-
const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = {
523
+
static const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = {
524
524
{"NPK_VNN_REQ_STS", BIT(4)},
525
525
{"DFXAGG_VNN_REQ_STS", BIT(8)},
526
526
{"EXI_VNN_REQ_STS", BIT(9)},
···
531
531
{}
532
532
};
533
533
534
-
const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = {
534
+
static const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = {
535
535
{"FIA2_VNN_REQ_STS", BIT(0)},
536
536
{"CSMERTC_VNN_REQ_STS", BIT(1)},
537
537
{"CSE_VNN_REQ_STS", BIT(4)},
···
549
549
{}
550
550
};
551
551
552
-
const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[] = {
552
+
static const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[] = {
553
553
{"ESE_VNN_REQ_STS", BIT(3)},
554
554
{"DTS0_VNN_REQ_STS", BIT(7)},
555
555
{"GPIOCOM5_VNN_REQ_STS", BIT(11)},
···
557
557
{}
558
558
};
559
559
560
-
const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = {
560
+
static const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = {
561
561
{"CPU_C10_REQ_STS", BIT(0)},
562
562
{"TS_OFF_REQ_STS", BIT(1)},
563
563
{"PNDE_MET_REQ_STS", BIT(2)},
···
587
587
{}
588
588
};
589
589
590
-
const struct pmc_bit_map arl_pchs_signal_status_map[] = {
590
+
static const struct pmc_bit_map arl_pchs_signal_status_map[] = {
591
591
{"LSX_Wake0_STS", BIT(0)},
592
592
{"LSX_Wake1_STS", BIT(1)},
593
593
{"LSX_Wake2_STS", BIT(2)},
···
607
607
{}
608
608
};
609
609
610
-
const struct pmc_bit_map *arl_pchs_lpm_maps[] = {
610
+
static const struct pmc_bit_map *arl_pchs_lpm_maps[] = {
611
611
arl_pchs_clocksource_status_map,
612
612
arl_pchs_power_gating_status_0_map,
613
613
arl_pchs_power_gating_status_1_map,
···
625
625
NULL
626
626
};
627
627
628
-
const struct pmc_reg_map arl_pchs_reg_map = {
628
+
static const struct pmc_reg_map arl_pchs_reg_map = {
629
629
.pfear_sts = ext_arl_socs_pfear_map,
630
630
.ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES,
631
631
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
+4
-4
drivers/platform/x86/intel/pmc/cnp.c
+4
-4
drivers/platform/x86/intel/pmc/cnp.c
···
88
88
{}
89
89
};
90
90
91
-
const struct pmc_bit_map *ext_cnp_pfear_map[] = {
91
+
static const struct pmc_bit_map *ext_cnp_pfear_map[] = {
92
92
/*
93
93
* Check intel_pmc_core_ids[] users of cnp_reg_map for
94
94
* a list of core SoCs using this.
···
97
97
NULL
98
98
};
99
99
100
-
const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
100
+
static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
101
101
{"AUDIO_D3", BIT(0)},
102
102
{"OTG_D3", BIT(1)},
103
103
{"XHCI_D3", BIT(2)},
···
110
110
{}
111
111
};
112
112
113
-
const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
113
+
static const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
114
114
{"SDIO_PLL_OFF", BIT(0)},
115
115
{"USB2_PLL_OFF", BIT(1)},
116
116
{"AUDIO_PLL_OFF", BIT(2)},
···
127
127
{}
128
128
};
129
129
130
-
const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
130
+
static const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
131
131
{"MPHY_CORE_GATED", BIT(0)},
132
132
{"CSME_GATED", BIT(1)},
133
133
{"USB2_SUS_GATED", BIT(2)},
-126
drivers/platform/x86/intel/pmc/core.h
-126
drivers/platform/x86/intel/pmc/core.h
···
467
467
};
468
468
469
469
extern const struct pmc_bit_map msr_map[];
470
-
extern const struct pmc_bit_map spt_pll_map[];
471
-
extern const struct pmc_bit_map spt_mphy_map[];
472
-
extern const struct pmc_bit_map spt_pfear_map[];
473
-
extern const struct pmc_bit_map *ext_spt_pfear_map[];
474
-
extern const struct pmc_bit_map spt_ltr_show_map[];
475
-
extern const struct pmc_reg_map spt_reg_map;
476
470
extern const struct pmc_bit_map cnp_pfear_map[];
477
-
extern const struct pmc_bit_map *ext_cnp_pfear_map[];
478
-
extern const struct pmc_bit_map cnp_slps0_dbg0_map[];
479
-
extern const struct pmc_bit_map cnp_slps0_dbg1_map[];
480
-
extern const struct pmc_bit_map cnp_slps0_dbg2_map[];
481
471
extern const struct pmc_bit_map *cnp_slps0_dbg_maps[];
482
472
extern const struct pmc_bit_map cnp_ltr_show_map[];
483
473
extern const struct pmc_reg_map cnp_reg_map;
484
-
extern const struct pmc_bit_map icl_pfear_map[];
485
-
extern const struct pmc_bit_map *ext_icl_pfear_map[];
486
-
extern const struct pmc_reg_map icl_reg_map;
487
-
extern const struct pmc_bit_map tgl_pfear_map[];
488
-
extern const struct pmc_bit_map *ext_tgl_pfear_map[];
489
-
extern const struct pmc_bit_map tgl_clocksource_status_map[];
490
-
extern const struct pmc_bit_map tgl_power_gating_status_map[];
491
-
extern const struct pmc_bit_map tgl_d3_status_map[];
492
-
extern const struct pmc_bit_map tgl_vnn_req_status_map[];
493
-
extern const struct pmc_bit_map tgl_vnn_misc_status_map[];
494
474
extern const struct pmc_bit_map tgl_signal_status_map[];
495
-
extern const struct pmc_bit_map *tgl_lpm_maps[];
496
-
extern const struct pmc_reg_map tgl_reg_map;
497
-
extern const struct pmc_reg_map tgl_h_reg_map;
498
-
extern const struct pmc_bit_map adl_pfear_map[];
499
-
extern const struct pmc_bit_map *ext_adl_pfear_map[];
500
-
extern const struct pmc_bit_map adl_ltr_show_map[];
501
-
extern const struct pmc_bit_map adl_clocksource_status_map[];
502
-
extern const struct pmc_bit_map adl_power_gating_status_0_map[];
503
-
extern const struct pmc_bit_map adl_power_gating_status_1_map[];
504
-
extern const struct pmc_bit_map adl_power_gating_status_2_map[];
505
-
extern const struct pmc_bit_map adl_d3_status_0_map[];
506
-
extern const struct pmc_bit_map adl_d3_status_1_map[];
507
-
extern const struct pmc_bit_map adl_d3_status_2_map[];
508
-
extern const struct pmc_bit_map adl_d3_status_3_map[];
509
-
extern const struct pmc_bit_map adl_vnn_req_status_0_map[];
510
-
extern const struct pmc_bit_map adl_vnn_req_status_1_map[];
511
-
extern const struct pmc_bit_map adl_vnn_req_status_2_map[];
512
-
extern const struct pmc_bit_map adl_vnn_req_status_3_map[];
513
-
extern const struct pmc_bit_map adl_vnn_misc_status_map[];
514
-
extern const struct pmc_bit_map *adl_lpm_maps[];
515
475
extern const struct pmc_reg_map adl_reg_map;
516
476
extern const struct pmc_bit_map mtl_socm_pfear_map[];
517
-
extern const struct pmc_bit_map *ext_mtl_socm_pfear_map[];
518
-
extern const struct pmc_bit_map mtl_socm_ltr_show_map[];
519
-
extern const struct pmc_bit_map mtl_socm_clocksource_status_map[];
520
-
extern const struct pmc_bit_map mtl_socm_power_gating_status_0_map[];
521
-
extern const struct pmc_bit_map mtl_socm_power_gating_status_1_map[];
522
-
extern const struct pmc_bit_map mtl_socm_power_gating_status_2_map[];
523
477
extern const struct pmc_bit_map mtl_socm_d3_status_0_map[];
524
478
extern const struct pmc_bit_map mtl_socm_d3_status_1_map[];
525
-
extern const struct pmc_bit_map mtl_socm_d3_status_2_map[];
526
-
extern const struct pmc_bit_map mtl_socm_d3_status_3_map[];
527
479
extern const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[];
528
480
extern const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[];
529
481
extern const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[];
530
-
extern const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[];
531
482
extern const struct pmc_bit_map mtl_socm_vnn_misc_status_map[];
532
483
extern const struct pmc_bit_map mtl_socm_signal_status_map[];
533
-
extern const struct pmc_bit_map *mtl_socm_lpm_maps[];
534
484
extern const struct pmc_reg_map mtl_socm_reg_map;
535
-
extern const struct pmc_bit_map mtl_ioep_pfear_map[];
536
-
extern const struct pmc_bit_map *ext_mtl_ioep_pfear_map[];
537
-
extern const struct pmc_bit_map mtl_ioep_ltr_show_map[];
538
-
extern const struct pmc_bit_map mtl_ioep_clocksource_status_map[];
539
-
extern const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[];
540
-
extern const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[];
541
-
extern const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[];
542
-
extern const struct pmc_bit_map mtl_ioep_d3_status_0_map[];
543
-
extern const struct pmc_bit_map mtl_ioep_d3_status_1_map[];
544
-
extern const struct pmc_bit_map mtl_ioep_d3_status_2_map[];
545
-
extern const struct pmc_bit_map mtl_ioep_d3_status_3_map[];
546
-
extern const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[];
547
-
extern const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[];
548
-
extern const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[];
549
-
extern const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[];
550
-
extern const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[];
551
-
extern const struct pmc_bit_map *mtl_ioep_lpm_maps[];
552
485
extern const struct pmc_reg_map mtl_ioep_reg_map;
553
-
extern const struct pmc_bit_map mtl_ioem_pfear_map[];
554
-
extern const struct pmc_bit_map *ext_mtl_ioem_pfear_map[];
555
-
extern const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[];
556
-
extern const struct pmc_bit_map mtl_ioem_vnn_req_status_1_map[];
557
-
extern const struct pmc_bit_map *mtl_ioem_lpm_maps[];
558
-
extern const struct pmc_reg_map mtl_ioem_reg_map;
559
-
extern const struct pmc_reg_map lnl_socm_reg_map;
560
-
561
-
/* LNL */
562
-
extern const struct pmc_bit_map lnl_ltr_show_map[];
563
-
extern const struct pmc_bit_map lnl_clocksource_status_map[];
564
-
extern const struct pmc_bit_map lnl_power_gating_status_0_map[];
565
-
extern const struct pmc_bit_map lnl_power_gating_status_1_map[];
566
-
extern const struct pmc_bit_map lnl_power_gating_status_2_map[];
567
-
extern const struct pmc_bit_map lnl_d3_status_0_map[];
568
-
extern const struct pmc_bit_map lnl_d3_status_1_map[];
569
-
extern const struct pmc_bit_map lnl_d3_status_2_map[];
570
-
extern const struct pmc_bit_map lnl_d3_status_3_map[];
571
-
extern const struct pmc_bit_map lnl_vnn_req_status_0_map[];
572
-
extern const struct pmc_bit_map lnl_vnn_req_status_1_map[];
573
-
extern const struct pmc_bit_map lnl_vnn_req_status_2_map[];
574
-
extern const struct pmc_bit_map lnl_vnn_req_status_3_map[];
575
-
extern const struct pmc_bit_map lnl_vnn_misc_status_map[];
576
-
extern const struct pmc_bit_map *lnl_lpm_maps[];
577
-
extern const struct pmc_bit_map *lnl_blk_maps[];
578
-
extern const struct pmc_bit_map lnl_pfear_map[];
579
-
extern const struct pmc_bit_map *ext_lnl_pfear_map[];
580
-
extern const struct pmc_bit_map lnl_signal_status_map[];
581
-
582
-
/* ARL */
583
-
extern const struct pmc_bit_map arl_socs_ltr_show_map[];
584
-
extern const struct pmc_bit_map arl_socs_clocksource_status_map[];
585
-
extern const struct pmc_bit_map arl_socs_power_gating_status_0_map[];
586
-
extern const struct pmc_bit_map arl_socs_power_gating_status_1_map[];
587
-
extern const struct pmc_bit_map arl_socs_power_gating_status_2_map[];
588
-
extern const struct pmc_bit_map arl_socs_d3_status_2_map[];
589
-
extern const struct pmc_bit_map arl_socs_d3_status_3_map[];
590
-
extern const struct pmc_bit_map arl_socs_vnn_req_status_3_map[];
591
-
extern const struct pmc_bit_map *arl_socs_lpm_maps[];
592
-
extern const struct pmc_bit_map arl_socs_pfear_map[];
593
-
extern const struct pmc_bit_map *ext_arl_socs_pfear_map[];
594
-
extern const struct pmc_reg_map arl_socs_reg_map;
595
-
extern const struct pmc_bit_map arl_pchs_ltr_show_map[];
596
-
extern const struct pmc_bit_map arl_pchs_clocksource_status_map[];
597
-
extern const struct pmc_bit_map arl_pchs_power_gating_status_0_map[];
598
-
extern const struct pmc_bit_map arl_pchs_power_gating_status_1_map[];
599
-
extern const struct pmc_bit_map arl_pchs_power_gating_status_2_map[];
600
-
extern const struct pmc_bit_map arl_pchs_d3_status_0_map[];
601
-
extern const struct pmc_bit_map arl_pchs_d3_status_1_map[];
602
-
extern const struct pmc_bit_map arl_pchs_d3_status_2_map[];
603
-
extern const struct pmc_bit_map arl_pchs_d3_status_3_map[];
604
-
extern const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[];
605
-
extern const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[];
606
-
extern const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[];
607
-
extern const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[];
608
-
extern const struct pmc_bit_map arl_pchs_vnn_misc_status_map[];
609
-
extern const struct pmc_bit_map arl_pchs_signal_status_map[];
610
-
extern const struct pmc_bit_map *arl_pchs_lpm_maps[];
611
-
extern const struct pmc_reg_map arl_pchs_reg_map;
612
486
613
487
extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
614
488
extern int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev);
+3
-3
drivers/platform/x86/intel/pmc/icl.c
+3
-3
drivers/platform/x86/intel/pmc/icl.c
···
10
10
11
11
#include "core.h"
12
12
13
-
const struct pmc_bit_map icl_pfear_map[] = {
13
+
static const struct pmc_bit_map icl_pfear_map[] = {
14
14
{"RES_65", BIT(0)},
15
15
{"RES_66", BIT(1)},
16
16
{"RES_67", BIT(2)},
···
22
22
{}
23
23
};
24
24
25
-
const struct pmc_bit_map *ext_icl_pfear_map[] = {
25
+
static const struct pmc_bit_map *ext_icl_pfear_map[] = {
26
26
/*
27
27
* Check intel_pmc_core_ids[] users of icl_reg_map for
28
28
* a list of core SoCs using this.
···
32
32
NULL
33
33
};
34
34
35
-
const struct pmc_reg_map icl_reg_map = {
35
+
static const struct pmc_reg_map icl_reg_map = {
36
36
.pfear_sts = ext_icl_pfear_map,
37
37
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
38
38
.slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP,
+21
-21
drivers/platform/x86/intel/pmc/lnl.c
+21
-21
drivers/platform/x86/intel/pmc/lnl.c
···
13
13
14
14
#include "core.h"
15
15
16
-
const struct pmc_bit_map lnl_ltr_show_map[] = {
16
+
static const struct pmc_bit_map lnl_ltr_show_map[] = {
17
17
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
18
18
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
19
19
{"SATA", CNP_PMC_LTR_SATA},
···
55
55
{}
56
56
};
57
57
58
-
const struct pmc_bit_map lnl_power_gating_status_0_map[] = {
58
+
static const struct pmc_bit_map lnl_power_gating_status_0_map[] = {
59
59
{"PMC_PGD0_PG_STS", BIT(0), 0},
60
60
{"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0},
61
61
{"ESPISPI_PGD0_PG_STS", BIT(2), 0},
···
91
91
{}
92
92
};
93
93
94
-
const struct pmc_bit_map lnl_power_gating_status_1_map[] = {
94
+
static const struct pmc_bit_map lnl_power_gating_status_1_map[] = {
95
95
{"USBR0_PGD0_PG_STS", BIT(0), 1},
96
96
{"SUSRAM_PGD0_PG_STS", BIT(1), 1},
97
97
{"SMT1_PGD0_PG_STS", BIT(2), 1},
···
127
127
{}
128
128
};
129
129
130
-
const struct pmc_bit_map lnl_power_gating_status_2_map[] = {
130
+
static const struct pmc_bit_map lnl_power_gating_status_2_map[] = {
131
131
{"PSF8_PGD0_PG_STS", BIT(0), 0},
132
132
{"SBR16B2_PGD0_PG_STS", BIT(1), 0},
133
133
{"D2D_IPU_PGD0_PG_STS", BIT(2), 1},
···
163
163
{}
164
164
};
165
165
166
-
const struct pmc_bit_map lnl_d3_status_0_map[] = {
166
+
static const struct pmc_bit_map lnl_d3_status_0_map[] = {
167
167
{"LPSS_D3_STS", BIT(3), 1},
168
168
{"XDCI_D3_STS", BIT(4), 1},
169
169
{"XHCI_D3_STS", BIT(5), 1},
···
175
175
{}
176
176
};
177
177
178
-
const struct pmc_bit_map lnl_d3_status_1_map[] = {
178
+
static const struct pmc_bit_map lnl_d3_status_1_map[] = {
179
179
{"OSSE_SMT1_D3_STS", BIT(7), 0},
180
180
{"GBE_D3_STS", BIT(19), 0},
181
181
{"ITSS_D3_STS", BIT(23), 0},
···
185
185
{}
186
186
};
187
187
188
-
const struct pmc_bit_map lnl_d3_status_2_map[] = {
188
+
static const struct pmc_bit_map lnl_d3_status_2_map[] = {
189
189
{"ESE_D3_STS", BIT(0), 0},
190
190
{"CSMERTC_D3_STS", BIT(1), 0},
191
191
{"SUSRAM_D3_STS", BIT(2), 0},
···
205
205
{}
206
206
};
207
207
208
-
const struct pmc_bit_map lnl_d3_status_3_map[] = {
208
+
static const struct pmc_bit_map lnl_d3_status_3_map[] = {
209
209
{"THC0_D3_STS", BIT(14), 1},
210
210
{"THC1_D3_STS", BIT(15), 1},
211
211
{"OSSE_SMT3_D3_STS", BIT(21), 0},
···
213
213
{}
214
214
};
215
215
216
-
const struct pmc_bit_map lnl_vnn_req_status_0_map[] = {
216
+
static const struct pmc_bit_map lnl_vnn_req_status_0_map[] = {
217
217
{"LPSS_VNN_REQ_STS", BIT(3), 1},
218
218
{"OSSE_VNN_REQ_STS", BIT(15), 1},
219
219
{"ESPISPI_VNN_REQ_STS", BIT(18), 1},
220
220
{}
221
221
};
222
222
223
-
const struct pmc_bit_map lnl_vnn_req_status_1_map[] = {
223
+
static const struct pmc_bit_map lnl_vnn_req_status_1_map[] = {
224
224
{"NPK_VNN_REQ_STS", BIT(4), 1},
225
225
{"OSSE_SMT1_VNN_REQ_STS", BIT(7), 1},
226
226
{"DFXAGG_VNN_REQ_STS", BIT(8), 0},
···
232
232
{}
233
233
};
234
234
235
-
const struct pmc_bit_map lnl_vnn_req_status_2_map[] = {
235
+
static const struct pmc_bit_map lnl_vnn_req_status_2_map[] = {
236
236
{"eSE_VNN_REQ_STS", BIT(0), 1},
237
237
{"CSMERTC_VNN_REQ_STS", BIT(1), 1},
238
238
{"CSE_VNN_REQ_STS", BIT(4), 1},
···
249
249
{}
250
250
};
251
251
252
-
const struct pmc_bit_map lnl_vnn_req_status_3_map[] = {
252
+
static const struct pmc_bit_map lnl_vnn_req_status_3_map[] = {
253
253
{"DISP_SHIM_VNN_REQ_STS", BIT(2), 0},
254
254
{"DTS0_VNN_REQ_STS", BIT(7), 0},
255
255
{"GPIOCOM5_VNN_REQ_STS", BIT(11), 2},
256
256
{}
257
257
};
258
258
259
-
const struct pmc_bit_map lnl_vnn_misc_status_map[] = {
259
+
static const struct pmc_bit_map lnl_vnn_misc_status_map[] = {
260
260
{"CPU_C10_REQ_STS", BIT(0), 0},
261
261
{"TS_OFF_REQ_STS", BIT(1), 0},
262
262
{"PNDE_MET_REQ_STS", BIT(2), 1},
···
292
292
{}
293
293
};
294
294
295
-
const struct pmc_bit_map lnl_clocksource_status_map[] = {
295
+
static const struct pmc_bit_map lnl_clocksource_status_map[] = {
296
296
{"AON2_OFF_STS", BIT(0), 0},
297
297
{"AON3_OFF_STS", BIT(1), 1},
298
298
{"AON4_OFF_STS", BIT(2), 1},
···
317
317
{}
318
318
};
319
319
320
-
const struct pmc_bit_map lnl_signal_status_map[] = {
320
+
static const struct pmc_bit_map lnl_signal_status_map[] = {
321
321
{"LSX_Wake0_STS", BIT(0), 0},
322
322
{"LSX_Wake1_STS", BIT(1), 0},
323
323
{"LSX_Wake2_STS", BIT(2), 0},
···
337
337
{}
338
338
};
339
339
340
-
const struct pmc_bit_map lnl_rsc_status_map[] = {
340
+
static const struct pmc_bit_map lnl_rsc_status_map[] = {
341
341
{"Memory", 0, 1},
342
342
{"PSF0", 0, 1},
343
343
{"PSF4", 0, 1},
···
349
349
{}
350
350
};
351
351
352
-
const struct pmc_bit_map *lnl_lpm_maps[] = {
352
+
static const struct pmc_bit_map *lnl_lpm_maps[] = {
353
353
lnl_clocksource_status_map,
354
354
lnl_power_gating_status_0_map,
355
355
lnl_power_gating_status_1_map,
···
367
367
NULL
368
368
};
369
369
370
-
const struct pmc_bit_map *lnl_blk_maps[] = {
370
+
static const struct pmc_bit_map *lnl_blk_maps[] = {
371
371
lnl_power_gating_status_0_map,
372
372
lnl_power_gating_status_1_map,
373
373
lnl_power_gating_status_2_map,
···
386
386
NULL
387
387
};
388
388
389
-
const struct pmc_bit_map lnl_pfear_map[] = {
389
+
static const struct pmc_bit_map lnl_pfear_map[] = {
390
390
{"PMC_0", BIT(0)},
391
391
{"FUSE_OSSE", BIT(1)},
392
392
{"ESPISPI", BIT(2)},
···
498
498
{}
499
499
};
500
500
501
-
const struct pmc_bit_map *ext_lnl_pfear_map[] = {
501
+
static const struct pmc_bit_map *ext_lnl_pfear_map[] = {
502
502
lnl_pfear_map,
503
503
NULL
504
504
};
505
505
506
-
const struct pmc_reg_map lnl_socm_reg_map = {
506
+
static const struct pmc_reg_map lnl_socm_reg_map = {
507
507
.pfear_sts = ext_lnl_pfear_map,
508
508
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
509
509
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
+32
-32
drivers/platform/x86/intel/pmc/mtl.c
+32
-32
drivers/platform/x86/intel/pmc/mtl.c
···
102
102
{}
103
103
};
104
104
105
-
const struct pmc_bit_map *ext_mtl_socm_pfear_map[] = {
105
+
static const struct pmc_bit_map *ext_mtl_socm_pfear_map[] = {
106
106
mtl_socm_pfear_map,
107
107
NULL
108
108
};
109
109
110
-
const struct pmc_bit_map mtl_socm_ltr_show_map[] = {
110
+
static const struct pmc_bit_map mtl_socm_ltr_show_map[] = {
111
111
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
112
112
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
113
113
{"SATA", CNP_PMC_LTR_SATA},
···
141
141
{}
142
142
};
143
143
144
-
const struct pmc_bit_map mtl_socm_clocksource_status_map[] = {
144
+
static const struct pmc_bit_map mtl_socm_clocksource_status_map[] = {
145
145
{"AON2_OFF_STS", BIT(0)},
146
146
{"AON3_OFF_STS", BIT(1)},
147
147
{"AON4_OFF_STS", BIT(2)},
···
167
167
{}
168
168
};
169
169
170
-
const struct pmc_bit_map mtl_socm_power_gating_status_0_map[] = {
170
+
static const struct pmc_bit_map mtl_socm_power_gating_status_0_map[] = {
171
171
{"PMC_PGD0_PG_STS", BIT(0)},
172
172
{"DMI_PGD0_PG_STS", BIT(1)},
173
173
{"ESPISPI_PGD0_PG_STS", BIT(2)},
···
203
203
{}
204
204
};
205
205
206
-
const struct pmc_bit_map mtl_socm_power_gating_status_1_map[] = {
206
+
static const struct pmc_bit_map mtl_socm_power_gating_status_1_map[] = {
207
207
{"USBR0_PGD0_PG_STS", BIT(0)},
208
208
{"SUSRAM_PGD0_PG_STS", BIT(1)},
209
209
{"SMT1_PGD0_PG_STS", BIT(2)},
···
239
239
{}
240
240
};
241
241
242
-
const struct pmc_bit_map mtl_socm_power_gating_status_2_map[] = {
242
+
static const struct pmc_bit_map mtl_socm_power_gating_status_2_map[] = {
243
243
{"PSF8_PGD0_PG_STS", BIT(0)},
244
244
{"FIA_PGD0_PG_STS", BIT(1)},
245
245
{"SOC_D2D_PGD1_PG_STS", BIT(2)},
···
291
291
{}
292
292
};
293
293
294
-
const struct pmc_bit_map mtl_socm_d3_status_2_map[] = {
294
+
static const struct pmc_bit_map mtl_socm_d3_status_2_map[] = {
295
295
{"GNA_D3_STS", BIT(0)},
296
296
{"CSMERTC_D3_STS", BIT(1)},
297
297
{"SUSRAM_D3_STS", BIT(2)},
···
310
310
{}
311
311
};
312
312
313
-
const struct pmc_bit_map mtl_socm_d3_status_3_map[] = {
313
+
static const struct pmc_bit_map mtl_socm_d3_status_3_map[] = {
314
314
{"ESE_D3_STS", BIT(2)},
315
315
{"GBETSN_D3_STS", BIT(13)},
316
316
{"THC0_D3_STS", BIT(14)},
···
353
353
{}
354
354
};
355
355
356
-
const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[] = {
356
+
static const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[] = {
357
357
{"ESE_VNN_REQ_STS", BIT(2)},
358
358
{"DTS0_VNN_REQ_STS", BIT(7)},
359
359
{"GPIOCOM5_VNN_REQ_STS", BIT(11)},
···
432
432
{}
433
433
};
434
434
435
-
const struct pmc_bit_map *mtl_socm_lpm_maps[] = {
435
+
static const struct pmc_bit_map *mtl_socm_lpm_maps[] = {
436
436
mtl_socm_clocksource_status_map,
437
437
mtl_socm_power_gating_status_0_map,
438
438
mtl_socm_power_gating_status_1_map,
···
476
476
.lpm_reg_index = MTL_LPM_REG_INDEX,
477
477
};
478
478
479
-
const struct pmc_bit_map mtl_ioep_pfear_map[] = {
479
+
static const struct pmc_bit_map mtl_ioep_pfear_map[] = {
480
480
{"PMC_0", BIT(0)},
481
481
{"OPI", BIT(1)},
482
482
{"TCSS", BIT(2)},
···
563
563
{}
564
564
};
565
565
566
-
const struct pmc_bit_map *ext_mtl_ioep_pfear_map[] = {
566
+
static const struct pmc_bit_map *ext_mtl_ioep_pfear_map[] = {
567
567
mtl_ioep_pfear_map,
568
568
NULL
569
569
};
570
570
571
-
const struct pmc_bit_map mtl_ioep_ltr_show_map[] = {
571
+
static const struct pmc_bit_map mtl_ioep_ltr_show_map[] = {
572
572
{"SOUTHPORT_A", CNP_PMC_LTR_SPA},
573
573
{"SOUTHPORT_B", CNP_PMC_LTR_SPB},
574
574
{"SATA", CNP_PMC_LTR_SATA},
···
600
600
{}
601
601
};
602
602
603
-
const struct pmc_bit_map mtl_ioep_clocksource_status_map[] = {
603
+
static const struct pmc_bit_map mtl_ioep_clocksource_status_map[] = {
604
604
{"AON2_OFF_STS", BIT(0)},
605
605
{"AON3_OFF_STS", BIT(1)},
606
606
{"AON4_OFF_STS", BIT(2)},
···
623
623
{}
624
624
};
625
625
626
-
const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[] = {
626
+
static const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[] = {
627
627
{"PMC_PGD0_PG_STS", BIT(0)},
628
628
{"DMI_PGD0_PG_STS", BIT(1)},
629
629
{"TCSS_PGD0_PG_STS", BIT(2)},
···
650
650
{}
651
651
};
652
652
653
-
const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[] = {
653
+
static const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[] = {
654
654
{"PSF9_PGD0_PG_STS", BIT(0)},
655
655
{"MPFPW4_PGD0_PG_STS", BIT(1)},
656
656
{"SBR0_PGD0_PG_STS", BIT(8)},
···
668
668
{}
669
669
};
670
670
671
-
const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[] = {
671
+
static const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[] = {
672
672
{"FIA_PGD0_PG_STS", BIT(1)},
673
673
{"FIA_P_PGD0_PG_STS", BIT(3)},
674
674
{"TAM_PGD0_PG_STS", BIT(4)},
···
680
680
{}
681
681
};
682
682
683
-
const struct pmc_bit_map mtl_ioep_d3_status_0_map[] = {
683
+
static const struct pmc_bit_map mtl_ioep_d3_status_0_map[] = {
684
684
{"SPF_D3_STS", BIT(0)},
685
685
{"SPA_D3_STS", BIT(12)},
686
686
{"SPB_D3_STS", BIT(13)},
···
691
691
{}
692
692
};
693
693
694
-
const struct pmc_bit_map mtl_ioep_d3_status_1_map[] = {
694
+
static const struct pmc_bit_map mtl_ioep_d3_status_1_map[] = {
695
695
{"GBETSN1_D3_STS", BIT(14)},
696
696
{"P2S_D3_STS", BIT(24)},
697
697
{}
698
698
};
699
699
700
-
const struct pmc_bit_map mtl_ioep_d3_status_2_map[] = {
700
+
static const struct pmc_bit_map mtl_ioep_d3_status_2_map[] = {
701
701
{}
702
702
};
703
703
704
-
const struct pmc_bit_map mtl_ioep_d3_status_3_map[] = {
704
+
static const struct pmc_bit_map mtl_ioep_d3_status_3_map[] = {
705
705
{"GBETSN_D3_STS", BIT(13)},
706
706
{"ACE_D3_STS", BIT(23)},
707
707
{}
708
708
};
709
709
710
-
const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[] = {
710
+
static const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[] = {
711
711
{"FIA_VNN_REQ_STS", BIT(17)},
712
712
{}
713
713
};
714
714
715
-
const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[] = {
715
+
static const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[] = {
716
716
{"DFXAGG_VNN_REQ_STS", BIT(8)},
717
717
{}
718
718
};
719
719
720
-
const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[] = {
720
+
static const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[] = {
721
721
{}
722
722
};
723
723
724
-
const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[] = {
724
+
static const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[] = {
725
725
{"DTS0_VNN_REQ_STS", BIT(7)},
726
726
{"DISP_VNN_REQ_STS", BIT(19)},
727
727
{}
728
728
};
729
729
730
-
const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[] = {
730
+
static const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[] = {
731
731
{"CPU_C10_REQ_STS", BIT(0)},
732
732
{"TS_OFF_REQ_STS", BIT(1)},
733
733
{"PNDE_MET_REQ_STS", BIT(2)},
···
762
762
{}
763
763
};
764
764
765
-
const struct pmc_bit_map *mtl_ioep_lpm_maps[] = {
765
+
static const struct pmc_bit_map *mtl_ioep_lpm_maps[] = {
766
766
mtl_ioep_clocksource_status_map,
767
767
mtl_ioep_power_gating_status_0_map,
768
768
mtl_ioep_power_gating_status_1_map,
···
800
800
.lpm_reg_index = MTL_LPM_REG_INDEX,
801
801
};
802
802
803
-
const struct pmc_bit_map mtl_ioem_pfear_map[] = {
803
+
static const struct pmc_bit_map mtl_ioem_pfear_map[] = {
804
804
{"PMC_0", BIT(0)},
805
805
{"OPI", BIT(1)},
806
806
{"TCSS", BIT(2)},
···
887
887
{}
888
888
};
889
889
890
-
const struct pmc_bit_map *ext_mtl_ioem_pfear_map[] = {
890
+
static const struct pmc_bit_map *ext_mtl_ioem_pfear_map[] = {
891
891
mtl_ioem_pfear_map,
892
892
NULL
893
893
};
894
894
895
-
const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[] = {
895
+
static const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[] = {
896
896
{"PSF9_PGD0_PG_STS", BIT(0)},
897
897
{"MPFPW4_PGD0_PG_STS", BIT(1)},
898
898
{"SBR0_PGD0_PG_STS", BIT(8)},
···
909
909
{}
910
910
};
911
911
912
-
const struct pmc_bit_map *mtl_ioem_lpm_maps[] = {
912
+
static const struct pmc_bit_map *mtl_ioem_lpm_maps[] = {
913
913
mtl_ioep_clocksource_status_map,
914
914
mtl_ioep_power_gating_status_0_map,
915
915
mtl_ioem_power_gating_status_1_map,
···
927
927
NULL
928
928
};
929
929
930
-
const struct pmc_reg_map mtl_ioem_reg_map = {
930
+
static const struct pmc_reg_map mtl_ioem_reg_map = {
931
931
.regmap_length = MTL_IOE_PMC_MMIO_REG_LEN,
932
932
.pfear_sts = ext_mtl_ioem_pfear_map,
933
933
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
+6
-6
drivers/platform/x86/intel/pmc/spt.c
+6
-6
drivers/platform/x86/intel/pmc/spt.c
···
12
12
13
13
#include "core.h"
14
14
15
-
const struct pmc_bit_map spt_pll_map[] = {
15
+
static const struct pmc_bit_map spt_pll_map[] = {
16
16
{"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
17
17
{"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
18
18
{"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
···
20
20
{}
21
21
};
22
22
23
-
const struct pmc_bit_map spt_mphy_map[] = {
23
+
static const struct pmc_bit_map spt_mphy_map[] = {
24
24
{"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
25
25
{"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
26
26
{"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
···
40
40
{}
41
41
};
42
42
43
-
const struct pmc_bit_map spt_pfear_map[] = {
43
+
static const struct pmc_bit_map spt_pfear_map[] = {
44
44
{"PMC", SPT_PMC_BIT_PMC},
45
45
{"OPI-DMI", SPT_PMC_BIT_OPI},
46
46
{"SPI / eSPI", SPT_PMC_BIT_SPI},
···
84
84
{}
85
85
};
86
86
87
-
const struct pmc_bit_map *ext_spt_pfear_map[] = {
87
+
static const struct pmc_bit_map *ext_spt_pfear_map[] = {
88
88
/*
89
89
* Check intel_pmc_core_ids[] users of spt_reg_map for
90
90
* a list of core SoCs using this.
···
93
93
NULL
94
94
};
95
95
96
-
const struct pmc_bit_map spt_ltr_show_map[] = {
96
+
static const struct pmc_bit_map spt_ltr_show_map[] = {
97
97
{"SOUTHPORT_A", SPT_PMC_LTR_SPA},
98
98
{"SOUTHPORT_B", SPT_PMC_LTR_SPB},
99
99
{"SATA", SPT_PMC_LTR_SATA},
···
118
118
{}
119
119
};
120
120
121
-
const struct pmc_reg_map spt_reg_map = {
121
+
static const struct pmc_reg_map spt_reg_map = {
122
122
.pfear_sts = ext_spt_pfear_map,
123
123
.mphy_sts = spt_mphy_map,
124
124
.pll_sts = spt_pll_map,
+10
-10
drivers/platform/x86/intel/pmc/tgl.c
+10
-10
drivers/platform/x86/intel/pmc/tgl.c
···
18
18
PCH_LP
19
19
};
20
20
21
-
const struct pmc_bit_map tgl_pfear_map[] = {
21
+
static const struct pmc_bit_map tgl_pfear_map[] = {
22
22
{"PSF9", BIT(0)},
23
23
{"RES_66", BIT(1)},
24
24
{"RES_67", BIT(2)},
···
29
29
{}
30
30
};
31
31
32
-
const struct pmc_bit_map *ext_tgl_pfear_map[] = {
32
+
static const struct pmc_bit_map *ext_tgl_pfear_map[] = {
33
33
/*
34
34
* Check intel_pmc_core_ids[] users of tgl_reg_map for
35
35
* a list of core SoCs using this.
···
39
39
NULL
40
40
};
41
41
42
-
const struct pmc_bit_map tgl_clocksource_status_map[] = {
42
+
static const struct pmc_bit_map tgl_clocksource_status_map[] = {
43
43
{"USB2PLL_OFF_STS", BIT(18)},
44
44
{"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)},
45
45
{"PCIe_Gen3PLL_OFF_STS", BIT(20)},
···
55
55
{}
56
56
};
57
57
58
-
const struct pmc_bit_map tgl_power_gating_status_map[] = {
58
+
static const struct pmc_bit_map tgl_power_gating_status_map[] = {
59
59
{"CSME_PG_STS", BIT(0)},
60
60
{"SATA_PG_STS", BIT(1)},
61
61
{"xHCI_PG_STS", BIT(2)},
···
83
83
{}
84
84
};
85
85
86
-
const struct pmc_bit_map tgl_d3_status_map[] = {
86
+
static const struct pmc_bit_map tgl_d3_status_map[] = {
87
87
{"ADSP_D3_STS", BIT(0)},
88
88
{"SATA_D3_STS", BIT(1)},
89
89
{"xHCI0_D3_STS", BIT(2)},
···
98
98
{}
99
99
};
100
100
101
-
const struct pmc_bit_map tgl_vnn_req_status_map[] = {
101
+
static const struct pmc_bit_map tgl_vnn_req_status_map[] = {
102
102
{"GPIO_COM0_VNN_REQ_STS", BIT(1)},
103
103
{"GPIO_COM1_VNN_REQ_STS", BIT(2)},
104
104
{"GPIO_COM2_VNN_REQ_STS", BIT(3)},
···
123
123
{}
124
124
};
125
125
126
-
const struct pmc_bit_map tgl_vnn_misc_status_map[] = {
126
+
static const struct pmc_bit_map tgl_vnn_misc_status_map[] = {
127
127
{"CPU_C10_REQ_STS_0", BIT(0)},
128
128
{"PCIe_LPM_En_REQ_STS_3", BIT(3)},
129
129
{"ITH_REQ_STS_5", BIT(5)},
···
175
175
{}
176
176
};
177
177
178
-
const struct pmc_bit_map *tgl_lpm_maps[] = {
178
+
static const struct pmc_bit_map *tgl_lpm_maps[] = {
179
179
tgl_clocksource_status_map,
180
180
tgl_power_gating_status_map,
181
181
tgl_d3_status_map,
···
185
185
NULL
186
186
};
187
187
188
-
const struct pmc_reg_map tgl_reg_map = {
188
+
static const struct pmc_reg_map tgl_reg_map = {
189
189
.pfear_sts = ext_tgl_pfear_map,
190
190
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
191
191
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
···
210
210
.etr3_offset = ETR3_OFFSET,
211
211
};
212
212
213
-
const struct pmc_reg_map tgl_h_reg_map = {
213
+
static const struct pmc_reg_map tgl_h_reg_map = {
214
214
.pfear_sts = ext_tgl_pfear_map,
215
215
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
216
216
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,