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linux
ASoC: mediatek: mt7986: support etdm in platform driver
Add mt7986 etdm dai driver support.
Signed-off-by: Maso Huang <maso.huang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230817101338.18782-3-maso.huang@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Maso Huang
and committed by
Mark Brown
9f8df795
c4c3c32d
+411
+411
sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
+411
sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek ALSA SoC Audio DAI eTDM Control
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*
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* Copyright (c) 2023 MediaTek Inc.
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* Authors: Vic Wu <vic.wu@mediatek.com>
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* Maso Huang <maso.huang@mediatek.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/regmap.h>
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#include <sound/pcm_params.h>
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#include "mt7986-afe-common.h"
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#include "mt7986-reg.h"
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#define HOPPING_CLK 0
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#define APLL_CLK 1
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#define MTK_DAI_ETDM_FORMAT_I2S 0
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#define MTK_DAI_ETDM_FORMAT_DSPA 4
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#define MTK_DAI_ETDM_FORMAT_DSPB 5
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enum {
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MTK_ETDM_RATE_8K = 0,
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MTK_ETDM_RATE_12K = 1,
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MTK_ETDM_RATE_16K = 2,
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MTK_ETDM_RATE_24K = 3,
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MTK_ETDM_RATE_32K = 4,
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MTK_ETDM_RATE_48K = 5,
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MTK_ETDM_RATE_96K = 7,
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MTK_ETDM_RATE_192K = 9,
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MTK_ETDM_RATE_11K = 16,
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MTK_ETDM_RATE_22K = 17,
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MTK_ETDM_RATE_44K = 18,
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MTK_ETDM_RATE_88K = 19,
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MTK_ETDM_RATE_176K = 20,
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};
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struct mtk_dai_etdm_priv {
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bool bck_inv;
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bool lrck_inv;
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bool slave_mode;
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unsigned int format;
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};
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static unsigned int mt7986_etdm_rate_transform(struct device *dev, unsigned int rate)
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{
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switch (rate) {
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case 8000:
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return MTK_ETDM_RATE_8K;
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case 11025:
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return MTK_ETDM_RATE_11K;
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case 12000:
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return MTK_ETDM_RATE_12K;
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case 16000:
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return MTK_ETDM_RATE_16K;
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case 22050:
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return MTK_ETDM_RATE_22K;
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case 24000:
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return MTK_ETDM_RATE_24K;
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case 32000:
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return MTK_ETDM_RATE_32K;
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case 44100:
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return MTK_ETDM_RATE_44K;
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case 48000:
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return MTK_ETDM_RATE_48K;
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case 88200:
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return MTK_ETDM_RATE_88K;
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case 96000:
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return MTK_ETDM_RATE_96K;
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case 176400:
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return MTK_ETDM_RATE_176K;
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case 192000:
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return MTK_ETDM_RATE_192K;
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default:
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dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n",
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__func__, rate, MTK_ETDM_RATE_48K);
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return MTK_ETDM_RATE_48K;
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}
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}
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static int get_etdm_wlen(unsigned int bitwidth)
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{
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return bitwidth <= 16 ? 16 : 32;
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}
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/* dai component */
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/* interconnection */
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static const struct snd_kcontrol_new o124_mix[] = {
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SOC_DAPM_SINGLE_AUTODISABLE("I032_Switch", AFE_CONN124_1, 0, 1, 0),
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};
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static const struct snd_kcontrol_new o125_mix[] = {
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SOC_DAPM_SINGLE_AUTODISABLE("I033_Switch", AFE_CONN125_1, 1, 1, 0),
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};
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static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = {
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/* DL */
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SND_SOC_DAPM_MIXER("I150", SND_SOC_NOPM, 0, 0, NULL, 0),
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SND_SOC_DAPM_MIXER("I151", SND_SOC_NOPM, 0, 0, NULL, 0),
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/* UL */
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SND_SOC_DAPM_MIXER("O124", SND_SOC_NOPM, 0, 0, o124_mix, ARRAY_SIZE(o124_mix)),
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SND_SOC_DAPM_MIXER("O125", SND_SOC_NOPM, 0, 0, o125_mix, ARRAY_SIZE(o125_mix)),
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};
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static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = {
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{"I150", NULL, "ETDM Capture"},
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{"I151", NULL, "ETDM Capture"},
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{"ETDM Playback", NULL, "O124"},
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{"ETDM Playback", NULL, "O125"},
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{"O124", "I032_Switch", "I032"},
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{"O125", "I033_Switch", "I033"},
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};
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/* dai ops */
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static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
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struct mt7986_afe_private *afe_priv = afe->platform_priv;
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int ret;
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ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks);
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if (ret)
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return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n");
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+
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regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK, 0);
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regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK, 0);
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return 0;
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}
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static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
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struct mt7986_afe_private *afe_priv = afe->platform_priv;
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regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK,
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CLK_OUT5_PDN);
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regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK,
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CLK_IN5_PDN);
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clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks);
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}
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static unsigned int get_etdm_ch_fixup(unsigned int channels)
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{
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if (channels > 16)
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return 24;
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else if (channels > 8)
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return 16;
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else if (channels > 4)
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return 8;
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else if (channels > 2)
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return 4;
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else
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return 2;
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}
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static int mtk_dai_etdm_config(struct mtk_base_afe *afe,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai,
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int stream)
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{
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struct mt7986_afe_private *afe_priv = afe->platform_priv;
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struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
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unsigned int rate = params_rate(params);
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unsigned int etdm_rate = mt7986_etdm_rate_transform(afe->dev, rate);
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unsigned int afe_rate = mt7986_afe_rate_transform(afe->dev, rate);
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unsigned int channels = params_channels(params);
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unsigned int bit_width = params_width(params);
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unsigned int wlen = get_etdm_wlen(bit_width);
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unsigned int val = 0;
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unsigned int mask = 0;
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dev_dbg(afe->dev, "%s(), stream %d, rate %u, bitwidth %u\n",
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__func__, stream, rate, bit_width);
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/* CON0 */
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mask |= ETDM_BIT_LEN_MASK;
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val |= FIELD_PREP(ETDM_BIT_LEN_MASK, bit_width - 1);
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mask |= ETDM_WRD_LEN_MASK;
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val |= FIELD_PREP(ETDM_WRD_LEN_MASK, wlen - 1);
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mask |= ETDM_FMT_MASK;
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val |= FIELD_PREP(ETDM_FMT_MASK, etdm_data->format);
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mask |= ETDM_CH_NUM_MASK;
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val |= FIELD_PREP(ETDM_CH_NUM_MASK, get_etdm_ch_fixup(channels) - 1);
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mask |= RELATCH_SRC_MASK;
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val |= FIELD_PREP(RELATCH_SRC_MASK, APLL_CLK);
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+
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switch (stream) {
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case SNDRV_PCM_STREAM_PLAYBACK:
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/* set ETDM_OUT5_CON0 */
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regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, mask, val);
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/* set ETDM_OUT5_CON4 */
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regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
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OUT_RELATCH_MASK, OUT_RELATCH(afe_rate));
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regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
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OUT_CLK_SRC_MASK, OUT_CLK_SRC(APLL_CLK));
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regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
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OUT_SEL_FS_MASK, OUT_SEL_FS(etdm_rate));
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+
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/* set ETDM_OUT5_CON5 */
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regmap_update_bits(afe->regmap, ETDM_OUT5_CON5,
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ETDM_CLK_DIV_MASK, ETDM_CLK_DIV);
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break;
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case SNDRV_PCM_STREAM_CAPTURE:
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/* set ETDM_IN5_CON0 */
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regmap_update_bits(afe->regmap, ETDM_IN5_CON0, mask, val);
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regmap_update_bits(afe->regmap, ETDM_IN5_CON0,
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ETDM_SYNC_MASK, ETDM_SYNC);
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+
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/* set ETDM_IN5_CON2 */
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regmap_update_bits(afe->regmap, ETDM_IN5_CON2,
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IN_CLK_SRC_MASK, IN_CLK_SRC(APLL_CLK));
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+
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/* set ETDM_IN5_CON3 */
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regmap_update_bits(afe->regmap, ETDM_IN5_CON3,
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IN_SEL_FS_MASK, IN_SEL_FS(etdm_rate));
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+
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/* set ETDM_IN5_CON4 */
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regmap_update_bits(afe->regmap, ETDM_IN5_CON4,
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IN_RELATCH_MASK, IN_RELATCH(afe_rate));
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break;
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default:
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break;
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}
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return 0;
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}
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static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
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+
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mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
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mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
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return 0;
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}
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static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
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+
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dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK,
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ETDM_EN);
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regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK,
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ETDM_EN);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK,
265
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0);
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regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK,
267
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0);
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break;
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default:
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break;
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}
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return 0;
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}
275
+
276
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static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
277
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{
278
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struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
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struct mt7986_afe_private *afe_priv = afe->platform_priv;
280
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struct mtk_dai_etdm_priv *etdm_data;
281
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void *priv_data;
282
+
283
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switch (dai->id) {
284
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case MT7986_DAI_ETDM:
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break;
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default:
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dev_warn(afe->dev, "%s(), id %d not support\n",
288
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__func__, dai->id);
289
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return -EINVAL;
290
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}
291
+
292
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priv_data = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_etdm_priv),
293
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GFP_KERNEL);
294
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if (!priv_data)
295
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return -ENOMEM;
296
+
297
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afe_priv->dai_priv[dai->id] = priv_data;
298
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etdm_data = afe_priv->dai_priv[dai->id];
299
+
300
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
301
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case SND_SOC_DAIFMT_I2S:
302
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etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S;
303
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break;
304
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case SND_SOC_DAIFMT_DSP_A:
305
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etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA;
306
+
break;
307
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case SND_SOC_DAIFMT_DSP_B:
308
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etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB;
309
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break;
310
+
default:
311
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return -EINVAL;
312
+
}
313
+
314
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
315
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case SND_SOC_DAIFMT_NB_NF:
316
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etdm_data->bck_inv = false;
317
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etdm_data->lrck_inv = false;
318
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break;
319
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case SND_SOC_DAIFMT_NB_IF:
320
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etdm_data->bck_inv = false;
321
+
etdm_data->lrck_inv = true;
322
+
break;
323
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case SND_SOC_DAIFMT_IB_NF:
324
+
etdm_data->bck_inv = true;
325
+
etdm_data->lrck_inv = false;
326
+
break;
327
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case SND_SOC_DAIFMT_IB_IF:
328
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etdm_data->bck_inv = true;
329
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etdm_data->lrck_inv = true;
330
+
break;
331
+
default:
332
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return -EINVAL;
333
+
}
334
+
335
+
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
336
+
case SND_SOC_DAIFMT_CBM_CFM:
337
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etdm_data->slave_mode = true;
338
+
break;
339
+
case SND_SOC_DAIFMT_CBS_CFS:
340
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etdm_data->slave_mode = false;
341
+
break;
342
+
default:
343
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return -EINVAL;
344
+
}
345
+
346
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return 0;
347
+
}
348
+
349
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static const struct snd_soc_dai_ops mtk_dai_etdm_ops = {
350
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.startup = mtk_dai_etdm_startup,
351
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.shutdown = mtk_dai_etdm_shutdown,
352
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.hw_params = mtk_dai_etdm_hw_params,
353
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.trigger = mtk_dai_etdm_trigger,
354
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.set_fmt = mtk_dai_etdm_set_fmt,
355
+
};
356
+
357
+
/* dai driver */
358
+
#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
359
+
SNDRV_PCM_RATE_88200 |\
360
+
SNDRV_PCM_RATE_96000 |\
361
+
SNDRV_PCM_RATE_176400 |\
362
+
SNDRV_PCM_RATE_192000)
363
+
364
+
#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
365
+
SNDRV_PCM_FMTBIT_S24_LE |\
366
+
SNDRV_PCM_FMTBIT_S32_LE)
367
+
368
+
static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = {
369
+
{
370
+
.name = "ETDM",
371
+
.id = MT7986_DAI_ETDM,
372
+
.capture = {
373
+
.stream_name = "ETDM Capture",
374
+
.channels_min = 1,
375
+
.channels_max = 2,
376
+
.rates = MTK_ETDM_RATES,
377
+
.formats = MTK_ETDM_FORMATS,
378
+
},
379
+
.playback = {
380
+
.stream_name = "ETDM Playback",
381
+
.channels_min = 1,
382
+
.channels_max = 2,
383
+
.rates = MTK_ETDM_RATES,
384
+
.formats = MTK_ETDM_FORMATS,
385
+
},
386
+
.ops = &mtk_dai_etdm_ops,
387
+
.symmetric_rate = 1,
388
+
.symmetric_sample_bits = 1,
389
+
},
390
+
};
391
+
392
+
int mt7986_dai_etdm_register(struct mtk_base_afe *afe)
393
+
{
394
+
struct mtk_base_afe_dai *dai;
395
+
396
+
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
397
+
if (!dai)
398
+
return -ENOMEM;
399
+
400
+
list_add(&dai->list, &afe->sub_dais);
401
+
402
+
dai->dai_drivers = mtk_dai_etdm_driver;
403
+
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver);
404
+
405
+
dai->dapm_widgets = mtk_dai_etdm_widgets;
406
+
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets);
407
+
dai->dapm_routes = mtk_dai_etdm_routes;
408
+
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes);
409
+
410
+
return 0;
411
+
}