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dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains

To configure the camera PLLs and enable the camera GDSCs on SM8450, SM8475,
SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX.
Therefore, update the camcc bindings to include the MXC power domain on
these platforms.

Fixes: 9cbc64745fc6 ("dt-bindings: clock: qcom: Add SM8550 camera clock controller")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-2-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Vladimir Zapolskiy and committed by
Bjorn Andersson a02a8f8c 1a42f4d4

+12 -6
+12 -6
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
··· 37 37 - description: Sleep clock source 38 38 39 39 power-domains: 40 - maxItems: 1 41 40 description: 42 - A phandle and PM domain specifier for the MMCX power domain. 41 + Power domains required for the clock controller to operate 42 + items: 43 + - description: MMCX power domain 44 + - description: MXC power domain 43 45 44 46 required-opps: 45 - maxItems: 1 46 47 description: 47 - A phandle to an OPP node describing required MMCX performance point. 48 + OPP nodes that describe required performance points on power domains 49 + items: 50 + - description: MMCX performance point 51 + - description: MXC performance point 48 52 49 53 reg: 50 54 maxItems: 1 ··· 86 82 <&rpmhcc RPMH_CXO_CLK>, 87 83 <&rpmhcc RPMH_CXO_CLK_A>, 88 84 <&sleep_clk>; 89 - power-domains = <&rpmhpd RPMHPD_MMCX>; 90 - required-opps = <&rpmhpd_opp_low_svs>; 85 + power-domains = <&rpmhpd RPMHPD_MMCX>, 86 + <&rpmhpd RPMHPD_MXC>; 87 + required-opps = <&rpmhpd_opp_low_svs>, 88 + <&rpmhpd_opp_low_svs>; 91 89 #clock-cells = <1>; 92 90 #reset-cells = <1>; 93 91 #power-domain-cells = <1>;