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rswitch: Fix PHY station management clock setting

Fix the MPIC.PSMCS value following the programming example in the
section 6.4.2 Management Data Clock (MDC) Setting, Ethernet MAC IP,
S4 Hardware User Manual Rev.1.00.

The value is calculated by
MPIC.PSMCS = clk[MHz] / (MDC frequency[MHz] * 2) - 1
with the input clock frequency from clk_get_rate() and MDC frequency
of 2.5MHz. Otherwise, this driver cannot communicate PHYs on the R-Car
S4 Starter Kit board.

Fixes: 3590918b5d07 ("net: ethernet: renesas: Add support for "Ethernet Switch"")
Reported-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20230926123054.3976752-1-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Yoshihiro Shimoda and committed by
Jakub Kicinski a0c55bba dfc7f7a9

+14 -1
+12 -1
drivers/net/ethernet/renesas/rswitch.c
··· 4 4 * Copyright (C) 2022 Renesas Electronics Corporation 5 5 */ 6 6 7 + #include <linux/clk.h> 7 8 #include <linux/dma-mapping.h> 8 9 #include <linux/err.h> 9 10 #include <linux/etherdevice.h> ··· 1050 1049 static void rswitch_etha_enable_mii(struct rswitch_etha *etha) 1051 1050 { 1052 1051 rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, 1053 - MPIC_PSMCS(0x05) | MPIC_PSMHT(0x06)); 1052 + MPIC_PSMCS(etha->psmcs) | MPIC_PSMHT(0x06)); 1054 1053 rswitch_modify(etha->addr, MPSM, 0, MPSM_MFF_C45); 1055 1054 } 1056 1055 ··· 1694 1693 etha->index = index; 1695 1694 etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + index * RSWITCH_ETHA_SIZE; 1696 1695 etha->coma_addr = priv->addr; 1696 + 1697 + /* MPIC.PSMCS = (clk [MHz] / (MDC frequency [MHz] * 2) - 1. 1698 + * Calculating PSMCS value as MDC frequency = 2.5MHz. So, multiply 1699 + * both the numerator and the denominator by 10. 1700 + */ 1701 + etha->psmcs = clk_get_rate(priv->clk) / 100000 / (25 * 2) - 1; 1697 1702 } 1698 1703 1699 1704 static int rswitch_device_alloc(struct rswitch_private *priv, int index) ··· 1906 1899 if (!priv) 1907 1900 return -ENOMEM; 1908 1901 spin_lock_init(&priv->lock); 1902 + 1903 + priv->clk = devm_clk_get(&pdev->dev, NULL); 1904 + if (IS_ERR(priv->clk)) 1905 + return PTR_ERR(priv->clk); 1909 1906 1910 1907 attr = soc_device_match(rswitch_soc_no_speed_change); 1911 1908 if (attr)
+2
drivers/net/ethernet/renesas/rswitch.h
··· 915 915 bool external_phy; 916 916 struct mii_bus *mii; 917 917 phy_interface_t phy_interface; 918 + u32 psmcs; 918 919 u8 mac_addr[MAX_ADDR_LEN]; 919 920 int link; 920 921 int speed; ··· 1013 1012 struct rswitch_mfwd mfwd; 1014 1013 1015 1014 spinlock_t lock; /* lock interrupt registers' control */ 1015 + struct clk *clk; 1016 1016 1017 1017 bool etha_no_runtime_change; 1018 1018 bool gwca_halt;