Merge tag 'qcom-arm64-for-6.20-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

+1

Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml

··· 43 43 - qcom,apss-wdt-sm6350 44 44 - qcom,apss-wdt-sm8150 45 45 - qcom,apss-wdt-sm8250 46 + - qcom,apss-wdt-x1e80100 46 47 - const: qcom,kpss-wdt 47 48 - const: qcom,kpss-wdt 48 49 deprecated: true

+47 -2

arch/arm64/boot/dts/qcom/agatti.dtsi

··· 1643 1643 1644 1644 gpu: gpu@5900000 { 1645 1645 compatible = "qcom,adreno-07000200", "qcom,adreno"; 1646 - reg = <0x0 0x05900000 0x0 0x40000>; 1647 - reg-names = "kgsl_3d0_reg_memory"; 1646 + reg = <0x0 0x05900000 0x0 0x40000>, 1647 + <0x0 0x0599e000 0x0 0x1000>, 1648 + <0x0 0x05961000 0x0 0x800>; 1649 + reg-names = "kgsl_3d0_reg_memory", 1650 + "cx_mem", 1651 + "cx_dbgc"; 1648 1652 1649 1653 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1650 1654 ··· 2289 2285 compatible = "qcom,q6adm-routing"; 2290 2286 #sound-dai-cells = <0>; 2291 2287 }; 2288 + }; 2289 + }; 2290 + 2291 + fastrpc { 2292 + compatible = "qcom,fastrpc"; 2293 + qcom,glink-channels = "fastrpcglink-apps-dsp"; 2294 + label = "adsp"; 2295 + 2296 + qcom,non-secure-domain; 2297 + 2298 + #address-cells = <1>; 2299 + #size-cells = <0>; 2300 + 2301 + compute-cb@3 { 2302 + compatible = "qcom,fastrpc-compute-cb"; 2303 + reg = <3>; 2304 + iommus = <&apps_smmu 0x1c3 0x0>; 2305 + }; 2306 + 2307 + compute-cb@4 { 2308 + compatible = "qcom,fastrpc-compute-cb"; 2309 + reg = <4>; 2310 + iommus = <&apps_smmu 0x1c4 0x0>; 2311 + }; 2312 + 2313 + compute-cb@5 { 2314 + compatible = "qcom,fastrpc-compute-cb"; 2315 + reg = <5>; 2316 + iommus = <&apps_smmu 0x1c5 0x0>; 2317 + }; 2318 + 2319 + compute-cb@6 { 2320 + compatible = "qcom,fastrpc-compute-cb"; 2321 + reg = <6>; 2322 + iommus = <&apps_smmu 0x1c6 0x0>; 2323 + }; 2324 + 2325 + compute-cb@7 { 2326 + compatible = "qcom,fastrpc-compute-cb"; 2327 + reg = <7>; 2328 + iommus = <&apps_smmu 0x1c7 0x0>; 2292 2329 }; 2293 2330 }; 2294 2331 };

+8

arch/arm64/boot/dts/qcom/hamoa.dtsi

··· 8360 8360 }; 8361 8361 }; 8362 8362 8363 + apss_watchdog: watchdog@17410000 { 8364 + compatible = "qcom,apss-wdt-x1e80100", "qcom,kpss-wdt"; 8365 + reg = <0x0 0x17410000 0x0 0x1000>; 8366 + clocks = <&sleep_clk>; 8367 + interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 8368 + status = "reserved"; /* Reserved by Gunyah */ 8369 + }; 8370 + 8363 8371 cpucp_mbox: mailbox@17430000 { 8364 8372 compatible = "qcom,x1e80100-cpucp-mbox"; 8365 8373 reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>;

+4 -4

arch/arm64/boot/dts/qcom/msm8916.dtsi

··· 1945 1945 interrupt-names = "wdog", "fatal", "ready", 1946 1946 "handover", "stop-ack"; 1947 1947 1948 - power-domains = <&rpmpd MSM8916_VDDCX>, 1949 - <&rpmpd MSM8916_VDDMX>; 1948 + power-domains = <&rpmpd RPMPD_VDDCX>, 1949 + <&rpmpd RPMPD_VDDMX>; 1950 1950 power-domain-names = "cx", "mx"; 1951 1951 1952 1952 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, ··· 2449 2449 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2450 2450 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 2451 2451 2452 - power-domains = <&rpmpd MSM8916_VDDCX>, 2453 - <&rpmpd MSM8916_VDDMX>; 2452 + power-domains = <&rpmpd RPMPD_VDDCX>, 2453 + <&rpmpd RPMPD_VDDMX>; 2454 2454 power-domain-names = "cx", "mx"; 2455 2455 2456 2456 qcom,smem-states = <&wcnss_smp2p_out 0>;

+5 -5

arch/arm64/boot/dts/qcom/msm8917.dtsi

··· 1070 1070 phys = <&mdss_dsi0_phy>; 1071 1071 1072 1072 operating-points-v2 = <&mdss_dsi0_opp_table>; 1073 - power-domains = <&rpmpd MSM8917_VDDCX>; 1073 + power-domains = <&rpmpd RPMPD_VDDCX>; 1074 1074 1075 1075 #address-cells = <1>; 1076 1076 #size-cells = <0>; ··· 1288 1288 pinctrl-0 = <&sdc1_default>; 1289 1289 pinctrl-1 = <&sdc1_sleep>; 1290 1290 pinctrl-names = "default", "sleep"; 1291 - power-domains = <&rpmpd MSM8917_VDDCX>; 1291 + power-domains = <&rpmpd RPMPD_VDDCX>; 1292 1292 mmc-hs200-1_8v; 1293 1293 mmc-hs400-1_8v; 1294 1294 mmc-ddr-1_8v; ··· 1313 1313 pinctrl-0 = <&sdc2_default>; 1314 1314 pinctrl-1 = <&sdc2_sleep>; 1315 1315 pinctrl-names = "default", "sleep"; 1316 - power-domains = <&rpmpd MSM8917_VDDCX>; 1316 + power-domains = <&rpmpd RPMPD_VDDCX>; 1317 1317 bus-width = <4>; 1318 1318 status = "disabled"; 1319 1319 }; ··· 1517 1517 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1518 1518 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1519 1519 1520 - power-domains = <&rpmpd MSM8917_VDDCX>, 1521 - <&rpmpd MSM8917_VDDMX>; 1520 + power-domains = <&rpmpd RPMPD_VDDCX>, 1521 + <&rpmpd RPMPD_VDDMX>; 1522 1522 power-domain-names = "cx", "mx"; 1523 1523 1524 1524 qcom,smem-states = <&wcnss_smp2p_out 0>;

+6 -6

arch/arm64/boot/dts/qcom/msm8937.dtsi

··· 1122 1122 phys = <&mdss_dsi0_phy>; 1123 1123 1124 1124 operating-points-v2 = <&mdss_dsi0_opp_table>; 1125 - power-domains = <&rpmpd MSM8937_VDDCX>; 1125 + power-domains = <&rpmpd RPMPD_VDDCX>; 1126 1126 1127 1127 #address-cells = <1>; 1128 1128 #size-cells = <0>; ··· 1210 1210 phys = <&mdss_dsi1_phy>; 1211 1211 1212 1212 operating-points-v2 = <&mdss_dsi1_opp_table>; 1213 - power-domains = <&rpmpd MSM8937_VDDCX>; 1213 + power-domains = <&rpmpd RPMPD_VDDCX>; 1214 1214 1215 1215 #address-cells = <1>; 1216 1216 #size-cells = <0>; ··· 1457 1457 pinctrl-1 = <&sdc1_sleep>; 1458 1458 pinctrl-names = "default", 1459 1459 "sleep"; 1460 - power-domains = <&rpmpd MSM8937_VDDCX>; 1460 + power-domains = <&rpmpd RPMPD_VDDCX>; 1461 1461 mmc-hs200-1_8v; 1462 1462 mmc-hs400-1_8v; 1463 1463 mmc-ddr-1_8v; ··· 1487 1487 pinctrl-1 = <&sdc2_sleep>; 1488 1488 pinctrl-names = "default", 1489 1489 "sleep"; 1490 - power-domains = <&rpmpd MSM8937_VDDCX>; 1490 + power-domains = <&rpmpd RPMPD_VDDCX>; 1491 1491 bus-width = <4>; 1492 1492 status = "disabled"; 1493 1493 }; ··· 1710 1710 "handover", 1711 1711 "stop-ack"; 1712 1712 1713 - power-domains = <&rpmpd MSM8937_VDDCX>, 1714 - <&rpmpd MSM8937_VDDMX>; 1713 + power-domains = <&rpmpd RPMPD_VDDCX>, 1714 + <&rpmpd RPMPD_VDDMX>; 1715 1715 power-domain-names = "cx", 1716 1716 "mx"; 1717 1717

+362 -306

arch/arm64/boot/dts/qcom/msm8953.dtsi

··· 545 545 interrupt-controller; 546 546 #interrupt-cells = <2>; 547 547 548 + i2c_1_default: i2c-1-default-state { 549 + pins = "gpio2", "gpio3"; 550 + function = "blsp_i2c1"; 551 + drive-strength = <2>; 552 + bias-disable; 553 + }; 554 + 555 + i2c_1_sleep: i2c-1-sleep-state { 556 + pins = "gpio2", "gpio3"; 557 + function = "gpio"; 558 + drive-strength = <2>; 559 + bias-disable; 560 + }; 561 + 548 562 uart_console_active: uart-console-active-state { 549 563 pins = "gpio4", "gpio5"; 550 564 function = "blsp_uart2"; ··· 571 557 function = "blsp_uart2"; 572 558 drive-strength = <2>; 573 559 bias-pull-down; 560 + }; 561 + 562 + i2c_2_default: i2c-2-default-state { 563 + pins = "gpio6", "gpio7"; 564 + function = "blsp_i2c2"; 565 + drive-strength = <2>; 566 + bias-disable; 567 + }; 568 + 569 + i2c_2_sleep: i2c-2-sleep-state { 570 + pins = "gpio6", "gpio7"; 571 + function = "gpio"; 572 + drive-strength = <2>; 573 + bias-disable; 574 + }; 575 + 576 + spi_3_default: spi-3-default-state { 577 + cs-pins { 578 + pins = "gpio10"; 579 + function = "blsp_spi3"; 580 + drive-strength = <2>; 581 + bias-disable; 582 + }; 583 + 584 + spi-pins { 585 + pins = "gpio8", "gpio9", "gpio11"; 586 + function = "blsp_spi3"; 587 + drive-strength = <12>; 588 + bias-disable; 589 + }; 590 + }; 591 + 592 + spi_3_sleep: spi-3-sleep-state { 593 + cs-pins { 594 + pins = "gpio10"; 595 + function = "gpio"; 596 + drive-strength = <2>; 597 + bias-disable; 598 + }; 599 + 600 + spi-pins { 601 + pins = "gpio8", "gpio9", "gpio11"; 602 + function = "gpio"; 603 + drive-strength = <2>; 604 + bias-pull-down; 605 + }; 606 + }; 607 + 608 + i2c_3_default: i2c-3-default-state { 609 + pins = "gpio10", "gpio11"; 610 + function = "blsp_i2c3"; 611 + drive-strength = <2>; 612 + bias-disable; 613 + }; 614 + 615 + i2c_3_sleep: i2c-3-sleep-state { 616 + pins = "gpio10", "gpio11"; 617 + function = "gpio"; 618 + drive-strength = <2>; 619 + bias-disable; 620 + }; 621 + 622 + i2c_4_default: i2c-4-default-state { 623 + pins = "gpio14", "gpio15"; 624 + function = "blsp_i2c4"; 625 + drive-strength = <2>; 626 + bias-disable; 627 + }; 628 + 629 + i2c_4_sleep: i2c-4-sleep-state { 630 + pins = "gpio14", "gpio15"; 631 + function = "gpio"; 632 + drive-strength = <2>; 633 + bias-disable; 634 + }; 635 + 636 + spi_5_default: spi-5-default-state { 637 + cs-pins { 638 + pins = "gpio18"; 639 + function = "blsp_spi5"; 640 + drive-strength = <2>; 641 + bias-disable; 642 + }; 643 + 644 + spi-pins { 645 + pins = "gpio16", "gpio17", "gpio19"; 646 + function = "blsp_spi5"; 647 + drive-strength = <12>; 648 + bias-disable; 649 + }; 650 + }; 651 + 652 + spi_5_sleep: spi-5-sleep-state { 653 + cs-pins { 654 + pins = "gpio18"; 655 + function = "gpio"; 656 + drive-strength = <2>; 657 + bias-disable; 658 + }; 659 + 660 + spi-pins { 661 + pins = "gpio16", "gpio17", "gpio19"; 662 + function = "gpio"; 663 + drive-strength = <2>; 664 + bias-pull-down; 665 + }; 666 + }; 667 + 668 + uart_5_default: uart-5-default-state { 669 + pins = "gpio16", "gpio17", "gpio18", "gpio19"; 670 + function = "blsp_uart5"; 671 + drive-strength = <16>; 672 + bias-disable; 673 + }; 674 + 675 + uart_5_sleep: uart-5-sleep-state { 676 + pins = "gpio16", "gpio17", "gpio18", "gpio19"; 677 + function = "gpio"; 678 + drive-strength = <2>; 679 + bias-disable; 680 + }; 681 + 682 + i2c_5_default: i2c-5-default-state { 683 + pins = "gpio18", "gpio19"; 684 + function = "blsp_i2c5"; 685 + drive-strength = <2>; 686 + bias-disable; 687 + }; 688 + 689 + i2c_5_sleep: i2c-5-sleep-state { 690 + pins = "gpio18", "gpio19"; 691 + function = "gpio"; 692 + drive-strength = <2>; 693 + bias-disable; 694 + }; 695 + 696 + spi_6_default: spi-6-default-state { 697 + cs-pins { 698 + pins = "gpio22"; 699 + function = "blsp_spi6"; 700 + drive-strength = <2>; 701 + bias-disable; 702 + }; 703 + 704 + spi-pins { 705 + pins = "gpio20", "gpio21", "gpio23"; 706 + function = "blsp_spi6"; 707 + drive-strength = <12>; 708 + bias-disable; 709 + }; 710 + }; 711 + 712 + spi_6_sleep: spi-6-sleep-state { 713 + cs-pins { 714 + pins = "gpio22"; 715 + function = "gpio"; 716 + drive-strength = <2>; 717 + bias-disable; 718 + }; 719 + 720 + spi-pins { 721 + pins = "gpio20", "gpio21", "gpio23"; 722 + function = "gpio"; 723 + drive-strength = <2>; 724 + bias-pull-down; 725 + }; 726 + }; 727 + 728 + i2c_6_default: i2c-6-default-state { 729 + pins = "gpio22", "gpio23"; 730 + function = "blsp_i2c6"; 731 + drive-strength = <2>; 732 + bias-disable; 733 + }; 734 + 735 + i2c_6_sleep: i2c-6-sleep-state { 736 + pins = "gpio22", "gpio23"; 737 + function = "gpio"; 738 + drive-strength = <2>; 739 + bias-disable; 740 + }; 741 + 742 + cci0_default: cci0-default-state { 743 + pins = "gpio29", "gpio30"; 744 + function = "cci_i2c"; 745 + drive-strength = <2>; 746 + bias-disable; 747 + }; 748 + 749 + cci1_default: cci1-default-state { 750 + pins = "gpio31", "gpio32"; 751 + function = "cci_i2c"; 752 + drive-strength = <2>; 753 + bias-disable; 754 + }; 755 + 756 + wcnss_pin_a: wcnss-active-state { 757 + wcss-wlan2-pins { 758 + pins = "gpio76"; 759 + function = "wcss_wlan2"; 760 + drive-strength = <6>; 761 + bias-pull-up; 762 + }; 763 + 764 + wcss-wlan1-pins { 765 + pins = "gpio77"; 766 + function = "wcss_wlan1"; 767 + drive-strength = <6>; 768 + bias-pull-up; 769 + }; 770 + 771 + wcss-wlan0-pins { 772 + pins = "gpio78"; 773 + function = "wcss_wlan0"; 774 + drive-strength = <6>; 775 + bias-pull-up; 776 + }; 777 + 778 + wcss-wlan-pins { 779 + pins = "gpio79", "gpio80"; 780 + function = "wcss_wlan"; 781 + drive-strength = <6>; 782 + bias-pull-up; 783 + }; 784 + }; 785 + 786 + gpio_key_default: gpio-key-default-state { 787 + pins = "gpio85"; 788 + function = "gpio"; 789 + drive-strength = <2>; 790 + bias-pull-up; 791 + }; 792 + 793 + i2c_8_default: i2c-8-default-state { 794 + pins = "gpio98", "gpio99"; 795 + function = "blsp_i2c8"; 796 + drive-strength = <2>; 797 + bias-disable; 798 + }; 799 + 800 + i2c_8_sleep: i2c-8-sleep-state { 801 + pins = "gpio98", "gpio99"; 802 + function = "gpio"; 803 + drive-strength = <2>; 804 + bias-disable; 805 + }; 806 + 807 + sdc2_cd_on: cd-on-state { 808 + pins = "gpio133"; 809 + function = "gpio"; 810 + drive-strength = <2>; 811 + bias-pull-up; 812 + }; 813 + 814 + sdc2_cd_off: cd-off-state { 815 + pins = "gpio133"; 816 + function = "gpio"; 817 + drive-strength = <2>; 818 + bias-disable; 819 + }; 820 + 821 + i2c_7_default: i2c-7-default-state { 822 + pins = "gpio135", "gpio136"; 823 + function = "blsp_i2c7"; 824 + drive-strength = <2>; 825 + bias-disable; 826 + }; 827 + 828 + i2c_7_sleep: i2c-7-sleep-state { 829 + pins = "gpio135", "gpio136"; 830 + function = "gpio"; 831 + drive-strength = <2>; 832 + bias-disable; 833 + }; 834 + 835 + spi_7_default: spi-7-default-state { 836 + cs-pins { 837 + pins = "gpio136"; 838 + function = "blsp_spi7"; 839 + drive-strength = <2>; 840 + bias-disable; 841 + }; 842 + 843 + spi-pins { 844 + pins = "gpio135", "gpio137", "gpio138"; 845 + function = "blsp_spi7"; 846 + drive-strength = <12>; 847 + bias-disable; 848 + }; 849 + }; 850 + 851 + spi_7_sleep: spi-7-sleep-state { 852 + cs-pins { 853 + pins = "gpio136"; 854 + function = "gpio"; 855 + drive-strength = <2>; 856 + bias-disable; 857 + }; 858 + 859 + spi-pins { 860 + pins = "gpio135", "gpio137", "gpio138"; 861 + function = "gpio"; 862 + drive-strength = <2>; 863 + bias-pull-down; 864 + }; 574 865 }; 575 866 576 867 sdc1_clk_on: sdc1-clk-on-state { ··· 958 639 pins = "sdc2_data"; 959 640 bias-pull-up; 960 641 drive-strength = <2>; 961 - }; 962 - 963 - sdc2_cd_on: cd-on-state { 964 - pins = "gpio133"; 965 - function = "gpio"; 966 - drive-strength = <2>; 967 - bias-pull-up; 968 - }; 969 - 970 - sdc2_cd_off: cd-off-state { 971 - pins = "gpio133"; 972 - function = "gpio"; 973 - drive-strength = <2>; 974 - bias-disable; 975 - }; 976 - 977 - gpio_key_default: gpio-key-default-state { 978 - pins = "gpio85"; 979 - function = "gpio"; 980 - drive-strength = <2>; 981 - bias-pull-up; 982 - }; 983 - 984 - i2c_1_default: i2c-1-default-state { 985 - pins = "gpio2", "gpio3"; 986 - function = "blsp_i2c1"; 987 - drive-strength = <2>; 988 - bias-disable; 989 - }; 990 - 991 - i2c_1_sleep: i2c-1-sleep-state { 992 - pins = "gpio2", "gpio3"; 993 - function = "gpio"; 994 - drive-strength = <2>; 995 - bias-disable; 996 - }; 997 - 998 - i2c_2_default: i2c-2-default-state { 999 - pins = "gpio6", "gpio7"; 1000 - function = "blsp_i2c2"; 1001 - drive-strength = <2>; 1002 - bias-disable; 1003 - }; 1004 - 1005 - i2c_2_sleep: i2c-2-sleep-state { 1006 - pins = "gpio6", "gpio7"; 1007 - function = "gpio"; 1008 - drive-strength = <2>; 1009 - bias-disable; 1010 - }; 1011 - 1012 - i2c_3_default: i2c-3-default-state { 1013 - pins = "gpio10", "gpio11"; 1014 - function = "blsp_i2c3"; 1015 - drive-strength = <2>; 1016 - bias-disable; 1017 - }; 1018 - 1019 - i2c_3_sleep: i2c-3-sleep-state { 1020 - pins = "gpio10", "gpio11"; 1021 - function = "gpio"; 1022 - drive-strength = <2>; 1023 - bias-disable; 1024 - }; 1025 - 1026 - i2c_4_default: i2c-4-default-state { 1027 - pins = "gpio14", "gpio15"; 1028 - function = "blsp_i2c4"; 1029 - drive-strength = <2>; 1030 - bias-disable; 1031 - }; 1032 - 1033 - i2c_4_sleep: i2c-4-sleep-state { 1034 - pins = "gpio14", "gpio15"; 1035 - function = "gpio"; 1036 - drive-strength = <2>; 1037 - bias-disable; 1038 - }; 1039 - 1040 - i2c_5_default: i2c-5-default-state { 1041 - pins = "gpio18", "gpio19"; 1042 - function = "blsp_i2c5"; 1043 - drive-strength = <2>; 1044 - bias-disable; 1045 - }; 1046 - 1047 - i2c_5_sleep: i2c-5-sleep-state { 1048 - pins = "gpio18", "gpio19"; 1049 - function = "gpio"; 1050 - drive-strength = <2>; 1051 - bias-disable; 1052 - }; 1053 - 1054 - i2c_6_default: i2c-6-default-state { 1055 - pins = "gpio22", "gpio23"; 1056 - function = "blsp_i2c6"; 1057 - drive-strength = <2>; 1058 - bias-disable; 1059 - }; 1060 - 1061 - i2c_6_sleep: i2c-6-sleep-state { 1062 - pins = "gpio22", "gpio23"; 1063 - function = "gpio"; 1064 - drive-strength = <2>; 1065 - bias-disable; 1066 - }; 1067 - 1068 - i2c_7_default: i2c-7-default-state { 1069 - pins = "gpio135", "gpio136"; 1070 - function = "blsp_i2c7"; 1071 - drive-strength = <2>; 1072 - bias-disable; 1073 - }; 1074 - 1075 - i2c_7_sleep: i2c-7-sleep-state { 1076 - pins = "gpio135", "gpio136"; 1077 - function = "gpio"; 1078 - drive-strength = <2>; 1079 - bias-disable; 1080 - }; 1081 - 1082 - i2c_8_default: i2c-8-default-state { 1083 - pins = "gpio98", "gpio99"; 1084 - function = "blsp_i2c8"; 1085 - drive-strength = <2>; 1086 - bias-disable; 1087 - }; 1088 - 1089 - i2c_8_sleep: i2c-8-sleep-state { 1090 - pins = "gpio98", "gpio99"; 1091 - function = "gpio"; 1092 - drive-strength = <2>; 1093 - bias-disable; 1094 - }; 1095 - 1096 - spi_3_default: spi-3-default-state { 1097 - cs-pins { 1098 - pins = "gpio10"; 1099 - function = "blsp_spi3"; 1100 - drive-strength = <2>; 1101 - bias-disable; 1102 - }; 1103 - 1104 - spi-pins { 1105 - pins = "gpio8", "gpio9", "gpio11"; 1106 - function = "blsp_spi3"; 1107 - drive-strength = <12>; 1108 - bias-disable; 1109 - }; 1110 - }; 1111 - 1112 - spi_3_sleep: spi-3-sleep-state { 1113 - cs-pins { 1114 - pins = "gpio10"; 1115 - function = "gpio"; 1116 - drive-strength = <2>; 1117 - bias-disable; 1118 - }; 1119 - 1120 - spi-pins { 1121 - pins = "gpio8", "gpio9", "gpio11"; 1122 - function = "gpio"; 1123 - drive-strength = <2>; 1124 - bias-pull-down; 1125 - }; 1126 - }; 1127 - 1128 - spi_5_default: spi-5-default-state { 1129 - cs-pins { 1130 - pins = "gpio18"; 1131 - function = "blsp_spi5"; 1132 - drive-strength = <2>; 1133 - bias-disable; 1134 - }; 1135 - 1136 - spi-pins { 1137 - pins = "gpio16", "gpio17", "gpio19"; 1138 - function = "blsp_spi5"; 1139 - drive-strength = <12>; 1140 - bias-disable; 1141 - }; 1142 - }; 1143 - 1144 - spi_5_sleep: spi-5-sleep-state { 1145 - cs-pins { 1146 - pins = "gpio18"; 1147 - function = "gpio"; 1148 - drive-strength = <2>; 1149 - bias-disable; 1150 - }; 1151 - 1152 - spi-pins { 1153 - pins = "gpio16", "gpio17", "gpio19"; 1154 - function = "gpio"; 1155 - drive-strength = <2>; 1156 - bias-pull-down; 1157 - }; 1158 - }; 1159 - 1160 - spi_6_default: spi-6-default-state { 1161 - cs-pins { 1162 - pins = "gpio22"; 1163 - function = "blsp_spi6"; 1164 - drive-strength = <2>; 1165 - bias-disable; 1166 - }; 1167 - 1168 - spi-pins { 1169 - pins = "gpio20", "gpio21", "gpio23"; 1170 - function = "blsp_spi6"; 1171 - drive-strength = <12>; 1172 - bias-disable; 1173 - }; 1174 - }; 1175 - 1176 - spi_6_sleep: spi-6-sleep-state { 1177 - cs-pins { 1178 - pins = "gpio22"; 1179 - function = "gpio"; 1180 - drive-strength = <2>; 1181 - bias-disable; 1182 - }; 1183 - 1184 - spi-pins { 1185 - pins = "gpio20", "gpio21", "gpio23"; 1186 - function = "gpio"; 1187 - drive-strength = <2>; 1188 - bias-pull-down; 1189 - }; 1190 - }; 1191 - 1192 - spi_7_default: spi-7-default-state { 1193 - cs-pins { 1194 - pins = "gpio136"; 1195 - function = "blsp_spi7"; 1196 - drive-strength = <2>; 1197 - bias-disable; 1198 - }; 1199 - 1200 - spi-pins { 1201 - pins = "gpio135", "gpio137", "gpio138"; 1202 - function = "blsp_spi7"; 1203 - drive-strength = <12>; 1204 - bias-disable; 1205 - }; 1206 - }; 1207 - 1208 - spi_7_sleep: spi-7-sleep-state { 1209 - cs-pins { 1210 - pins = "gpio136"; 1211 - function = "gpio"; 1212 - drive-strength = <2>; 1213 - bias-disable; 1214 - }; 1215 - 1216 - spi-pins { 1217 - pins = "gpio135", "gpio137", "gpio138"; 1218 - function = "gpio"; 1219 - drive-strength = <2>; 1220 - bias-pull-down; 1221 - }; 1222 - }; 1223 - 1224 - uart_5_default: uart-5-default-state { 1225 - pins = "gpio16", "gpio17", "gpio18", "gpio19"; 1226 - function = "blsp_uart5"; 1227 - drive-strength = <16>; 1228 - bias-disable; 1229 - }; 1230 - 1231 - uart_5_sleep: uart-5-sleep-state { 1232 - pins = "gpio16", "gpio17", "gpio18", "gpio19"; 1233 - function = "gpio"; 1234 - drive-strength = <2>; 1235 - bias-disable; 1236 - }; 1237 - 1238 - wcnss_pin_a: wcnss-active-state { 1239 - 1240 - wcss-wlan2-pins { 1241 - pins = "gpio76"; 1242 - function = "wcss_wlan2"; 1243 - drive-strength = <6>; 1244 - bias-pull-up; 1245 - }; 1246 - 1247 - wcss-wlan1-pins { 1248 - pins = "gpio77"; 1249 - function = "wcss_wlan1"; 1250 - drive-strength = <6>; 1251 - bias-pull-up; 1252 - }; 1253 - 1254 - wcss-wlan0-pins { 1255 - pins = "gpio78"; 1256 - function = "wcss_wlan0"; 1257 - drive-strength = <6>; 1258 - bias-pull-up; 1259 - }; 1260 - 1261 - wcss-wlan-pins { 1262 - pins = "gpio79", "gpio80"; 1263 - function = "wcss_wlan"; 1264 - drive-strength = <6>; 1265 - bias-pull-up; 1266 - }; 1267 642 }; 1268 643 }; 1269 644 ··· 1211 1198 clock-names = "iface", "ref"; 1212 1199 1213 1200 status = "disabled"; 1201 + }; 1202 + }; 1203 + 1204 + cci: cci@1b0c000 { 1205 + compatible = "qcom,msm8953-cci"; 1206 + reg = <0x1b0c000 0x4000>; 1207 + 1208 + interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 1209 + 1210 + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1211 + <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1212 + <&gcc GCC_CAMSS_CCI_CLK>, 1213 + <&gcc GCC_CAMSS_AHB_CLK>; 1214 + clock-names = "camss_top_ahb", 1215 + "cci_ahb", 1216 + "cci", 1217 + "camss_ahb"; 1218 + 1219 + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1220 + <&gcc GCC_CAMSS_CCI_CLK>; 1221 + assigned-clock-rates = <80000000>, 1222 + <19200000>; 1223 + 1224 + pinctrl-0 = <&cci0_default &cci1_default>; 1225 + pinctrl-names = "default"; 1226 + 1227 + #address-cells = <1>; 1228 + #size-cells = <0>; 1229 + 1230 + status = "disabled"; 1231 + 1232 + cci_i2c0: i2c-bus@0 { 1233 + reg = <0>; 1234 + clock-frequency = <400000>; 1235 + #address-cells = <1>; 1236 + #size-cells = <0>; 1237 + }; 1238 + 1239 + cci_i2c1: i2c-bus@1 { 1240 + reg = <1>; 1241 + clock-frequency = <400000>; 1242 + #address-cells = <1>; 1243 + #size-cells = <0>; 1214 1244 }; 1215 1245 }; 1216 1246

+2 -2

arch/arm64/boot/dts/qcom/msm8976.dtsi

··· 1558 1558 "handover", 1559 1559 "stop-ack"; 1560 1560 1561 - power-domains = <&rpmpd MSM8976_VDDCX>, 1562 - <&rpmpd MSM8976_VDDMX>; 1561 + power-domains = <&rpmpd RPMPD_VDDCX>, 1562 + <&rpmpd RPMPD_VDDMX>; 1563 1563 power-domain-names = "cx", "mx"; 1564 1564 1565 1565 qcom,smem-states = <&wcnss_smp2p_out 0>;

+8 -8

arch/arm64/boot/dts/qcom/msm8998.dtsi

··· 1497 1497 1498 1498 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1499 1499 1500 - power-domains = <&rpmpd MSM8998_VDDCX>, 1501 - <&rpmpd MSM8998_VDDMX>; 1500 + power-domains = <&rpmpd RPMPD_VDDCX>, 1501 + <&rpmpd RPMPD_VDDMX>; 1502 1502 power-domain-names = "cx", "mx"; 1503 1503 1504 1504 status = "disabled"; ··· 1544 1544 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1545 1545 iommus = <&adreno_smmu 0>; 1546 1546 operating-points-v2 = <&gpu_opp_table>; 1547 - power-domains = <&rpmpd MSM8998_VDDMX>; 1547 + power-domains = <&rpmpd RPMPD_VDDMX>; 1548 1548 status = "disabled"; 1549 1549 1550 1550 gpu_opp_table: opp-table { ··· 1680 1680 qcom,smem-states = <&slpi_smp2p_out 0>; 1681 1681 qcom,smem-state-names = "stop"; 1682 1682 1683 - power-domains = <&rpmpd MSM8998_SSCCX>; 1683 + power-domains = <&rpmpd RPMPD_SSCCX>; 1684 1684 power-domain-names = "ssc_cx"; 1685 1685 1686 1686 status = "disabled"; ··· 2871 2871 assigned-clock-rates = <19200000>; 2872 2872 2873 2873 operating-points-v2 = <&mdp_opp_table>; 2874 - power-domains = <&rpmpd MSM8998_VDDMX>; 2874 + power-domains = <&rpmpd RPMPD_VDDMX>; 2875 2875 2876 2876 mdp_opp_table: opp-table { 2877 2877 compatible = "operating-points-v2"; ··· 2953 2953 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2954 2954 2955 2955 operating-points-v2 = <&dsi_opp_table>; 2956 - power-domains = <&rpmpd MSM8998_VDDCX>; 2956 + power-domains = <&rpmpd RPMPD_VDDCX>; 2957 2957 2958 2958 phys = <&mdss_dsi0_phy>; 2959 2959 phy-names = "dsi"; ··· 3029 3029 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 3030 3030 3031 3031 operating-points-v2 = <&dsi_opp_table>; 3032 - power-domains = <&rpmpd MSM8998_VDDCX>; 3032 + power-domains = <&rpmpd RPMPD_VDDCX>; 3033 3033 3034 3034 phys = <&mdss_dsi1_phy>; 3035 3035 phy-names = "dsi"; ··· 3277 3277 qcom,smem-states = <&adsp_smp2p_out 0>; 3278 3278 qcom,smem-state-names = "stop"; 3279 3279 3280 - power-domains = <&rpmpd MSM8998_VDDCX>; 3280 + power-domains = <&rpmpd RPMPD_VDDCX>; 3281 3281 power-domain-names = "cx"; 3282 3282 3283 3283 status = "disabled";

+8 -8

arch/arm64/boot/dts/qcom/sdm630.dtsi

··· 1058 1058 1059 1059 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1060 1060 1061 - power-domains = <&rpmpd SDM660_VDDCX>, 1062 - <&rpmpd SDM660_VDDMX>; 1061 + power-domains = <&rpmpd RPMPD_VDDCX>, 1062 + <&rpmpd RPMPD_VDDMX>; 1063 1063 power-domain-names = "cx", "mx"; 1064 1064 1065 1065 memory-region = <&mba_region>, <&mpss_region>, <&mdata_mem>; ··· 1096 1096 "rbcpr", 1097 1097 "core"; 1098 1098 1099 - power-domains = <&rpmpd SDM660_VDDMX>; 1099 + power-domains = <&rpmpd RPMPD_VDDMX>; 1100 1100 iommus = <&kgsl_smmu 0>; 1101 1101 1102 1102 nvmem-cells = <&gpu_speed_bin>; ··· 1401 1401 pinctrl-names = "default", "sleep"; 1402 1402 pinctrl-0 = <&sdc2_state_on>; 1403 1403 pinctrl-1 = <&sdc2_state_off>; 1404 - power-domains = <&rpmpd SDM660_VDDCX>; 1404 + power-domains = <&rpmpd RPMPD_VDDCX>; 1405 1405 1406 1406 status = "disabled"; 1407 1407 ··· 1455 1455 pinctrl-names = "default", "sleep"; 1456 1456 pinctrl-0 = <&sdc1_state_on>; 1457 1457 pinctrl-1 = <&sdc1_state_off>; 1458 - power-domains = <&rpmpd SDM660_VDDCX>; 1458 + power-domains = <&rpmpd RPMPD_VDDCX>; 1459 1459 1460 1460 bus-width = <8>; 1461 1461 non-removable; ··· 1618 1618 "rotator-mem"; 1619 1619 iommus = <&mmss_smmu 0>; 1620 1620 operating-points-v2 = <&mdp_opp_table>; 1621 - power-domains = <&rpmpd SDM660_VDDCX>; 1621 + power-domains = <&rpmpd RPMPD_VDDCX>; 1622 1622 1623 1623 ports { 1624 1624 #address-cells = <1>; ··· 1670 1670 reg-names = "dsi_ctrl"; 1671 1671 1672 1672 operating-points-v2 = <&dsi_opp_table>; 1673 - power-domains = <&rpmpd SDM660_VDDCX>; 1673 + power-domains = <&rpmpd RPMPD_VDDCX>; 1674 1674 1675 1675 interrupt-parent = <&mdss>; 1676 1676 interrupts = <4>; ··· 2359 2359 clock-names = "xo"; 2360 2360 2361 2361 memory-region = <&adsp_region>; 2362 - power-domains = <&rpmpd SDM660_VDDCX>; 2362 + power-domains = <&rpmpd RPMPD_VDDCX>; 2363 2363 power-domain-names = "cx"; 2364 2364 2365 2365 qcom,smem-states = <&adsp_smp2p_out 0>;

+57

arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts

··· 36 36 }; 37 37 }; 38 38 39 + vreg_cam_af_2p85: regulator-cam-af-2p85 { 40 + compatible = "regulator-fixed"; 41 + regulator-name = "cam_af_2p85"; 42 + regulator-min-microvolt = <2850000>; 43 + regulator-max-microvolt = <2850000>; 44 + 45 + gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>; 46 + enable-active-high; 47 + 48 + vin-supply = <&vph_pwr>; 49 + }; 50 + 51 + vreg_cam_io_1p8: regulator-cam-io-1p8 { 52 + compatible = "regulator-fixed"; 53 + regulator-name = "cam_io_1p8"; 54 + regulator-min-microvolt = <1800000>; 55 + regulator-max-microvolt = <1800000>; 56 + 57 + gpio = <&tlmm 130 GPIO_ACTIVE_HIGH>; 58 + enable-active-high; 59 + 60 + vin-supply = <&vph_pwr>; 61 + }; 62 + 63 + vreg_cam2_dig_1p2: regulator-cam2-dig-1p2 { 64 + compatible = "regulator-fixed"; 65 + regulator-name = "cam2_dig_1p2"; 66 + regulator-min-microvolt = <1200000>; 67 + regulator-max-microvolt = <1200000>; 68 + 69 + gpio = <&tlmm 46 GPIO_ACTIVE_HIGH>; 70 + enable-active-high; 71 + 72 + vin-supply = <&vph_pwr>; 73 + }; 74 + 39 75 /* Dummy regulator until PMI632 has LCDB VSP/VSN support */ 40 76 lcdb_dummy: regulator-lcdb-dummy { 41 77 compatible = "regulator-fixed"; ··· 86 50 regulator-always-on; 87 51 regulator-boot-on; 88 52 }; 53 + }; 54 + 55 + &cci { 56 + status = "okay"; 57 + }; 58 + 59 + &cci_i2c0 { 60 + /* Sony IMX363 (rear) @ 0x10 */ 61 + 62 + eeprom@50 { 63 + compatible = "belling,bl24s64", "atmel,24c64"; 64 + reg = <0x50>; 65 + vcc-supply = <&vreg_cam_io_1p8>; 66 + read-only; 67 + }; 68 + 69 + /* ON Semi LC898217 VCM @ 0x72 */ 70 + }; 71 + 72 + &cci_i2c1 { 73 + /* Samsung S5K4H7YX (front) @ 0x10 */ 89 74 }; 90 75 91 76 &gpu {

+1 -1

arch/arm64/boot/dts/qcom/sdm660.dtsi

··· 194 194 195 195 /* DSI1 shares the OPP table with DSI0 */ 196 196 operating-points-v2 = <&dsi_opp_table>; 197 - power-domains = <&rpmpd SDM660_VDDCX>; 197 + power-domains = <&rpmpd RPMPD_VDDCX>; 198 198 199 199 interrupt-parent = <&mdss>; 200 200 interrupts = <5>;

+2

arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts

··· 45 45 }; 46 46 47 47 &i2c4 { 48 + clock-frequency = <100000>; 49 + 48 50 status = "okay"; 49 51 50 52 max98927_codec: max98927@3a {

+6 -2

arch/arm64/boot/dts/qcom/sm6115.dtsi

··· 1715 1715 1716 1716 gpu: gpu@5900000 { 1717 1717 compatible = "qcom,adreno-610.0", "qcom,adreno"; 1718 - reg = <0x0 0x05900000 0x0 0x40000>; 1719 - reg-names = "kgsl_3d0_reg_memory"; 1718 + reg = <0x0 0x05900000 0x0 0x40000>, 1719 + <0x0 0x0599e000 0x0 0x1000>, 1720 + <0x0 0x05961000 0x0 0x800>; 1721 + reg-names = "kgsl_3d0_reg_memory", 1722 + "cx_mem", 1723 + "cx_dbgc"; 1720 1724 1721 1725 /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ 1722 1726 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,

+6 -6

arch/arm64/boot/dts/qcom/sm6125.dtsi

··· 724 724 clock-names = "iface", "core", "xo"; 725 725 iommus = <&apps_smmu 0x160 0x0>; 726 726 727 - power-domains = <&rpmpd SM6125_VDDCX>; 727 + power-domains = <&rpmpd RPMPD_VDDCX>; 728 728 729 729 qcom,dll-config = <0x000f642c>; 730 730 qcom,ddr-config = <0x80040873>; ··· 755 755 pinctrl-1 = <&sdc2_off_state>; 756 756 pinctrl-names = "default", "sleep"; 757 757 758 - power-domains = <&rpmpd SM6125_VDDCX>; 758 + power-domains = <&rpmpd RPMPD_VDDCX>; 759 759 760 760 qcom,dll-config = <0x0007642c>; 761 761 qcom,ddr-config = <0x80040873>; ··· 1275 1275 assigned-clock-rates = <19200000>; 1276 1276 1277 1277 operating-points-v2 = <&mdp_opp_table>; 1278 - power-domains = <&rpmpd SM6125_VDDCX>; 1278 + power-domains = <&rpmpd RPMPD_VDDCX>; 1279 1279 1280 1280 ports { 1281 1281 #address-cells = <1>; ··· 1345 1345 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1346 1346 1347 1347 operating-points-v2 = <&dsi_opp_table>; 1348 - power-domains = <&rpmpd SM6125_VDDCX>; 1348 + power-domains = <&rpmpd RPMPD_VDDCX>; 1349 1349 1350 1350 phys = <&mdss_dsi0_phy>; 1351 1351 phy-names = "dsi"; ··· 1406 1406 "ref"; 1407 1407 1408 1408 required-opps = <&rpmpd_opp_nom>; 1409 - power-domains = <&rpmpd SM6125_VDDMX>; 1409 + power-domains = <&rpmpd RPMPD_VDDMX>; 1410 1410 1411 1411 status = "disabled"; 1412 1412 }; ··· 1434 1434 "gcc_disp_gpll0_div_clk_src"; 1435 1435 1436 1436 required-opps = <&rpmpd_opp_ret>; 1437 - power-domains = <&rpmpd SM6125_VDDCX>; 1437 + power-domains = <&rpmpd RPMPD_VDDCX>; 1438 1438 1439 1439 #clock-cells = <1>; 1440 1440 #power-domain-cells = <1>;

+3

arch/arm64/boot/dts/qcom/sm6350.dtsi

··· 1117 1117 reg = <0x0 0x016e0000 0x0 0x15080>; 1118 1118 #interconnect-cells = <2>; 1119 1119 qcom,bcm-voters = <&apps_bcm_voter>; 1120 + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 1120 1121 }; 1121 1122 1122 1123 aggre2_noc: interconnect@1700000 { ··· 1125 1124 reg = <0x0 0x01700000 0x0 0x1f880>; 1126 1125 #interconnect-cells = <2>; 1127 1126 qcom,bcm-voters = <&apps_bcm_voter>; 1127 + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1128 + <&rpmhcc RPMH_IPA_CLK>; 1128 1129 1129 1130 compute_noc: interconnect-compute-noc { 1130 1131 compatible = "qcom,sm6350-compute-noc";

+1049

arch/arm64/boot/dts/qcom/sm8750.dtsi

··· 8 8 #include <dt-bindings/clock/qcom,sm8750-tcsr.h> 9 9 #include <dt-bindings/clock/qcom,sm8750-videocc.h> 10 10 #include <dt-bindings/dma/qcom-gpi.h> 11 + #include <dt-bindings/firmware/qcom,scm.h> 11 12 #include <dt-bindings/gpio/gpio.h> 12 13 #include <dt-bindings/interconnect/qcom,icc.h> 13 14 #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h> ··· 540 539 llcc_lpi_mem: llcc-lpi@ff800000 { 541 540 reg = <0x0 0xff800000 0x0 0x800000>; 542 541 no-map; 542 + }; 543 + 544 + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap { 545 + compatible = "shared-dma-pool"; 546 + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; 547 + alignment = <0x0 0x400000>; 548 + size = <0x0 0xc00000>; 549 + reusable; 543 550 }; 544 551 }; 545 552 ··· 2223 2214 qcom,remote-pid = <2>; 2224 2215 label = "lpass"; 2225 2216 2217 + fastrpc { 2218 + compatible = "qcom,fastrpc"; 2219 + qcom,glink-channels = "fastrpcglink-apps-dsp"; 2220 + label = "adsp"; 2221 + memory-region = <&adsp_rpc_remote_heap_mem>; 2222 + qcom,vmids = <QCOM_SCM_VMID_LPASS 2223 + QCOM_SCM_VMID_ADSP_HEAP>; 2224 + #address-cells = <1>; 2225 + #size-cells = <0>; 2226 + 2227 + compute-cb@3 { 2228 + compatible = "qcom,fastrpc-compute-cb"; 2229 + reg = <3>; 2230 + iommus = <&apps_smmu 0x1003 0x80>, 2231 + <&apps_smmu 0x1043 0x20>; 2232 + dma-coherent; 2233 + }; 2234 + 2235 + compute-cb@4 { 2236 + compatible = "qcom,fastrpc-compute-cb"; 2237 + reg = <4>; 2238 + iommus = <&apps_smmu 0x1004 0x80>, 2239 + <&apps_smmu 0x1044 0x20>; 2240 + dma-coherent; 2241 + }; 2242 + 2243 + compute-cb@5 { 2244 + compatible = "qcom,fastrpc-compute-cb"; 2245 + reg = <5>; 2246 + iommus = <&apps_smmu 0x1005 0x80>, 2247 + <&apps_smmu 0x1045 0x20>; 2248 + dma-coherent; 2249 + }; 2250 + 2251 + compute-cb@6 { 2252 + compatible = "qcom,fastrpc-compute-cb"; 2253 + reg = <6>; 2254 + iommus = <&apps_smmu 0x1006 0x80>, 2255 + <&apps_smmu 0x1046 0x20>; 2256 + dma-coherent; 2257 + }; 2258 + 2259 + compute-cb@7 { 2260 + compatible = "qcom,fastrpc-compute-cb"; 2261 + reg = <7>; 2262 + iommus = <&apps_smmu 0x1007 0x40>, 2263 + <&apps_smmu 0x1067 0x0>, 2264 + <&apps_smmu 0x1087 0x0>; 2265 + dma-coherent; 2266 + }; 2267 + 2268 + compute-cb@8 { 2269 + compatible = "qcom,fastrpc-compute-cb"; 2270 + reg = <8>; 2271 + iommus = <&apps_smmu 0x1008 0x80>, 2272 + <&apps_smmu 0x1048 0x20>; 2273 + dma-coherent; 2274 + }; 2275 + }; 2276 + 2226 2277 gpr { 2227 2278 compatible = "qcom,gpr"; 2228 2279 qcom,glink-channels = "adsp_apps"; ··· 3574 3505 #reset-cells = <1>; 3575 3506 }; 3576 3507 3508 + stm@10002000 { 3509 + compatible = "arm,coresight-stm", "arm,primecell"; 3510 + reg = <0x0 0x10002000 0x0 0x1000>, 3511 + <0x0 0x37280000 0x0 0x180000>; 3512 + reg-names = "stm-base", 3513 + "stm-stimulus-base"; 3514 + 3515 + clocks = <&aoss_qmp>; 3516 + clock-names = "apb_pclk"; 3517 + 3518 + out-ports { 3519 + port { 3520 + stm_out: endpoint { 3521 + remote-endpoint = <&funnel_in0_in7>; 3522 + }; 3523 + }; 3524 + }; 3525 + }; 3526 + 3527 + tpda@10004000 { 3528 + compatible = "qcom,coresight-tpda", "arm,primecell"; 3529 + reg = <0x0 0x10004000 0x0 0x1000>; 3530 + 3531 + clocks = <&aoss_qmp>; 3532 + clock-names = "apb_pclk"; 3533 + 3534 + in-ports { 3535 + #address-cells = <1>; 3536 + #size-cells = <0>; 3537 + 3538 + port@1 { 3539 + reg = <1>; 3540 + 3541 + tpda_qdss_in1: endpoint { 3542 + remote-endpoint = <&tpdm_spdm_out>; 3543 + }; 3544 + }; 3545 + 3546 + }; 3547 + 3548 + out-ports { 3549 + port { 3550 + tpda_qdss_out: endpoint { 3551 + remote-endpoint = <&funnel_in0_in6>; 3552 + }; 3553 + }; 3554 + }; 3555 + }; 3556 + 3557 + tpdm@1000f000 { 3558 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 3559 + reg = <0x0 0x1000f000 0x0 0x1000>; 3560 + 3561 + clocks = <&aoss_qmp>; 3562 + clock-names = "apb_pclk"; 3563 + 3564 + qcom,cmb-element-bits = <64>; 3565 + qcom,cmb-msrs-num = <32>; 3566 + 3567 + out-ports { 3568 + port { 3569 + tpdm_spdm_out: endpoint { 3570 + remote-endpoint = <&tpda_qdss_in1>; 3571 + }; 3572 + }; 3573 + }; 3574 + }; 3575 + 3576 + funnel@10041000 { 3577 + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3578 + reg = <0x0 0x10041000 0x0 0x1000>; 3579 + 3580 + clocks = <&aoss_qmp>; 3581 + clock-names = "apb_pclk"; 3582 + 3583 + in-ports { 3584 + #address-cells = <1>; 3585 + #size-cells = <0>; 3586 + 3587 + port@0 { 3588 + reg = <0>; 3589 + 3590 + funnel_in0_in0: endpoint { 3591 + remote-endpoint = <&tn_ag_out>; 3592 + }; 3593 + }; 3594 + 3595 + port@6 { 3596 + reg = <6>; 3597 + 3598 + funnel_in0_in6: endpoint { 3599 + remote-endpoint = <&tpda_qdss_out>; 3600 + }; 3601 + }; 3602 + 3603 + port@7 { 3604 + reg = <7>; 3605 + 3606 + funnel_in0_in7: endpoint { 3607 + remote-endpoint = <&stm_out>; 3608 + }; 3609 + }; 3610 + }; 3611 + 3612 + out-ports { 3613 + port { 3614 + funnel_in0_out: endpoint { 3615 + remote-endpoint = <&funnel_aoss_in7>; 3616 + }; 3617 + }; 3618 + }; 3619 + }; 3620 + 3621 + tpdm@10800000 { 3622 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 3623 + reg = <0x0 0x10800000 0x0 0x1000>; 3624 + 3625 + clocks = <&aoss_qmp>; 3626 + clock-names = "apb_pclk"; 3627 + 3628 + qcom,dsb-element-bits = <32>; 3629 + qcom,dsb-msrs-num = <32>; 3630 + 3631 + out-ports { 3632 + port { 3633 + tpdm_modem0_out: endpoint { 3634 + remote-endpoint = <&tpda_modem_in0>; 3635 + }; 3636 + }; 3637 + }; 3638 + }; 3639 + 3640 + tpda@10803000 { 3641 + compatible = "qcom,coresight-tpda", "arm,primecell"; 3642 + reg = <0x0 0x10803000 0x0 0x1000>; 3643 + 3644 + clocks = <&aoss_qmp>; 3645 + clock-names = "apb_pclk"; 3646 + 3647 + in-ports { 3648 + #address-cells = <1>; 3649 + #size-cells = <0>; 3650 + 3651 + port@0 { 3652 + reg = <0>; 3653 + 3654 + tpda_modem_in0: endpoint { 3655 + remote-endpoint = <&tpdm_modem0_out>; 3656 + }; 3657 + }; 3658 + 3659 + port@1 { 3660 + reg = <1>; 3661 + 3662 + tpda_modem_in1: endpoint { 3663 + remote-endpoint = <&tpdm_modem1_out>; 3664 + }; 3665 + }; 3666 + }; 3667 + 3668 + out-ports { 3669 + port { 3670 + tpda_modem_out: endpoint { 3671 + remote-endpoint = <&funnel_modem_dl_in0>; 3672 + }; 3673 + }; 3674 + }; 3675 + }; 3676 + 3677 + funnel@10804000 { 3678 + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3679 + reg = <0x0 0x10804000 0x0 0x1000>; 3680 + 3681 + clocks = <&aoss_qmp>; 3682 + clock-names = "apb_pclk"; 3683 + 3684 + in-ports { 3685 + port { 3686 + funnel_modem_dl_in0: endpoint { 3687 + remote-endpoint = <&tpda_modem_out>; 3688 + }; 3689 + }; 3690 + }; 3691 + 3692 + out-ports { 3693 + port { 3694 + funnel_modem_dl_out: endpoint { 3695 + remote-endpoint = <&tn_ag_in13>; 3696 + }; 3697 + }; 3698 + }; 3699 + }; 3700 + 3701 + cti@1080b000 { 3702 + compatible = "arm,coresight-cti", "arm,primecell"; 3703 + reg = <0x0 0x1080b000 0x0 0x1000>; 3704 + 3705 + clocks = <&aoss_qmp>; 3706 + clock-names = "apb_pclk"; 3707 + }; 3708 + 3709 + tpdm@1082c000 { 3710 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 3711 + reg = <0x0 0x1082c000 0x0 0x1000>; 3712 + 3713 + clocks = <&aoss_qmp>; 3714 + clock-names = "apb_pclk"; 3715 + 3716 + qcom,dsb-msrs-num = <32>; 3717 + 3718 + out-ports { 3719 + port { 3720 + tpdm_gcc_out: endpoint { 3721 + remote-endpoint = <&tn_ag_in17>; 3722 + }; 3723 + }; 3724 + }; 3725 + }; 3726 + 3727 + tpdm@10841000 { 3728 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 3729 + reg = <0x0 0x10841000 0x0 0x1000>; 3730 + 3731 + clocks = <&aoss_qmp>; 3732 + clock-names = "apb_pclk"; 3733 + 3734 + qcom,cmb-msrs-num = <32>; 3735 + 3736 + out-ports { 3737 + port { 3738 + tpdm_prng_out: endpoint { 3739 + remote-endpoint = <&tn_ag_in18>; 3740 + }; 3741 + }; 3742 + }; 3743 + }; 3744 + 3745 + tpdm@1084e000 { 3746 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 3747 + reg = <0x0 0x1084e000 0x0 0x1000>; 3748 + 3749 + clocks = <&aoss_qmp>; 3750 + clock-names = "apb_pclk"; 3751 + 3752 + qcom,cmb-element-bits = <32>; 3753 + qcom,cmb-msrs-num = <32>; 3754 + 3755 + out-ports { 3756 + port { 3757 + tpdm_mm_bcv_out: endpoint { 3758 + remote-endpoint = <&tpda_mm_in0>; 3759 + }; 3760 + }; 3761 + }; 3762 + }; 3763 + 3764 + tpdm@1084f000 { 3765 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 3766 + reg = <0x0 0x1084f000 0x0 0x1000>; 3767 + 3768 + clocks = <&aoss_qmp>; 3769 + clock-names = "apb_pclk"; 3770 + 3771 + qcom,cmb-element-bits = <32>; 3772 + qcom,cmb-msrs-num = <32>; 3773 + 3774 + out-ports { 3775 + port { 3776 + tpdm_mm_lmh_out: endpoint { 3777 + remote-endpoint = <&tpda_mm_in1>; 3778 + }; 3779 + }; 3780 + }; 3781 + }; 3782 + 3783 + tpdm@10850000 { 3784 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 3785 + reg = <0x0 0x10850000 0x0 0x1000>; 3786 + 3787 + clocks = <&aoss_qmp>; 3788 + clock-names = "apb_pclk"; 3789 + 3790 + qcom,cmb-element-bits = <64>; 3791 + qcom,cmb-msrs-num = <32>; 3792 + 3793 + out-ports { 3794 + port { 3795 + tpdm_mm_dpm_out: endpoint { 3796 + remote-endpoint = <&tpda_mm_in2>; 3797 + }; 3798 + }; 3799 + }; 3800 + }; 3801 + 3802 + tpda@10851000 { 3803 + compatible = "qcom,coresight-tpda", "arm,primecell"; 3804 + reg = <0x0 0x10851000 0x0 0x1000>; 3805 + 3806 + clocks = <&aoss_qmp>; 3807 + clock-names = "apb_pclk"; 3808 + 3809 + in-ports { 3810 + #address-cells = <1>; 3811 + #size-cells = <0>; 3812 + 3813 + port@0 { 3814 + reg = <0>; 3815 + 3816 + tpda_mm_in0: endpoint { 3817 + remote-endpoint = <&tpdm_mm_bcv_out>; 3818 + }; 3819 + }; 3820 + 3821 + port@1 { 3822 + reg = <1>; 3823 + 3824 + tpda_mm_in1: endpoint { 3825 + remote-endpoint = <&tpdm_mm_lmh_out>; 3826 + }; 3827 + }; 3828 + 3829 + port@2 { 3830 + reg = <2>; 3831 + 3832 + tpda_mm_in2: endpoint { 3833 + remote-endpoint = <&tpdm_mm_dpm_out>; 3834 + }; 3835 + }; 3836 + }; 3837 + 3838 + out-ports { 3839 + port { 3840 + tpda_mm_out: endpoint { 3841 + remote-endpoint = <&tn_ag_in4>; 3842 + }; 3843 + }; 3844 + }; 3845 + }; 3846 + 3847 + tpdm@10980000 { 3848 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 3849 + reg = <0x0 0x10980000 0x0 0x1000>; 3850 + 3851 + clocks = <&aoss_qmp>; 3852 + clock-names = "apb_pclk"; 3853 + 3854 + qcom,dsb-element-bits = <32>; 3855 + qcom,dsb-msrs-num = <32>; 3856 + 3857 + out-ports { 3858 + port { 3859 + tpdm_cdsp_out: endpoint { 3860 + remote-endpoint = <&tpda_cdsp_in0>; 3861 + }; 3862 + }; 3863 + }; 3864 + }; 3865 + 3866 + tpda@10986000 { 3867 + compatible = "qcom,coresight-tpda", "arm,primecell"; 3868 + reg = <0x0 0x10986000 0x0 0x1000>; 3869 + 3870 + clocks = <&aoss_qmp>; 3871 + clock-names = "apb_pclk"; 3872 + 3873 + in-ports { 3874 + #address-cells = <1>; 3875 + #size-cells = <0>; 3876 + 3877 + port@0 { 3878 + reg = <0>; 3879 + 3880 + tpda_cdsp_in0: endpoint { 3881 + remote-endpoint = <&tpdm_cdsp_out>; 3882 + }; 3883 + }; 3884 + 3885 + port@1 { 3886 + reg = <1>; 3887 + 3888 + tpda_cdsp_in1: endpoint { 3889 + remote-endpoint = <&tpdm_cdsp_llm_out>; 3890 + }; 3891 + }; 3892 + 3893 + port@2 { 3894 + reg = <2>; 3895 + 3896 + tpda_cdsp_in2: endpoint { 3897 + remote-endpoint = <&tpdm_cdsp_llm2_out>; 3898 + }; 3899 + }; 3900 + }; 3901 + 3902 + out-ports { 3903 + port { 3904 + tpda_cdsp_out: endpoint { 3905 + remote-endpoint = <&funnel_cdsp_in0>; 3906 + }; 3907 + }; 3908 + }; 3909 + }; 3910 + 3911 + funnel@10987000 { 3912 + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3913 + reg = <0x0 0x10987000 0x0 0x1000>; 3914 + 3915 + clocks = <&aoss_qmp>; 3916 + clock-names = "apb_pclk"; 3917 + 3918 + in-ports { 3919 + port { 3920 + funnel_cdsp_in0: endpoint { 3921 + remote-endpoint = <&tpda_cdsp_out>; 3922 + }; 3923 + }; 3924 + }; 3925 + 3926 + out-ports { 3927 + port { 3928 + funnel_cdsp_out: endpoint { 3929 + remote-endpoint = <&tn_ag_in16>; 3930 + }; 3931 + }; 3932 + }; 3933 + }; 3934 + 3935 + cti@1098b000 { 3936 + compatible = "arm,coresight-cti", "arm,primecell"; 3937 + reg = <0x0 0x1098b000 0x0 0x1000>; 3938 + 3939 + clocks = <&aoss_qmp>; 3940 + clock-names = "apb_pclk"; 3941 + }; 3942 + 3943 + tpdm@109a3000 { 3944 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 3945 + reg = <0x0 0x109a3000 0x0 0x1000>; 3946 + 3947 + clocks = <&aoss_qmp>; 3948 + clock-names = "apb_pclk"; 3949 + 3950 + qcom,cmb-msrs-num = <32>; 3951 + qcom,dsb-msrs-num = <32>; 3952 + 3953 + out-ports { 3954 + port { 3955 + tpdm_pmu_out: endpoint { 3956 + remote-endpoint = <&tn_ag_in29>; 3957 + }; 3958 + }; 3959 + }; 3960 + }; 3961 + 3962 + tpdm@109a4000 { 3963 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 3964 + reg = <0x0 0x109a4000 0x0 0x1000>; 3965 + 3966 + clocks = <&aoss_qmp>; 3967 + clock-names = "apb_pclk"; 3968 + 3969 + qcom,cmb-msrs-num = <32>; 3970 + 3971 + out-ports { 3972 + port { 3973 + tpdm_ipcc_cmb_out: endpoint { 3974 + remote-endpoint = <&tn_ag_in28>; 3975 + }; 3976 + }; 3977 + }; 3978 + }; 3979 + 3980 + tpdm@109a5000 { 3981 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 3982 + reg = <0x0 0x109a5000 0x0 0x1000>; 3983 + 3984 + clocks = <&aoss_qmp>; 3985 + clock-names = "apb_pclk"; 3986 + 3987 + qcom,dsb-msrs-num = <32>; 3988 + 3989 + out-ports { 3990 + port { 3991 + tpdm_dl_mm_out: endpoint { 3992 + remote-endpoint = <&tn_ag_in25>; 3993 + }; 3994 + }; 3995 + }; 3996 + }; 3997 + 3998 + tpdm@109a6000 { 3999 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 4000 + reg = <0x0 0x109a6000 0x0 0x1000>; 4001 + 4002 + clocks = <&aoss_qmp>; 4003 + clock-names = "apb_pclk"; 4004 + 4005 + qcom,dsb-msrs-num = <32>; 4006 + 4007 + out-ports { 4008 + port { 4009 + tpdm_north_dsb_out: endpoint { 4010 + remote-endpoint = <&tn_ag_in26>; 4011 + }; 4012 + }; 4013 + }; 4014 + }; 4015 + 4016 + tpdm@109a7000 { 4017 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 4018 + reg = <0x0 0x109a7000 0x0 0x1000>; 4019 + 4020 + clocks = <&aoss_qmp>; 4021 + clock-names = "apb_pclk"; 4022 + 4023 + qcom,dsb-msrs-num = <32>; 4024 + 4025 + out-ports { 4026 + port { 4027 + tpdm_south_dsb_out: endpoint { 4028 + remote-endpoint = <&tn_ag_in27>; 4029 + }; 4030 + }; 4031 + }; 4032 + }; 4033 + 4034 + tpdm@109a8000 { 4035 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 4036 + reg = <0x0 0x109a8000 0x0 0x1000>; 4037 + 4038 + clocks = <&aoss_qmp>; 4039 + clock-names = "apb_pclk"; 4040 + 4041 + qcom,cmb-msrs-num = <32>; 4042 + 4043 + out-ports { 4044 + port { 4045 + tpdm_rdpm_cmb0_out: endpoint { 4046 + remote-endpoint = <&tn_ag_in30>; 4047 + }; 4048 + }; 4049 + }; 4050 + }; 4051 + 4052 + tpdm@109a9000 { 4053 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 4054 + reg = <0x0 0x109a9000 0x0 0x1000>; 4055 + 4056 + clocks = <&aoss_qmp>; 4057 + clock-names = "apb_pclk"; 4058 + 4059 + qcom,cmb-msrs-num = <32>; 4060 + 4061 + out-ports { 4062 + port { 4063 + tpdm_rdpm_cmb1_out: endpoint { 4064 + remote-endpoint = <&tn_ag_in31>; 4065 + }; 4066 + }; 4067 + }; 4068 + }; 4069 + 4070 + tpdm@109aa000 { 4071 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 4072 + reg = <0x0 0x109aa000 0x0 0x1000>; 4073 + 4074 + clocks = <&aoss_qmp>; 4075 + clock-names = "apb_pclk"; 4076 + 4077 + qcom,cmb-msrs-num = <32>; 4078 + 4079 + out-ports { 4080 + port { 4081 + tpdm_rdpm_cmb2_out: endpoint { 4082 + remote-endpoint = <&tn_ag_in32>; 4083 + }; 4084 + }; 4085 + }; 4086 + }; 4087 + 4088 + tn@109ab000 { 4089 + compatible = "qcom,coresight-tnoc", "arm,primecell"; 4090 + reg = <0x0 0x109ab000 0x0 0x4200>; 4091 + 4092 + clocks = <&aoss_qmp>; 4093 + clock-names = "apb_pclk"; 4094 + 4095 + in-ports { 4096 + #address-cells = <1>; 4097 + #size-cells = <0>; 4098 + 4099 + port@4 { 4100 + reg = <4>; 4101 + 4102 + tn_ag_in4: endpoint { 4103 + remote-endpoint = <&tpda_mm_out>; 4104 + }; 4105 + }; 4106 + 4107 + port@d { 4108 + reg = <0xd>; 4109 + 4110 + tn_ag_in13: endpoint { 4111 + remote-endpoint = <&funnel_modem_dl_out>; 4112 + }; 4113 + }; 4114 + 4115 + port@10 { 4116 + reg = <0x10>; 4117 + 4118 + tn_ag_in16: endpoint { 4119 + remote-endpoint = <&funnel_cdsp_out>; 4120 + }; 4121 + }; 4122 + 4123 + port@11 { 4124 + reg = <0x11>; 4125 + 4126 + tn_ag_in17: endpoint { 4127 + remote-endpoint = <&tpdm_gcc_out>; 4128 + }; 4129 + }; 4130 + 4131 + port@12 { 4132 + reg = <0x12>; 4133 + 4134 + tn_ag_in18: endpoint { 4135 + remote-endpoint = <&tpdm_prng_out>; 4136 + }; 4137 + }; 4138 + 4139 + port@13 { 4140 + reg = <0x13>; 4141 + 4142 + tn_ag_in19: endpoint { 4143 + remote-endpoint = <&tpdm_qm_out>; 4144 + }; 4145 + }; 4146 + 4147 + port@19 { 4148 + reg = <0x19>; 4149 + 4150 + tn_ag_in25: endpoint { 4151 + remote-endpoint = <&tpdm_dl_mm_out>; 4152 + }; 4153 + }; 4154 + 4155 + port@1a { 4156 + reg = <0x1a>; 4157 + 4158 + tn_ag_in26: endpoint { 4159 + remote-endpoint = <&tpdm_north_dsb_out>; 4160 + }; 4161 + }; 4162 + 4163 + port@1b { 4164 + reg = <0x1b>; 4165 + 4166 + tn_ag_in27: endpoint { 4167 + remote-endpoint = <&tpdm_south_dsb_out>; 4168 + }; 4169 + }; 4170 + 4171 + port@1c { 4172 + reg = <0x1c>; 4173 + 4174 + tn_ag_in28: endpoint { 4175 + remote-endpoint = <&tpdm_ipcc_cmb_out>; 4176 + }; 4177 + }; 4178 + 4179 + port@1d { 4180 + reg = <0x1d>; 4181 + 4182 + tn_ag_in29: endpoint { 4183 + remote-endpoint = <&tpdm_pmu_out>; 4184 + }; 4185 + }; 4186 + 4187 + port@1e { 4188 + reg = <0x1e>; 4189 + 4190 + tn_ag_in30: endpoint { 4191 + remote-endpoint = <&tpdm_rdpm_cmb0_out>; 4192 + }; 4193 + }; 4194 + 4195 + port@1f { 4196 + reg = <0x1f>; 4197 + 4198 + tn_ag_in31: endpoint { 4199 + remote-endpoint = <&tpdm_rdpm_cmb1_out>; 4200 + }; 4201 + }; 4202 + 4203 + port@20 { 4204 + reg = <0x20>; 4205 + 4206 + tn_ag_in32: endpoint { 4207 + remote-endpoint = <&tpdm_rdpm_cmb2_out>; 4208 + }; 4209 + }; 4210 + }; 4211 + 4212 + out-ports { 4213 + port { 4214 + tn_ag_out: endpoint { 4215 + remote-endpoint = <&funnel_in0_in0>; 4216 + }; 4217 + }; 4218 + }; 4219 + }; 4220 + 4221 + tpdm@109d0000 { 4222 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 4223 + reg = <0x0 0x109d0000 0x0 0x1000>; 4224 + 4225 + clocks = <&aoss_qmp>; 4226 + clock-names = "apb_pclk"; 4227 + 4228 + qcom,dsb-msrs-num = <32>; 4229 + 4230 + out-ports { 4231 + port { 4232 + tpdm_qm_out: endpoint { 4233 + remote-endpoint = <&tn_ag_in19>; 4234 + }; 4235 + }; 4236 + }; 4237 + }; 4238 + 4239 + funnel@10b04000 { 4240 + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4241 + reg = <0x0 0x10b04000 0x0 0x1000>; 4242 + 4243 + clocks = <&aoss_qmp>; 4244 + clock-names = "apb_pclk"; 4245 + 4246 + in-ports { 4247 + #address-cells = <1>; 4248 + #size-cells = <0>; 4249 + 4250 + port@6 { 4251 + reg = <6>; 4252 + 4253 + funnel_aoss_in6: endpoint { 4254 + remote-endpoint = <&tpda_aoss_out>; 4255 + }; 4256 + }; 4257 + 4258 + port@7 { 4259 + reg = <7>; 4260 + 4261 + funnel_aoss_in7: endpoint { 4262 + remote-endpoint = <&funnel_in0_out>; 4263 + }; 4264 + }; 4265 + 4266 + }; 4267 + 4268 + out-ports { 4269 + port { 4270 + funnel_aoss_out: endpoint { 4271 + remote-endpoint = <&tmc_etf_in>; 4272 + }; 4273 + }; 4274 + }; 4275 + }; 4276 + 4277 + tmc@10b05000 { 4278 + compatible = "arm,coresight-tmc", "arm,primecell"; 4279 + reg = <0x0 0x10b05000 0x0 0x1000>; 4280 + 4281 + clocks = <&aoss_qmp>; 4282 + clock-names = "apb_pclk"; 4283 + 4284 + in-ports { 4285 + port { 4286 + tmc_etf_in: endpoint { 4287 + remote-endpoint = <&funnel_aoss_out>; 4288 + }; 4289 + }; 4290 + }; 4291 + }; 4292 + 4293 + tpda@10b08000 { 4294 + compatible = "qcom,coresight-tpda", "arm,primecell"; 4295 + reg = <0x0 0x10b08000 0x0 0x1000>; 4296 + 4297 + clocks = <&aoss_qmp>; 4298 + clock-names = "apb_pclk"; 4299 + 4300 + in-ports { 4301 + #address-cells = <1>; 4302 + #size-cells = <0>; 4303 + 4304 + port@0 { 4305 + reg = <0>; 4306 + 4307 + tpda_aoss_in0: endpoint { 4308 + remote-endpoint = <&tpdm_swao_prio0_out>; 4309 + }; 4310 + }; 4311 + 4312 + port@1 { 4313 + reg = <1>; 4314 + 4315 + tpda_aoss_in1: endpoint { 4316 + remote-endpoint = <&tpdm_swao_prio1_out>; 4317 + }; 4318 + }; 4319 + 4320 + port@2 { 4321 + reg = <2>; 4322 + 4323 + tpda_aoss_in2: endpoint { 4324 + remote-endpoint = <&tpdm_swao_prio2_out>; 4325 + }; 4326 + }; 4327 + 4328 + port@3 { 4329 + reg = <3>; 4330 + 4331 + tpda_aoss_in3: endpoint { 4332 + remote-endpoint = <&tpdm_swao_prio3_out>; 4333 + }; 4334 + }; 4335 + 4336 + port@4 { 4337 + reg = <4>; 4338 + 4339 + tpda_aoss_in4: endpoint { 4340 + remote-endpoint =<&tpdm_swao_out>; 4341 + }; 4342 + }; 4343 + }; 4344 + 4345 + out-ports { 4346 + port { 4347 + tpda_aoss_out: endpoint { 4348 + remote-endpoint = <&funnel_aoss_in6>; 4349 + }; 4350 + }; 4351 + }; 4352 + }; 4353 + 4354 + tpdm@10b09000 { 4355 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 4356 + reg = <0x0 0x10b09000 0x0 0x1000>; 4357 + 4358 + clocks = <&aoss_qmp>; 4359 + clock-names = "apb_pclk"; 4360 + 4361 + qcom,cmb-element-bits = <64>; 4362 + qcom,cmb-msrs-num = <32>; 4363 + 4364 + out-ports { 4365 + port { 4366 + tpdm_swao_prio0_out: endpoint { 4367 + remote-endpoint = <&tpda_aoss_in0>; 4368 + }; 4369 + }; 4370 + }; 4371 + }; 4372 + 4373 + tpdm@10b0a000 { 4374 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 4375 + reg = <0x0 0x10b0a000 0x0 0x1000>; 4376 + 4377 + clocks = <&aoss_qmp>; 4378 + clock-names = "apb_pclk"; 4379 + 4380 + qcom,cmb-element-bits = <64>; 4381 + qcom,cmb-msrs-num = <32>; 4382 + 4383 + out-ports { 4384 + port { 4385 + tpdm_swao_prio1_out: endpoint { 4386 + remote-endpoint = <&tpda_aoss_in1>; 4387 + }; 4388 + }; 4389 + }; 4390 + }; 4391 + 4392 + tpdm@10b0b000 { 4393 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 4394 + reg = <0x0 0x10b0b000 0x0 0x1000>; 4395 + 4396 + clocks = <&aoss_qmp>; 4397 + clock-names = "apb_pclk"; 4398 + 4399 + qcom,cmb-element-bits = <64>; 4400 + qcom,cmb-msrs-num = <32>; 4401 + 4402 + out-ports { 4403 + port { 4404 + tpdm_swao_prio2_out: endpoint { 4405 + remote-endpoint = <&tpda_aoss_in2>; 4406 + }; 4407 + }; 4408 + }; 4409 + }; 4410 + 4411 + tpdm@10b0c000 { 4412 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 4413 + reg = <0x0 0x10b0c000 0x0 0x1000>; 4414 + 4415 + clocks = <&aoss_qmp>; 4416 + clock-names = "apb_pclk"; 4417 + 4418 + qcom,cmb-element-bits = <64>; 4419 + qcom,cmb-msrs-num = <32>; 4420 + 4421 + out-ports { 4422 + port { 4423 + tpdm_swao_prio3_out: endpoint { 4424 + remote-endpoint = <&tpda_aoss_in3>; 4425 + }; 4426 + }; 4427 + }; 4428 + }; 4429 + 4430 + tpdm@10b0d000 { 4431 + compatible = "qcom,coresight-tpdm", "arm,primecell"; 4432 + reg = <0x0 0x10b0d000 0x0 0x1000>; 4433 + 4434 + clocks = <&aoss_qmp>; 4435 + clock-names = "apb_pclk"; 4436 + 4437 + qcom,dsb-element-bits = <32>; 4438 + qcom,dsb-msrs-num = <32>; 4439 + 4440 + out-ports { 4441 + port { 4442 + tpdm_swao_out: endpoint { 4443 + remote-endpoint = <&tpda_aoss_in4>; 4444 + }; 4445 + }; 4446 + }; 4447 + }; 4448 + 3577 4449 apps_smmu: iommu@15000000 { 3578 4450 compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3579 4451 reg = <0x0 0x15000000 0x0 0x100000>; ··· 5466 4456 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5467 4457 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5468 4458 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4459 + }; 4460 + 4461 + tpdm-cdsp-llm { 4462 + compatible = "qcom,coresight-static-tpdm"; 4463 + qcom,cmb-element-bits = <32>; 4464 + 4465 + out-ports { 4466 + port { 4467 + tpdm_cdsp_llm_out: endpoint { 4468 + remote-endpoint = <&tpda_cdsp_in1>; 4469 + }; 4470 + }; 4471 + }; 4472 + }; 4473 + 4474 + tpdm-cdsp-llm2 { 4475 + compatible = "qcom,coresight-static-tpdm"; 4476 + qcom,cmb-element-bits = <32>; 4477 + 4478 + out-ports { 4479 + port { 4480 + tpdm_cdsp_llm2_out: endpoint { 4481 + remote-endpoint = <&tpda_cdsp_in2>; 4482 + }; 4483 + }; 4484 + }; 4485 + }; 4486 + 4487 + tpdm-modem1 { 4488 + compatible = "qcom,coresight-static-tpdm"; 4489 + qcom,dsb-element-bits = <32>; 4490 + 4491 + out-ports { 4492 + port { 4493 + tpdm_modem1_out: endpoint { 4494 + remote-endpoint = <&tpda_modem_in1>; 4495 + }; 4496 + }; 4497 + }; 5469 4498 }; 5470 4499 };

-1

arch/arm64/boot/dts/qcom/talos.dtsi

··· 532 532 533 533 qup_opp_table: opp-table-qup { 534 534 compatible = "operating-points-v2"; 535 - opp-shared; 536 535 537 536 opp-75000000 { 538 537 opp-hz = /bits/ 64 <75000000>;

+4

arch/arm64/boot/dts/qcom/x1-el2.dtso

··· 7 7 /dts-v1/; 8 8 /plugin/; 9 9 10 + &apss_watchdog { 11 + status = "okay"; 12 + }; 13 + 10 14 /* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ 11 15 &gpu_zap_shader { 12 16 status = "disabled";

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