Merge tag 'reset-for-v6.20' of https://git.pengutronix.de/git/pza/linux into soc/drivers

+7 -1

Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml

··· 10 10 - Haylen Chu <heylenay@4d2.org> 11 11 12 12 description: 13 - System controllers found on SpacemiT K1 SoC, which are capable of 13 + System controllers found on SpacemiT K1/K3 SoC, which are capable of 14 14 clock, reset and power-management functions. 15 15 16 16 properties: ··· 46 46 47 47 "#reset-cells": 48 48 const: 1 49 + description: | 50 + ID of the reset controller line. Valid IDs are defined in corresponding 51 + files: 52 + 53 + For SpacemiT K1, see include/dt-bindings/clock/spacemit,k1-syscon.h 54 + For SpacemiT K3, see include/dt-bindings/reset/spacemit,k3-resets.h 49 55 50 56 required: 51 57 - compatible

+3 -11

drivers/reset/Kconfig

··· 161 161 config RESET_K230 162 162 tristate "Reset controller driver for Canaan Kendryte K230 SoC" 163 163 depends on ARCH_CANAAN || COMPILE_TEST 164 - depends on OF 164 + default ARCH_CANAAN 165 165 help 166 166 Support for the Canaan Kendryte K230 RISC-V SoC reset controller. 167 167 Say Y if you want to control reset signals provided by this ··· 299 299 This enables the reset driver for the SoCFPGA ARMv7 platforms. This 300 300 driver gets initialized early during platform init calls. 301 301 302 - config RESET_SPACEMIT 303 - tristate "SpacemiT reset driver" 304 - depends on ARCH_SPACEMIT || COMPILE_TEST 305 - select AUXILIARY_BUS 306 - default ARCH_SPACEMIT 307 - help 308 - This enables the reset controller driver for SpacemiT SoCs, 309 - including the K1. 310 - 311 302 config RESET_SUNPLUS 312 303 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST 313 304 default ARCH_SUNPLUS ··· 397 406 This enables the reset controller driver for Xilinx ZynqMP SoCs. 398 407 399 408 source "drivers/reset/amlogic/Kconfig" 409 + source "drivers/reset/hisilicon/Kconfig" 410 + source "drivers/reset/spacemit/Kconfig" 400 411 source "drivers/reset/starfive/Kconfig" 401 412 source "drivers/reset/sti/Kconfig" 402 - source "drivers/reset/hisilicon/Kconfig" 403 413 source "drivers/reset/tegra/Kconfig" 404 414 405 415 endif

+1 -1

drivers/reset/Makefile

··· 2 2 obj-y += core.o 3 3 obj-y += amlogic/ 4 4 obj-y += hisilicon/ 5 + obj-y += spacemit/ 5 6 obj-y += starfive/ 6 7 obj-y += sti/ 7 8 obj-y += tegra/ ··· 39 38 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o 40 39 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o 41 40 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o 42 - obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o 43 41 obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o 44 42 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o 45 43 obj-$(CONFIG_RESET_TH1520) += reset-th1520.o

+4 -3

drivers/reset/core.c

··· 868 868 */ 869 869 static int __reset_add_reset_gpio_device(const struct of_phandle_args *args) 870 870 { 871 - struct property_entry properties[2] = { }; 871 + struct property_entry properties[3] = { }; 872 872 unsigned int offset, of_flags, lflags; 873 873 struct reset_gpio_lookup *rgpio_dev; 874 874 struct device *parent; 875 - int id, ret; 875 + int id, ret, prop = 0; 876 876 877 877 /* 878 878 * Currently only #gpio-cells=2 is supported with the meaning of: ··· 923 923 924 924 lflags = GPIO_PERSISTENT | (of_flags & GPIO_ACTIVE_LOW); 925 925 parent = gpio_device_to_device(gdev); 926 - properties[0] = PROPERTY_ENTRY_GPIO("reset-gpios", parent->fwnode, offset, lflags); 926 + properties[prop++] = PROPERTY_ENTRY_STRING("compatible", "reset-gpio"); 927 + properties[prop++] = PROPERTY_ENTRY_GPIO("reset-gpios", parent->fwnode, offset, lflags); 927 928 928 929 id = ida_alloc(&reset_gpio_ida, GFP_KERNEL); 929 930 if (id < 0)

+3 -6

drivers/reset/reset-gpio.c

··· 22 22 { 23 23 struct reset_gpio_priv *priv = rc_to_reset_gpio(rc); 24 24 25 - gpiod_set_value_cansleep(priv->reset, 1); 26 - 27 - return 0; 25 + return gpiod_set_value_cansleep(priv->reset, 1); 28 26 } 29 27 30 28 static int reset_gpio_deassert(struct reset_controller_dev *rc, ··· 30 32 { 31 33 struct reset_gpio_priv *priv = rc_to_reset_gpio(rc); 32 34 33 - gpiod_set_value_cansleep(priv->reset, 0); 34 - 35 - return 0; 35 + return gpiod_set_value_cansleep(priv->reset, 0); 36 36 } 37 37 38 38 static int reset_gpio_status(struct reset_controller_dev *rc, unsigned long id) ··· 107 111 .id_table = reset_gpio_ids, 108 112 .driver = { 109 113 .name = "reset-gpio", 114 + .suppress_bind_attrs = true, 110 115 }, 111 116 }; 112 117 module_auxiliary_driver(reset_gpio_driver);

+125 -44

drivers/reset/reset-imx8mp-audiomix.c

··· 3 3 * Copyright 2024 NXP 4 4 */ 5 5 6 + #include <dt-bindings/reset/fsl,imx8ulp-sim-lpav.h> 6 7 #include <dt-bindings/reset/imx8mp-reset-audiomix.h> 7 8 8 9 #include <linux/auxiliary_bus.h> 10 + #include <linux/bits.h> 9 11 #include <linux/device.h> 10 12 #include <linux/io.h> 11 13 #include <linux/module.h> 12 14 #include <linux/of.h> 13 15 #include <linux/of_address.h> 16 + #include <linux/regmap.h> 14 17 #include <linux/reset-controller.h> 15 18 16 19 #define IMX8MP_AUDIOMIX_EARC_RESET_OFFSET 0x200 17 - #define IMX8MP_AUDIOMIX_EARC_RESET_MASK BIT(0) 18 - #define IMX8MP_AUDIOMIX_EARC_PHY_RESET_MASK BIT(1) 19 - 20 20 #define IMX8MP_AUDIOMIX_DSP_RUNSTALL_OFFSET 0x108 21 - #define IMX8MP_AUDIOMIX_DSP_RUNSTALL_MASK BIT(5) 21 + 22 + #define IMX8ULP_SIM_LPAV_SYSCTRL0_OFFSET 0x8 22 23 23 24 struct imx8mp_reset_map { 24 25 unsigned int offset; ··· 27 26 bool active_low; 28 27 }; 29 28 30 - static const struct imx8mp_reset_map reset_map[] = { 29 + struct imx8mp_reset_info { 30 + const struct imx8mp_reset_map *map; 31 + int num_lines; 32 + }; 33 + 34 + static const struct imx8mp_reset_map imx8mp_reset_map[] = { 31 35 [IMX8MP_AUDIOMIX_EARC_RESET] = { 32 36 .offset = IMX8MP_AUDIOMIX_EARC_RESET_OFFSET, 33 - .mask = IMX8MP_AUDIOMIX_EARC_RESET_MASK, 37 + .mask = BIT(0), 34 38 .active_low = true, 35 39 }, 36 40 [IMX8MP_AUDIOMIX_EARC_PHY_RESET] = { 37 41 .offset = IMX8MP_AUDIOMIX_EARC_RESET_OFFSET, 38 - .mask = IMX8MP_AUDIOMIX_EARC_PHY_RESET_MASK, 42 + .mask = BIT(1), 39 43 .active_low = true, 40 44 }, 41 45 [IMX8MP_AUDIOMIX_DSP_RUNSTALL] = { 42 46 .offset = IMX8MP_AUDIOMIX_DSP_RUNSTALL_OFFSET, 43 - .mask = IMX8MP_AUDIOMIX_DSP_RUNSTALL_MASK, 47 + .mask = BIT(5), 44 48 .active_low = false, 45 49 }, 46 50 }; 47 51 52 + static const struct imx8mp_reset_info imx8mp_reset_info = { 53 + .map = imx8mp_reset_map, 54 + .num_lines = ARRAY_SIZE(imx8mp_reset_map), 55 + }; 56 + 57 + static const struct imx8mp_reset_map imx8ulp_reset_map[] = { 58 + [IMX8ULP_SIM_LPAV_HIFI4_DSP_DBG_RST] = { 59 + .offset = IMX8ULP_SIM_LPAV_SYSCTRL0_OFFSET, 60 + .mask = BIT(25), 61 + .active_low = false, 62 + }, 63 + [IMX8ULP_SIM_LPAV_HIFI4_DSP_RST] = { 64 + .offset = IMX8ULP_SIM_LPAV_SYSCTRL0_OFFSET, 65 + .mask = BIT(16), 66 + .active_low = false, 67 + }, 68 + [IMX8ULP_SIM_LPAV_HIFI4_DSP_STALL] = { 69 + .offset = IMX8ULP_SIM_LPAV_SYSCTRL0_OFFSET, 70 + .mask = BIT(13), 71 + .active_low = false, 72 + }, 73 + [IMX8ULP_SIM_LPAV_DSI_RST_BYTE_N] = { 74 + .offset = IMX8ULP_SIM_LPAV_SYSCTRL0_OFFSET, 75 + .mask = BIT(5), 76 + .active_low = true, 77 + }, 78 + [IMX8ULP_SIM_LPAV_DSI_RST_ESC_N] = { 79 + .offset = IMX8ULP_SIM_LPAV_SYSCTRL0_OFFSET, 80 + .mask = BIT(4), 81 + .active_low = true, 82 + }, 83 + [IMX8ULP_SIM_LPAV_DSI_RST_DPI_N] = { 84 + .offset = IMX8ULP_SIM_LPAV_SYSCTRL0_OFFSET, 85 + .mask = BIT(3), 86 + .active_low = true, 87 + }, 88 + }; 89 + 90 + static const struct imx8mp_reset_info imx8ulp_reset_info = { 91 + .map = imx8ulp_reset_map, 92 + .num_lines = ARRAY_SIZE(imx8ulp_reset_map), 93 + }; 94 + 48 95 struct imx8mp_audiomix_reset { 49 96 struct reset_controller_dev rcdev; 50 - spinlock_t lock; /* protect register read-modify-write cycle */ 51 - void __iomem *base; 97 + struct regmap *regmap; 98 + const struct imx8mp_reset_map *map; 52 99 }; 53 100 54 101 static struct imx8mp_audiomix_reset *to_imx8mp_audiomix_reset(struct reset_controller_dev *rcdev) ··· 108 59 unsigned long id, bool assert) 109 60 { 110 61 struct imx8mp_audiomix_reset *priv = to_imx8mp_audiomix_reset(rcdev); 111 - void __iomem *reg_addr = priv->base; 112 - unsigned int mask, offset, active_low; 113 - unsigned long reg, flags; 62 + const struct imx8mp_reset_map *reset_map = priv->map; 63 + unsigned int mask, offset, active_low, val; 114 64 115 65 mask = reset_map[id].mask; 116 66 offset = reset_map[id].offset; 117 67 active_low = reset_map[id].active_low; 68 + val = (active_low ^ assert) ? mask : ~mask; 118 69 119 - spin_lock_irqsave(&priv->lock, flags); 120 - 121 - reg = readl(reg_addr + offset); 122 - if (active_low ^ assert) 123 - reg |= mask; 124 - else 125 - reg &= ~mask; 126 - writel(reg, reg_addr + offset); 127 - 128 - spin_unlock_irqrestore(&priv->lock, flags); 129 - 130 - return 0; 70 + return regmap_update_bits(priv->regmap, offset, mask, val); 131 71 } 132 72 133 73 static int imx8mp_audiomix_reset_assert(struct reset_controller_dev *rcdev, ··· 136 98 .deassert = imx8mp_audiomix_reset_deassert, 137 99 }; 138 100 101 + static const struct regmap_config regmap_config = { 102 + .reg_bits = 32, 103 + .val_bits = 32, 104 + .reg_stride = 4, 105 + }; 106 + 107 + /* assumption: registered only if not using parent regmap */ 108 + static void imx8mp_audiomix_reset_iounmap(void *data) 109 + { 110 + void __iomem *base = (void __iomem *)data; 111 + 112 + iounmap(base); 113 + } 114 + 115 + static int imx8mp_audiomix_reset_get_regmap(struct imx8mp_audiomix_reset *priv) 116 + { 117 + void __iomem *base; 118 + struct device *dev; 119 + int ret; 120 + 121 + dev = priv->rcdev.dev; 122 + 123 + /* try to use the parent's regmap */ 124 + priv->regmap = dev_get_regmap(dev->parent, NULL); 125 + if (priv->regmap) 126 + return 0; 127 + 128 + /* ... if that's not possible then initialize the regmap right now */ 129 + base = of_iomap(dev->parent->of_node, 0); 130 + if (!base) 131 + return dev_err_probe(dev, -ENOMEM, "failed to iomap address space\n"); 132 + 133 + ret = devm_add_action_or_reset(dev, 134 + imx8mp_audiomix_reset_iounmap, 135 + (void __force *)base); 136 + if (ret) 137 + return dev_err_probe(dev, ret, "failed to register action\n"); 138 + 139 + priv->regmap = devm_regmap_init_mmio(dev, base, &regmap_config); 140 + if (IS_ERR(priv->regmap)) 141 + return dev_err_probe(dev, PTR_ERR(priv->regmap), 142 + "failed to initialize regmap\n"); 143 + 144 + return 0; 145 + } 146 + 139 147 static int imx8mp_audiomix_reset_probe(struct auxiliary_device *adev, 140 148 const struct auxiliary_device_id *id) 141 149 { 150 + const struct imx8mp_reset_info *rinfo; 142 151 struct imx8mp_audiomix_reset *priv; 143 152 struct device *dev = &adev->dev; 144 153 int ret; 154 + 155 + rinfo = (void *)id->driver_data; 145 156 146 157 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 147 158 if (!priv) 148 159 return -ENOMEM; 149 160 150 - spin_lock_init(&priv->lock); 151 - 152 161 priv->rcdev.owner = THIS_MODULE; 153 - priv->rcdev.nr_resets = ARRAY_SIZE(reset_map); 162 + priv->map = rinfo->map; 163 + priv->rcdev.nr_resets = rinfo->num_lines; 154 164 priv->rcdev.ops = &imx8mp_audiomix_reset_ops; 155 165 priv->rcdev.of_node = dev->parent->of_node; 156 166 priv->rcdev.dev = dev; 157 167 priv->rcdev.of_reset_n_cells = 1; 158 - priv->base = of_iomap(dev->parent->of_node, 0); 159 - if (!priv->base) 160 - return -ENOMEM; 161 168 162 169 dev_set_drvdata(dev, priv); 163 170 171 + ret = imx8mp_audiomix_reset_get_regmap(priv); 172 + if (ret) 173 + return dev_err_probe(dev, ret, "failed to get regmap\n"); 174 + 164 175 ret = devm_reset_controller_register(dev, &priv->rcdev); 165 176 if (ret) 166 - goto out_unmap; 177 + return dev_err_probe(dev, ret, 178 + "failed to register reset controller\n"); 167 179 168 180 return 0; 169 - 170 - out_unmap: 171 - iounmap(priv->base); 172 - return ret; 173 - } 174 - 175 - static void imx8mp_audiomix_reset_remove(struct auxiliary_device *adev) 176 - { 177 - struct imx8mp_audiomix_reset *priv = dev_get_drvdata(&adev->dev); 178 - 179 - iounmap(priv->base); 180 181 } 181 182 182 183 static const struct auxiliary_device_id imx8mp_audiomix_reset_ids[] = { 183 184 { 184 185 .name = "clk_imx8mp_audiomix.reset", 186 + .driver_data = (kernel_ulong_t)&imx8mp_reset_info, 187 + }, 188 + { 189 + .name = "clk_imx8ulp_sim_lpav.reset", 190 + .driver_data = (kernel_ulong_t)&imx8ulp_reset_info, 185 191 }, 186 192 { } 187 193 }; ··· 233 151 234 152 static struct auxiliary_driver imx8mp_audiomix_reset_driver = { 235 153 .probe = imx8mp_audiomix_reset_probe, 236 - .remove = imx8mp_audiomix_reset_remove, 237 154 .id_table = imx8mp_audiomix_reset_ids, 238 155 }; 239 156

+91 -19

drivers/reset/reset-rzg2l-usbphy-ctrl.c

··· 36 36 struct reset_control *rstc; 37 37 void __iomem *base; 38 38 struct platform_device *vdev; 39 + struct regmap_field *pwrrdy; 39 40 40 41 spinlock_t lock; 41 42 }; ··· 93 92 return !!(readl(priv->base + RESET) & port_mask); 94 93 } 95 94 95 + /* put pll and phy into reset state */ 96 + static void rzg2l_usbphy_ctrl_init(struct rzg2l_usbphy_ctrl_priv *priv) 97 + { 98 + unsigned long flags; 99 + u32 val; 100 + 101 + spin_lock_irqsave(&priv->lock, flags); 102 + val = readl(priv->base + RESET); 103 + val |= RESET_SEL_PLLRESET | RESET_PLLRESET | PHY_RESET_PORT2 | PHY_RESET_PORT1; 104 + writel(val, priv->base + RESET); 105 + spin_unlock_irqrestore(&priv->lock, flags); 106 + } 107 + 96 108 #define RZG2L_USBPHY_CTRL_PWRRDY 1 97 109 98 110 static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = { ··· 131 117 .max_register = 1, 132 118 }; 133 119 134 - static void rzg2l_usbphy_ctrl_set_pwrrdy(struct regmap_field *pwrrdy, 135 - bool power_on) 120 + static int rzg2l_usbphy_ctrl_set_pwrrdy(struct regmap_field *pwrrdy, 121 + bool power_on) 136 122 { 137 123 u32 val = power_on ? 0 : 1; 138 124 139 125 /* The initialization path guarantees that the mask is 1 bit long. */ 140 - regmap_field_update_bits(pwrrdy, 1, val); 126 + return regmap_field_update_bits(pwrrdy, 1, val); 141 127 } 142 128 143 129 static void rzg2l_usbphy_ctrl_pwrrdy_off(void *data) ··· 145 131 rzg2l_usbphy_ctrl_set_pwrrdy(data, false); 146 132 } 147 133 148 - static int rzg2l_usbphy_ctrl_pwrrdy_init(struct device *dev) 134 + static int rzg2l_usbphy_ctrl_pwrrdy_init(struct device *dev, 135 + struct rzg2l_usbphy_ctrl_priv *priv) 149 136 { 150 - struct regmap_field *pwrrdy; 151 137 struct reg_field field; 152 138 struct regmap *regmap; 153 139 const int *data; 154 140 u32 args[2]; 141 + int ret; 155 142 156 143 data = device_get_match_data(dev); 157 144 if ((uintptr_t)data != RZG2L_USBPHY_CTRL_PWRRDY) ··· 172 157 field.lsb = __ffs(args[1]); 173 158 field.msb = __fls(args[1]); 174 159 175 - pwrrdy = devm_regmap_field_alloc(dev, regmap, field); 176 - if (IS_ERR(pwrrdy)) 177 - return PTR_ERR(pwrrdy); 160 + priv->pwrrdy = devm_regmap_field_alloc(dev, regmap, field); 161 + if (IS_ERR(priv->pwrrdy)) 162 + return PTR_ERR(priv->pwrrdy); 178 163 179 - rzg2l_usbphy_ctrl_set_pwrrdy(pwrrdy, true); 164 + ret = rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, true); 165 + if (ret) 166 + return ret; 180 167 181 - return devm_add_action_or_reset(dev, rzg2l_usbphy_ctrl_pwrrdy_off, pwrrdy); 168 + return devm_add_action_or_reset(dev, rzg2l_usbphy_ctrl_pwrrdy_off, priv->pwrrdy); 182 169 } 183 170 184 171 static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev) ··· 189 172 struct rzg2l_usbphy_ctrl_priv *priv; 190 173 struct platform_device *vdev; 191 174 struct regmap *regmap; 192 - unsigned long flags; 193 175 int error; 194 - u32 val; 195 176 196 177 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 197 178 if (!priv) ··· 203 188 if (IS_ERR(regmap)) 204 189 return PTR_ERR(regmap); 205 190 206 - error = rzg2l_usbphy_ctrl_pwrrdy_init(dev); 191 + error = rzg2l_usbphy_ctrl_pwrrdy_init(dev, priv); 207 192 if (error) 208 193 return error; 209 194 ··· 226 211 goto err_pm_disable_reset_deassert; 227 212 } 228 213 229 - /* put pll and phy into reset state */ 230 - spin_lock_irqsave(&priv->lock, flags); 231 - val = readl(priv->base + RESET); 232 - val |= RESET_SEL_PLLRESET | RESET_PLLRESET | PHY_RESET_PORT2 | PHY_RESET_PORT1; 233 - writel(val, priv->base + RESET); 234 - spin_unlock_irqrestore(&priv->lock, flags); 214 + rzg2l_usbphy_ctrl_init(priv); 235 215 236 216 priv->rcdev.ops = &rzg2l_usbphy_ctrl_reset_ops; 237 217 priv->rcdev.of_reset_n_cells = 1; ··· 273 263 reset_control_assert(priv->rstc); 274 264 } 275 265 266 + static int rzg2l_usbphy_ctrl_suspend(struct device *dev) 267 + { 268 + struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(dev); 269 + u32 val; 270 + int ret; 271 + 272 + val = readl(priv->base + RESET); 273 + if (!(val & PHY_RESET_PORT2) || !(val & PHY_RESET_PORT1)) 274 + WARN(1, "Suspend with resets de-asserted\n"); 275 + 276 + pm_runtime_put_sync(dev); 277 + 278 + ret = reset_control_assert(priv->rstc); 279 + if (ret) 280 + goto rpm_resume; 281 + 282 + ret = rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, false); 283 + if (ret) 284 + goto reset_deassert; 285 + 286 + return 0; 287 + 288 + reset_deassert: 289 + reset_control_deassert(priv->rstc); 290 + rpm_resume: 291 + pm_runtime_resume_and_get(dev); 292 + return ret; 293 + } 294 + 295 + static int rzg2l_usbphy_ctrl_resume(struct device *dev) 296 + { 297 + struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(dev); 298 + int ret; 299 + 300 + ret = rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, true); 301 + if (ret) 302 + return ret; 303 + 304 + ret = reset_control_deassert(priv->rstc); 305 + if (ret) 306 + goto pwrrdy_off; 307 + 308 + ret = pm_runtime_resume_and_get(dev); 309 + if (ret) 310 + goto reset_assert; 311 + 312 + rzg2l_usbphy_ctrl_init(priv); 313 + 314 + return 0; 315 + 316 + reset_assert: 317 + reset_control_assert(priv->rstc); 318 + pwrrdy_off: 319 + rzg2l_usbphy_ctrl_set_pwrrdy(priv->pwrrdy, false); 320 + return ret; 321 + } 322 + 323 + static DEFINE_SIMPLE_DEV_PM_OPS(rzg2l_usbphy_ctrl_pm_ops, 324 + rzg2l_usbphy_ctrl_suspend, 325 + rzg2l_usbphy_ctrl_resume); 326 + 276 327 static struct platform_driver rzg2l_usbphy_ctrl_driver = { 277 328 .driver = { 278 329 .name = "rzg2l_usbphy_ctrl", 279 330 .of_match_table = rzg2l_usbphy_ctrl_match_table, 331 + .pm = pm_ptr(&rzg2l_usbphy_ctrl_pm_ops), 280 332 }, 281 333 .probe = rzg2l_usbphy_ctrl_probe, 282 334 .remove = rzg2l_usbphy_ctrl_remove,

+10 -99

drivers/reset/reset-spacemit.c drivers/reset/spacemit/reset-spacemit-k1.c

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 3 - /* SpacemiT reset controller driver */ 3 + /* SpacemiT K1 reset controller driver */ 4 4 5 - #include <linux/auxiliary_bus.h> 6 - #include <linux/container_of.h> 7 - #include <linux/device.h> 8 5 #include <linux/module.h> 9 - #include <linux/regmap.h> 10 - #include <linux/reset-controller.h> 11 - #include <linux/types.h> 12 6 13 - #include <soc/spacemit/k1-syscon.h> 14 7 #include <dt-bindings/clock/spacemit,k1-syscon.h> 8 + #include <soc/spacemit/k1-syscon.h> 15 9 16 - struct ccu_reset_data { 17 - u32 offset; 18 - u32 assert_mask; 19 - u32 deassert_mask; 20 - }; 21 - 22 - struct ccu_reset_controller_data { 23 - const struct ccu_reset_data *reset_data; /* array */ 24 - size_t count; 25 - }; 26 - 27 - struct ccu_reset_controller { 28 - struct reset_controller_dev rcdev; 29 - const struct ccu_reset_controller_data *data; 30 - struct regmap *regmap; 31 - }; 32 - 33 - #define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ 34 - { \ 35 - .offset = (_offset), \ 36 - .assert_mask = (_assert_mask), \ 37 - .deassert_mask = (_deassert_mask), \ 38 - } 10 + #include "reset-spacemit-common.h" 39 11 40 12 static const struct ccu_reset_data k1_mpmu_resets[] = { 41 13 [RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), ··· 186 214 .count = ARRAY_SIZE(k1_apbc2_resets), 187 215 }; 188 216 189 - static int spacemit_reset_update(struct reset_controller_dev *rcdev, 190 - unsigned long id, bool assert) 191 - { 192 - struct ccu_reset_controller *controller; 193 - const struct ccu_reset_data *data; 194 - u32 mask; 195 - u32 val; 196 - 197 - controller = container_of(rcdev, struct ccu_reset_controller, rcdev); 198 - data = &controller->data->reset_data[id]; 199 - mask = data->assert_mask | data->deassert_mask; 200 - val = assert ? data->assert_mask : data->deassert_mask; 201 - 202 - return regmap_update_bits(controller->regmap, data->offset, mask, val); 203 - } 204 - 205 - static int spacemit_reset_assert(struct reset_controller_dev *rcdev, 206 - unsigned long id) 207 - { 208 - return spacemit_reset_update(rcdev, id, true); 209 - } 210 - 211 - static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, 212 - unsigned long id) 213 - { 214 - return spacemit_reset_update(rcdev, id, false); 215 - } 216 - 217 - static const struct reset_control_ops spacemit_reset_control_ops = { 218 - .assert = spacemit_reset_assert, 219 - .deassert = spacemit_reset_deassert, 220 - }; 221 - 222 - static int spacemit_reset_controller_register(struct device *dev, 223 - struct ccu_reset_controller *controller) 224 - { 225 - struct reset_controller_dev *rcdev = &controller->rcdev; 226 - 227 - rcdev->ops = &spacemit_reset_control_ops; 228 - rcdev->owner = THIS_MODULE; 229 - rcdev->of_node = dev->of_node; 230 - rcdev->nr_resets = controller->data->count; 231 - 232 - return devm_reset_controller_register(dev, &controller->rcdev); 233 - } 234 - 235 - static int spacemit_reset_probe(struct auxiliary_device *adev, 236 - const struct auxiliary_device_id *id) 237 - { 238 - struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev); 239 - struct ccu_reset_controller *controller; 240 - struct device *dev = &adev->dev; 241 - 242 - controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); 243 - if (!controller) 244 - return -ENOMEM; 245 - controller->data = (const struct ccu_reset_controller_data *)id->driver_data; 246 - controller->regmap = rdev->regmap; 247 - 248 - return spacemit_reset_controller_register(dev, controller); 249 - } 250 - 251 217 #define K1_AUX_DEV_ID(_unit) \ 252 218 { \ 253 - .name = "spacemit_ccu_k1." #_unit "-reset", \ 219 + .name = "spacemit_ccu.k1-" #_unit "-reset", \ 254 220 .driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \ 255 221 } 256 222 257 - static const struct auxiliary_device_id spacemit_reset_ids[] = { 223 + static const struct auxiliary_device_id spacemit_k1_reset_ids[] = { 258 224 K1_AUX_DEV_ID(mpmu), 259 225 K1_AUX_DEV_ID(apbc), 260 226 K1_AUX_DEV_ID(apmu), 261 227 K1_AUX_DEV_ID(rcpu), 262 228 K1_AUX_DEV_ID(rcpu2), 263 229 K1_AUX_DEV_ID(apbc2), 264 - { }, 230 + { /* sentinel */ } 265 231 }; 266 - MODULE_DEVICE_TABLE(auxiliary, spacemit_reset_ids); 232 + MODULE_DEVICE_TABLE(auxiliary, spacemit_k1_reset_ids); 267 233 268 234 static struct auxiliary_driver spacemit_k1_reset_driver = { 269 235 .probe = spacemit_reset_probe, 270 - .id_table = spacemit_reset_ids, 236 + .id_table = spacemit_k1_reset_ids, 271 237 }; 272 238 module_auxiliary_driver(spacemit_k1_reset_driver); 273 239 240 + MODULE_IMPORT_NS("RESET_SPACEMIT"); 274 241 MODULE_AUTHOR("Alex Elder <elder@kernel.org>"); 275 - MODULE_DESCRIPTION("SpacemiT reset controller driver"); 242 + MODULE_DESCRIPTION("SpacemiT K1 reset controller driver"); 276 243 MODULE_LICENSE("GPL");

+36

drivers/reset/spacemit/Kconfig

··· 1 + # SPDX-License-Identifier: GPL-2.0-only 2 + 3 + menu "Reset support for SpacemiT platforms" 4 + depends on ARCH_SPACEMIT || COMPILE_TEST 5 + 6 + config RESET_SPACEMIT_COMMON 7 + tristate 8 + select AUXILIARY_BUS 9 + help 10 + Common reset controller infrastructure for SpacemiT SoCs. 11 + This provides shared code and helper functions used by 12 + reset drivers for various SpacemiT SoC families. 13 + 14 + config RESET_SPACEMIT_K1 15 + tristate "Support for SpacemiT K1 SoC" 16 + depends on SPACEMIT_K1_CCU 17 + select RESET_SPACEMIT_COMMON 18 + default SPACEMIT_K1_CCU 19 + help 20 + Support for reset controller in SpacemiT K1 SoC. 21 + This driver works with the SpacemiT K1 clock controller 22 + unit (CCU) driver to provide reset control functionality 23 + for various peripherals and subsystems in the SoC. 24 + 25 + config RESET_SPACEMIT_K3 26 + tristate "Support for SpacemiT K3 SoC" 27 + depends on SPACEMIT_K3_CCU 28 + select RESET_SPACEMIT_COMMON 29 + default SPACEMIT_K3_CCU 30 + help 31 + Support for reset controller in SpacemiT K3 SoC. 32 + This driver works with the SpacemiT K3 clock controller 33 + unit (CCU) driver to provide reset control functionality 34 + for various peripherals and subsystems in the SoC. 35 + 36 + endmenu

+5

drivers/reset/spacemit/Makefile

··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + obj-$(CONFIG_RESET_SPACEMIT_COMMON) += reset-spacemit-common.o 3 + 4 + obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o 5 + obj-$(CONFIG_RESET_SPACEMIT_K3) += reset-spacemit-k3.o

+77

drivers/reset/spacemit/reset-spacemit-common.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + 3 + /* SpacemiT reset controller driver - common implementation */ 4 + 5 + #include <linux/container_of.h> 6 + #include <linux/device.h> 7 + #include <linux/module.h> 8 + 9 + #include <soc/spacemit/ccu.h> 10 + 11 + #include "reset-spacemit-common.h" 12 + 13 + static int spacemit_reset_update(struct reset_controller_dev *rcdev, 14 + unsigned long id, bool assert) 15 + { 16 + struct ccu_reset_controller *controller; 17 + const struct ccu_reset_data *data; 18 + u32 mask; 19 + u32 val; 20 + 21 + controller = container_of(rcdev, struct ccu_reset_controller, rcdev); 22 + data = &controller->data->reset_data[id]; 23 + mask = data->assert_mask | data->deassert_mask; 24 + val = assert ? data->assert_mask : data->deassert_mask; 25 + 26 + return regmap_update_bits(controller->regmap, data->offset, mask, val); 27 + } 28 + 29 + static int spacemit_reset_assert(struct reset_controller_dev *rcdev, 30 + unsigned long id) 31 + { 32 + return spacemit_reset_update(rcdev, id, true); 33 + } 34 + 35 + static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, 36 + unsigned long id) 37 + { 38 + return spacemit_reset_update(rcdev, id, false); 39 + } 40 + 41 + static const struct reset_control_ops spacemit_reset_control_ops = { 42 + .assert = spacemit_reset_assert, 43 + .deassert = spacemit_reset_deassert, 44 + }; 45 + 46 + static int spacemit_reset_controller_register(struct device *dev, 47 + struct ccu_reset_controller *controller) 48 + { 49 + struct reset_controller_dev *rcdev = &controller->rcdev; 50 + 51 + rcdev->ops = &spacemit_reset_control_ops; 52 + rcdev->owner = dev->driver->owner; 53 + rcdev->of_node = dev->of_node; 54 + rcdev->nr_resets = controller->data->count; 55 + 56 + return devm_reset_controller_register(dev, &controller->rcdev); 57 + } 58 + 59 + int spacemit_reset_probe(struct auxiliary_device *adev, 60 + const struct auxiliary_device_id *id) 61 + { 62 + struct spacemit_ccu_adev *rdev = to_spacemit_ccu_adev(adev); 63 + struct ccu_reset_controller *controller; 64 + struct device *dev = &adev->dev; 65 + 66 + controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); 67 + if (!controller) 68 + return -ENOMEM; 69 + controller->data = (const struct ccu_reset_controller_data *)id->driver_data; 70 + controller->regmap = rdev->regmap; 71 + 72 + return spacemit_reset_controller_register(dev, controller); 73 + } 74 + EXPORT_SYMBOL_NS_GPL(spacemit_reset_probe, "RESET_SPACEMIT"); 75 + 76 + MODULE_DESCRIPTION("SpacemiT reset controller driver - common code"); 77 + MODULE_LICENSE("GPL");

+42

drivers/reset/spacemit/reset-spacemit-common.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + /* 3 + * SpacemiT reset controller driver - common definitions 4 + */ 5 + 6 + #ifndef _RESET_SPACEMIT_COMMON_H_ 7 + #define _RESET_SPACEMIT_COMMON_H_ 8 + 9 + #include <linux/auxiliary_bus.h> 10 + #include <linux/regmap.h> 11 + #include <linux/reset-controller.h> 12 + #include <linux/types.h> 13 + 14 + struct ccu_reset_data { 15 + u32 offset; 16 + u32 assert_mask; 17 + u32 deassert_mask; 18 + }; 19 + 20 + struct ccu_reset_controller_data { 21 + const struct ccu_reset_data *reset_data; /* array */ 22 + size_t count; 23 + }; 24 + 25 + struct ccu_reset_controller { 26 + struct reset_controller_dev rcdev; 27 + const struct ccu_reset_controller_data *data; 28 + struct regmap *regmap; 29 + }; 30 + 31 + #define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ 32 + { \ 33 + .offset = (_offset), \ 34 + .assert_mask = (_assert_mask), \ 35 + .deassert_mask = (_deassert_mask), \ 36 + } 37 + 38 + /* Common probe function */ 39 + int spacemit_reset_probe(struct auxiliary_device *adev, 40 + const struct auxiliary_device_id *id); 41 + 42 + #endif /* _RESET_SPACEMIT_COMMON_H_ */

+233

drivers/reset/spacemit/reset-spacemit-k3.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + 3 + /* SpacemiT K3 reset controller driver */ 4 + 5 + #include <linux/module.h> 6 + 7 + #include <dt-bindings/reset/spacemit,k3-resets.h> 8 + #include <soc/spacemit/k3-syscon.h> 9 + 10 + #include "reset-spacemit-common.h" 11 + 12 + static const struct ccu_reset_data k3_mpmu_resets[] = { 13 + [RESET_MPMU_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), 14 + [RESET_MPMU_RIPC] = RESET_DATA(MPMU_RIPCCR, BIT(2), 0), 15 + }; 16 + 17 + static const struct ccu_reset_controller_data k3_mpmu_reset_data = { 18 + .reset_data = k3_mpmu_resets, 19 + .count = ARRAY_SIZE(k3_mpmu_resets), 20 + }; 21 + 22 + static const struct ccu_reset_data k3_apbc_resets[] = { 23 + [RESET_APBC_UART0] = RESET_DATA(APBC_UART0_CLK_RST, BIT(2), 0), 24 + [RESET_APBC_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), 25 + [RESET_APBC_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), 26 + [RESET_APBC_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), 27 + [RESET_APBC_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), 28 + [RESET_APBC_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), 29 + [RESET_APBC_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), 30 + [RESET_APBC_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), 31 + [RESET_APBC_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), 32 + [RESET_APBC_UART10] = RESET_DATA(APBC_UART10_CLK_RST, BIT(2), 0), 33 + [RESET_APBC_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), 34 + [RESET_APBC_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), 0), 35 + [RESET_APBC_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), 0), 36 + [RESET_APBC_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), 0), 37 + [RESET_APBC_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), 0), 38 + [RESET_APBC_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), 0), 39 + [RESET_APBC_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), 0), 40 + [RESET_APBC_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), 0), 41 + [RESET_APBC_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), 0), 42 + [RESET_APBC_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), 0), 43 + [RESET_APBC_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), 0), 44 + [RESET_APBC_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), 0), 45 + [RESET_APBC_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), 0), 46 + [RESET_APBC_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), 0), 47 + [RESET_APBC_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), 0), 48 + [RESET_APBC_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), 0), 49 + [RESET_APBC_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), 0), 50 + [RESET_APBC_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), 0), 51 + [RESET_APBC_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), 0), 52 + [RESET_APBC_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), 0), 53 + [RESET_APBC_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), 0), 54 + [RESET_APBC_SPI0] = RESET_DATA(APBC_SSP0_CLK_RST, BIT(2), 0), 55 + [RESET_APBC_SPI1] = RESET_DATA(APBC_SSP1_CLK_RST, BIT(2), 0), 56 + [RESET_APBC_SPI3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), 57 + [RESET_APBC_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), 58 + [RESET_APBC_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), 59 + [RESET_APBC_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), 60 + [RESET_APBC_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), 61 + [RESET_APBC_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), 62 + [RESET_APBC_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), 63 + [RESET_APBC_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), 64 + [RESET_APBC_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), 65 + [RESET_APBC_TIMERS0] = RESET_DATA(APBC_TIMERS0_CLK_RST, BIT(2), 0), 66 + [RESET_APBC_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), 67 + [RESET_APBC_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), 68 + [RESET_APBC_TIMERS3] = RESET_DATA(APBC_TIMERS3_CLK_RST, BIT(2), 0), 69 + [RESET_APBC_TIMERS4] = RESET_DATA(APBC_TIMERS4_CLK_RST, BIT(2), 0), 70 + [RESET_APBC_TIMERS5] = RESET_DATA(APBC_TIMERS5_CLK_RST, BIT(2), 0), 71 + [RESET_APBC_TIMERS6] = RESET_DATA(APBC_TIMERS6_CLK_RST, BIT(2), 0), 72 + [RESET_APBC_TIMERS7] = RESET_DATA(APBC_TIMERS7_CLK_RST, BIT(2), 0), 73 + [RESET_APBC_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), 74 + [RESET_APBC_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), 75 + [RESET_APBC_I2S0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), 76 + [RESET_APBC_I2S1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), 77 + [RESET_APBC_I2S2] = RESET_DATA(APBC_SSPA2_CLK_RST, BIT(2), 0), 78 + [RESET_APBC_I2S3] = RESET_DATA(APBC_SSPA3_CLK_RST, BIT(2), 0), 79 + [RESET_APBC_I2S4] = RESET_DATA(APBC_SSPA4_CLK_RST, BIT(2), 0), 80 + [RESET_APBC_I2S5] = RESET_DATA(APBC_SSPA5_CLK_RST, BIT(2), 0), 81 + [RESET_APBC_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), 82 + [RESET_APBC_IR0] = RESET_DATA(APBC_IR0_CLK_RST, BIT(2), 0), 83 + [RESET_APBC_IR1] = RESET_DATA(APBC_IR1_CLK_RST, BIT(2), 0), 84 + [RESET_APBC_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), 85 + [RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), 86 + [RESET_APBC_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), 87 + [RESET_APBC_CAN1] = RESET_DATA(APBC_CAN1_CLK_RST, BIT(2), 0), 88 + [RESET_APBC_CAN2] = RESET_DATA(APBC_CAN2_CLK_RST, BIT(2), 0), 89 + [RESET_APBC_CAN3] = RESET_DATA(APBC_CAN3_CLK_RST, BIT(2), 0), 90 + [RESET_APBC_CAN4] = RESET_DATA(APBC_CAN4_CLK_RST, BIT(2), 0), 91 + }; 92 + 93 + static const struct ccu_reset_controller_data k3_apbc_reset_data = { 94 + .reset_data = k3_apbc_resets, 95 + .count = ARRAY_SIZE(k3_apbc_resets), 96 + }; 97 + 98 + static const struct ccu_reset_data k3_apmu_resets[] = { 99 + [RESET_APMU_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), 100 + [RESET_APMU_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), 101 + [RESET_APMU_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), 102 + [RESET_APMU_ISP_CIBUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), 103 + [RESET_APMU_DSI_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), 104 + [RESET_APMU_LCD] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), 105 + [RESET_APMU_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), 106 + [RESET_APMU_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), 107 + [RESET_APMU_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(15)), 108 + [RESET_APMU_SC2_HCLK] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(0)), 109 + [RESET_APMU_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), 110 + [RESET_APMU_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), 111 + [RESET_APMU_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), 112 + [RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), 113 + [RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), 114 + [RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), 115 + [RESET_APMU_USB2] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, 116 + BIT(1)|BIT(2)|BIT(3)), 117 + [RESET_APMU_USB3_PORTA] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, 118 + BIT(5)|BIT(6)|BIT(7)), 119 + [RESET_APMU_USB3_PORTB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, 120 + BIT(9)|BIT(10)|BIT(11)), 121 + [RESET_APMU_USB3_PORTC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, 122 + BIT(13)|BIT(14)|BIT(15)), 123 + [RESET_APMU_USB3_PORTD] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, 124 + BIT(17)|BIT(18)|BIT(19)), 125 + [RESET_APMU_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), 126 + [RESET_APMU_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), 127 + [RESET_APMU_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), 128 + [RESET_APMU_AES_WTM] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), 129 + [RESET_APMU_MCB_DCLK] = RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(0)), 130 + [RESET_APMU_MCB_ACLK] = RESET_DATA(APMU_MCB_CLK_RES_CTRL, 0, BIT(1)), 131 + [RESET_APMU_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), 132 + [RESET_APMU_DTC] = RESET_DATA(APMU_DTC_CLK_RES_CTRL, 0, BIT(0)), 133 + [RESET_APMU_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), 134 + [RESET_APMU_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), 135 + [RESET_APMU_CPU0_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(0), 0), 136 + [RESET_APMU_CPU0_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(1), 0), 137 + [RESET_APMU_CPU1_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(3), 0), 138 + [RESET_APMU_CPU1_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(4), 0), 139 + [RESET_APMU_CPU2_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(6), 0), 140 + [RESET_APMU_CPU2_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(7), 0), 141 + [RESET_APMU_CPU3_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(9), 0), 142 + [RESET_APMU_CPU3_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(10), 0), 143 + [RESET_APMU_C0_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(12), 0), 144 + [RESET_APMU_CPU4_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(16), 0), 145 + [RESET_APMU_CPU4_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(17), 0), 146 + [RESET_APMU_CPU5_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(19), 0), 147 + [RESET_APMU_CPU5_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(20), 0), 148 + [RESET_APMU_CPU6_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(22), 0), 149 + [RESET_APMU_CPU6_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(23), 0), 150 + [RESET_APMU_CPU7_POP] = RESET_DATA(APMU_PMU_CC2_AP, BIT(25), 0), 151 + [RESET_APMU_CPU7_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(26), 0), 152 + [RESET_APMU_C1_MPSUB_SW] = RESET_DATA(APMU_PMU_CC2_AP, BIT(28), 0), 153 + [RESET_APMU_MPSUB_DBG] = RESET_DATA(APMU_PMU_CC2_AP, BIT(29), 0), 154 + [RESET_APMU_UCIE] = RESET_DATA(APMU_UCIE_CTRL, 155 + BIT(1) | BIT(2) | BIT(3), 0), 156 + [RESET_APMU_RCPU] = RESET_DATA(APMU_RCPU_CLK_RES_CTRL, 0, 157 + BIT(3) | BIT(2) | BIT(0)), 158 + [RESET_APMU_DSI4LN2_ESCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(3)), 159 + [RESET_APMU_DSI4LN2_LCD_SW] = RESET_DATA(APMU_LCD_CLK_RES_CTRL3, 0, BIT(4)), 160 + [RESET_APMU_DSI4LN2_LCD_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(9)), 161 + [RESET_APMU_DSI4LN2_LCD_DSCCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL4, 0, BIT(15)), 162 + [RESET_APMU_DSI4LN2_DPU_ACLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(0)), 163 + [RESET_APMU_DPU_ACLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL5, 0, BIT(15)), 164 + [RESET_APMU_UFS_ACLK] = RESET_DATA(APMU_UFS_CLK_RES_CTRL, 0, BIT(0)), 165 + [RESET_APMU_EDP0] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(0)), 166 + [RESET_APMU_EDP1] = RESET_DATA(APMU_LCD_EDP_CTRL, 0, BIT(16)), 167 + [RESET_APMU_PCIE_PORTA] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_A, 0, 168 + BIT(5) | BIT(4) | BIT(3)), 169 + [RESET_APMU_PCIE_PORTB] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_B, 0, 170 + BIT(5) | BIT(4) | BIT(3)), 171 + [RESET_APMU_PCIE_PORTC] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_C, 0, 172 + BIT(5) | BIT(4) | BIT(3)), 173 + [RESET_APMU_PCIE_PORTD] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_D, 0, 174 + BIT(5) | BIT(4) | BIT(3)), 175 + [RESET_APMU_PCIE_PORTE] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_E, 0, 176 + BIT(5) | BIT(4) | BIT(3)), 177 + [RESET_APMU_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), 178 + [RESET_APMU_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), 179 + [RESET_APMU_EMAC2] = RESET_DATA(APMU_EMAC2_CLK_RES_CTRL, 0, BIT(1)), 180 + [RESET_APMU_ESPI_MCLK] = RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(0)), 181 + [RESET_APMU_ESPI_SCLK] = RESET_DATA(APMU_ESPI_CLK_RES_CTRL, 0, BIT(2)), 182 + }; 183 + 184 + static const struct ccu_reset_controller_data k3_apmu_reset_data = { 185 + .reset_data = k3_apmu_resets, 186 + .count = ARRAY_SIZE(k3_apmu_resets), 187 + }; 188 + 189 + static const struct ccu_reset_data k3_dciu_resets[] = { 190 + [RESET_DCIU_HDMA] = RESET_DATA(DCIU_DMASYS_RSTN, 0, BIT(0)), 191 + [RESET_DCIU_DMA350] = RESET_DATA(DCIU_DMASYS_SDMA_RSTN, 0, BIT(0)), 192 + [RESET_DCIU_DMA350_0] = RESET_DATA(DCIU_DMASYS_S0_RSTN, 0, BIT(0)), 193 + [RESET_DCIU_DMA350_1] = RESET_DATA(DCIU_DMASYS_S1_RSTN, 0, BIT(0)), 194 + [RESET_DCIU_AXIDMA0] = RESET_DATA(DCIU_DMASYS_A0_RSTN, 0, BIT(0)), 195 + [RESET_DCIU_AXIDMA1] = RESET_DATA(DCIU_DMASYS_A1_RSTN, 0, BIT(0)), 196 + [RESET_DCIU_AXIDMA2] = RESET_DATA(DCIU_DMASYS_A2_RSTN, 0, BIT(0)), 197 + [RESET_DCIU_AXIDMA3] = RESET_DATA(DCIU_DMASYS_A3_RSTN, 0, BIT(0)), 198 + [RESET_DCIU_AXIDMA4] = RESET_DATA(DCIU_DMASYS_A4_RSTN, 0, BIT(0)), 199 + [RESET_DCIU_AXIDMA5] = RESET_DATA(DCIU_DMASYS_A5_RSTN, 0, BIT(0)), 200 + [RESET_DCIU_AXIDMA6] = RESET_DATA(DCIU_DMASYS_A6_RSTN, 0, BIT(0)), 201 + [RESET_DCIU_AXIDMA7] = RESET_DATA(DCIU_DMASYS_A7_RSTN, 0, BIT(0)), 202 + }; 203 + 204 + static const struct ccu_reset_controller_data k3_dciu_reset_data = { 205 + .reset_data = k3_dciu_resets, 206 + .count = ARRAY_SIZE(k3_dciu_resets), 207 + }; 208 + 209 + #define K3_AUX_DEV_ID(_unit) \ 210 + { \ 211 + .name = "spacemit_ccu.k3-" #_unit "-reset", \ 212 + .driver_data = (kernel_ulong_t)&k3_ ## _unit ## _reset_data, \ 213 + } 214 + 215 + static const struct auxiliary_device_id spacemit_k3_reset_ids[] = { 216 + K3_AUX_DEV_ID(mpmu), 217 + K3_AUX_DEV_ID(apbc), 218 + K3_AUX_DEV_ID(apmu), 219 + K3_AUX_DEV_ID(dciu), 220 + { /* sentinel */ } 221 + }; 222 + MODULE_DEVICE_TABLE(auxiliary, spacemit_k3_reset_ids); 223 + 224 + static struct auxiliary_driver spacemit_k3_reset_driver = { 225 + .probe = spacemit_reset_probe, 226 + .id_table = spacemit_k3_reset_ids, 227 + }; 228 + module_auxiliary_driver(spacemit_k3_reset_driver); 229 + 230 + MODULE_IMPORT_NS("RESET_SPACEMIT"); 231 + MODULE_AUTHOR("Guodong Xu <guodong@riscstar.com>"); 232 + MODULE_DESCRIPTION("SpacemiT K3 reset controller driver"); 233 + MODULE_LICENSE("GPL");

+171

include/dt-bindings/reset/spacemit,k3-resets.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2025 SpacemiT Technology Co. Ltd 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_ 7 + #define _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_ 8 + 9 + /* MPMU resets */ 10 + #define RESET_MPMU_WDT 0 11 + #define RESET_MPMU_RIPC 1 12 + 13 + /* APBC resets */ 14 + #define RESET_APBC_UART0 0 15 + #define RESET_APBC_UART2 1 16 + #define RESET_APBC_UART3 2 17 + #define RESET_APBC_UART4 3 18 + #define RESET_APBC_UART5 4 19 + #define RESET_APBC_UART6 5 20 + #define RESET_APBC_UART7 6 21 + #define RESET_APBC_UART8 7 22 + #define RESET_APBC_UART9 8 23 + #define RESET_APBC_UART10 9 24 + #define RESET_APBC_GPIO 10 25 + #define RESET_APBC_PWM0 11 26 + #define RESET_APBC_PWM1 12 27 + #define RESET_APBC_PWM2 13 28 + #define RESET_APBC_PWM3 14 29 + #define RESET_APBC_PWM4 15 30 + #define RESET_APBC_PWM5 16 31 + #define RESET_APBC_PWM6 17 32 + #define RESET_APBC_PWM7 18 33 + #define RESET_APBC_PWM8 19 34 + #define RESET_APBC_PWM9 20 35 + #define RESET_APBC_PWM10 21 36 + #define RESET_APBC_PWM11 22 37 + #define RESET_APBC_PWM12 23 38 + #define RESET_APBC_PWM13 24 39 + #define RESET_APBC_PWM14 25 40 + #define RESET_APBC_PWM15 26 41 + #define RESET_APBC_PWM16 27 42 + #define RESET_APBC_PWM17 28 43 + #define RESET_APBC_PWM18 29 44 + #define RESET_APBC_PWM19 30 45 + #define RESET_APBC_SPI0 31 46 + #define RESET_APBC_SPI1 32 47 + #define RESET_APBC_SPI3 33 48 + #define RESET_APBC_RTC 34 49 + #define RESET_APBC_TWSI0 35 50 + #define RESET_APBC_TWSI1 36 51 + #define RESET_APBC_TWSI2 37 52 + #define RESET_APBC_TWSI4 38 53 + #define RESET_APBC_TWSI5 39 54 + #define RESET_APBC_TWSI6 40 55 + #define RESET_APBC_TWSI8 41 56 + #define RESET_APBC_TIMERS0 42 57 + #define RESET_APBC_TIMERS1 43 58 + #define RESET_APBC_TIMERS2 44 59 + #define RESET_APBC_TIMERS3 45 60 + #define RESET_APBC_TIMERS4 46 61 + #define RESET_APBC_TIMERS5 47 62 + #define RESET_APBC_TIMERS6 48 63 + #define RESET_APBC_TIMERS7 49 64 + #define RESET_APBC_AIB 50 65 + #define RESET_APBC_ONEWIRE 51 66 + #define RESET_APBC_I2S0 52 67 + #define RESET_APBC_I2S1 53 68 + #define RESET_APBC_I2S2 54 69 + #define RESET_APBC_I2S3 55 70 + #define RESET_APBC_I2S4 56 71 + #define RESET_APBC_I2S5 57 72 + #define RESET_APBC_DRO 58 73 + #define RESET_APBC_IR0 59 74 + #define RESET_APBC_IR1 60 75 + #define RESET_APBC_TSEN 61 76 + #define RESET_IPC_AP2AUD 62 77 + #define RESET_APBC_CAN0 63 78 + #define RESET_APBC_CAN1 64 79 + #define RESET_APBC_CAN2 65 80 + #define RESET_APBC_CAN3 66 81 + #define RESET_APBC_CAN4 67 82 + 83 + /* APMU resets */ 84 + #define RESET_APMU_CSI 0 85 + #define RESET_APMU_CCIC2PHY 1 86 + #define RESET_APMU_CCIC3PHY 2 87 + #define RESET_APMU_ISP_CIBUS 3 88 + #define RESET_APMU_DSI_ESC 4 89 + #define RESET_APMU_LCD 5 90 + #define RESET_APMU_V2D 6 91 + #define RESET_APMU_LCD_MCLK 7 92 + #define RESET_APMU_LCD_DSCCLK 8 93 + #define RESET_APMU_SC2_HCLK 9 94 + #define RESET_APMU_CCIC_4X 10 95 + #define RESET_APMU_CCIC1_PHY 11 96 + #define RESET_APMU_SDH_AXI 12 97 + #define RESET_APMU_SDH0 13 98 + #define RESET_APMU_SDH1 14 99 + #define RESET_APMU_SDH2 15 100 + #define RESET_APMU_USB2 16 101 + #define RESET_APMU_USB3_PORTA 17 102 + #define RESET_APMU_USB3_PORTB 18 103 + #define RESET_APMU_USB3_PORTC 19 104 + #define RESET_APMU_USB3_PORTD 20 105 + #define RESET_APMU_QSPI 21 106 + #define RESET_APMU_QSPI_BUS 22 107 + #define RESET_APMU_DMA 23 108 + #define RESET_APMU_AES_WTM 24 109 + #define RESET_APMU_MCB_DCLK 25 110 + #define RESET_APMU_MCB_ACLK 26 111 + #define RESET_APMU_VPU 27 112 + #define RESET_APMU_DTC 28 113 + #define RESET_APMU_GPU 29 114 + #define RESET_APMU_ALZO 30 115 + #define RESET_APMU_MC 31 116 + #define RESET_APMU_CPU0_POP 32 117 + #define RESET_APMU_CPU0_SW 33 118 + #define RESET_APMU_CPU1_POP 34 119 + #define RESET_APMU_CPU1_SW 35 120 + #define RESET_APMU_CPU2_POP 36 121 + #define RESET_APMU_CPU2_SW 37 122 + #define RESET_APMU_CPU3_POP 38 123 + #define RESET_APMU_CPU3_SW 39 124 + #define RESET_APMU_C0_MPSUB_SW 40 125 + #define RESET_APMU_CPU4_POP 41 126 + #define RESET_APMU_CPU4_SW 42 127 + #define RESET_APMU_CPU5_POP 43 128 + #define RESET_APMU_CPU5_SW 44 129 + #define RESET_APMU_CPU6_POP 45 130 + #define RESET_APMU_CPU6_SW 46 131 + #define RESET_APMU_CPU7_POP 47 132 + #define RESET_APMU_CPU7_SW 48 133 + #define RESET_APMU_C1_MPSUB_SW 49 134 + #define RESET_APMU_MPSUB_DBG 50 135 + #define RESET_APMU_UCIE 51 136 + #define RESET_APMU_RCPU 52 137 + #define RESET_APMU_DSI4LN2_ESCCLK 53 138 + #define RESET_APMU_DSI4LN2_LCD_SW 54 139 + #define RESET_APMU_DSI4LN2_LCD_MCLK 55 140 + #define RESET_APMU_DSI4LN2_LCD_DSCCLK 56 141 + #define RESET_APMU_DSI4LN2_DPU_ACLK 57 142 + #define RESET_APMU_DPU_ACLK 58 143 + #define RESET_APMU_UFS_ACLK 59 144 + #define RESET_APMU_EDP0 60 145 + #define RESET_APMU_EDP1 61 146 + #define RESET_APMU_PCIE_PORTA 62 147 + #define RESET_APMU_PCIE_PORTB 63 148 + #define RESET_APMU_PCIE_PORTC 64 149 + #define RESET_APMU_PCIE_PORTD 65 150 + #define RESET_APMU_PCIE_PORTE 66 151 + #define RESET_APMU_EMAC0 67 152 + #define RESET_APMU_EMAC1 68 153 + #define RESET_APMU_EMAC2 69 154 + #define RESET_APMU_ESPI_MCLK 70 155 + #define RESET_APMU_ESPI_SCLK 71 156 + 157 + /* DCIU resets*/ 158 + #define RESET_DCIU_HDMA 0 159 + #define RESET_DCIU_DMA350 1 160 + #define RESET_DCIU_DMA350_0 2 161 + #define RESET_DCIU_DMA350_1 3 162 + #define RESET_DCIU_AXIDMA0 4 163 + #define RESET_DCIU_AXIDMA1 5 164 + #define RESET_DCIU_AXIDMA2 6 165 + #define RESET_DCIU_AXIDMA3 7 166 + #define RESET_DCIU_AXIDMA4 8 167 + #define RESET_DCIU_AXIDMA5 9 168 + #define RESET_DCIU_AXIDMA6 10 169 + #define RESET_DCIU_AXIDMA7 11 170 + 171 + #endif /* _DT_BINDINGS_RESET_SPACEMIT_K3_H_ */

+21

include/soc/spacemit/ccu.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + 3 + #ifndef __SOC_SPACEMIT_CCU_H__ 4 + #define __SOC_SPACEMIT_CCU_H__ 5 + 6 + #include <linux/auxiliary_bus.h> 7 + #include <linux/regmap.h> 8 + 9 + /* Auxiliary device used to represent a CCU reset controller */ 10 + struct spacemit_ccu_adev { 11 + struct auxiliary_device adev; 12 + struct regmap *regmap; 13 + }; 14 + 15 + static inline struct spacemit_ccu_adev * 16 + to_spacemit_ccu_adev(struct auxiliary_device *adev) 17 + { 18 + return container_of(adev, struct spacemit_ccu_adev, adev); 19 + } 20 + 21 + #endif /* __SOC_SPACEMIT_CCU_H__ */

+1 -11

include/soc/spacemit/k1-syscon.h

··· 5 5 #ifndef __SOC_K1_SYSCON_H__ 6 6 #define __SOC_K1_SYSCON_H__ 7 7 8 - /* Auxiliary device used to represent a CCU reset controller */ 9 - struct spacemit_ccu_adev { 10 - struct auxiliary_device adev; 11 - struct regmap *regmap; 12 - }; 13 - 14 - static inline struct spacemit_ccu_adev * 15 - to_spacemit_ccu_adev(struct auxiliary_device *adev) 16 - { 17 - return container_of(adev, struct spacemit_ccu_adev, adev); 18 - } 8 + #include "ccu.h" 19 9 20 10 /* APBS register offset */ 21 11 #define APBS_PLL1_SWCR1 0x100

+273

include/soc/spacemit/k3-syscon.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + 3 + /* SpacemiT clock and reset driver definitions for the K3 SoC */ 4 + 5 + #ifndef __SOC_K3_SYSCON_H__ 6 + #define __SOC_K3_SYSCON_H__ 7 + 8 + #include "ccu.h" 9 + 10 + /* APBS register offset */ 11 + #define APBS_PLL1_SWCR1 0x100 12 + #define APBS_PLL1_SWCR2 0x104 13 + #define APBS_PLL1_SWCR3 0x108 14 + #define APBS_PLL2_SWCR1 0x118 15 + #define APBS_PLL2_SWCR2 0x11c 16 + #define APBS_PLL2_SWCR3 0x120 17 + #define APBS_PLL3_SWCR1 0x124 18 + #define APBS_PLL3_SWCR2 0x128 19 + #define APBS_PLL3_SWCR3 0x12c 20 + #define APBS_PLL4_SWCR1 0x130 21 + #define APBS_PLL4_SWCR2 0x134 22 + #define APBS_PLL4_SWCR3 0x138 23 + #define APBS_PLL5_SWCR1 0x13c 24 + #define APBS_PLL5_SWCR2 0x140 25 + #define APBS_PLL5_SWCR3 0x144 26 + #define APBS_PLL6_SWCR1 0x148 27 + #define APBS_PLL6_SWCR2 0x14c 28 + #define APBS_PLL6_SWCR3 0x150 29 + #define APBS_PLL7_SWCR1 0x158 30 + #define APBS_PLL7_SWCR2 0x15c 31 + #define APBS_PLL7_SWCR3 0x160 32 + #define APBS_PLL8_SWCR1 0x180 33 + #define APBS_PLL8_SWCR2 0x184 34 + #define APBS_PLL8_SWCR3 0x188 35 + 36 + /* MPMU register offset */ 37 + #define MPMU_FCCR 0x0008 38 + #define MPMU_POSR 0x0010 39 + #define POSR_PLL1_LOCK BIT(24) 40 + #define POSR_PLL2_LOCK BIT(25) 41 + #define POSR_PLL3_LOCK BIT(26) 42 + #define POSR_PLL4_LOCK BIT(27) 43 + #define POSR_PLL5_LOCK BIT(28) 44 + #define POSR_PLL6_LOCK BIT(29) 45 + #define POSR_PLL7_LOCK BIT(30) 46 + #define POSR_PLL8_LOCK BIT(31) 47 + #define MPMU_SUCCR 0x0014 48 + #define MPMU_ISCCR 0x0044 49 + #define MPMU_WDTPCR 0x0200 50 + #define MPMU_RIPCCR 0x0210 51 + #define MPMU_ACGR 0x1024 52 + #define MPMU_APBCSCR 0x1050 53 + #define MPMU_SUCCR_1 0x10b0 54 + 55 + #define MPMU_I2S0_SYSCLK 0x1100 56 + #define MPMU_I2S2_SYSCLK 0x1104 57 + #define MPMU_I2S3_SYSCLK 0x1108 58 + #define MPMU_I2S4_SYSCLK 0x110c 59 + #define MPMU_I2S5_SYSCLK 0x1110 60 + #define MPMU_I2S_SYSCLK_CTRL 0x1114 61 + 62 + /* APBC register offset */ 63 + #define APBC_UART0_CLK_RST 0x00 64 + #define APBC_UART2_CLK_RST 0x04 65 + #define APBC_GPIO_CLK_RST 0x08 66 + #define APBC_PWM0_CLK_RST 0x0c 67 + #define APBC_PWM1_CLK_RST 0x10 68 + #define APBC_PWM2_CLK_RST 0x14 69 + #define APBC_PWM3_CLK_RST 0x18 70 + #define APBC_TWSI8_CLK_RST 0x20 71 + #define APBC_UART3_CLK_RST 0x24 72 + #define APBC_RTC_CLK_RST 0x28 73 + #define APBC_TWSI0_CLK_RST 0x2c 74 + #define APBC_TWSI1_CLK_RST 0x30 75 + #define APBC_TIMERS0_CLK_RST 0x34 76 + #define APBC_TWSI2_CLK_RST 0x38 77 + #define APBC_AIB_CLK_RST 0x3c 78 + #define APBC_TWSI4_CLK_RST 0x40 79 + #define APBC_TIMERS1_CLK_RST 0x44 80 + #define APBC_ONEWIRE_CLK_RST 0x48 81 + #define APBC_TWSI5_CLK_RST 0x4c 82 + #define APBC_DRO_CLK_RST 0x58 83 + #define APBC_IR0_CLK_RST 0x5c 84 + #define APBC_IR1_CLK_RST 0x1c 85 + #define APBC_TWSI6_CLK_RST 0x60 86 + #define APBC_COUNTER_CLK_SEL 0x64 87 + #define APBC_TSEN_CLK_RST 0x6c 88 + #define APBC_UART4_CLK_RST 0x70 89 + #define APBC_UART5_CLK_RST 0x74 90 + #define APBC_UART6_CLK_RST 0x78 91 + #define APBC_SSP3_CLK_RST 0x7c 92 + #define APBC_SSPA0_CLK_RST 0x80 93 + #define APBC_SSPA1_CLK_RST 0x84 94 + #define APBC_SSPA2_CLK_RST 0x88 95 + #define APBC_SSPA3_CLK_RST 0x8c 96 + #define APBC_IPC_AP2AUD_CLK_RST 0x90 97 + #define APBC_UART7_CLK_RST 0x94 98 + #define APBC_UART8_CLK_RST 0x98 99 + #define APBC_UART9_CLK_RST 0x9c 100 + #define APBC_CAN0_CLK_RST 0xa0 101 + #define APBC_CAN1_CLK_RST 0xa4 102 + #define APBC_PWM4_CLK_RST 0xa8 103 + #define APBC_PWM5_CLK_RST 0xac 104 + #define APBC_PWM6_CLK_RST 0xb0 105 + #define APBC_PWM7_CLK_RST 0xb4 106 + #define APBC_PWM8_CLK_RST 0xb8 107 + #define APBC_PWM9_CLK_RST 0xbc 108 + #define APBC_PWM10_CLK_RST 0xc0 109 + #define APBC_PWM11_CLK_RST 0xc4 110 + #define APBC_PWM12_CLK_RST 0xc8 111 + #define APBC_PWM13_CLK_RST 0xcc 112 + #define APBC_PWM14_CLK_RST 0xd0 113 + #define APBC_PWM15_CLK_RST 0xd4 114 + #define APBC_PWM16_CLK_RST 0xd8 115 + #define APBC_PWM17_CLK_RST 0xdc 116 + #define APBC_PWM18_CLK_RST 0xe0 117 + #define APBC_PWM19_CLK_RST 0xe4 118 + #define APBC_TIMERS2_CLK_RST 0x11c 119 + #define APBC_TIMERS3_CLK_RST 0x120 120 + #define APBC_TIMERS4_CLK_RST 0x124 121 + #define APBC_TIMERS5_CLK_RST 0x128 122 + #define APBC_TIMERS6_CLK_RST 0x12c 123 + #define APBC_TIMERS7_CLK_RST 0x130 124 + 125 + #define APBC_CAN2_CLK_RST 0x148 126 + #define APBC_CAN3_CLK_RST 0x14c 127 + #define APBC_CAN4_CLK_RST 0x150 128 + #define APBC_UART10_CLK_RST 0x154 129 + #define APBC_SSP0_CLK_RST 0x158 130 + #define APBC_SSP1_CLK_RST 0x15c 131 + #define APBC_SSPA4_CLK_RST 0x160 132 + #define APBC_SSPA5_CLK_RST 0x164 133 + 134 + /* APMU register offset */ 135 + #define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 136 + #define APMU_ISP_CLK_RES_CTRL 0x038 137 + #define APMU_PMU_CLK_GATE_CTRL 0x040 138 + #define APMU_LCD_CLK_RES_CTRL1 0x044 139 + #define APMU_LCD_SPI_CLK_RES_CTRL 0x048 140 + #define APMU_LCD_CLK_RES_CTRL2 0x04c 141 + #define APMU_CCIC_CLK_RES_CTRL 0x050 142 + #define APMU_SDH0_CLK_RES_CTRL 0x054 143 + #define APMU_SDH1_CLK_RES_CTRL 0x058 144 + #define APMU_USB_CLK_RES_CTRL 0x05c 145 + #define APMU_QSPI_CLK_RES_CTRL 0x060 146 + #define APMU_DMA_CLK_RES_CTRL 0x064 147 + #define APMU_AES_CLK_RES_CTRL 0x068 148 + #define APMU_MCB_CLK_RES_CTRL 0x06c 149 + #define APMU_VPU_CLK_RES_CTRL 0x0a4 150 + #define APMU_DTC_CLK_RES_CTRL 0x0ac 151 + #define APMU_GPU_CLK_RES_CTRL 0x0cc 152 + #define APMU_SDH2_CLK_RES_CTRL 0x0e0 153 + #define APMU_PMUA_MC_CTRL 0x0e8 154 + #define APMU_PMU_CC2_AP 0x100 155 + #define APMU_PMUA_EM_CLK_RES_CTRL 0x104 156 + #define APMU_UCIE_CTRL 0x11c 157 + #define APMU_RCPU_CLK_RES_CTRL 0x14c 158 + #define APMU_TOP_DCLK_CTRL 0x158 159 + #define APMU_LCD_EDP_CTRL 0x23c 160 + #define APMU_UFS_CLK_RES_CTRL 0x268 161 + #define APMU_LCD_CLK_RES_CTRL3 0x26c 162 + #define APMU_LCD_CLK_RES_CTRL4 0x270 163 + #define APMU_LCD_CLK_RES_CTRL5 0x274 164 + #define APMU_CCI550_CLK_CTRL 0x300 165 + #define APMU_ACLK_CLK_CTRL 0x388 166 + #define APMU_CPU_C0_CLK_CTRL 0x38C 167 + #define APMU_CPU_C1_CLK_CTRL 0x390 168 + #define APMU_CPU_C2_CLK_CTRL 0x394 169 + #define APMU_CPU_C3_CLK_CTRL 0x208 170 + #define APMU_PCIE_CLK_RES_CTRL_A 0x1f0 171 + #define APMU_PCIE_CLK_RES_CTRL_B 0x1c8 172 + #define APMU_PCIE_CLK_RES_CTRL_C 0x1d0 173 + #define APMU_PCIE_CLK_RES_CTRL_D 0x1e0 174 + #define APMU_PCIE_CLK_RES_CTRL_E 0x1e8 175 + #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 176 + #define APMU_EMAC1_CLK_RES_CTRL 0x3ec 177 + #define APMU_EMAC2_CLK_RES_CTRL 0x248 178 + #define APMU_ESPI_CLK_RES_CTRL 0x240 179 + #define APMU_SNR_ISIM_VCLK_CTRL 0x3f8 180 + 181 + /* DCIU register offsets */ 182 + #define DCIU_DMASYS_CLK_EN 0x234 183 + #define DCIU_DMASYS_SDMA_CLK_EN 0x238 184 + #define DCIU_C2_TCM_PIPE_CLK 0x244 185 + #define DCIU_C3_TCM_PIPE_CLK 0x248 186 + 187 + #define DCIU_DMASYS_S0_RSTN 0x204 188 + #define DCIU_DMASYS_S1_RSTN 0x208 189 + #define DCIU_DMASYS_A0_RSTN 0x20C 190 + #define DCIU_DMASYS_A1_RSTN 0x210 191 + #define DCIU_DMASYS_A2_RSTN 0x214 192 + #define DCIU_DMASYS_A3_RSTN 0x218 193 + #define DCIU_DMASYS_A4_RSTN 0x21C 194 + #define DCIU_DMASYS_A5_RSTN 0x220 195 + #define DCIU_DMASYS_A6_RSTN 0x224 196 + #define DCIU_DMASYS_A7_RSTN 0x228 197 + #define DCIU_DMASYS_RSTN 0x22C 198 + #define DCIU_DMASYS_SDMA_RSTN 0x230 199 + 200 + /* RCPU SYSCTRL register offsets */ 201 + #define RCPU_CAN_CLK_RST 0x4c 202 + #define RCPU_CAN1_CLK_RST 0xF0 203 + #define RCPU_CAN2_CLK_RST 0xF4 204 + #define RCPU_CAN3_CLK_RST 0xF8 205 + #define RCPU_CAN4_CLK_RST 0xFC 206 + #define RCPU_IRC_CLK_RST 0x48 207 + #define RCPU_IRC1_CLK_RST 0xEC 208 + #define RCPU_GMAC_CLK_RST 0xE4 209 + #define RCPU_ESPI_CLK_RST 0xDC 210 + #define RCPU_AUDIO_I2S0_SYS_CLK_CTRL 0x70 211 + #define RCPU_AUDIO_I2S1_SYS_CLK_CTRL 0x44 212 + 213 + /* RCPU UARTCTRL register offsets */ 214 + #define RCPU1_UART0_CLK_RST 0x00 215 + #define RCPU1_UART1_CLK_RST 0x04 216 + #define RCPU1_UART2_CLK_RST 0x08 217 + #define RCPU1_UART3_CLK_RST 0x0c 218 + #define RCPU1_UART4_CLK_RST 0x10 219 + #define RCPU1_UART5_CLK_RST 0x14 220 + 221 + /* RCPU I2SCTRL register offsets */ 222 + #define RCPU2_AUDIO_I2S0_TX_RX_CLK_CTRL 0x60 223 + #define RCPU2_AUDIO_I2S1_TX_RX_CLK_CTRL 0x64 224 + #define RCPU2_AUDIO_I2S2_TX_RX_CLK_CTRL 0x68 225 + #define RCPU2_AUDIO_I2S3_TX_RX_CLK_CTRL 0x6C 226 + 227 + #define RCPU2_AUDIO_I2S2_SYS_CLK_CTRL 0x44 228 + #define RCPU2_AUDIO_I2S3_SYS_CLK_CTRL 0x54 229 + 230 + /* RCPU SPICTRL register offsets */ 231 + #define RCPU3_SSP0_CLK_RST 0x00 232 + #define RCPU3_SSP1_CLK_RST 0x04 233 + #define RCPU3_PWR_SSP_CLK_RST 0x08 234 + 235 + /* RCPU I2CCTRL register offsets */ 236 + #define RCPU4_I2C0_CLK_RST 0x00 237 + #define RCPU4_I2C1_CLK_RST 0x04 238 + #define RCPU4_PWR_I2C_CLK_RST 0x08 239 + 240 + /* RPMU register offsets */ 241 + #define RCPU5_AON_PER_CLK_RST_CTRL 0x2C 242 + #define RCPU5_TIMER1_CLK_RST 0x4C 243 + #define RCPU5_TIMER2_CLK_RST 0x70 244 + #define RCPU5_TIMER3_CLK_RST 0x78 245 + #define RCPU5_TIMER4_CLK_RST 0x7C 246 + #define RCPU5_GPIO_AND_EDGE_CLK_RST 0x74 247 + #define RCPU5_RCPU_BUS_CLK_CTRL 0xC0 248 + #define RCPU5_RT24_CORE0_CLK_CTRL 0xC4 249 + #define RCPU5_RT24_CORE1_CLK_CTRL 0xC8 250 + #define RCPU5_RT24_CORE0_SW_RESET 0xCC 251 + #define RCPU5_RT24_CORE1_SW_RESET 0xD0 252 + 253 + /* RCPU PWMCTRL register offsets */ 254 + #define RCPU6_PWM0_CLK_RST 0x00 255 + #define RCPU6_PWM1_CLK_RST 0x04 256 + #define RCPU6_PWM2_CLK_RST 0x08 257 + #define RCPU6_PWM3_CLK_RST 0x0c 258 + #define RCPU6_PWM4_CLK_RST 0x10 259 + #define RCPU6_PWM5_CLK_RST 0x14 260 + #define RCPU6_PWM6_CLK_RST 0x18 261 + #define RCPU6_PWM7_CLK_RST 0x1c 262 + #define RCPU6_PWM8_CLK_RST 0x20 263 + #define RCPU6_PWM9_CLK_RST 0x24 264 + 265 + /* APBC2 SEC register offsets */ 266 + #define APBC2_UART1_CLK_RST 0x00 267 + #define APBC2_SSP2_CLK_RST 0x04 268 + #define APBC2_TWSI3_CLK_RST 0x08 269 + #define APBC2_RTC_CLK_RST 0x0c 270 + #define APBC2_TIMERS_CLK_RST 0x10 271 + #define APBC2_GPIO_CLK_RST 0x1c 272 + 273 + #endif /* __SOC_K3_SYSCON_H__ */

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