Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
spi: cadence-qspi: Add support for the Renesas RZ/N1 controller
Renesas RZ/N1 QSPI controllers embed a modified version of the Cadence
IP with the following settings:
- a limited bus clock range
- no DTR support
- no DMA
- no useful interrupt flag
- only direct accesses (no INDAC mode)
- write protection
The controller has been tested by running the SPI NOR check list with a
custom RZ/N1D400 based board mounted with a Spansion s25fl128s1 quad
SPI.
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20260205-schneider-6-19-rc1-qspi-v5-3-843632b3c674@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Miquel Raynal (Schneider Electric)
and committed by
Mark Brown
a40236fe
324ecc77
+42
-14
+42
-14
drivers/spi/spi-cadence-quadspi.c
+42
-14
drivers/spi/spi-cadence-quadspi.c
···
110
110
bool apb_ahb_hazard;
111
111
112
112
bool is_jh7110; /* Flag for StarFive JH7110 SoC */
113
+
bool is_rzn1; /* Flag for Renesas RZ/N1 SoC */
113
114
bool disable_stig_mode;
114
115
refcount_t refcount;
115
116
refcount_t inflight_ops;
···
1338
1337
* mode. So, we can not use direct mode when in DTR mode for writing
1339
1338
* data.
1340
1339
*/
1341
-
if (!op->cmd.dtr && cqspi->use_direct_mode &&
1342
-
cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) {
1340
+
if ((!op->cmd.dtr && cqspi->use_direct_mode &&
1341
+
cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) ||
1342
+
(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) {
1343
1343
memcpy_toio(cqspi->ahb_base + to, buf, len);
1344
1344
return cqspi_wait_idle(cqspi);
1345
1345
}
···
1514
1512
static bool cqspi_supports_mem_op(struct spi_mem *mem,
1515
1513
const struct spi_mem_op *op)
1516
1514
{
1515
+
struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
1517
1516
bool all_true, all_false;
1518
1517
1519
1518
/*
···
1540
1537
1541
1538
/* A single opcode is supported, it will be repeated */
1542
1539
if ((op->cmd.opcode >> 8) != (op->cmd.opcode & 0xFF))
1540
+
return false;
1541
+
1542
+
if (cqspi->is_rzn1)
1543
1543
return false;
1544
1544
} else if (!all_false) {
1545
1545
/* Mixed DTR modes are not supported. */
···
1597
1591
1598
1592
cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1599
1593
1600
-
if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1601
-
/* Zero signals FIFO depth should be runtime detected. */
1602
-
cqspi->fifo_depth = 0;
1603
-
}
1594
+
if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) {
1595
+
if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1596
+
/* Zero signals FIFO depth should be runtime detected. */
1597
+
cqspi->fifo_depth = 0;
1598
+
}
1604
1599
1605
-
if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width))
1606
-
cqspi->fifo_width = 4;
1600
+
if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width))
1601
+
cqspi->fifo_width = 4;
1607
1602
1608
-
if (of_property_read_u32(np, "cdns,trigger-address",
1609
-
&cqspi->trigger_address)) {
1610
-
dev_err(dev, "couldn't determine trigger-address\n");
1611
-
return -ENXIO;
1603
+
if (of_property_read_u32(np, "cdns,trigger-address",
1604
+
&cqspi->trigger_address)) {
1605
+
dev_err(dev, "couldn't determine trigger-address\n");
1606
+
return -ENXIO;
1607
+
}
1612
1608
}
1613
1609
1614
1610
if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
···
1673
1665
{
1674
1666
struct device *dev = &cqspi->pdev->dev;
1675
1667
u32 reg, fifo_depth;
1668
+
1669
+
if (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)
1670
+
return;
1676
1671
1677
1672
/*
1678
1673
* Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N
···
1801
1790
cqspi = spi_controller_get_devdata(host);
1802
1791
if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi"))
1803
1792
cqspi->is_jh7110 = true;
1793
+
if (of_device_is_compatible(pdev->dev.of_node, "renesas,rzn1-qspi"))
1794
+
cqspi->is_rzn1 = true;
1804
1795
1805
1796
cqspi->pdev = pdev;
1806
1797
cqspi->host = host;
···
1900
1887
reset_control_deassert(rstc_ocp);
1901
1888
1902
1889
cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clks[CLK_QSPI_REF].clk);
1903
-
host->max_speed_hz = cqspi->master_ref_clk_hz;
1890
+
if (!cqspi->is_rzn1) {
1891
+
host->max_speed_hz = cqspi->master_ref_clk_hz;
1892
+
} else {
1893
+
host->max_speed_hz = cqspi->master_ref_clk_hz / 2;
1894
+
host->min_speed_hz = cqspi->master_ref_clk_hz / 32;
1895
+
}
1904
1896
1905
1897
/* write completion is supported by default */
1906
1898
cqspi->wr_completion = true;
···
1970
1952
if (ddata && (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET))
1971
1953
cqspi_device_reset(cqspi);
1972
1954
1973
-
if (cqspi->use_direct_mode) {
1955
+
if (cqspi->use_direct_mode && !cqspi->is_rzn1) {
1974
1956
ret = cqspi_request_mmap_dma(cqspi);
1975
1957
if (ret == -EPROBE_DEFER) {
1976
1958
dev_err_probe(&pdev->dev, ret, "Failed to request mmap DMA\n");
···
2150
2132
CQSPI_RD_NO_IRQ,
2151
2133
};
2152
2134
2135
+
static const struct cqspi_driver_platdata renesas_rzn1_qspi = {
2136
+
.hwcaps_mask = CQSPI_SUPPORTS_QUAD,
2137
+
.quirks = CQSPI_NO_SUPPORT_WR_COMPLETION | CQSPI_RD_NO_IRQ |
2138
+
CQSPI_HAS_WR_PROTECT | CQSPI_NO_INDIRECT_MODE,
2139
+
};
2140
+
2153
2141
static const struct of_device_id cqspi_dt_ids[] = {
2154
2142
{
2155
2143
.compatible = "cdns,qspi-nor",
···
2196
2172
{
2197
2173
.compatible = "amd,versal2-ospi",
2198
2174
.data = &versal2_ospi,
2175
+
},
2176
+
{
2177
+
.compatible = "renesas,rzn1-qspi",
2178
+
.data = &renesas_rzn1_qspi,
2199
2179
},
2200
2180
{ /* end of table */ }
2201
2181
};