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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
crypto: qat - relocate and rename bank state structure definition
The `bank_state` structure represents the state of a bank of rings.
As part of recent refactoring, the functions that interact with this
structure have been moved to a new unit, adf_bank_state.c.
To align with this reorganization, rename `struct bank_state` to
`struct adf_bank_state` and move its definition to adf_bank_state.h.
Also relocate the associated `struct ring_config` to the same header
to consolidate related definitions.
Update all references to use the new structure name.
This does not introduce any functional change.
Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Suman Kumar Chakraborty
and committed by
Herbert Xu
a47dc5d1
e9eec291
+47
-45
+3
-35
drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
+3
-35
drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
···
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u32 mailbox_offset;
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};
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-
struct ring_config {
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u64 base;
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-
u32 config;
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-
u32 head;
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-
u32 tail;
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u32 reserved0;
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};
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-
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struct bank_state {
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u32 ringstat0;
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u32 ringstat1;
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-
u32 ringuostat;
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u32 ringestat;
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u32 ringnestat;
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u32 ringnfstat;
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u32 ringfstat;
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u32 ringcstat0;
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u32 ringcstat1;
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u32 ringcstat2;
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u32 ringcstat3;
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u32 iaintflagen;
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u32 iaintflagreg;
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u32 iaintflagsrcsel0;
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u32 iaintflagsrcsel1;
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u32 iaintcolen;
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u32 iaintcolctl;
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u32 iaintflagandcolen;
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u32 ringexpstat;
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u32 ringexpintenable;
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u32 ringsrvarben;
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u32 reserved0;
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struct ring_config rings[ADF_ETR_MAX_RINGS_PER_BANK];
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};
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+
struct adf_bank_state;
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struct adf_hw_csr_ops {
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u64 (*build_csr_ring_base_addr)(dma_addr_t addr, u32 size);
···
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void (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev);
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int (*ring_pair_reset)(struct adf_accel_dev *accel_dev, u32 bank_nr);
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int (*bank_state_save)(struct adf_accel_dev *accel_dev, u32 bank_number,
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-
struct bank_state *state);
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struct adf_bank_state *state);
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int (*bank_state_restore)(struct adf_accel_dev *accel_dev,
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u32 bank_number, struct bank_state *state);
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+
u32 bank_number, struct adf_bank_state *state);
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void (*reset_device)(struct adf_accel_dev *accel_dev);
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void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);
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const char *(*uof_get_name)(struct adf_accel_dev *accel_dev, u32 obj_num);
+4
-4
drivers/crypto/intel/qat/qat_common/adf_bank_state.c
+4
-4
drivers/crypto/intel/qat/qat_common/adf_bank_state.c
···
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}
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static void bank_state_save(struct adf_hw_csr_ops *ops, void __iomem *base,
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u32 bank, struct bank_state *state, u32 num_rings)
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u32 bank, struct adf_bank_state *state, u32 num_rings)
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{
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u32 i;
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···
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}
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static int bank_state_restore(struct adf_hw_csr_ops *ops, void __iomem *base,
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u32 bank, struct bank_state *state, u32 num_rings,
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+
u32 bank, struct adf_bank_state *state, u32 num_rings,
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int tx_rx_gap)
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{
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u32 val, tmp_val, i;
···
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* Returns 0 on success, error code otherwise
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*/
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int adf_bank_state_save(struct adf_accel_dev *accel_dev, u32 bank_number,
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struct bank_state *state)
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+
struct adf_bank_state *state)
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{
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struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);
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struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
···
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* Returns 0 on success, error code otherwise
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*/
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int adf_bank_state_restore(struct adf_accel_dev *accel_dev, u32 bank_number,
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struct bank_state *state)
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struct adf_bank_state *state)
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{
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struct adf_hw_device_data *hw_data = GET_HW_DATA(accel_dev);
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struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(accel_dev);
+36
-3
drivers/crypto/intel/qat/qat_common/adf_bank_state.h
+36
-3
drivers/crypto/intel/qat/qat_common/adf_bank_state.h
···
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#include <linux/types.h>
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struct adf_accel_dev;
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-
struct bank_state;
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+
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+
struct ring_config {
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u64 base;
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u32 config;
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u32 head;
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u32 tail;
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+
u32 reserved0;
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};
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+
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struct adf_bank_state {
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u32 ringstat0;
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u32 ringstat1;
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u32 ringuostat;
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u32 ringestat;
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u32 ringnestat;
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u32 ringnfstat;
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u32 ringfstat;
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u32 ringcstat0;
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u32 ringcstat1;
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u32 ringcstat2;
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u32 ringcstat3;
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u32 iaintflagen;
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u32 iaintflagreg;
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u32 iaintflagsrcsel0;
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u32 iaintflagsrcsel1;
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+
u32 iaintcolen;
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+
u32 iaintcolctl;
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+
u32 iaintflagandcolen;
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u32 ringexpstat;
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u32 ringexpintenable;
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u32 ringsrvarben;
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u32 reserved0;
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struct ring_config rings[ADF_ETR_MAX_RINGS_PER_BANK];
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};
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int adf_bank_state_restore(struct adf_accel_dev *accel_dev, u32 bank_number,
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-
struct bank_state *state);
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struct adf_bank_state *state);
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int adf_bank_state_save(struct adf_accel_dev *accel_dev, u32 bank_number,
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-
struct bank_state *state);
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struct adf_bank_state *state);
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#endif
+4
-3
drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c
+4
-3
drivers/crypto/intel/qat/qat_common/adf_gen4_vf_mig.c
···
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#include <asm/errno.h>
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#include "adf_accel_devices.h"
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#include "adf_bank_state.h"
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#include "adf_common_drv.h"
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#include "adf_gen4_hw_data.h"
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#include "adf_gen4_pfvf.h"
···
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pf_bank_nr = vf_bank_info->bank_nr + vf_bank_info->vf_nr * hw_data->num_banks_per_vf;
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ret = hw_data->bank_state_restore(accel_dev, pf_bank_nr,
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(struct bank_state *)state);
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(struct adf_bank_state *)state);
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if (ret) {
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dev_err(&GET_DEV(accel_dev),
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"Failed to load regs for vf%d bank%d\n",
···
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pf_bank_nr += vf_bank_info->vf_nr * hw_data->num_banks_per_vf;
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ret = hw_data->bank_state_save(accel_dev, pf_bank_nr,
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(struct bank_state *)state);
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(struct adf_bank_state *)state);
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if (ret) {
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dev_err(&GET_DEV(accel_dev),
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"Failed to save regs for vf%d bank%d\n",
···
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return ret;
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}
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-
return sizeof(struct bank_state);
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+
return sizeof(struct adf_bank_state);
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}
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static int adf_gen4_vfmig_save_etr_bank(struct adf_accel_dev *accel_dev,