Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: octeontx2 - hardware configuration for inline IPsec
On OcteonTX2/OctoenTX3 variants of silicon, Admin function (AF)
handles resource allocation and configuration for PFs and their VFs.
PFs request the AF directly, via mailboxes.
Unlike PFs, VFs cannot send a mailbox request directly. A VF sends
mailbox messages to its parent PF, with which it shares a
mailbox region. The PF then forwards these messages to the AF.
This patch adds code to configure inline-IPsec HW resources for
CPT VFs as CPT VFs cannot send a mailbox request directly to AF.
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Srujana Challa
and committed by
Herbert Xu
a4855a8c
5c553114
+261
-38
+15
drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
+15
drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
···
40
40
};
41
41
42
42
/* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */
43
+
#define MBOX_MSG_RX_INLINE_IPSEC_LF_CFG 0xBFE
43
44
#define MBOX_MSG_GET_ENG_GRP_NUM 0xBFF
44
45
#define MBOX_MSG_GET_CAPS 0xBFD
45
46
#define MBOX_MSG_GET_KVF_LIMITS 0xBFC
47
+
48
+
/*
49
+
* Message request to config cpt lf for inline inbound ipsec.
50
+
* This message is only used between CPT PF <-> CPT VF
51
+
*/
52
+
struct otx2_cpt_rx_inline_lf_cfg {
53
+
struct mbox_msghdr hdr;
54
+
u16 sso_pf_func;
55
+
u16 param1;
56
+
u16 param2;
57
+
u16 opcode;
58
+
u32 credit;
59
+
u32 reserved;
60
+
};
46
61
47
62
/*
48
63
* Message request and response to get engine group number
+3
drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c
+3
drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c
···
141
141
req->hdr.sig = OTX2_MBOX_REQ_SIG;
142
142
req->hdr.pcifunc = 0;
143
143
req->cptlfs = lfs->lfs_num;
144
+
req->cpt_blkaddr = lfs->blkaddr;
145
+
req->modify = 1;
144
146
ret = otx2_cpt_send_mbox_msg(mbox, lfs->pdev);
145
147
if (ret)
146
148
return ret;
···
170
168
req->hdr.id = MBOX_MSG_DETACH_RESOURCES;
171
169
req->hdr.sig = OTX2_MBOX_REQ_SIG;
172
170
req->hdr.pcifunc = 0;
171
+
req->cptlfs = 1;
173
172
ret = otx2_cpt_send_mbox_msg(mbox, lfs->pdev);
174
173
if (ret)
175
174
return ret;
+17
-17
drivers/crypto/marvell/octeontx2/otx2_cptlf.c
+17
-17
drivers/crypto/marvell/octeontx2/otx2_cptlf.c
···
13
13
{
14
14
union otx2_cptx_lf_done_wait done_wait;
15
15
16
-
done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
17
-
OTX2_CPT_LF_DONE_WAIT);
16
+
done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,
17
+
lf->slot, OTX2_CPT_LF_DONE_WAIT);
18
18
done_wait.s.time_wait = time_wait;
19
-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
19
+
otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
20
20
OTX2_CPT_LF_DONE_WAIT, done_wait.u);
21
21
}
22
22
···
24
24
{
25
25
union otx2_cptx_lf_done_wait done_wait;
26
26
27
-
done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
28
-
OTX2_CPT_LF_DONE_WAIT);
27
+
done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,
28
+
lf->slot, OTX2_CPT_LF_DONE_WAIT);
29
29
done_wait.s.num_wait = num_wait;
30
-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
30
+
otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
31
31
OTX2_CPT_LF_DONE_WAIT, done_wait.u);
32
32
}
33
33
···
147
147
irq_misc.s.nwrp = 0x1;
148
148
149
149
for (slot = 0; slot < lfs->lfs_num; slot++)
150
-
otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot, reg,
150
+
otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot, reg,
151
151
irq_misc.u);
152
152
}
153
153
···
157
157
158
158
/* Enable done interrupts */
159
159
for (slot = 0; slot < lfs->lfs_num; slot++)
160
-
otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot,
160
+
otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,
161
161
OTX2_CPT_LF_DONE_INT_ENA_W1S, 0x1);
162
162
/* Enable Misc interrupts */
163
163
cptlf_set_misc_intrs(lfs, true);
···
168
168
int slot;
169
169
170
170
for (slot = 0; slot < lfs->lfs_num; slot++)
171
-
otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot,
171
+
otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,
172
172
OTX2_CPT_LF_DONE_INT_ENA_W1C, 0x1);
173
173
cptlf_set_misc_intrs(lfs, false);
174
174
}
···
177
177
{
178
178
union otx2_cptx_lf_done irq_cnt;
179
179
180
-
irq_cnt.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
180
+
irq_cnt.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
181
181
OTX2_CPT_LF_DONE);
182
182
return irq_cnt.s.done;
183
183
}
···
189
189
struct device *dev;
190
190
191
191
dev = &lf->lfs->pdev->dev;
192
-
irq_misc.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
193
-
OTX2_CPT_LF_MISC_INT);
192
+
irq_misc.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,
193
+
lf->slot, OTX2_CPT_LF_MISC_INT);
194
194
irq_misc_ack.u = 0x0;
195
195
196
196
if (irq_misc.s.fault) {
···
222
222
}
223
223
224
224
/* Acknowledge interrupts */
225
-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
225
+
otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
226
226
OTX2_CPT_LF_MISC_INT, irq_misc_ack.u);
227
227
228
228
return IRQ_HANDLED;
···
237
237
/* Read the number of completed requests */
238
238
irq_cnt = cptlf_read_done_cnt(lf);
239
239
if (irq_cnt) {
240
-
done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0,
240
+
done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, lf->lfs->blkaddr,
241
241
lf->slot, OTX2_CPT_LF_DONE_WAIT);
242
242
/* Acknowledge the number of completed requests */
243
-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
243
+
otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
244
244
OTX2_CPT_LF_DONE_ACK, irq_cnt);
245
245
246
-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
246
+
otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
247
247
OTX2_CPT_LF_DONE_WAIT, done_wait.u);
248
248
if (unlikely(!lf->wqe)) {
249
249
dev_err(&lf->lfs->pdev->dev, "No work for LF %d\n",
···
393
393
OTX2_CPT_LMT_LF_LMTLINEX(0));
394
394
395
395
lfs->lf[slot].ioreg = lfs->reg_base +
396
-
OTX2_CPT_RVU_FUNC_ADDR_S(BLKADDR_CPT0, slot,
396
+
OTX2_CPT_RVU_FUNC_ADDR_S(lfs->blkaddr, slot,
397
397
OTX2_CPT_LF_NQX(0));
398
398
}
399
399
/* Send request to attach LFs */
+24
-9
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
+24
-9
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
···
180
180
181
181
for (slot = 0; slot < lfs->lfs_num; slot++) {
182
182
lf_q_base.u = lfs->lf[slot].iqueue.dma_addr;
183
-
otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot,
183
+
otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,
184
184
OTX2_CPT_LF_Q_BASE, lf_q_base.u);
185
185
}
186
186
}
···
191
191
192
192
lf_q_size.s.size_div40 = OTX2_CPT_SIZE_DIV40 +
193
193
OTX2_CPT_EXTRA_SIZE_DIV40;
194
-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
194
+
otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,
195
195
OTX2_CPT_LF_Q_SIZE, lf_q_size.u);
196
196
}
197
197
···
207
207
{
208
208
union otx2_cptx_lf_ctl lf_ctl = { .u = 0x0 };
209
209
union otx2_cptx_lf_inprog lf_inprog;
210
+
u8 blkaddr = lf->lfs->blkaddr;
210
211
int timeout = 20;
211
212
212
213
/* Disable instructions enqueuing */
213
-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
214
+
otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
214
215
OTX2_CPT_LF_CTL, lf_ctl.u);
215
216
216
217
/* Wait for instruction queue to become empty */
217
218
do {
218
-
lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0,
219
+
lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr,
219
220
lf->slot, OTX2_CPT_LF_INPROG);
220
221
if (!lf_inprog.s.inflight)
221
222
break;
···
235
234
* the queue should be empty at this point
236
235
*/
237
236
lf_inprog.s.eena = 0x0;
238
-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
237
+
otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
239
238
OTX2_CPT_LF_INPROG, lf_inprog.u);
240
239
}
241
240
···
250
249
static inline void otx2_cptlf_set_iqueue_enq(struct otx2_cptlf_info *lf,
251
250
bool enable)
252
251
{
252
+
u8 blkaddr = lf->lfs->blkaddr;
253
253
union otx2_cptx_lf_ctl lf_ctl;
254
254
255
-
lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
255
+
lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,
256
256
OTX2_CPT_LF_CTL);
257
257
258
258
/* Set iqueue's enqueuing */
259
259
lf_ctl.s.ena = enable ? 0x1 : 0x0;
260
-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
260
+
otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
261
261
OTX2_CPT_LF_CTL, lf_ctl.u);
262
262
}
263
263
···
271
269
bool enable)
272
270
{
273
271
union otx2_cptx_lf_inprog lf_inprog;
272
+
u8 blkaddr = lf->lfs->blkaddr;
274
273
275
-
lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
274
+
lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,
276
275
OTX2_CPT_LF_INPROG);
277
276
278
277
/* Set iqueue's execution */
279
278
lf_inprog.s.eena = enable ? 0x1 : 0x0;
280
-
otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
279
+
otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
281
280
OTX2_CPT_LF_INPROG, lf_inprog.u);
282
281
}
283
282
···
365
362
static inline bool otx2_cptlf_started(struct otx2_cptlfs_info *lfs)
366
363
{
367
364
return atomic_read(&lfs->state) == OTX2_CPTLF_STARTED;
365
+
}
366
+
367
+
static inline void otx2_cptlf_set_dev_info(struct otx2_cptlfs_info *lfs,
368
+
struct pci_dev *pdev,
369
+
void __iomem *reg_base,
370
+
struct otx2_mbox *mbox,
371
+
int blkaddr)
372
+
{
373
+
lfs->pdev = pdev;
374
+
lfs->reg_base = reg_base;
375
+
lfs->mbox = mbox;
376
+
lfs->blkaddr = blkaddr;
368
377
}
369
378
370
379
int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri,
+3
drivers/crypto/marvell/octeontx2/otx2_cptpf.h
+3
drivers/crypto/marvell/octeontx2/otx2_cptpf.h
···
31
31
struct otx2_cptvf_info vf[OTX2_CPT_MAX_VFS_NUM];
32
32
struct otx2_cpt_eng_grps eng_grps;/* Engine groups information */
33
33
struct otx2_cptlfs_info lfs; /* CPT LFs attached to this PF */
34
+
struct otx2_cptlfs_info cpt1_lfs; /* CPT1 LFs attached to this PF */
34
35
/* HW capabilities for each engine type */
35
36
union otx2_cpt_eng_caps eng_caps[OTX2_CPT_MAX_ENG_TYPES];
36
37
bool is_eng_caps_discovered;
···
56
55
u8 pf_id; /* RVU PF number */
57
56
u8 max_vfs; /* Maximum number of VFs supported by CPT */
58
57
u8 enabled_vfs; /* Number of enabled VFs */
58
+
u8 sso_pf_func_ovrd; /* SSO PF_FUNC override bit */
59
59
u8 kvf_limits; /* Kernel crypto limits */
60
60
bool has_cpt1;
61
+
u8 rsrc_req_blkaddr;
61
62
62
63
/* Devlink */
63
64
struct devlink *dl;
+31
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
+31
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
···
13
13
#define OTX2_CPT_DRV_NAME "rvu_cptpf"
14
14
#define OTX2_CPT_DRV_STRING "Marvell RVU CPT Physical Function Driver"
15
15
16
+
#define CPT_UC_RID_CN9K_B0 1
17
+
16
18
static void cptpf_enable_vfpf_mbox_intr(struct otx2_cptpf_dev *cptpf,
17
19
int num_vfs)
18
20
{
···
500
498
otx2_mbox_destroy(&cptpf->afpf_mbox_up);
501
499
}
502
500
501
+
static ssize_t sso_pf_func_ovrd_show(struct device *dev,
502
+
struct device_attribute *attr, char *buf)
503
+
{
504
+
struct otx2_cptpf_dev *cptpf = dev_get_drvdata(dev);
505
+
506
+
return sprintf(buf, "%d\n", cptpf->sso_pf_func_ovrd);
507
+
}
508
+
509
+
static ssize_t sso_pf_func_ovrd_store(struct device *dev,
510
+
struct device_attribute *attr,
511
+
const char *buf, size_t count)
512
+
{
513
+
struct otx2_cptpf_dev *cptpf = dev_get_drvdata(dev);
514
+
u8 sso_pf_func_ovrd;
515
+
516
+
if (!(cptpf->pdev->revision == CPT_UC_RID_CN9K_B0))
517
+
return count;
518
+
519
+
if (kstrtou8(buf, 0, &sso_pf_func_ovrd))
520
+
return -EINVAL;
521
+
522
+
cptpf->sso_pf_func_ovrd = sso_pf_func_ovrd;
523
+
524
+
return count;
525
+
}
526
+
503
527
static ssize_t kvf_limits_show(struct device *dev,
504
528
struct device_attribute *attr, char *buf)
505
529
{
···
556
528
}
557
529
558
530
static DEVICE_ATTR_RW(kvf_limits);
531
+
static DEVICE_ATTR_RW(sso_pf_func_ovrd);
532
+
559
533
static struct attribute *cptpf_attrs[] = {
560
534
&dev_attr_kvf_limits.attr,
535
+
&dev_attr_sso_pf_func_ovrd.attr,
561
536
NULL
562
537
};
563
538
+159
-2
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
+159
-2
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
···
5
5
#include "otx2_cptpf.h"
6
6
#include "rvu_reg.h"
7
7
8
+
/* Fastpath ipsec opcode with inplace processing */
9
+
#define CPT_INLINE_RX_OPCODE (0x26 | (1 << 6))
10
+
#define CN10K_CPT_INLINE_RX_OPCODE (0x29 | (1 << 6))
11
+
12
+
#define cpt_inline_rx_opcode(pdev) \
13
+
({ \
14
+
u8 opcode; \
15
+
if (is_dev_otx2(pdev)) \
16
+
opcode = CPT_INLINE_RX_OPCODE; \
17
+
else \
18
+
opcode = CN10K_CPT_INLINE_RX_OPCODE; \
19
+
(opcode); \
20
+
})
21
+
8
22
/*
9
23
* CPT PF driver version, It will be incremented by 1 for every feature
10
24
* addition in CPT mailbox messages.
···
126
112
return 0;
127
113
}
128
114
115
+
static int send_inline_ipsec_inbound_msg(struct otx2_cptpf_dev *cptpf,
116
+
int sso_pf_func, u8 slot)
117
+
{
118
+
struct cpt_inline_ipsec_cfg_msg *req;
119
+
struct pci_dev *pdev = cptpf->pdev;
120
+
121
+
req = (struct cpt_inline_ipsec_cfg_msg *)
122
+
otx2_mbox_alloc_msg_rsp(&cptpf->afpf_mbox, 0,
123
+
sizeof(*req), sizeof(struct msg_rsp));
124
+
if (req == NULL) {
125
+
dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
126
+
return -EFAULT;
127
+
}
128
+
memset(req, 0, sizeof(*req));
129
+
req->hdr.id = MBOX_MSG_CPT_INLINE_IPSEC_CFG;
130
+
req->hdr.sig = OTX2_MBOX_REQ_SIG;
131
+
req->hdr.pcifunc = OTX2_CPT_RVU_PFFUNC(cptpf->pf_id, 0);
132
+
req->dir = CPT_INLINE_INBOUND;
133
+
req->slot = slot;
134
+
req->sso_pf_func_ovrd = cptpf->sso_pf_func_ovrd;
135
+
req->sso_pf_func = sso_pf_func;
136
+
req->enable = 1;
137
+
138
+
return otx2_cpt_send_mbox_msg(&cptpf->afpf_mbox, pdev);
139
+
}
140
+
141
+
static int rx_inline_ipsec_lf_cfg(struct otx2_cptpf_dev *cptpf, u8 egrp,
142
+
struct otx2_cpt_rx_inline_lf_cfg *req)
143
+
{
144
+
struct nix_inline_ipsec_cfg *nix_req;
145
+
struct pci_dev *pdev = cptpf->pdev;
146
+
int ret;
147
+
148
+
nix_req = (struct nix_inline_ipsec_cfg *)
149
+
otx2_mbox_alloc_msg_rsp(&cptpf->afpf_mbox, 0,
150
+
sizeof(*nix_req),
151
+
sizeof(struct msg_rsp));
152
+
if (nix_req == NULL) {
153
+
dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
154
+
return -EFAULT;
155
+
}
156
+
memset(nix_req, 0, sizeof(*nix_req));
157
+
nix_req->hdr.id = MBOX_MSG_NIX_INLINE_IPSEC_CFG;
158
+
nix_req->hdr.sig = OTX2_MBOX_REQ_SIG;
159
+
nix_req->enable = 1;
160
+
if (!req->credit || req->credit > OTX2_CPT_INST_QLEN_MSGS)
161
+
nix_req->cpt_credit = OTX2_CPT_INST_QLEN_MSGS - 1;
162
+
else
163
+
nix_req->cpt_credit = req->credit - 1;
164
+
nix_req->gen_cfg.egrp = egrp;
165
+
if (req->opcode)
166
+
nix_req->gen_cfg.opcode = req->opcode;
167
+
else
168
+
nix_req->gen_cfg.opcode = cpt_inline_rx_opcode(pdev);
169
+
nix_req->gen_cfg.param1 = req->param1;
170
+
nix_req->gen_cfg.param2 = req->param2;
171
+
nix_req->inst_qsel.cpt_pf_func = OTX2_CPT_RVU_PFFUNC(cptpf->pf_id, 0);
172
+
nix_req->inst_qsel.cpt_slot = 0;
173
+
ret = otx2_cpt_send_mbox_msg(&cptpf->afpf_mbox, pdev);
174
+
if (ret)
175
+
return ret;
176
+
177
+
if (cptpf->has_cpt1) {
178
+
ret = send_inline_ipsec_inbound_msg(cptpf, req->sso_pf_func, 1);
179
+
if (ret)
180
+
return ret;
181
+
}
182
+
183
+
return send_inline_ipsec_inbound_msg(cptpf, req->sso_pf_func, 0);
184
+
}
185
+
186
+
static int handle_msg_rx_inline_ipsec_lf_cfg(struct otx2_cptpf_dev *cptpf,
187
+
struct mbox_msghdr *req)
188
+
{
189
+
struct otx2_cpt_rx_inline_lf_cfg *cfg_req;
190
+
u8 egrp;
191
+
int ret;
192
+
193
+
cfg_req = (struct otx2_cpt_rx_inline_lf_cfg *)req;
194
+
if (cptpf->lfs.lfs_num) {
195
+
dev_err(&cptpf->pdev->dev,
196
+
"LF is already configured for RX inline ipsec.\n");
197
+
return -EEXIST;
198
+
}
199
+
/*
200
+
* Allow LFs to execute requests destined to only grp IE_TYPES and
201
+
* set queue priority of each LF to high
202
+
*/
203
+
egrp = otx2_cpt_get_eng_grp(&cptpf->eng_grps, OTX2_CPT_IE_TYPES);
204
+
if (egrp == OTX2_CPT_INVALID_CRYPTO_ENG_GRP) {
205
+
dev_err(&cptpf->pdev->dev,
206
+
"Engine group for inline ipsec is not available\n");
207
+
return -ENOENT;
208
+
}
209
+
210
+
otx2_cptlf_set_dev_info(&cptpf->lfs, cptpf->pdev, cptpf->reg_base,
211
+
&cptpf->afpf_mbox, BLKADDR_CPT0);
212
+
ret = otx2_cptlf_init(&cptpf->lfs, 1 << egrp, OTX2_CPT_QUEUE_HI_PRIO,
213
+
1);
214
+
if (ret) {
215
+
dev_err(&cptpf->pdev->dev,
216
+
"LF configuration failed for RX inline ipsec.\n");
217
+
return ret;
218
+
}
219
+
220
+
if (cptpf->has_cpt1) {
221
+
cptpf->rsrc_req_blkaddr = BLKADDR_CPT1;
222
+
otx2_cptlf_set_dev_info(&cptpf->cpt1_lfs, cptpf->pdev,
223
+
cptpf->reg_base, &cptpf->afpf_mbox,
224
+
BLKADDR_CPT1);
225
+
ret = otx2_cptlf_init(&cptpf->cpt1_lfs, 1 << egrp,
226
+
OTX2_CPT_QUEUE_HI_PRIO, 1);
227
+
if (ret) {
228
+
dev_err(&cptpf->pdev->dev,
229
+
"LF configuration failed for RX inline ipsec.\n");
230
+
goto lf_cleanup;
231
+
}
232
+
cptpf->rsrc_req_blkaddr = 0;
233
+
}
234
+
235
+
ret = rx_inline_ipsec_lf_cfg(cptpf, egrp, cfg_req);
236
+
if (ret)
237
+
goto lf1_cleanup;
238
+
239
+
return 0;
240
+
241
+
lf1_cleanup:
242
+
otx2_cptlf_shutdown(&cptpf->cpt1_lfs);
243
+
lf_cleanup:
244
+
otx2_cptlf_shutdown(&cptpf->lfs);
245
+
return ret;
246
+
}
247
+
129
248
static int cptpf_handle_vf_req(struct otx2_cptpf_dev *cptpf,
130
249
struct otx2_cptvf_info *vf,
131
250
struct mbox_msghdr *req, int size)
···
279
132
case MBOX_MSG_GET_KVF_LIMITS:
280
133
err = handle_msg_kvf_limits(cptpf, vf, req);
281
134
break;
135
+
case MBOX_MSG_RX_INLINE_IPSEC_LF_CFG:
136
+
err = handle_msg_rx_inline_ipsec_lf_cfg(cptpf, req);
137
+
break;
138
+
282
139
default:
283
140
err = forward_to_af(cptpf, vf, req, size);
284
141
break;
···
407
256
static void process_afpf_mbox_msg(struct otx2_cptpf_dev *cptpf,
408
257
struct mbox_msghdr *msg)
409
258
{
259
+
struct otx2_cptlfs_info *lfs = &cptpf->lfs;
410
260
struct device *dev = &cptpf->pdev->dev;
411
261
struct cpt_rd_wr_reg_msg *rsp_rd_wr;
412
262
···
420
268
msg->sig, msg->id);
421
269
return;
422
270
}
271
+
if (cptpf->rsrc_req_blkaddr == BLKADDR_CPT1)
272
+
lfs = &cptpf->cpt1_lfs;
423
273
424
274
switch (msg->id) {
425
275
case MBOX_MSG_READY:
···
441
287
break;
442
288
case MBOX_MSG_ATTACH_RESOURCES:
443
289
if (!msg->rc)
444
-
cptpf->lfs.are_lfs_attached = 1;
290
+
lfs->are_lfs_attached = 1;
445
291
break;
446
292
case MBOX_MSG_DETACH_RESOURCES:
447
293
if (!msg->rc)
448
-
cptpf->lfs.are_lfs_attached = 0;
294
+
lfs->are_lfs_attached = 0;
295
+
break;
296
+
case MBOX_MSG_CPT_INLINE_IPSEC_CFG:
297
+
case MBOX_MSG_NIX_INLINE_IPSEC_CFG:
449
298
break;
450
299
451
300
default:
+4
-6
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
+4
-6
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
···
1504
1504
if (ret)
1505
1505
goto delete_grps;
1506
1506
1507
-
lfs->pdev = pdev;
1508
-
lfs->reg_base = cptpf->reg_base;
1509
-
lfs->mbox = &cptpf->afpf_mbox;
1510
-
lfs->blkaddr = BLKADDR_CPT0;
1511
-
ret = otx2_cptlf_init(&cptpf->lfs, OTX2_CPT_ALL_ENG_GRPS_MASK,
1507
+
otx2_cptlf_set_dev_info(lfs, cptpf->pdev, cptpf->reg_base,
1508
+
&cptpf->afpf_mbox, BLKADDR_CPT0);
1509
+
ret = otx2_cptlf_init(lfs, OTX2_CPT_ALL_ENG_GRPS_MASK,
1512
1510
OTX2_CPT_QUEUE_HI_PRIO, 1);
1513
1511
if (ret)
1514
1512
goto delete_grps;
···
1560
1562
free_result:
1561
1563
kfree(result);
1562
1564
lf_cleanup:
1563
-
otx2_cptlf_shutdown(&cptpf->lfs);
1565
+
otx2_cptlf_shutdown(lfs);
1564
1566
delete_grps:
1565
1567
delete_engine_grps(pdev, &cptpf->eng_grps);
1566
1568
+1
drivers/crypto/marvell/octeontx2/otx2_cptvf.h
+1
drivers/crypto/marvell/octeontx2/otx2_cptvf.h
+4
-4
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
+4
-4
drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
···
277
277
if (ret)
278
278
return ret;
279
279
280
-
lfs->reg_base = cptvf->reg_base;
281
-
lfs->pdev = cptvf->pdev;
282
-
lfs->mbox = &cptvf->pfvf_mbox;
283
-
284
280
lfs_num = cptvf->lfs.kvf_limits ? cptvf->lfs.kvf_limits :
285
281
num_online_cpus();
282
+
283
+
otx2_cptlf_set_dev_info(lfs, cptvf->pdev, cptvf->reg_base,
284
+
&cptvf->pfvf_mbox, cptvf->blkaddr);
286
285
ret = otx2_cptlf_init(lfs, eng_grp_msk, OTX2_CPT_QUEUE_HI_PRIO,
287
286
lfs_num);
288
287
if (ret)
···
379
380
if (ret)
380
381
goto destroy_pfvf_mbox;
381
382
383
+
cptvf->blkaddr = BLKADDR_CPT0;
382
384
/* Initialize CPT LFs */
383
385
ret = cptvf_lf_init(cptvf);
384
386
if (ret)