Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence
We need to enable and disable the Tx for each active lane after the
Non-TBT enable sequence is done.
Bspec: 74500, 74497, 74701
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-21-suraj.kandpal@intel.com
+91
+87
drivers/gpu/drm/i915/display/intel_lt_phy.c
+87
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
1507
1507
}
1508
1508
}
1509
1509
1510
+
static void
1511
+
intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder,
1512
+
const struct intel_crtc_state *crtc_state)
1513
+
{
1514
+
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1515
+
bool lane_reversal = dig_port->lane_reversal;
1516
+
u8 lane_count = crtc_state->lane_count;
1517
+
bool is_dp_alt =
1518
+
intel_tc_port_in_dp_alt_mode(dig_port);
1519
+
enum intel_tc_pin_assignment tc_pin =
1520
+
intel_tc_port_get_pin_assignment(dig_port);
1521
+
u8 transmitter_mask = 0;
1522
+
1523
+
/*
1524
+
* We have a two transmitters per lane and total of 2 PHY lanes so a total
1525
+
* of 4 transmitters. We prepare a mask of the lanes that need to be activated
1526
+
* and the transmitter which need to be activated for each lane. TX 0,1 correspond
1527
+
* to LANE0 and TX 2, 3 correspond to LANE1.
1528
+
*/
1529
+
1530
+
switch (lane_count) {
1531
+
case 1:
1532
+
transmitter_mask = lane_reversal ? REG_BIT8(3) : REG_BIT8(0);
1533
+
if (is_dp_alt) {
1534
+
if (tc_pin == INTEL_TC_PIN_ASSIGNMENT_D)
1535
+
transmitter_mask = REG_BIT8(0);
1536
+
else
1537
+
transmitter_mask = REG_BIT8(1);
1538
+
}
1539
+
break;
1540
+
case 2:
1541
+
transmitter_mask = lane_reversal ? REG_GENMASK8(3, 2) : REG_GENMASK8(1, 0);
1542
+
if (is_dp_alt)
1543
+
transmitter_mask = REG_GENMASK8(1, 0);
1544
+
break;
1545
+
case 3:
1546
+
transmitter_mask = lane_reversal ? REG_GENMASK8(3, 1) : REG_GENMASK8(2, 0);
1547
+
if (is_dp_alt)
1548
+
transmitter_mask = REG_GENMASK8(2, 0);
1549
+
break;
1550
+
case 4:
1551
+
transmitter_mask = REG_GENMASK8(3, 0);
1552
+
break;
1553
+
default:
1554
+
MISSING_CASE(lane_count);
1555
+
transmitter_mask = REG_GENMASK8(3, 0);
1556
+
break;
1557
+
}
1558
+
1559
+
if (transmitter_mask & BIT(0)) {
1560
+
intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(0),
1561
+
LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(0),
1562
+
LT_PHY_TX_LANE_ENABLE);
1563
+
} else {
1564
+
intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(0),
1565
+
0, LT_PHY_TXY_CTL10_MAC(0), 0);
1566
+
}
1567
+
1568
+
if (transmitter_mask & BIT(1)) {
1569
+
intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(1),
1570
+
LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(1),
1571
+
LT_PHY_TX_LANE_ENABLE);
1572
+
} else {
1573
+
intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(1),
1574
+
0, LT_PHY_TXY_CTL10_MAC(1), 0);
1575
+
}
1576
+
1577
+
if (transmitter_mask & BIT(2)) {
1578
+
intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(0),
1579
+
LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(0),
1580
+
LT_PHY_TX_LANE_ENABLE);
1581
+
} else {
1582
+
intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(0),
1583
+
0, LT_PHY_TXY_CTL10_MAC(0), 0);
1584
+
}
1585
+
1586
+
if (transmitter_mask & BIT(3)) {
1587
+
intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(1),
1588
+
LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(1),
1589
+
LT_PHY_TX_LANE_ENABLE);
1590
+
} else {
1591
+
intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(1),
1592
+
0, LT_PHY_TXY_CTL10_MAC(1), 0);
1593
+
}
1594
+
}
1595
+
1510
1596
void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
1511
1597
const struct intel_crtc_state *crtc_state)
1512
1598
{
···
1719
1633
intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
1720
1634
XELPDP_P0_STATE_ACTIVE);
1721
1635
1636
+
intel_lt_phy_enable_disable_tx(encoder, crtc_state);
1722
1637
intel_lt_phy_transaction_end(encoder, wakeref);
1723
1638
}
1724
1639
+4
drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+4
drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
···
32
32
#define LT_PHY_TX_CURSOR_MASK REG_GENMASK8(5, 0)
33
33
#define LT_PHY_TX_CURSOR(val) REG_FIELD_PREP8(LT_PHY_TX_CURSOR_MASK, val)
34
34
35
+
#define LT_PHY_TXY_CTL10(idx) (0x40A + (0x200 * (idx)))
36
+
#define LT_PHY_TXY_CTL10_MAC(idx) _MMIO(LT_PHY_TXY_CTL10(idx))
37
+
#define LT_PHY_TX_LANE_ENABLE REG_BIT8(0)
38
+
35
39
/* LT Phy Vendor Register */
36
40
#define LT_PHY_VDR_0_CONFIG 0xC02
37
41
#define LT_PHY_VDR_DP_PLL_ENABLE REG_BIT(7)