Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
irqchip/gic-v3: Make distributor priorities variables
In subsequent patches the GICv3 driver will choose the regular interrupt
priority at boot time.
In preparation for using dynamic priorities, place the priorities in
variables and update the code to pass these as parameters. Users of
GICD_INT_DEF_PRI_X4 are modified to replicate the priority byte using
REPEAT_BYTE_U32().
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Tested-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20240617111841.2529370-4-mark.rutland@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
authored by
Mark Rutland
and committed by
Catalin Marinas
a6156e70
e95c64a7
+32
-30
+6
-4
drivers/irqchip/irq-gic-common.c
+6
-4
drivers/irqchip/irq-gic-common.c
···
7
7
#include <linux/io.h>
8
8
#include <linux/irq.h>
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9
#include <linux/irqchip/arm-gic.h>
10
+
#include <linux/kernel.h>
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#include "irq-gic-common.h"
12
13
···
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return ret;
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}
90
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91
-
void gic_dist_config(void __iomem *base, int gic_irqs)
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+
void gic_dist_config(void __iomem *base, int gic_irqs, u8 priority)
92
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{
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unsigned int i;
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93
···
103
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* Set priority on all global interrupts.
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*/
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for (i = 32; i < gic_irqs; i += 4)
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-
writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
105
+
writel_relaxed(REPEAT_BYTE_U32(priority),
106
+
base + GIC_DIST_PRI + i);
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/*
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* Deactivate and disable all SPIs. Leave the PPI and SGIs
···
118
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}
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}
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-
void gic_cpu_config(void __iomem *base, int nr)
119
+
void gic_cpu_config(void __iomem *base, int nr, u8 priority)
122
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{
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int i;
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···
137
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* Set priority on PPI and SGI interrupts
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*/
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for (i = 0; i < nr; i += 4)
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-
writel_relaxed(GICD_INT_DEF_PRI_X4,
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+
writel_relaxed(REPEAT_BYTE_U32(priority),
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base + GIC_DIST_PRI + i * 4 / 4);
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}
+2
-2
drivers/irqchip/irq-gic-common.h
+2
-2
drivers/irqchip/irq-gic-common.h
···
21
21
22
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int gic_configure_irq(unsigned int irq, unsigned int type,
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void __iomem *base);
24
-
void gic_dist_config(void __iomem *base, int gic_irqs);
25
-
void gic_cpu_config(void __iomem *base, int nr);
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+
void gic_dist_config(void __iomem *base, int gic_irqs, u8 priority);
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+
void gic_cpu_config(void __iomem *base, int nr, u8 priority);
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void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
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void *data);
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void gic_enable_of_quirks(const struct device_node *np,
+6
-5
drivers/irqchip/irq-gic-v3-its.c
+6
-5
drivers/irqchip/irq-gic-v3-its.c
···
59
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#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
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#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
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-
#define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
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+
static u8 __ro_after_init lpi_prop_prio;
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/*
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* Collection structure - just an ID, and a redistributor address to
···
1926
1926
/* and restore the physical one */
1927
1927
irqd_clr_forwarded_to_vcpu(d);
1928
1928
its_send_mapti(its_dev, d->hwirq, event);
1929
-
lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1929
+
lpi_update_config(d, 0xff, (lpi_prop_prio |
1930
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LPI_PROP_ENABLED |
1931
1931
LPI_PROP_GROUP1));
1932
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···
2181
2181
2182
2182
static void gic_reset_prop_table(void *va)
2183
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{
2184
-
/* Priority 0xa0, Group-1, disabled */
2185
-
memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
2184
+
/* Regular IRQ priority, Group-1, disabled */
2185
+
memset(va, lpi_prop_prio | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
2186
2186
2187
2187
/* Make sure the GIC will observe the written configuration */
2188
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gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
···
5650
5650
}
5651
5651
5652
5652
int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
5653
-
struct irq_domain *parent_domain)
5653
+
struct irq_domain *parent_domain, u8 irq_prio)
5654
5654
{
5655
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struct device_node *of_node;
5656
5656
struct its_node *its;
···
5660
5660
5661
5661
gic_rdists = rdists;
5662
5662
5663
+
lpi_prop_prio = irq_prio;
5663
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its_parent = parent_domain;
5664
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of_node = to_of_node(handle);
5665
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if (of_node)
+11
-8
drivers/irqchip/irq-gic-v3.c
+11
-8
drivers/irqchip/irq-gic-v3.c
···
12
12
#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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+
#include <linux/kernel.h>
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#include <linux/kstrtox.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
···
37
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#include "irq-gic-common.h"
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-
#define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)
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static u8 dist_prio_irq __ro_after_init = GICD_INT_DEF_PRI;
40
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static u8 dist_prio_nmi __ro_after_init = GICD_INT_DEF_PRI & ~0x80;
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#define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
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#define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
···
558
556
desc->handle_irq = handle_fasteoi_nmi;
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}
560
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561
-
gic_irq_set_prio(d, GICD_INT_NMI_PRI);
559
+
gic_irq_set_prio(d, dist_prio_nmi);
562
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return 0;
564
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}
···
593
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desc->handle_irq = handle_fasteoi_irq;
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}
595
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596
-
gic_irq_set_prio(d, GICD_INT_DEF_PRI);
594
+
gic_irq_set_prio(d, dist_prio_irq);
597
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}
598
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static bool gic_arm64_erratum_2941627_needed(struct irq_data *d)
···
755
753
if (!gic_supports_nmi())
756
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return false;
757
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-
return unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI));
756
+
return unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(dist_prio_nmi));
759
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}
760
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static bool gic_irqnr_is_special(u32 irqnr)
···
939
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writel_relaxed(0, base + GICD_ICFGRnE + i / 4);
940
938
941
939
for (i = 0; i < GIC_ESPI_NR; i += 4)
942
-
writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i);
940
+
writel_relaxed(REPEAT_BYTE_U32(dist_prio_irq),
941
+
base + GICD_IPRIORITYRnE + i);
943
942
944
943
/* Now do the common stuff */
945
-
gic_dist_config(base, GIC_LINE_NR);
944
+
gic_dist_config(base, GIC_LINE_NR, dist_prio_irq);
946
945
947
946
val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1;
948
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if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) {
···
1285
1282
for (i = 0; i < gic_data.ppi_nr + SGI_NR; i += 32)
1286
1283
writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8);
1287
1284
1288
-
gic_cpu_config(rbase, gic_data.ppi_nr + SGI_NR);
1285
+
gic_cpu_config(rbase, gic_data.ppi_nr + SGI_NR, dist_prio_irq);
1289
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gic_redist_wait_for_rwp();
1290
1287
1291
1288
/* initialise system registers */
···
2069
2066
gic_cpu_pm_init();
2070
2067
2071
2068
if (gic_dist_supports_lpis()) {
2072
-
its_init(handle, &gic_data.rdists, gic_data.domain);
2069
+
its_init(handle, &gic_data.rdists, gic_data.domain, dist_prio_irq);
2073
2070
its_cpu_init();
2074
2071
its_lpi_memreserve_init();
2075
2072
} else {
+4
-4
drivers/irqchip/irq-gic.c
+4
-4
drivers/irqchip/irq-gic.c
···
479
479
for (i = 32; i < gic_irqs; i += 4)
480
480
writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
481
481
482
-
gic_dist_config(base, gic_irqs);
482
+
gic_dist_config(base, gic_irqs, GICD_INT_DEF_PRI);
483
483
484
484
writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
485
485
}
···
516
516
gic_cpu_map[i] &= ~cpu_mask;
517
517
}
518
518
519
-
gic_cpu_config(dist_base, 32);
519
+
gic_cpu_config(dist_base, 32, GICD_INT_DEF_PRI);
520
520
521
521
writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
522
522
gic_cpu_if_up(gic);
···
608
608
dist_base + GIC_DIST_CONFIG + i * 4);
609
609
610
610
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
611
-
writel_relaxed(GICD_INT_DEF_PRI_X4,
611
+
writel_relaxed(REPEAT_BYTE_U32(GICD_INT_DEF_PRI),
612
612
dist_base + GIC_DIST_PRI + i * 4);
613
613
614
614
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
···
697
697
writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
698
698
699
699
for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
700
-
writel_relaxed(GICD_INT_DEF_PRI_X4,
700
+
writel_relaxed(REPEAT_BYTE_U32(GICD_INT_DEF_PRI),
701
701
dist_base + GIC_DIST_PRI + i * 4);
702
702
703
703
writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
+2
-2
drivers/irqchip/irq-hip04.c
+2
-2
drivers/irqchip/irq-hip04.c
···
260
260
for (i = 32; i < nr_irqs; i += 2)
261
261
writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3));
262
262
263
-
gic_dist_config(base, nr_irqs);
263
+
gic_dist_config(base, nr_irqs, GICD_INT_DEF_PRI);
264
264
265
265
writel_relaxed(1, base + GIC_DIST_CTRL);
266
266
}
···
287
287
if (i != cpu)
288
288
hip04_cpu_map[i] &= ~cpu_mask;
289
289
290
-
gic_cpu_config(dist_base, 32);
290
+
gic_cpu_config(dist_base, 32, GICD_INT_DEF_PRI);
291
291
292
292
writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
293
293
writel_relaxed(1, base + GIC_CPU_CTRL);
-4
include/linux/irqchip/arm-gic-common.h
-4
include/linux/irqchip/arm-gic-common.h
···
10
10
#include <linux/irqchip/arm-vgic-info.h>
11
11
12
12
#define GICD_INT_DEF_PRI 0xa0
13
-
#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\
14
-
(GICD_INT_DEF_PRI << 16) |\
15
-
(GICD_INT_DEF_PRI << 8) |\
16
-
GICD_INT_DEF_PRI)
17
13
18
14
struct irq_domain;
19
15
struct fwnode_handle;
+1
-1
include/linux/irqchip/arm-gic-v3.h
+1
-1
include/linux/irqchip/arm-gic-v3.h
···
638
638
int __init its_lpi_memreserve_init(void);
639
639
int its_cpu_init(void);
640
640
int its_init(struct fwnode_handle *handle, struct rdists *rdists,
641
-
struct irq_domain *domain);
641
+
struct irq_domain *domain, u8 irq_prio);
642
642
int mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent);
643
643
644
644
static inline bool gic_enable_sre(void)