clk: qcom: mmcc-msm8998: get rid of test clock

-25

1 changed file

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drivers

clk

qcom

mmcc-msm8998.c

-25

drivers/clk/qcom/mmcc-msm8998.c

··· 44 44 P_HDMIPLL, 45 45 P_DPVCO, 46 46 P_DPLINK, 47 - P_CORE_BI_PLL_TEST_SE, 48 47 }; 49 48 50 49 static struct clk_fixed_factor gpll0_div = { ··· 302 303 static const struct parent_map mmss_xo_hdmi_map[] = { 303 304 { P_XO, 0 }, 304 305 { P_HDMIPLL, 1 }, 305 - { P_CORE_BI_PLL_TEST_SE, 7 } 306 306 }; 307 307 308 308 static const struct clk_parent_data mmss_xo_hdmi[] = { 309 309 { .fw_name = "xo" }, 310 310 { .fw_name = "hdmipll" }, 311 - { .fw_name = "core_bi_pll_test_se" }, 312 311 }; 313 312 314 313 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { 315 314 { P_XO, 0 }, 316 315 { P_DSI0PLL, 1 }, 317 316 { P_DSI1PLL, 2 }, 318 - { P_CORE_BI_PLL_TEST_SE, 7 } 319 317 }; 320 318 321 319 static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = { 322 320 { .fw_name = "xo" }, 323 321 { .fw_name = "dsi0dsi" }, 324 322 { .fw_name = "dsi1dsi" }, 325 - { .fw_name = "core_bi_pll_test_se" }, 326 323 }; 327 324 328 325 static const struct parent_map mmss_xo_dsibyte_map[] = { 329 326 { P_XO, 0 }, 330 327 { P_DSI0PLL_BYTE, 1 }, 331 328 { P_DSI1PLL_BYTE, 2 }, 332 - { P_CORE_BI_PLL_TEST_SE, 7 } 333 329 }; 334 330 335 331 static const struct clk_parent_data mmss_xo_dsibyte[] = { 336 332 { .fw_name = "xo" }, 337 333 { .fw_name = "dsi0byte" }, 338 334 { .fw_name = "dsi1byte" }, 339 - { .fw_name = "core_bi_pll_test_se" }, 340 335 }; 341 336 342 337 static const struct parent_map mmss_xo_dp_map[] = { 343 338 { P_XO, 0 }, 344 339 { P_DPLINK, 1 }, 345 340 { P_DPVCO, 2 }, 346 - { P_CORE_BI_PLL_TEST_SE, 7 } 347 341 }; 348 342 349 343 static const struct clk_parent_data mmss_xo_dp[] = { 350 344 { .fw_name = "xo" }, 351 345 { .fw_name = "dplink" }, 352 346 { .fw_name = "dpvco" }, 353 - { .fw_name = "core_bi_pll_test_se" }, 354 347 }; 355 348 356 349 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { 357 350 { P_XO, 0 }, 358 351 { P_GPLL0, 5 }, 359 352 { P_GPLL0_DIV, 6 }, 360 - { P_CORE_BI_PLL_TEST_SE, 7 } 361 353 }; 362 354 363 355 static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = { 364 356 { .fw_name = "xo" }, 365 357 { .fw_name = "gpll0" }, 366 358 { .hw = &gpll0_div.hw }, 367 - { .fw_name = "core_bi_pll_test_se" }, 368 359 }; 369 360 370 361 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { ··· 362 373 { P_MMPLL0_OUT_EVEN, 1 }, 363 374 { P_GPLL0, 5 }, 364 375 { P_GPLL0_DIV, 6 }, 365 - { P_CORE_BI_PLL_TEST_SE, 7 } 366 376 }; 367 377 368 378 static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = { ··· 369 381 { .hw = &mmpll0_out_even.clkr.hw }, 370 382 { .fw_name = "gpll0" }, 371 383 { .hw = &gpll0_div.hw }, 372 - { .fw_name = "core_bi_pll_test_se" }, 373 384 }; 374 385 375 386 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { ··· 377 390 { P_MMPLL1_OUT_EVEN, 2 }, 378 391 { P_GPLL0, 5 }, 379 392 { P_GPLL0_DIV, 6 }, 380 - { P_CORE_BI_PLL_TEST_SE, 7 } 381 393 }; 382 394 383 395 static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { ··· 385 399 { .hw = &mmpll1_out_even.clkr.hw }, 386 400 { .fw_name = "gpll0" }, 387 401 { .hw = &gpll0_div.hw }, 388 - { .fw_name = "core_bi_pll_test_se" }, 389 402 }; 390 403 391 404 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { ··· 393 408 { P_MMPLL5_OUT_EVEN, 2 }, 394 409 { P_GPLL0, 5 }, 395 410 { P_GPLL0_DIV, 6 }, 396 - { P_CORE_BI_PLL_TEST_SE, 7 } 397 411 }; 398 412 399 413 static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { ··· 401 417 { .hw = &mmpll5_out_even.clkr.hw }, 402 418 { .fw_name = "gpll0" }, 403 419 { .hw = &gpll0_div.hw }, 404 - { .fw_name = "core_bi_pll_test_se" }, 405 420 }; 406 421 407 422 static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = { ··· 410 427 { P_MMPLL6_OUT_EVEN, 4 }, 411 428 { P_GPLL0, 5 }, 412 429 { P_GPLL0_DIV, 6 }, 413 - { P_CORE_BI_PLL_TEST_SE, 7 } 414 430 }; 415 431 416 432 static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div[] = { ··· 419 437 { .hw = &mmpll6_out_even.clkr.hw }, 420 438 { .fw_name = "gpll0" }, 421 439 { .hw = &gpll0_div.hw }, 422 - { .fw_name = "core_bi_pll_test_se" }, 423 440 }; 424 441 425 442 static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = { ··· 428 447 { P_MMPLL10_OUT_EVEN, 3 }, 429 448 { P_GPLL0, 5 }, 430 449 { P_GPLL0_DIV, 6 }, 431 - { P_CORE_BI_PLL_TEST_SE, 7 } 432 450 }; 433 451 434 452 static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = { ··· 437 457 { .hw = &mmpll10_out_even.clkr.hw }, 438 458 { .fw_name = "gpll0" }, 439 459 { .hw = &gpll0_div.hw }, 440 - { .fw_name = "core_bi_pll_test_se" }, 441 460 }; 442 461 443 462 static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = { ··· 446 467 { P_MMPLL10_OUT_EVEN, 3 }, 447 468 { P_GPLL0, 5 }, 448 469 { P_GPLL0_DIV, 6 }, 449 - { P_CORE_BI_PLL_TEST_SE, 7 } 450 470 }; 451 471 452 472 static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div[] = { ··· 455 477 { .hw = &mmpll10_out_even.clkr.hw }, 456 478 { .fw_name = "gpll0" }, 457 479 { .hw = &gpll0_div.hw }, 458 - { .fw_name = "core_bi_pll_test_se" }, 459 480 }; 460 481 461 482 static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = { ··· 465 488 { P_MMPLL10_OUT_EVEN, 4 }, 466 489 { P_GPLL0, 5 }, 467 490 { P_GPLL0_DIV, 6 }, 468 - { P_CORE_BI_PLL_TEST_SE, 7 } 469 491 }; 470 492 471 493 static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = { ··· 475 499 { .hw = &mmpll10_out_even.clkr.hw }, 476 500 { .fw_name = "gpll0" }, 477 501 { .hw = &gpll0_div.hw }, 478 - { .fw_name = "core_bi_pll_test_se" }, 479 502 }; 480 503 481 504 static struct clk_rcg2 byte0_clk_src = {

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