Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
amdgpu/pm: Implement emit_clk_levels for vega10
(v1)
- implement emit_clk_levels for vega10, based on print_clk_levels,
but using sysfs_emit rather than sprintf
- modify local int vars to use uint32_t to match arg type of
called functions
- add return of error codes
- refactor OD_XXX cases to return early with -EOPNOTSUPP if
!(hwmgr->od_enabled)
Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Darren Powell
and committed by
Alex Deucher
a63e6b83
5d8539d2
+147
+147
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+147
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
···
4625
4625
>> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
4626
4626
}
4627
4627
4628
+
static int vega10_emit_clock_levels(struct pp_hwmgr *hwmgr,
4629
+
enum pp_clock_type type, char *buf, int *offset)
4630
+
{
4631
+
struct vega10_hwmgr *data = hwmgr->backend;
4632
+
struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4633
+
struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4634
+
struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table);
4635
+
struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table);
4636
+
struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
4637
+
uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
4638
+
PPTable_t *pptable = &(data->smc_state_table.pp_table);
4639
+
4640
+
uint32_t i, now, count = 0;
4641
+
int ret = 0;
4642
+
4643
+
switch (type) {
4644
+
case PP_SCLK:
4645
+
if (data->registry_data.sclk_dpm_key_disabled)
4646
+
return -EOPNOTSUPP;
4647
+
4648
+
ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now);
4649
+
if (unlikely(ret != 0))
4650
+
return ret;
4651
+
4652
+
if (hwmgr->pp_one_vf &&
4653
+
(hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK))
4654
+
count = 5;
4655
+
else
4656
+
count = sclk_table->count;
4657
+
for (i = 0; i < count; i++)
4658
+
*offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4659
+
i, sclk_table->dpm_levels[i].value / 100,
4660
+
(i == now) ? "*" : "");
4661
+
break;
4662
+
case PP_MCLK:
4663
+
if (data->registry_data.mclk_dpm_key_disabled)
4664
+
return -EOPNOTSUPP;
4665
+
4666
+
ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now);
4667
+
if (unlikely(ret != 0))
4668
+
return ret;
4669
+
4670
+
for (i = 0; i < mclk_table->count; i++)
4671
+
*offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4672
+
i, mclk_table->dpm_levels[i].value / 100,
4673
+
(i == now) ? "*" : "");
4674
+
break;
4675
+
case PP_SOCCLK:
4676
+
if (data->registry_data.socclk_dpm_key_disabled)
4677
+
return -EOPNOTSUPP;
4678
+
4679
+
ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now);
4680
+
if (unlikely(ret != 0))
4681
+
return ret;
4682
+
4683
+
for (i = 0; i < soc_table->count; i++)
4684
+
*offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4685
+
i, soc_table->dpm_levels[i].value / 100,
4686
+
(i == now) ? "*" : "");
4687
+
break;
4688
+
case PP_DCEFCLK:
4689
+
if (data->registry_data.dcefclk_dpm_key_disabled)
4690
+
return -EOPNOTSUPP;
4691
+
4692
+
ret = smum_send_msg_to_smc_with_parameter(hwmgr,
4693
+
PPSMC_MSG_GetClockFreqMHz,
4694
+
CLK_DCEFCLK, &now);
4695
+
if (unlikely(ret != 0))
4696
+
return ret;
4697
+
4698
+
for (i = 0; i < dcef_table->count; i++)
4699
+
*offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4700
+
i, dcef_table->dpm_levels[i].value / 100,
4701
+
(dcef_table->dpm_levels[i].value / 100 == now) ?
4702
+
"*" : "");
4703
+
break;
4704
+
case PP_PCIE:
4705
+
current_gen_speed =
4706
+
vega10_get_current_pcie_link_speed_level(hwmgr);
4707
+
current_lane_width =
4708
+
vega10_get_current_pcie_link_width_level(hwmgr);
4709
+
for (i = 0; i < NUM_LINK_LEVELS; i++) {
4710
+
gen_speed = pptable->PcieGenSpeed[i];
4711
+
lane_width = pptable->PcieLaneCount[i];
4712
+
4713
+
*offset += sysfs_emit_at(buf, *offset, "%d: %s %s %s\n", i,
4714
+
(gen_speed == 0) ? "2.5GT/s," :
4715
+
(gen_speed == 1) ? "5.0GT/s," :
4716
+
(gen_speed == 2) ? "8.0GT/s," :
4717
+
(gen_speed == 3) ? "16.0GT/s," : "",
4718
+
(lane_width == 1) ? "x1" :
4719
+
(lane_width == 2) ? "x2" :
4720
+
(lane_width == 3) ? "x4" :
4721
+
(lane_width == 4) ? "x8" :
4722
+
(lane_width == 5) ? "x12" :
4723
+
(lane_width == 6) ? "x16" : "",
4724
+
(current_gen_speed == gen_speed) &&
4725
+
(current_lane_width == lane_width) ?
4726
+
"*" : "");
4727
+
}
4728
+
break;
4729
+
4730
+
case OD_SCLK:
4731
+
if (!hwmgr->od_enabled)
4732
+
return -EOPNOTSUPP;
4733
+
4734
+
*offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_SCLK");
4735
+
podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4736
+
for (i = 0; i < podn_vdd_dep->count; i++)
4737
+
*offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n",
4738
+
i, podn_vdd_dep->entries[i].clk / 100,
4739
+
podn_vdd_dep->entries[i].vddc);
4740
+
break;
4741
+
case OD_MCLK:
4742
+
if (!hwmgr->od_enabled)
4743
+
return -EOPNOTSUPP;
4744
+
4745
+
*offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_MCLK");
4746
+
podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4747
+
for (i = 0; i < podn_vdd_dep->count; i++)
4748
+
*offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n",
4749
+
i, podn_vdd_dep->entries[i].clk/100,
4750
+
podn_vdd_dep->entries[i].vddc);
4751
+
break;
4752
+
case OD_RANGE:
4753
+
if (!hwmgr->od_enabled)
4754
+
return -EOPNOTSUPP;
4755
+
4756
+
*offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE");
4757
+
*offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMHz %10uMHz\n",
4758
+
data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
4759
+
hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4760
+
*offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMHz %10uMHz\n",
4761
+
data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
4762
+
hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4763
+
*offset += sysfs_emit_at(buf, *offset, "VDDC: %7umV %11umV\n",
4764
+
data->odn_dpm_table.min_vddc,
4765
+
data->odn_dpm_table.max_vddc);
4766
+
break;
4767
+
default:
4768
+
ret = -ENOENT;
4769
+
break;
4770
+
}
4771
+
return ret;
4772
+
}
4773
+
4628
4774
static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4629
4775
enum pp_clock_type type, char *buf)
4630
4776
{
···
5705
5559
.set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges,
5706
5560
.display_clock_voltage_request = vega10_display_clock_voltage_request,
5707
5561
.force_clock_level = vega10_force_clock_level,
5562
+
.emit_clock_levels = vega10_emit_clock_levels,
5708
5563
.print_clock_levels = vega10_print_clock_levels,
5709
5564
.display_config_changed = vega10_display_configuration_changed_task,
5710
5565
.powergate_uvd = vega10_power_gate_uvd,