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drm/i915/display: convert the display irq interfaces to struct intel_display

Convert the irq/error init/reset interfaces from struct intel_uncore to
struct intel_display, and drop the dependency on intel_uncore.h.

Since the intel_de_*() calls handle the DMC wakelock internally, we can
drop the wrappers handling wakelocks completely.

v2: Drop the wakelock wrappers (Ville)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/710e03906da91244208839b357fe9171e37441ba.1763370931.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Jani Nikula a651be53 b9241d0e

+68 -116
+68 -116
drivers/gpu/drm/i915/display/intel_display_irq.c
··· 19 19 #include "intel_display_trace.h" 20 20 #include "intel_display_types.h" 21 21 #include "intel_dmc.h" 22 - #include "intel_dmc_wl.h" 23 22 #include "intel_dp_aux.h" 24 23 #include "intel_dsb.h" 25 24 #include "intel_fdi_regs.h" ··· 30 31 #include "intel_pmdemand.h" 31 32 #include "intel_psr.h" 32 33 #include "intel_psr_regs.h" 33 - #include "intel_uncore.h" 34 34 35 - static void irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs) 35 + static void irq_reset(struct intel_display *display, struct i915_irq_regs regs) 36 36 { 37 - intel_uncore_write(uncore, regs.imr, 0xffffffff); 38 - intel_uncore_posting_read(uncore, regs.imr); 37 + intel_de_write(display, regs.imr, 0xffffffff); 38 + intel_de_posting_read(display, regs.imr); 39 39 40 - intel_uncore_write(uncore, regs.ier, 0); 40 + intel_de_write(display, regs.ier, 0); 41 41 42 42 /* IIR can theoretically queue up two events. Be paranoid. */ 43 - intel_uncore_write(uncore, regs.iir, 0xffffffff); 44 - intel_uncore_posting_read(uncore, regs.iir); 45 - intel_uncore_write(uncore, regs.iir, 0xffffffff); 46 - intel_uncore_posting_read(uncore, regs.iir); 43 + intel_de_write(display, regs.iir, 0xffffffff); 44 + intel_de_posting_read(display, regs.iir); 45 + intel_de_write(display, regs.iir, 0xffffffff); 46 + intel_de_posting_read(display, regs.iir); 47 47 } 48 48 49 49 /* 50 50 * We should clear IMR at preinstall/uninstall, and just check at postinstall. 51 51 */ 52 - static void assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg) 52 + static void assert_iir_is_zero(struct intel_display *display, i915_reg_t reg) 53 53 { 54 - u32 val = intel_uncore_read(uncore, reg); 54 + u32 val = intel_de_read(display, reg); 55 55 56 56 if (val == 0) 57 57 return; 58 58 59 - WARN(1, 59 + drm_WARN(display->drm, 1, 60 60 "Interrupt register 0x%x is not zero: 0x%08x\n", 61 61 i915_mmio_reg_offset(reg), val); 62 - intel_uncore_write(uncore, reg, 0xffffffff); 63 - intel_uncore_posting_read(uncore, reg); 64 - intel_uncore_write(uncore, reg, 0xffffffff); 65 - intel_uncore_posting_read(uncore, reg); 62 + intel_de_write(display, reg, 0xffffffff); 63 + intel_de_posting_read(display, reg); 64 + intel_de_write(display, reg, 0xffffffff); 65 + intel_de_posting_read(display, reg); 66 66 } 67 67 68 - static void irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs, 68 + static void irq_init(struct intel_display *display, struct i915_irq_regs regs, 69 69 u32 imr_val, u32 ier_val) 70 70 { 71 - assert_iir_is_zero(uncore, regs.iir); 71 + assert_iir_is_zero(display, regs.iir); 72 72 73 - intel_uncore_write(uncore, regs.ier, ier_val); 74 - intel_uncore_write(uncore, regs.imr, imr_val); 75 - intel_uncore_posting_read(uncore, regs.imr); 73 + intel_de_write(display, regs.ier, ier_val); 74 + intel_de_write(display, regs.imr, imr_val); 75 + intel_de_posting_read(display, regs.imr); 76 76 } 77 77 78 - static void error_reset(struct intel_uncore *uncore, struct i915_error_regs regs) 78 + static void error_reset(struct intel_display *display, struct i915_error_regs regs) 79 79 { 80 - intel_uncore_write(uncore, regs.emr, 0xffffffff); 81 - intel_uncore_posting_read(uncore, regs.emr); 80 + intel_de_write(display, regs.emr, 0xffffffff); 81 + intel_de_posting_read(display, regs.emr); 82 82 83 - intel_uncore_write(uncore, regs.eir, 0xffffffff); 84 - intel_uncore_posting_read(uncore, regs.eir); 85 - intel_uncore_write(uncore, regs.eir, 0xffffffff); 86 - intel_uncore_posting_read(uncore, regs.eir); 83 + intel_de_write(display, regs.eir, 0xffffffff); 84 + intel_de_posting_read(display, regs.eir); 85 + intel_de_write(display, regs.eir, 0xffffffff); 86 + intel_de_posting_read(display, regs.eir); 87 87 } 88 88 89 - static void error_init(struct intel_uncore *uncore, struct i915_error_regs regs, 89 + static void error_init(struct intel_display *display, struct i915_error_regs regs, 90 90 u32 emr_val) 91 91 { 92 - intel_uncore_write(uncore, regs.eir, 0xffffffff); 93 - intel_uncore_posting_read(uncore, regs.eir); 94 - intel_uncore_write(uncore, regs.eir, 0xffffffff); 95 - intel_uncore_posting_read(uncore, regs.eir); 92 + intel_de_write(display, regs.eir, 0xffffffff); 93 + intel_de_posting_read(display, regs.eir); 94 + intel_de_write(display, regs.eir, 0xffffffff); 95 + intel_de_posting_read(display, regs.eir); 96 96 97 - intel_uncore_write(uncore, regs.emr, emr_val); 98 - intel_uncore_posting_read(uncore, regs.emr); 99 - } 100 - 101 - static void 102 - intel_display_irq_regs_init(struct intel_display *display, struct i915_irq_regs regs, 103 - u32 imr_val, u32 ier_val) 104 - { 105 - intel_dmc_wl_get(display, regs.imr); 106 - intel_dmc_wl_get(display, regs.ier); 107 - intel_dmc_wl_get(display, regs.iir); 108 - 109 - irq_init(to_intel_uncore(display->drm), regs, imr_val, ier_val); 110 - 111 - intel_dmc_wl_put(display, regs.iir); 112 - intel_dmc_wl_put(display, regs.ier); 113 - intel_dmc_wl_put(display, regs.imr); 114 - } 115 - 116 - static void 117 - intel_display_irq_regs_reset(struct intel_display *display, struct i915_irq_regs regs) 118 - { 119 - intel_dmc_wl_get(display, regs.imr); 120 - intel_dmc_wl_get(display, regs.ier); 121 - intel_dmc_wl_get(display, regs.iir); 122 - 123 - irq_reset(to_intel_uncore(display->drm), regs); 124 - 125 - intel_dmc_wl_put(display, regs.iir); 126 - intel_dmc_wl_put(display, regs.ier); 127 - intel_dmc_wl_put(display, regs.imr); 128 - } 129 - 130 - static void 131 - intel_display_irq_regs_assert_irr_is_zero(struct intel_display *display, i915_reg_t reg) 132 - { 133 - intel_dmc_wl_get(display, reg); 134 - 135 - assert_iir_is_zero(to_intel_uncore(display->drm), reg); 136 - 137 - intel_dmc_wl_put(display, reg); 97 + intel_de_write(display, regs.emr, emr_val); 98 + intel_de_posting_read(display, regs.emr); 138 99 } 139 100 140 101 struct pipe_fault_handler { ··· 1943 1984 else 1944 1985 intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_VLV); 1945 1986 1946 - error_reset(to_intel_uncore(display->drm), VLV_ERROR_REGS); 1987 + error_reset(display, VLV_ERROR_REGS); 1947 1988 1948 1989 i915_hotplug_interrupt_update_locked(display, 0xffffffff, 0); 1949 1990 intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0); 1950 1991 1951 1992 i9xx_pipestat_irq_reset(display); 1952 1993 1953 - intel_display_irq_regs_reset(display, VLV_IRQ_REGS); 1994 + irq_reset(display, VLV_IRQ_REGS); 1954 1995 display->irq.vlv_imr_mask = ~0u; 1955 1996 } 1956 1997 ··· 2038 2079 DPINVGTT_STATUS_MASK_VLV | 2039 2080 DPINVGTT_EN_MASK_VLV); 2040 2081 2041 - error_init(to_intel_uncore(display->drm), VLV_ERROR_REGS, ~vlv_error_mask()); 2082 + error_init(display, VLV_ERROR_REGS, ~vlv_error_mask()); 2042 2083 2043 2084 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; 2044 2085 ··· 2061 2102 2062 2103 display->irq.vlv_imr_mask = ~enable_mask; 2063 2104 2064 - intel_display_irq_regs_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask); 2105 + irq_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask); 2065 2106 } 2066 2107 2067 2108 void vlv_display_irq_postinstall(struct intel_display *display) ··· 2077 2118 if (HAS_PCH_NOP(display)) 2078 2119 return; 2079 2120 2080 - irq_reset(to_intel_uncore(display->drm), SDE_IRQ_REGS); 2121 + irq_reset(display, SDE_IRQ_REGS); 2081 2122 2082 2123 if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display)) 2083 2124 intel_de_write(display, SERR_INT, 0xffffffff); ··· 2085 2126 2086 2127 void ilk_display_irq_reset(struct intel_display *display) 2087 2128 { 2088 - struct intel_uncore *uncore = to_intel_uncore(display->drm); 2089 - 2090 - irq_reset(uncore, DE_IRQ_REGS); 2129 + irq_reset(display, DE_IRQ_REGS); 2091 2130 display->irq.ilk_de_imr_mask = ~0u; 2092 2131 2093 2132 if (DISPLAY_VER(display) == 7) ··· 2112 2155 for_each_pipe(display, pipe) 2113 2156 if (intel_display_power_is_enabled(display, 2114 2157 POWER_DOMAIN_PIPE(pipe))) 2115 - intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2158 + irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2116 2159 2117 - intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS); 2118 - intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS); 2160 + irq_reset(display, GEN8_DE_PORT_IRQ_REGS); 2161 + irq_reset(display, GEN8_DE_MISC_IRQ_REGS); 2119 2162 2120 2163 if (HAS_PCH_SPLIT(display)) 2121 2164 ibx_display_irq_reset(display); ··· 2157 2200 for_each_pipe(display, pipe) 2158 2201 if (intel_display_power_is_enabled(display, 2159 2202 POWER_DOMAIN_PIPE(pipe))) 2160 - intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2203 + irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2161 2204 2162 - intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS); 2163 - intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS); 2205 + irq_reset(display, GEN8_DE_PORT_IRQ_REGS); 2206 + irq_reset(display, GEN8_DE_MISC_IRQ_REGS); 2164 2207 2165 2208 if (DISPLAY_VER(display) >= 14) 2166 - intel_display_irq_regs_reset(display, PICAINTERRUPT_IRQ_REGS); 2209 + irq_reset(display, PICAINTERRUPT_IRQ_REGS); 2167 2210 else 2168 - intel_display_irq_regs_reset(display, GEN11_DE_HPD_IRQ_REGS); 2211 + irq_reset(display, GEN11_DE_HPD_IRQ_REGS); 2169 2212 2170 2213 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 2171 - intel_display_irq_regs_reset(display, SDE_IRQ_REGS); 2214 + irq_reset(display, SDE_IRQ_REGS); 2172 2215 } 2173 2216 2174 2217 void gen8_irq_power_well_post_enable(struct intel_display *display, ··· 2187 2230 } 2188 2231 2189 2232 for_each_pipe_masked(display, pipe, pipe_mask) 2190 - intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), 2191 - display->irq.de_pipe_imr_mask[pipe], 2192 - ~display->irq.de_pipe_imr_mask[pipe] | extra_ier); 2233 + irq_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), 2234 + display->irq.de_pipe_imr_mask[pipe], 2235 + ~display->irq.de_pipe_imr_mask[pipe] | extra_ier); 2193 2236 2194 2237 spin_unlock_irq(&display->irq.lock); 2195 2238 } ··· 2208 2251 } 2209 2252 2210 2253 for_each_pipe_masked(display, pipe, pipe_mask) 2211 - intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2254 + irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2212 2255 2213 2256 spin_unlock_irq(&display->irq.lock); 2214 2257 ··· 2241 2284 else 2242 2285 mask = SDE_GMBUS_CPT; 2243 2286 2244 - intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); 2287 + irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); 2245 2288 } 2246 2289 2247 2290 void valleyview_enable_display_irqs(struct intel_display *display) ··· 2307 2350 } 2308 2351 2309 2352 if (display->platform.haswell) { 2310 - intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR); 2353 + assert_iir_is_zero(display, EDP_PSR_IIR); 2311 2354 display_mask |= DE_EDP_PSR_INT_HSW; 2312 2355 } 2313 2356 ··· 2318 2361 2319 2362 ibx_irq_postinstall(display); 2320 2363 2321 - intel_display_irq_regs_init(display, DE_IRQ_REGS, display->irq.ilk_de_imr_mask, 2322 - display_mask | extra_mask); 2364 + irq_init(display, DE_IRQ_REGS, display->irq.ilk_de_imr_mask, 2365 + display_mask | extra_mask); 2323 2366 } 2324 2367 2325 2368 static void mtp_irq_postinstall(struct intel_display *display); ··· 2395 2438 if (!intel_display_power_is_enabled(display, domain)) 2396 2439 continue; 2397 2440 2398 - intel_display_irq_regs_assert_irr_is_zero(display, 2399 - TRANS_PSR_IIR(display, trans)); 2441 + assert_iir_is_zero(display, TRANS_PSR_IIR(display, trans)); 2400 2442 } 2401 2443 } else { 2402 - intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR); 2444 + assert_iir_is_zero(display, EDP_PSR_IIR); 2403 2445 } 2404 2446 2405 2447 for_each_pipe(display, pipe) { ··· 2406 2450 2407 2451 if (intel_display_power_is_enabled(display, 2408 2452 POWER_DOMAIN_PIPE(pipe))) 2409 - intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), 2410 - display->irq.de_pipe_imr_mask[pipe], 2411 - de_pipe_enables); 2453 + irq_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), 2454 + display->irq.de_pipe_imr_mask[pipe], 2455 + de_pipe_enables); 2412 2456 } 2413 2457 2414 - intel_display_irq_regs_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, 2415 - de_port_enables); 2416 - intel_display_irq_regs_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, 2417 - de_misc_masked); 2458 + irq_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, de_port_enables); 2459 + irq_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, de_misc_masked); 2418 2460 2419 2461 if (IS_DISPLAY_VER(display, 11, 13)) { 2420 2462 u32 de_hpd_masked = 0; 2421 2463 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | 2422 2464 GEN11_DE_TBT_HOTPLUG_MASK; 2423 2465 2424 - intel_display_irq_regs_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, 2425 - de_hpd_enables); 2466 + irq_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, de_hpd_enables); 2426 2467 } 2427 2468 } 2428 2469 ··· 2430 2477 u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK | 2431 2478 XELPDP_TBT_HOTPLUG_MASK; 2432 2479 2433 - intel_display_irq_regs_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, 2434 - de_hpd_enables); 2480 + irq_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, de_hpd_enables); 2435 2481 2436 - intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff); 2482 + irq_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff); 2437 2483 } 2438 2484 2439 2485 static void icp_irq_postinstall(struct intel_display *display) 2440 2486 { 2441 2487 u32 mask = SDE_GMBUS_ICP; 2442 2488 2443 - intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); 2489 + irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); 2444 2490 } 2445 2491 2446 2492 void gen11_de_irq_postinstall(struct intel_display *display)