tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks

HSI1/2 PCIe and HSI0 USBDP debug outputs are fixed divide-by-8.
OTP also uses 1/8 from oscclk. Replace incorrect div clocks with
fixed-factor clocks to reflect hardware.

Fixes: bdd03ebf721f ("clk: samsung: Introduce Exynos990 clock controller driver")
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20250830-fix-cmu-top-v5-3-7c62f608309e@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

authored by

Denzeel Oliva and committed by
Krzysztof Kozlowski a66dabcd ce2eb09b

+12 -7
+12 -7
drivers/clk/samsung/clk-exynos990.c
··· 931 931 CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 3), 932 932 DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", 933 933 "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 4), 934 - DIV(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug", 935 - "gout_cmu_hsi0_usbdp_debug", CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG, 936 - 0, 4), 937 934 DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus", 938 935 CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 3), 939 936 DIV(CLK_DOUT_CMU_HSI1_MMC_CARD, "dout_cmu_hsi1_mmc_card", 940 937 "gout_cmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD, 941 938 0, 9), 942 - DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie", 943 - CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 7), 944 939 DIV(CLK_DOUT_CMU_HSI1_UFS_CARD, "dout_cmu_hsi1_ufs_card", 945 940 "gout_cmu_hsi1_ufs_card", CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD, 946 941 0, 3), ··· 944 949 0, 3), 945 950 DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus", 946 951 CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4), 947 - DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie", 948 - CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 7), 949 952 DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus", 950 953 CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4), 951 954 DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus", ··· 981 988 CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4), 982 989 DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu", 983 990 CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3), 991 + }; 992 + 993 + static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = { 994 + FFACTOR(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", 995 + "gout_cmu_hsi1_pcie", 1, 8, 0), 996 + FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0), 997 + FFACTOR(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug", 998 + "gout_cmu_hsi0_usbdp_debug", 1, 8, 0), 999 + FFACTOR(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", 1000 + "gout_cmu_hsi2_pcie", 1, 8, 0), 984 1001 }; 985 1002 986 1003 static const struct samsung_gate_clock top_gate_clks[] __initconst = { ··· 1136 1133 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 1137 1134 .div_clks = top_div_clks, 1138 1135 .nr_div_clks = ARRAY_SIZE(top_div_clks), 1136 + .fixed_factor_clks = cmu_top_ffactor, 1137 + .nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor), 1139 1138 .gate_clks = top_gate_clks, 1140 1139 .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 1141 1140 .nr_clk_ids = CLKS_NR_TOP,