clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths

Correct several mux/div widths (DSP_BUS, G2D_MSCL, HSI0 USBDP_DEBUG,
HSI1 UFS_EMBD, APM_BUS, CPUCL0_DBG_BUS, DPU) to match hardware.

Fixes: bdd03ebf721f ("clk: samsung: Introduce Exynos990 clock controller driver")
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20250830-fix-cmu-top-v5-2-7c62f608309e@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

authored by

Denzeel Oliva and committed by

Krzysztof Kozlowski 9 months ago ce2eb09b 19b50ab0

+9 -9

1 changed file

expand all

drivers

clk

samsung

clk-exynos990.c

+9 -9

drivers/clk/samsung/clk-exynos990.c

··· 766 766 MUX(CLK_MOUT_CMU_DPU_ALT, "mout_cmu_dpu_alt", 767 767 mout_cmu_dpu_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPU_ALT, 0, 2), 768 768 MUX(CLK_MOUT_CMU_DSP_BUS, "mout_cmu_dsp_bus", 769 - mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 2), 769 + mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 3), 770 770 MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", 771 771 mout_cmu_g2d_g2d_p, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2), 772 772 MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", 773 - mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 1), 773 + mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2), 774 774 MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", 775 775 mout_cmu_hpm_p, CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2), 776 776 MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus", ··· 782 782 0, 2), 783 783 MUX(CLK_MOUT_CMU_HSI0_USBDP_DEBUG, "mout_cmu_hsi0_usbdp_debug", 784 784 mout_cmu_hsi0_usbdp_debug_p, 785 - CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 2), 785 + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 1), 786 786 MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus", 787 787 mout_cmu_hsi1_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3), 788 788 MUX(CLK_MOUT_CMU_HSI1_MMC_CARD, "mout_cmu_hsi1_mmc_card", ··· 795 795 0, 2), 796 796 MUX(CLK_MOUT_CMU_HSI1_UFS_EMBD, "mout_cmu_hsi1_ufs_embd", 797 797 mout_cmu_hsi1_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD, 798 - 0, 1), 798 + 0, 2), 799 799 MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus", 800 800 mout_cmu_hsi2_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 1), 801 801 MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie", ··· 869 869 CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1), 870 870 871 871 DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus", 872 - CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), 872 + CLK_CON_DIV_CLKCMU_APM_BUS, 0, 2), 873 873 DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu", 874 874 CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3), 875 875 DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus", ··· 894 894 CLK_CON_DIV_CLKCMU_CMU_BOOST, 0, 2), 895 895 DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus", 896 896 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 897 - DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_debug", 897 + DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_dbg_bus", 898 898 "gout_cmu_cpucl0_dbg_bus", CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS, 899 - 0, 3), 899 + 0, 4), 900 900 DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", 901 901 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3), 902 902 DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", ··· 986 986 CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4), 987 987 DIV(CLK_DOUT_CMU_VRA_BUS, "dout_cmu_vra_bus", "gout_cmu_vra_bus", 988 988 CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4), 989 - DIV(CLK_DOUT_CMU_DPU, "dout_cmu_clkcmu_dpu", "gout_cmu_dpu", 990 - CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 4), 989 + DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu", 990 + CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3), 991 991 }; 992 992 993 993 static const struct samsung_gate_clock top_gate_clks[] __initconst = {

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