tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/amd/display: Enable dcn42 in DM

Add support for DCN 4.2 in Display Manager

Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Roman Li and committed by
Alex Deucher a6713b89 6b2dd7d3

+37 -7
+35 -6
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 1 1 // SPDX-License-Identifier: MIT 2 2 /* 3 - * Copyright 2015 Advanced Micro Devices, Inc. 3 + * Copyright 2015-2026 Advanced Micro Devices, Inc. 4 4 * 5 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 6 * copy of this software and associated documentation files (the "Software"), ··· 151 151 152 152 #define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin" 153 153 MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB); 154 + 155 + #define FIRMWARE_DCN_42_DMUB "amdgpu/dcn_4_2_dmcub.bin" 156 + MODULE_FIRMWARE(FIRMWARE_DCN_42_DMUB); 154 157 155 158 /** 156 159 * DOC: overview ··· 1371 1368 case IP_VERSION(3, 5, 0): 1372 1369 case IP_VERSION(3, 5, 1): 1373 1370 case IP_VERSION(3, 6, 0): 1371 + case IP_VERSION(4, 2, 0): 1374 1372 hw_params.ips_sequential_ono = adev->external_rev_id > 0x10; 1375 1373 hw_params.lower_hbr3_phy_ssc = true; 1376 1374 break; ··· 1819 1815 case IP_VERSION(4, 0, 1): 1820 1816 bb_size = sizeof(struct dml2_soc_bb); 1821 1817 break; 1818 + case IP_VERSION(4, 2, 0): 1819 + bb_size = sizeof(struct dml2_soc_bb); 1820 + break; 1822 1821 default: 1823 1822 return NULL; 1824 1823 } ··· 1865 1858 case IP_VERSION(3, 6, 0): 1866 1859 case IP_VERSION(3, 5, 1): 1867 1860 ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; 1861 + break; 1862 + case IP_VERSION(4, 2, 0): 1863 + ret = DMUB_IPS_DISABLE_ALL; 1868 1864 break; 1869 1865 default: 1870 1866 /* ASICs older than DCN35 do not have IPSs */ ··· 2012 2002 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) 2013 2003 init_data.num_virtual_links = 1; 2014 2004 2005 + /* DCN42 and above dpia switch to unified link training path */ 2006 + if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 2, 0)) { 2007 + init_data.flags.consolidated_dpia_dp_lt = true; 2008 + init_data.flags.enable_dpia_pre_training = true; 2009 + init_data.flags.unify_link_enc_assignment = true; 2010 + init_data.flags.usb4_bw_alloc_support = true; 2011 + } 2015 2012 retrieve_dmi_info(&adev->dm); 2016 2013 if (adev->dm.edp0_on_dp1_quirk) 2017 2014 init_data.flags.support_edp0_on_dp1 = true; ··· 2386 2369 case IP_VERSION(3, 5, 1): 2387 2370 case IP_VERSION(3, 6, 0): 2388 2371 case IP_VERSION(4, 0, 1): 2372 + case IP_VERSION(4, 2, 0): 2389 2373 return 0; 2390 2374 default: 2391 2375 break; ··· 2520 2502 case IP_VERSION(4, 0, 1): 2521 2503 dmub_asic = DMUB_ASIC_DCN401; 2522 2504 break; 2523 - 2505 + case IP_VERSION(4, 2, 0): 2506 + dmub_asic = DMUB_ASIC_DCN42; 2507 + break; 2524 2508 default: 2525 2509 /* ASIC doesn't support DMUB. */ 2526 2510 return 0; ··· 5469 5449 case IP_VERSION(3, 5, 1): 5470 5450 case IP_VERSION(3, 6, 0): 5471 5451 case IP_VERSION(4, 0, 1): 5452 + case IP_VERSION(4, 2, 0): 5472 5453 if (register_outbox_irq_handlers(dm->adev)) { 5473 5454 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 5474 5455 goto fail; ··· 5494 5473 case IP_VERSION(3, 5, 1): 5495 5474 case IP_VERSION(3, 6, 0): 5496 5475 case IP_VERSION(4, 0, 1): 5476 + case IP_VERSION(4, 2, 0): 5497 5477 psr_feature_enabled = true; 5498 5478 break; 5499 5479 default: ··· 5672 5650 case IP_VERSION(3, 5, 1): 5673 5651 case IP_VERSION(3, 6, 0): 5674 5652 case IP_VERSION(4, 0, 1): 5653 + case IP_VERSION(4, 2, 0): 5675 5654 if (dcn10_register_irq_handlers(dm->adev)) { 5676 5655 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 5677 5656 goto fail; ··· 5821 5798 case IP_VERSION(4, 0, 1): 5822 5799 fw_name_dmub = FIRMWARE_DCN_401_DMUB; 5823 5800 break; 5801 + case IP_VERSION(4, 2, 0): 5802 + fw_name_dmub = FIRMWARE_DCN_42_DMUB; 5803 + break; 5824 5804 default: 5825 5805 /* ASIC doesn't support DMUB. */ 5826 5806 return 0; ··· 5951 5925 case IP_VERSION(3, 5, 1): 5952 5926 case IP_VERSION(3, 6, 0): 5953 5927 case IP_VERSION(4, 0, 1): 5928 + case IP_VERSION(4, 2, 0): 5954 5929 adev->mode_info.num_crtc = 4; 5955 5930 adev->mode_info.num_hpd = 4; 5956 5931 adev->mode_info.num_dig = 4; ··· 12250 12223 int i; 12251 12224 12252 12225 /* Overlay cursor not supported on HW before DCN 12253 - * DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions 12254 - * as previous DCN generations, so enable native mode on DCN401 12226 + * DCN401/420 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions 12227 + * as previous DCN generations, so enable native mode on DCN401/420 12255 12228 */ 12256 - if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { 12229 + if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1) || 12230 + amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0)) { 12257 12231 *cursor_mode = DM_CURSOR_NATIVE_MODE; 12258 12232 return 0; 12259 12233 } ··· 12674 12646 12675 12647 /* Check if rotation or scaling is enabled on DCN401 */ 12676 12648 if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) && 12677 - amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { 12649 + (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0) || 12650 + amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1))) { 12678 12651 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); 12679 12652 12680 12653 is_rotated = new_cursor_state &&
+2 -1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
··· 1 1 // SPDX-License-Identifier: MIT 2 2 /* 3 - * Copyright 2022 Advanced Micro Devices, Inc. 3 + * Copyright 2022-2026 Advanced Micro Devices, Inc. 4 4 * 5 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 6 * copy of this software and associated documentation files (the "Software"), ··· 759 759 case AMDGPU_FAMILY_GC_11_0_0: 760 760 case AMDGPU_FAMILY_GC_11_0_1: 761 761 case AMDGPU_FAMILY_GC_11_5_0: 762 + case AMDGPU_FAMILY_GC_11_5_4: 762 763 amdgpu_dm_plane_add_gfx11_modifiers(adev, mods, &size, &capacity); 763 764 break; 764 765 case AMDGPU_FAMILY_GC_12_0_0: