Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Move umc ras block init to gmc ras sw_init
Initialize umc ras block only when umc ip block
supports ras. Driver queries ras capabilities after
early_init, ras block init needs to be moved to
sw_init.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Stanley Yang <Stanley.Yang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Hawking Zhang
and committed by
Alex Deucher
a6dcf9a7
f81c31d9
+52
-63
+8
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+8
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
···
447
447
} while (fault->timestamp < tmp);
448
448
}
449
449
450
-
int amdgpu_gmc_ras_early_init(struct amdgpu_device *adev)
450
+
int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev)
451
451
{
452
+
int r;
453
+
454
+
/* umc ras block */
455
+
r = amdgpu_umc_ras_sw_init(adev);
456
+
if (r)
457
+
return r;
458
+
452
459
if (!adev->gmc.xgmi.connected_to_cpu) {
453
460
adev->gmc.xgmi.ras = &xgmi_ras;
454
461
amdgpu_ras_register_ras_block(adev, &adev->gmc.xgmi.ras->ras_block);
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
···
351
351
uint16_t pasid, uint64_t timestamp);
352
352
void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
353
353
uint16_t pasid);
354
-
int amdgpu_gmc_ras_early_init(struct amdgpu_device *adev);
354
+
int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev);
355
355
int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev);
356
356
void amdgpu_gmc_ras_fini(struct amdgpu_device *adev);
357
357
int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev);
+30
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+30
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
···
208
208
return amdgpu_umc_do_page_retirement(adev, ras_error_status, entry, true);
209
209
}
210
210
211
+
int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev)
212
+
{
213
+
int err;
214
+
struct amdgpu_umc_ras *ras;
215
+
216
+
if (!adev->umc.ras)
217
+
return 0;
218
+
219
+
ras = adev->umc.ras;
220
+
221
+
err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
222
+
if (err) {
223
+
dev_err(adev->dev, "Failed to register umc ras block!\n");
224
+
return err;
225
+
}
226
+
227
+
strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");
228
+
ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;
229
+
ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
230
+
adev->umc.ras_if = &ras->ras_block.ras_comm;
231
+
232
+
if (!ras->ras_block.ras_late_init)
233
+
ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;
234
+
235
+
if (ras->ras_block.ras_cb)
236
+
ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;
237
+
238
+
return 0;
239
+
}
240
+
211
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int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
212
242
{
213
243
int r;
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
···
87
87
unsigned long active_mask;
88
88
};
89
89
90
+
int amdgpu_umc_ras_sw_init(struct amdgpu_device *adev);
90
91
int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
91
92
int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset);
92
93
int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
+4
-22
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+4
-22
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
···
699
699
default:
700
700
break;
701
701
}
702
-
if (adev->umc.ras) {
703
-
amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);
704
-
705
-
strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");
706
-
adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;
707
-
adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
708
-
adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;
709
-
710
-
/* If don't define special ras_late_init function, use default ras_late_init */
711
-
if (!adev->umc.ras->ras_block.ras_late_init)
712
-
adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;
713
-
714
-
/* If not defined special ras_cb function, use default ras_cb */
715
-
if (!adev->umc.ras->ras_block.ras_cb)
716
-
adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;
717
-
}
718
702
}
719
-
720
703
721
704
static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
722
705
{
···
737
754
738
755
static int gmc_v10_0_early_init(void *handle)
739
756
{
740
-
int r;
741
757
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
742
758
743
759
gmc_v10_0_set_mmhub_funcs(adev);
···
751
769
adev->gmc.private_aperture_start = 0x1000000000000000ULL;
752
770
adev->gmc.private_aperture_end =
753
771
adev->gmc.private_aperture_start + (4ULL << 30) - 1;
754
-
755
-
r = amdgpu_gmc_ras_early_init(adev);
756
-
if (r)
757
-
return r;
758
772
759
773
return 0;
760
774
}
···
1001
1023
adev->vm_manager.first_kfd_vmid = 8;
1002
1024
1003
1025
amdgpu_vm_manager_init(adev);
1026
+
1027
+
r = amdgpu_gmc_ras_sw_init(adev);
1028
+
if (r)
1029
+
return r;
1004
1030
1005
1031
return 0;
1006
1032
}
+4
-17
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+4
-17
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
···
581
581
default:
582
582
break;
583
583
}
584
-
585
-
if (adev->umc.ras) {
586
-
amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);
587
-
588
-
strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");
589
-
adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;
590
-
adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
591
-
adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;
592
-
593
-
/* If don't define special ras_late_init function, use default ras_late_init */
594
-
if (!adev->umc.ras->ras_block.ras_late_init)
595
-
adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;
596
-
597
-
/* If not define special ras_cb function, use default ras_cb */
598
-
if (!adev->umc.ras->ras_block.ras_cb)
599
-
adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;
600
-
}
601
584
}
602
585
603
586
···
828
845
adev->vm_manager.first_kfd_vmid = 8;
829
846
830
847
amdgpu_vm_manager_init(adev);
848
+
849
+
r = amdgpu_gmc_ras_sw_init(adev);
850
+
if (r)
851
+
return r;
831
852
832
853
return 0;
833
854
}
+4
-22
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+4
-22
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
···
1318
1318
default:
1319
1319
break;
1320
1320
}
1321
-
1322
-
if (adev->umc.ras) {
1323
-
amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);
1324
-
1325
-
strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");
1326
-
adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;
1327
-
adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
1328
-
adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;
1329
-
1330
-
/* If don't define special ras_late_init function, use default ras_late_init */
1331
-
if (!adev->umc.ras->ras_block.ras_late_init)
1332
-
adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;
1333
-
1334
-
/* If not defined special ras_cb function, use default ras_cb */
1335
-
if (!adev->umc.ras->ras_block.ras_cb)
1336
-
adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;
1337
-
}
1338
1321
}
1339
1322
1340
1323
static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
···
1389
1406
1390
1407
static int gmc_v9_0_early_init(void *handle)
1391
1408
{
1392
-
int r;
1393
1409
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1394
1410
1395
1411
/* ARCT and VEGA20 don't have XGMI defined in their IP discovery tables */
···
1417
1435
adev->gmc.private_aperture_start = 0x1000000000000000ULL;
1418
1436
adev->gmc.private_aperture_end =
1419
1437
adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1420
-
1421
-
r = amdgpu_gmc_ras_early_init(adev);
1422
-
if (r)
1423
-
return r;
1424
1438
1425
1439
return 0;
1426
1440
}
···
1775
1797
amdgpu_vm_manager_init(adev);
1776
1798
1777
1799
gmc_v9_0_save_registers(adev);
1800
+
1801
+
r = amdgpu_gmc_ras_sw_init(adev);
1802
+
if (r)
1803
+
return r;
1778
1804
1779
1805
return 0;
1780
1806
}